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April 1st, 2010 Renesas Electronics Corporation
Issued Renesas Electronics Corporation (http://www.renesas.com) Send inquiries http://www.renesas.com/inquiry.
Notice
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DATA SHEET
µPD703032A, 703032AY, 70F3032A, 70F3032AY
V850/SB1 32-BIT SINGLE-CHIP MICROCONTROLLERS
INTEGRATED CIRCUITS
DESCRIPTION µPD703032A, 703032AY, 70F3032A, 70F3032AY (V850/SB1) 32-bit single-chip microcontrollers V850 Series
equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, converter,
controller, integrated single chip. µPD70F3032A 70F3032AY have flash memory place internal mask µPD703032A 703032AY. Because flash memory allows program written erased electrically with device mounted board, these products ideal evaluation stages system development, small-scale production, rapid development products. µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY products with different ROM/RAM size also available. Detailed function descriptions provided following user's manuals. sure read them before designing. V850/SB1, V850/SB2 User's Manual Hardware: U13850E V850 Series User's Manual Architecture: U10243E FEATURES Number instructions: Minimum instruction execution time: internal operation) General-purpose registers: bits registers Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, manipulation instructions, load/store instructions Memory space: linear address space Internal memory ROM: (µPD703032A, 703032AY: mask ROM) (µPD70F3032A, 70F3032AY: flash memory) RAM: (µPD703032A, 703032AY, 70F3032A, 70F3032AY) Interrupt/exception: µPD703032A, 70F3032A (external: internal: sources, exception: source)
µPD703032AY, 70F3032AY (external: internal: sources, exception: source)
lines Total: Timer/counters: 16-bit timer channels: TM0, TM1) 8-bit timer channels: TM7) Watch timer: channel Watchdog timer: channel
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document U14893EJ2V0DS00 (2nd edition) Date Published February 2002 CP(K) Printed Japan
mark
shows major revised points.
2000
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Serial interface Asynchronous serial interface (UART0, UART1) Clocked serial interface (CSI0 CSI3) 3-wire variable length serial interface (CSI4) interface (µPD703032AY, 70F3032AY only)
10-bit resolution converter: channels controller: channels Real-time output port: bits channel bits channels correction: places corrected Power-saving function: HALT/IDLE/STOP modes Packages: 100-pin plastic
µPD70F3032A, 70F3032AY
replaced with µPD703032A 703032AY (internal mask ROM) mass production
APPLICATIONS
equipment (audio, audio, VCR, etc.)
ORDERING INFORMATION
Part Number Package 100-pin plastic 100-pin plastic 100-pin plastic 100-pin plastic Internal Mask (512 Mask (512 Flash memory (512 Flash memory (512
µPD70F3032AGF-3BA µPD70F3032AYGF-3BA
Remarks indicates code suffix. ROMless versions provided.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
CONFIGURATION (Top View)
100-pin plastic µPD70F3032AGF-3BA µPD70F3032AYGF-3BA
P13/SI1/RXD0 P12/SCK0/SCL0Note P11/SO0 P10/SI0/SDA0Note P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4
Notes
Connect directly (µPD703032A, 703032AY).
VPP: Connect normal operation mode (µPD70F3032A, 70F3032AY). SCL0, SCL1, SDA0, SDA1 available only µPD703032AY 70F3032AY.
P111/A2 P112/A3 P113/A4 RESET REGC CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0
P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note P21/SO2 P22/SCK2/SCL1Note P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/VPPNote P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1
P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
IDENTIFICATION
A21: AD15: ADTRG: ANI0 ANI11: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: DSTB: EVDD: EVSS: HLDAK: HLDRQ: INTP0 INTP6: KR7: LBEN: NMI: P07: P15: P27: P37: P47: P57: P65: P77: Address Address/Data Trigger Input Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Power Supply Interface Ground Interface Clock Output Data Strobe Power Supply Port Ground Port Hold Acknowledge Hold Request Internally Connected Interrupt Request from Peripherals Return Lower Byte Enable Non-Maskable Interrupt Request Port Port Port Port Port Port Port Port P83: P96: P100 P107: P110 P113: REGC: RESET: RTP0 RTP7: RTPTRG: R/W: RXD0, RXD1: SCK0 SCK4: SCL0, SCL1: SDA0, SDA1: SI4: SO4: TI00, TI01, TI10, TI11, TO5: TXD0, TXD1: UBEN: VDD: VPP: VSS: WAIT: WRH: WRL: XT1, XT2: Timer Output Transmit Data Upper Byte Enable Power Supply Programming Power Supply Ground Wait Write Strobe High Level Data Write Strobe Level Data Crystal Main Clock Crystal Sub-clock Port Port Port Port Read Regulator Control Reset Real-time Output Port Trigger Input Read/Write Status Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Timer Input
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
INTERNAL BLOCK DIAGRAM
INTP0 INTP6 TI00, TI01, TI10, TI11 TO0, TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5 SI0/SDA0Note SCK0/SCL0Note SI2/SDA1Note SCK2/SCL1Note SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SCK4
INTC
Note
32-bit barrel shifter correction Multiplier Instruction queue HLDRQ (P96) HLDAK (P95) ASTB (P94) DSTB/RD (P93) R/W/WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT (P110) (P100 P107, P110 P113) (P34 P36) (P60 P65) AD15 (P40 P47, P57)
Timer/counters 16-bit timer TM0, 8-bit timer CSI0/I2C0Note CSI2/I2C1Note
System registers
General-purpose registers bits
Note
CSI1/UART0 Ports CSI3/UART1 Variable length CSI4 return function DMAC: Watch timer Watchdog timer BVDD BVSS EVDD EVSS VPPNote ICNote converter CLKOUT RESET
P110 P113 P100 P107
RTP0 RTP7 RTPTRG AVDD AVREF AVSS ANI0 ANI11 ADTRG
Regulator
Notes
µPD703032A, 703032AY:
(mask ROM)
µPD70F3032A, 70F3032AY: (flash memory) µPD703032A, 703032AY, 70F3032A, 70F3032AY:
interface SDAn SCLn pins available only µPD703032AY 70F3032AY.
µPD70F3032A, 70F3032AY µPD703032A, 703032AY
REGC
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
CONTENTS
DIFFERENCES AMONG PRODUCTS.7 FUNCTIONS
Port Pins Non-Port Pins Circuits Recommended Connection Unused Pins.14
ELECTRICAL SPECIFICATIONS
Flash Memory Programming Mode (µPD70F3032A, 70F3032AY only)
PACKAGE DRAWING.43 RECOMMENDED SOLDERING CONDITIONS
APPENDIX NOTES TARGET SYSTEM DESIGN.46
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
DIFFERENCES AMONG PRODUCTS
Product Name Incorporated
Type Mask Size
Size
Flash Memory Programming
Package
µPD703031A µPD703031AY µPD703033A µPD703033AY µPD70F3033A µPD70F3033AY µPD703032A µPD703032AY µPD70F3032A µPD70F3032AY
100-pin 100-pin LQFP 100-pin 100-pin LQFP
Mask
Flash memory
(VPP)
Mask
100-pin
Flash memory
(VPP)
Cautions
There differences noise immunity noise radiation between flash memory mask versions. When pre-producing application with flash memory version then mass-producing with mask version, sure conduct sufficient evaluations commercial samples (not engineering samples) mask version.
When replacing flash memory versions with mask versions, write same code empty area internal ROM.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
FUNCTIONS Port Pins
(1/2)
Name Port 8-bit port Input/output specified 1-bit units. Port 8-bit port Input/output specified 1-bit units. Port 8-bit port Input/output specified 1-bit units. Port 8-bit port Input/output specified 1-bit units. Port 6-bit port Input/output specified 1-bit units. PULL Function Port 8-bit port Input/output specified 1-bit units. Alternate Function INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA0Note SCK0/SCL0Note SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1Note SCK2/SCL1Note SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 TI00 TI01 TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5
AD15
Note µPD703032AY, 70F3032AY only. Remark PULL: On-chip pull-up resistor
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
(2/2)
Name PULL Function Port 6-bit port Input/output specified 1-bit units. Port 8-bit input port Port 4-bit input port Port 7-bit port Input/output specified 1-bit units. Alternate Function
Input
ANI0 ANI7
Input
ANI8 ANI11
P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113
LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ
Port 8-bit port Input/output specified 1-bit units.
RTP0/A5/KR0 RTP1/A6/KR1 RTP2/A7/KR2 RTP3/A8/KR3 RTP4/A9/KR4 RTP5/A10/KR5 RTP6/A11/KR6 RTP7/A12/KR7
Port 4-bit port Input/output specified 1-bit units.
A1/WAIT
Remark
PULL: On-chip pull-up resistor
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Non-Port Pins
(1/4)
Name AD15 ADTRG ANI0 ANI7 ANI8 ANI11 ASCK0 ASCK1 ASTB AVDD AVREF AVSS BVDD BVSS CLKOUT DSTB EVDD EVSS HLDAK HLDRQ Output Input Output Output Output Input Input Baud rate clock input UART0 Baud rate clock input UART1 External address strobe output Positive power supply converter alternate port Reference voltage input converter Ground potential converter alternate port Positive power supply interface alternate port Ground potential interface alternate port Internal system clock output External data strobe output Positive power supply ports alternate-function pins (except interface alternate port) Ground potential ports alternate-function pins (except interface alternate port) hold acknowledge output hold request input Internally connected (µPD703032A, 703032AY only) P93/RD Input Input Output Higher address used external memory expansion 16-bit multiplexed address/data used external memory expansion converter external trigger input Analog input converter Output PULL Function Lower address used external memory expansion Alternate Function P110/WAIT P111 P112 P113 P100/RTP0/KR0 P101/RTP1/KR1 P102/RTP2/KR2 P103/RTP3/KR3 P104/RTP4/KR4 P105/RTP5/KR5 P106/RTP6/KR6 P107/RTP7/KR7 P34/TO0/SCK4 P35/TO1 P36/TO4/TI4 P05/INTP4 P15/SCK1 P25/SCK3
Remark
PULL: On-chip pull-up resistor
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
(2/4)
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 Input External interrupt request input (digital noise elimination supporting remote controller) return input Input External interrupt request input (digital noise elimination) Input PULL Function External interrupt request input (analog noise elimination) Alternate Function P05/ADTRG P06/RTPTRG
LBEN REGC RESET RTP0 RTP1 RTP2 RTP3 RTP4 RTP5 RTP6 RTP7 RTPTRG RXD0 RXD1
Input
P100/RTP0/A5 P101/RTP1/A6 P102/RTP2/A7 P103/RTP3/A8 P104/RTP4/A9 P105/RTP5/A10 P106/RTP6/A11 P107/RTP7/A12
Output Input Output Input Output
External data bus's lower byte enable output Non-maskable interrupt request input Read strobe output Regulator output stabilization capacitance connection System reset input Real-time output port
P90/WRL P93/DSTB P100/KR0/A5 P101/KR1/A6 P102/KR2/A7 P103/KR3/A8 P104/KR4/A9 P105/KR5/A10 P106/KR6/A11 P107/KR7/A12
Input Output Input
Real-time output port external trigger input External read/write status output Serial receive data input UART0 UART1
P06/INTP5 P92/WRH P13/SI1 P23/SI3
Remark
PULL: On-chip pull-up resistor
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
(3/4)
Name SCK0 SCK1 SCK2 SCK3 SCK4 SCL0 SCL1 SDA0 SDA1 TI00 TI01 TI10 Output Input Serial transmit data output (3-wire type) variable length CSI4 External count clock input TM0/external capture trigger input External capture trigger input External count clock input TM1/external capture trigger input External capture trigger input Input External count clock input Input Output Serial receive data input (3-wire type) variable length CSI4 Serial transmit data output (3-wire type) CSI0 CSI3 Input Serial clock (3-wire type) variable length CSI4 Serial clock (µPD703032AY, 70F3032AY only) Serial transmit/receive data (µPD703032AY, 70F3032AY only) Serial receive data input (3-wire type) CSI0 CSI3
PULL
Function Serial clock (3-wire type) CSI0 CSI3
Alternate Function P12/SCL0Note P15/ASCK0 P22/SCL1Note P25/ASCK1 P34/TO0/A13 P12/SCK0 P22/SCK2 P10/SI0 P20/SI2 P10/SDA0Note P13/RXD0 P20/SDA1Note P23/RXD1 P32/TI10 P14/TXD0 P24/TXD1 P33/TI11 P32/SI4
TI11 TXD0 TXD1 UBEN Output Output Output Output
P33/SO4 P26/TO2 P27/TO3 P36/TO4/A15 P37/TO5
Pulse signal output
P34/A13/SCK4 P35/A14
Pulse signal output
P26/TI2 P27/TI3 P36/TI4/A15 P37/TI5
Serial transmit data output UART0 UART1
P14/SO1 P24/SO3
Higher byte enable output external data Positive power supply
Note µPD703032AY, 70F3032AY only. Remark PULL: On-chip pull-up resistor
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
(4/4)
Name WAIT Input Output Output Input Input Resonator connection subsystem clock PULL Function High voltage apply program write/verify (µPD70F3032A, 70F3032AY only) Ground potential Control signal input inserting wait cycle Higher byte write strobe signal output external data Lower byte write strobe signal output external data Resonator connection main clock P110/A1 P92/R/W P90/LBEN Alternate Function
Remark
PULL: On-chip pull-up resistor
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Circuits Recommended Connection Unused Pins
input/output circuit type each recommended connection unused pins show Table 2-1. input/output schematic circuit diagram each type, refer Figure 2-1. Table 2-1. Types Circuits Recommended Connection Unused Pins (1/2)
Alternate Function Circuit Type Buffer Power Supply EVDD Recommended Connection Unused Pins
INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 TI00 TI01 TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 AD15
Input state:
Independently connect EVDD EVSS resistor. Output state: Leave open.
10-A 10-A 10-A 10-A 10-A 10-A
EVDD
Input state:
Independently connect EVDD EVSS resistor. Output state: Leave open.
EVDD
Input state:
Independently connect EVDD EVSS resistor. Output state: Leave open.
EVDD
Input state:
Independently connect EVDD EVSS resistor. Output state: Leave open.
BVDD BVDD BVDD
Input state:
Independently connect BVDD BVSS resistor. Output state: Leave open.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Table 2-1. Types Circuits Recommended Connection Unused Pins (2/2)
Alternate Function Circuit Type Buffer Power Supply AVDD AVDD BVDD Input state: Independently connect BVDD BVSS resistor. Output state: Leave open. Recommended Connection Unused Pins
P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 CLKOUT RESET AVREF
Note
ANI0 ANI7 ANI8 ANI11 LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP0/A5/KR0 RTP1/A6/KR1 RTP2/A7/KR2 RTP3/A8/KR3 RTP4/A9/KR4 RTP5/A10/KR5 RTP6/A11/KR6 RTP7/A12/KR7 A1/WAIT
Independently connect AVDD AVSS resistor.
10-A
EVDD
Input state:
Independently connect EVDD EVSS resistor. Output state: Leave open.
EVDD
Input state:
Independently connect EVDD EVSS resistor. Output state: Leave open.
BVDD EVDD
Leave open. Connect resistor. Leave open. Connect AVSS resistor. Connect directly VSS. Connect VSS.
Note
Notes
µPD703032A, 703032AY µPD70F3032A, 70F3032AY
Caution Three power supply systems available supply power buffers V850/SB1's pins: EVDD, BVDD, AVDD. voltage ranges that used these buffer power supplies shown below. EVDD, BVDD: AVDD: electrical specifications differ depending whether power supply voltage range under
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Figure 2-1. Input/Output Circuits (1/2)
Type
Type
Pull-up enable Data
P-ch P-ch IN/OUT
Output disable Schmitt-triggered input with hysteresis characteristics Input enable Type Data P-ch Output disable N-ch Pull-up enable Data Type
N-ch
P-ch P-ch IN/OUT
Output disable Push-pull output that high-impedance output (both P-ch N-ch off)
N-ch
Type Data P-ch IN/OUT Output disable N-ch
Type
P-ch N-ch
Comparator
VREF (threshold voltage)
Input enable
Input enable
Caution circuit diagrams read EVDD, BVDD, AVDD, appropriate.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Figure 2-1. Input/Output Circuits (2/2)
Type 10-A
Type
Pull-up enable Data P-ch
P-ch
Pull-up enable Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable N-ch
Open drain Output disable
N-ch
Type Feedback cutoff P-ch
Caution circuit diagrams read EVDD, BVDD, AVDD, appropriate.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol AVDD BVDD EVDD AVSS BVSS EVSS Input voltage Analog input voltage Analog reference input voltage Output current, VIAN AVREF (µPD70F3032A, 70F3032AY only) AVDD BVDD EVDD AVSS BVSS EVSS Note (BVDD pin) Note RESET (EVDD pin) Note (AVDD pin) AVREF Total P07, P15, Total P26, P27, P37, P100 P107, P110 P113 Total P47, P96, CLKOUT Total P57, Output current, high Total P07, P15, Total P26, P27, P37, P100 P107, P110 P113 Total P47, P96, CLKOUT Total P57, Output voltage Operating ambient temperature Note CLKOUT (BVDD pin) Note (EVDD pin) Normal operation mode Flash memory programming mode (µPD70F3032A, 70F3032AY only) Storage temperature Tstg Conditions Ratings -0.5 +7.0 -0.5 +8.5 -0.5 +7.0 -0.5 +7.0 -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 -0.5 +0.5 -0.5 BVDD -0.5 EVDD -0.5 AVDD -0.5 AVDD -4.0 -0.5 BVDD -0.5 EVDD +150 +125
Note Note
Unit
Note
Note
Note
Note
µPD703032A, 703032AY µPD70F3032A, 70F3032AY
Notes Ports their alternate-function pins Ports their alternate-function pins Ports their alternate-function pins sure exceed absolute maximum ratings (MAX. value) each supply voltage.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Cautions directly connect output I/O) pins products each other, VDD, VCC, GND. Open-drain pins open-collector pins, however, directly connected each other. Direct connection output pins between product external circuit possible, output pins high-impedance state output timing external circuit designed avoid output conflict. Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. ratings conditions indicated characteristics characteristics represent quality assurance range during normal operation. Capacitance AVDD BVDD EVDD AVSS BVSS EVSS
Parameter Input capacitance capacitance Output capacitance Symbol Conditions Unmeasured pins returned MIN. TYP. MAX. Unit
Operating Conditions Operating frequency
Operating Frequency (fXX) Note 32.768 Other than IDLE mode IDLE mode AVDD Note Note Note BVDD EVDD Remark
Notes When converter used When converter used During STOP mode (when only watch timer operating), Shifting STOP mode restoring from STOP mode must performed min. Shifting IDLE mode restoring from IDLE mode must performed min. operating frequency
Parameter operating frequency Symbol fCPU Conditions Main clock operation Subclock operation MIN. 0.25 32.768 TYP. MAX. Unit
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Recommended Oscillator Main clock oscillator Connection ceramic resonator crystal resonator
Parameter Oscillation frequency Oscillation stabilization time
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Upon reset release Upon STOP mode release
/fXX Note
Note TYP. value differs depending setting oscillation stabilization time select register (OSTS). Cautions main clock oscillator operates output voltage on-chip regulator (3.3 External clock input prohibited. When using main clock oscillator, wire follows area enclosed broken lines above figure avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. Ensure that duty oscillation waveform between 4.5. Sufficiently evaluate matching between µPD703032A, 703032AY, 70F3032A, 70F3032AY resonator.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Ceramic resonator
Manufacturer Part Number Oscillation Frequency (MHz) 8.00 Recommended Circuit Constant (pF) On-chip On-chip 12.5 On-chip On-chip 16.00 On-chip 20.00 On-chip On-chip (pF) On-chip On-chip On-chip On-chip On-chip On-chip On-chip Oscillation Voltage Range MIN. MAX.
Murata Mfg. Co., Ltd.
CSTLS8M00G56-B0 CSTCC8M00G56-R0 CSTLA12M5T55-B0 CSTCV12M5T54J-R0 CSALS16M0X55-B0 CSTCV16M0X51J-R0 CSTLS20M0X51-B0 CSTCW20M0X51-R0
Caution oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use. Subclock oscillator Connection crystal resonator
Parameter Oscillation frequency Oscillation stabilization time
Symbol
Conditions
MIN.
TYP. 32.768
MAX.
Unit
Cautions subclock oscillator operates output voltage on-chip regulator (3.3 External clock input prohibited. When using subclock oscillator, wire follows area enclosed broken lines above figure avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. Sufficiently evaluate matching between µPD703032A, 703032AY, 70F3032A, 70F3032AY resonator.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Characteristics BVDD EVDD AVDD (when converter used), AVDD (when converter used), AVSS BVSS EVSS (1/2)
Parameter Input voltage, high Symbol VIH1 Note Conditions BVDD BVDD VIH2 Note EVDD EVDD VIH3 Note RESET EVDD EVDD VIH4 Input voltage, VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH1 Note Note Note Note RESET Note Note CLKOUT BVDD -100 BVDD VOH2 Notes EVDD -100 EVDD Output voltage, BVDD, EVDD BVDD, EVDD power supply voltage Input leakage current, high Input leakage current, Output leakage current, high Output leakage current, VPP1 ILIH ILIL ILOH ILOL Normal operation BVDD EVDD AVDD BVDD EVDD AVDD MIN. 0.7BVDD 0.8BVDD 0.7EVDD 0.8EVDD 0.7EVDD 0.8EVDD 0.7AVDD BVSS EVSS EVSS AVSS BVDD TYP. MAX. BVDD BVDD EVDD EVDD EVDD EVDD AVDD 0.3BVDD 0.3EVDD 0.3EVDD 0.3AVDD Unit
BVDD
EVDD
EVDD
Notes Ports their alternate-function pins P11, P14, P21, P24, P34, P35, P110 P113, their alternate-function pins P07, P10, P12, P13, P15, P20, P22, P23, P27, P33, P36, P37, P100 P107, their alternate-function pins Ports their alternate-function pins
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Characteristics BVDD EVDD AVDD (when converter used), AVDD (when converter used), AVSS BVSS EVSS (2/2)
Parameter Supply current Symbol IDD1 IDD2 IDD3 Conditions normal operation mode HALT mode IDLE modeNote STOP mode
Note Note
MIN.
TYP.
MAX.
Unit
µPD703032A, µPD703032AY
Watch timer operating
IDD4
Watch timer, subclock oscillator operating Subclock oscillator stopped,
IDD5
normal operation mode (subclock operation)Note IDLE mode (subclock operation)Note normal operation mode HALT mode IDLE modeNote STOP mode
Note Note
IDD6
µPD70F3032A, µPD70F3032AY
IDD1 IDD2 IDD3
Watch timer operating
IDD4
Watch timer, subclock oscillator operating Subclock oscillator stopped,
IDD5
normal operation mode (subclock operation)Note IDLE mode (subclock operation)Note
IDD6 Pull-up resistance
Notes fCPU MHz, peripheral functions operating fCPU 32.768 kHz, main clock oscillator stopped Remark TYP. values reference values when BVDD EVDD AVDD current consumed output buffer included.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Data Retention Characteristics AVSS BVSS EVSS
Parameter Data retention voltage Symbol VDDDR Conditions STOP mode (all functions operating) VDDDR, (Subclock stopped) MIN.
Note
TYP.
MAX.
Unit
Data retention current
IDDDR
µPD703032A, µPD703032AY µPD70F3032A, µPD70F3032AY
Power supply voltage rise time Power supply voltage fall time Power supply voltage hold time (from STOP mode setting) STOP mode release signal input time Data retention high-level input voltage Data retention low-level input voltage
tRVD tFVD tHVD
tDREL VIHDR VILDR input ports input ports
0.9VDDDR VDDDR 0.1VDDDR
Note
During STOP mode (when only watch timer operating), Shifting STOP mode restoring from STOP mode must performed min.
Remark
TYP. values reference values when
Setting STOP mode
VNote tFVD tHVD DDDR tRVD tDREL
RESET (input)
IHDR
STOP mode release interrupt (NMI, etc.) (Release falling edge)
IHDR
STOP mode release interrupt (NMI, etc.) (Release rising edge) ILDR
Note indicates minimum operating voltage V850/SB1.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Characteristics BVDD EVDD AVDD (when converter used), AVDD (when converter used), AVSS BVSS EVSS Test Input Test Point (VDD: EVDD, BVDD, AVDD)
Input signal
Measurement points
Test Output Test Points (VDD: EVDD, BVDD)
Output signal
Measurement points
Load Conditions
(Device under test)
Caution load capacitance exceeds circuit configuration, bring load capacitance device less inserting buffer some other means.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Clock timing BVDD EVDD AVSS BVSS EVSS
Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol tCYK tWKH tWKL Conditions MIN. 0.4tCYK 0.4tCYK MAX. 31.2 Unit
BVDD EVDD AVSS BVSS EVSS
Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol tCYK tWKH tWKL Conditions MIN. 58.8 0.4tCYK 0.4tCYK MAX. 31.2 Unit
CLKOUT (output)
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Output waveform (other than port port port port CLKOUT) BVDD EVDD BVSS EVSS
Parameter Output rise time Output fall time Symbol Conditions MIN. MAX. Unit
Output signal
Reset timing BVDD EVDD AVSS BVSS EVSS
Parameter RESET high-level width RESET low-level width Symbol tWRSH tWRSL Conditions MIN. MAX. Unit
RESET (input)
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
timing Clock asynchronous BVDD EVDD AVSS BVSS EVSS
Parameter Address setup time ASTB) Address hold time (from ASTB) Address float delay time from DSTB Data input setup time from address Data input setup time from DSTB Delay time from ASTB DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB ASTB Delay time from DSTB ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time DSTB) Data output hold time (from DSTB) WAIT setup time address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> WAIT hold time (from address) <27> <28> WAIT setup time ASTB) <29> <30> WAIT hold time (from ASTB) <31> <32> HLDRQ high-level width HLDAK low-level width output delay time from HLDAK Delay time from HLDRQ HLDAK Delay time from HLDRQ HLDAK <33> <34> <35> <36> <37> tSAST tHSTA tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 tHSTWT1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 0.5T 7.5)T 1.5T (0.5 (1.5 1.5T (1.5 0.5T 0.5T (1.5 Conditions MIN. 0.5T 0.5T MAX. Unit
Remarks 1/fCPU (fCPU: operating clock frequency) Number wait clocks inserted cycle. sampling timing changes when programmable wait inserted. Number idle states inserted after read cycle values above specifications values when clocks with duty ratio input from
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Clock asynchronous BVDD EVDD AVSS BVSS EVSS
Parameter Address setup time ASTB) Address hold time (from ASTB) Address float delay time from DSTB Data input setup time from address Data input setup time from DSTB Delay time from ASTB DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB ASTB Delay time from DSTB ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time DSTB) Data output hold time (from DSTB) WAIT setup time address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> WAIT hold time (from address) <27> <28> WAIT setup time ASTB) <29> <30> WAIT hold time (from ASTB) <31> <32> HLDRQ high-level width HLDAK low-level width output delay time from HLDAK Delay time from HLDRQ HLDAK Delay time from HLDRQ HLDAK <33> <34> <35> <36> <37> tSAST tHSTA tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 tHSTWT1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 0.5T 7.5)T 1.5T (0.5 (1.5 1.5T (1.5 0.5T 0.5T (1.5 Conditions MIN. 0.5T 0.5T MAX. Unit
Remarks 1/fCPU (fCPU: operating clock frequency) Number wait clocks inserted cycle. sampling timing changes when programmable wait inserted. Number idle states inserted after read cycle values above specifications values when clocks with duty ratio input from
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Clock synchronous BVDD EVDD AVSS BVSS EVSS
Parameter Delay time from CLKOUT address Delay time from CLKOUT address float Delay time from CLKOUT ASTB Delay time from CLKOUT DSTB Data input setup time CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT address float (during hold) Delay time from CLKOUT HLDAK Symbol <38> <39> tDKA tFKA Conditions MIN. MAX. Unit
<40> <41> <42> <43> <44> <45> <46> <47> <48> <49>
tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF
<50>
tDKHA
Remark values above specifications values when clocks with duty ratio input from
Clock synchronous BVDD EVDD AVSS BVSS EVSS
Parameter Delay time from CLKOUT address Delay time from CLKOUT address float Delay time from CLKOUT ASTB Delay time from CLKOUT DSTB Data input setup time CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT address float (during hold) Delay time from CLKOUT HLDAK Symbol <38> <39> tDKA tFKA Conditions MIN. MAX. Unit
<40> <41> <42> <43> <44> <45> <46> <47> <48> <49>
tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF
<50>
tDKHA
Remark values above specifications values when clocks with duty ratio input from
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Read cycle (CLKOUT synchronous/asynchronous, wait)
CLKOUT (output)
<38>
(output) (output) Note (output)
<13> <39>
<42>
<43>
AD15 (I/O)
Address
Data
<40> <10> <11> <16> <40>
ASTB (output)
<21>
<41> <12> <15> <14>
<41> <18> <17> <19>
DSTB, (output) <20> <45>
<29><45> <46> <31> <30> <32> WAIT (input) <25> <27> <26> <28>
<46>
Note R/W, UBEN, LBEN Remarks broken lines indicate high impedance. high level.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Write cycle (CLKOUT synchronous/asynchronous, wait)
CLKOUT (output)
<38>
(output) (output) Note (output)
<44>
AD15 (I/O)
Address
Data
<40> <10> <11> <40>
ASTB (output)
<21>
<41> <22> <15> <23>
<41> <18> <24>
DSTB, WRL, (output) <20> <45>
<29><45> <46> <31> <30> <32> WAIT (input) <25> <27> <26> <28>
<46>
Note R/W, UBEN, LBEN Remarks broken lines indicate high impedance. high level.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
hold timing
CLKOUT (output)
<47> <47> <48> HLDRQ (input) <50> <36> HLDAK (output) <34> <49>
(output) Note (output)
<33>
<50> <37>
<35>
(output)
AD15 (I/O)
Data
ASTB (output)
DSTB, (output) WRL, (output)
Note R/W, UBEN, LBEN Remark broken lines indicate high impedance.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Interrupt timing BVDD EVDD AVSS BVSS EVSS
Parameter high-level width low-level width INTPn high-level width Symbol <51> <52> <53> tWNIH tWNIL tWITH analog noise elimination digital noise elimination digital noise elimination INTPn low-level width <54> tWITL analog noise elimination digital noise elimination digital noise elimination Conditions MIN. 3Tsmp 3Tsmp MAX. Unit
Remarks 1/fXX Tsmp Noise elimination sampling clock cycle
<51>
<52>
(input)
<53>
<54>
INTPn (input)
Remark
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
timing BVDD EVDD AVSS BVSS EVSS
Parameter TIn0, TIn1 high-level width TIn0, TIn1 low-level width high-level width low-level width Symbol <55> <56> <57> <58> tTIHn tTILn tTIHm tTILm Conditions MIN. 2Tsam
Note
MAX.
Unit
2Tsam 20Note
Note Tsam select following count clocks setting PRMn2 PRMn0 bits prescaler mode registers (PRMn0, PRMn1). When (TM0), Tsam 16T, 64T, 256T, 1/INTWTNI cycle When (TM1), Tsam 16T, 32T, 128T, 256T However, when TIn0 valid edge selected count clock, Tsam Remark 1/fXX
<55>
<56>
TIn0, TIn1 (input)
<57>
<58>
(input)
Remark
Asynchronous serial interface (UART0, UART1) timing BVDD EVDD AVSS BVSS EVSS
Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol <59> <60> <61> tKCY13 tKH13 tKL13 Conditions MIN. MAX. Unit
Remark
<59> <60> <61>
ASCKn (input)
Remark
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
3-wire serial interface (CSI0 CSI3) timing Master mode BVDD EVDD AVSS BVSS EVSS
Parameter SCKn cycle SCKn high-level width SCKn low-level width setup time SCKn) hold time (from SCKn) Delay time from SCKn output Symbol <62> <63> <64> <65> <66> <67> tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. MAX. Unit
Remark Slave mode BVDD EVDD AVSS BVSS EVSS
Parameter SCKn cycle SCKn high-level width SCKn low-level width setup time SCKn) hold time (from SCKn) Delay time from SCKn output Symbol <62> <63> <64> <65> <66> <67> tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 EVDD EVDD Conditions MIN. MAX. Unit
Remark
<62> <63> <64>
SCKn (I/O)
<65>
<66>
(input)
Input data
<67>
(output)
Output data
Remarks broken lines indicate high impedance.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
3-wire variable length serial interface (CSI4) timing Master mode BVDD EVDD AVSS BVSS EVSS
Parameter SCK4 cycle Symbol <68> tKCY1 Conditions EVDD EVDD SCK4 high-level width <69> tKH1 EVDD EVDD SCK4 low-level width <70> tKL1 EVDD EVDD setup time SCK4) <71> tSIK1 EVDD EVDD hold time (from SCK4) Delay time from SCK4 output <72> <73> tKSI1 tKSO1 MIN. MAX. Unit
Slave mode BVDD EVDD AVSS BVSS EVSS
Parameter SCK4 cycle Symbol <68> tKCY2 Conditions EVDD EVDD SCK4 high-level width <69> tKH2 EVDD EVDD SCK4 low-level width <70> tKL2 EVDD EVDD setup time SCK4) <71> tSIK2 EVDD EVDD hold time (from SCK4) Delay time from SCK4 output <72> <73> tKSI2 tKSO2 EVDD EVDD MIN. MAX. Unit
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
<68> <69> <70>
SCK4 (I/O)
<71>
<72>
(input)
Input data
<73>
(output)
Output data
Remark
broken lines indicate high impedance.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
(10) mode (µPD703032AY, 70F3032AY only)
BVDD EVDD AVSS BVSS EVSS
Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus-free time (between stop/start conditions) Hold timeNote SCLn clock low-level width SCLn clock high-level width Setup time start/restart conditions Data hold time CBUS compatible master mode Data setup time SDAn SCLn signal rise time SDAn SCLn signal fall time Stop condition setup time Pulse width spike suppressed input filter Capacitance load each line <80> <81> tSU:DAT <74> fCLK tBUF MAX. High-Speed Mode MIN. MAX. Unit
<75> <76> <77> <78>
tHD:STA tLOW tHIGH tSU:STA
<79>
tHD:DAT
0Note
1000
0Note
Note
0.9Note
Note
0.1Cb
<82>
0.1CbNote
<83> <84>
tSU:STO
Notes start condition, first clock pulse generated after hold time. system requires minimum hold time internally SDAn signal VIHmin. SCLn signal) order occupy undefined area falling edge SCLn. system does extend SCLn signal's low-level width (tLOW), only maximum data hold time (tHD:DAT) needs satisfied. high-speed mode used normal-mode system. this case, high-speed mode that meets following conditions. system does extend SCLn signal's low-level width: tSU:DAT system extends SCLn signal's low-level width: Transmit following data SDAn line prior SCLn line release (tRmax. tSU:DAT 1,000 1,250 Normal mode specification). Total capacitance line (unit:
Remark
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
<76>
<77>
SCLn (I/O)
<82> <75> <81> <79> <80> <78> <75> <84> <83>
SDAn (I/O)
<74> <81> <82>
Stop condition
Start condition
Restart condition
Stop condition
Remark
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Converter Characteristics AVDD AVREF AVSS Output load capacitance:
Parameter Resolution Overall error
Note
Symbol ADM2 ADM2
Conditions
MIN.
TYP.
MAX. ±0.6 ±1.0
Unit %FSR %FSR
Conversion time Zero-scale error Full-scale error
Note
tCONV ADM2 ADM2
±0.4 ±0.4 ±0.6 ±4.0 ±6.0 ±4.0 ±6.0
%FSR %FSR %FSR
Note
Integral linearity error
Note
ADM2 ADM2
Differential linearity error
Note
ADM2 ADM2
Analog reference voltage Analog power supply voltage Analog input voltage AVREF input current AVDD power supply current
AVREF AVDD VIAN AIREF AIDD
AVREF AVDD
AVSS
AVREF
ADM2 ADM2
Notes Excluding quantization error (±0.05 %FSR) Excluding quantization error (±0.5 LSB) Remarks LSB: Least Significant FSR: Full Scale Range ADM2: converter mode register Regulator
Parameter Output stabilization time Symbol tREG Conditions Stabilization capacitance (Connected REGC pin) MIN. TYP. MAX. Unit
Cautions sure start inputting supply voltage when RESET EVSS BVSS (the above state), make RESET high level after tREG period elapsed. supply voltage BVDD EVDD input before tREG period elapsed following input supply voltage VDD, note that data driven from pins until tREG period elapsed because buffers' power supply turned while circuit undefined state.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Flash Memory Programming Mode (µPD70F3032A, 70F3032AY only)
Write/erase characteristics AVDD BVDD EVDD AVSS BVSS EVSS
Parameter power supply voltage Symbol VPP2 Conditions During flash memory programming When VPP2, VPP2 Note When step erase time Note Note When write-back time Note MIN. TYP. MAX. Unit
power supply current power supply current Step erase time Overall erase time area
tERA
s/area
Write-back time Number write-backs write-back command
Count/writeback command Count
Number erase/write-backs Step writing time Overall writing time word
CERWB tWRW Note When step writing time word bytes), Note erase write after erase rewrite, Note
µs/word
Number rewrites area
CERWR
Count/area
Notes
recommended setting value step erase time prewrite time prior erasure erase verify time (write-back time) included. recommended setting value write-back time Write-back executed once issuance write-back command. Therefore, retry count must maximum value minus number commands issued. recommended setting value step writing time added actual writing time word. internal verify time during after writing included. When writing initially shipped products, counted rewrite both "erase write" "write only". Example Write, Erase) Shipped product rewrites Shipped product rewrites
Remarks When PG-FP3 used, time parameter required writing/erasing downloading parameter files automatically set. change settings unless otherwise specified. Area 000000H 01FFFFH Area 040000H 05FFFFH Area 020000H 03FFFFH Area 060000H 07FFFFH
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
PACKAGE DRAWING
100-PIN PLASTIC (14x20)
detail lead
NOTE Each lead centerline located within 0.15 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 23.6±0.4 20.0±0.2 14.0±0.2 17.6±0.4 0.30±0.10 0.15 0.65 (T.P.) 1.8±0.2 0.8±0.2 0.15+0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX.
P100GF-65-3BA1-4
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
RECOMMENDED SOLDERING CONDITIONS
µPD703032A, 703032AY, 70F3032A, 70F3032AY should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Table 5-1. Surface Mounting Type Soldering Conditions (1/2)
100-pin plastic 100-pin plastic
Soldering Conditions Recommended Condition Symbol IR35-207-2
Soldering Method
Infrared reflow
Package peak temperature: Time: seconds max. higher), Count: times less Exposure limit: daysNote (after that, prebake hours) Package peak temperature: Time: seconds higher), Count: times less Exposure limit: daysNote (after that, prebake hours) Solder bath temperature: max., Time: seconds max., Count: Once Preheating temperature: max. (package surface temperature) Exposure limit: daysNote (after that, prebake hours) temperature: max., Time: seconds max. (per row)
VP15-207-2
Wave soldering
WS60-207-1
Partial heating
Note After opening pack, store less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Table 5-1. Surface Mounting Type Soldering Conditions (2/2)
µPD70F3032AGF-3BA:
100-pin plastic
µPD70F3032AYGF-3BA: 100-pin plastic
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-203-2
Infrared reflow
Package peak temperature: Time: seconds max. higher), Count: times less Exposure limit: daysNote (after that, prebake hours) Package peak temperature: Time: seconds higher), Count: times less Exposure limit: daysNote (after that, prebake hours) Solder bath temperature: max., Time: seconds max., Count: once Preheating temperature: max. (package surface temperature) Exposure limit: daysNote (after that, prebake hours) temperature: max., Time: seconds max. (per row)
VP15-203-2
Wave soldering
WS60-203-1
Partial heating
Note After opening pack, store less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
APPENDIX NOTES TARGET SYSTEM DESIGN
following shows diagram connection conditions between in-circuit emulator option board conversion connector. Design your system making allowances conditions such form parts mounted target system shown below. Appendix-1. 100-pin Plastic
Side view
In-circuit emulator IE-703002-MC In-circuit emulator option board IE-703037-MC-EM1
Note
Conversion connector NEXB-100-SD/RB YQGUIDE YQPACK100RB NQPACK100RB
Target system
Note YQSOCKET100SDN (included with IE-703002-MC) this portion adjusting height (height: mm). view
IE-703002-MC
NEXB-100-SD/RB
Target system
position
IE-703037-MC-EM1
YQPACK100RB, NQPACK100RB, YQGUIDE
Connection condition diagram
IE-703037-MC-EM1 Connect IE-703002-MC. position
NEXB-100-SD/RB
YQPACK100RB NQPACK100RB
33.2
18.5
Target system
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Caution
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
Related document µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Data Sheet (U14734E) related documents this publication include preliminary versions. However, preliminary versions marked such. V850/SB1, V850/SB2, V850 Series trademarks Corporation.
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (France) S.A.
France Tel: 01-3067-58-00 Fax: 01-3067-58-99
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (France) S.A.
Madrid, Spain Tel: 091-504-27-87 Fax: 091-504-28-60
Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Branch Netherlands
Electronics Italiana S.R.L.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
Eindhoven, Netherlands Tel: 040-244 Fax: 040-244
Branch Sweden
Electronics Taiwan Ltd. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.12
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
[MEMO]
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
[MEMO]
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
[MEMO]
Data Sheet U14893EJ2V0DS
µPD703032A, 703032AY, 70F3032A, 70F3032AY
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative.
License needed: µPD70F3032A, 70F3032AY customer must judge need license: µPD703032A, 703032AY
information this document current November, 2001. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

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