uPD62A

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uPD62A - uPD62A

April 1st, 2010 Renesas Electronics Corporation
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DATA SHEET
INTEGRATED CIRCUIT
µPD62A
4-BIT SINGLE-CHIP MICROCONTROLLER INFRARED REMOTE CONTROL TRANSMISSION
DESCRIPTION
low-voltage operation, on-chip carrier generator infrared remote control transmission, standby release function through entry, programmable timer, µPD62A ideal infrared remote control transmitters. µPD62A, one-time PROM product µPD6P4B been made available program evaluation small-scale production.
FEATURES
Program memory (ROM): bits Data memory (RAM): bits On-chip carrier generator infrared remote control 9-bit programmable timer: channel Command execution time: (when operating MHz: ceramic oscillation) Stack levels: pins (KI/O): Input pins (KI): Sense input (S0) S1/LED (I/O): Power supply voltage: Oscillator frequency: When output mode, this remote control transmission display pin. (Stack also available data memory RF.)
Operating ambient temperature: +85°C (Power Clear) circuit (Mask option)
APPLICATION
Infrared remote control transmitter (for household electrical appliances)
information this document subject change without notice. Before using this document, please confirm that this latest version. devices/types available every country. Please check with local representative availability additional information. Document U14474EJ2V0DS00 (2nd edition) Date Published August 2000 CP(K) Printed Japan
mark
shows major revised points.
1999
µPD62A
ORDERING INFORMATION
Part Number Package 20-pin plastic SSOP (7.62 (300))
Remark indicates code suffix.
CONFIGURATION (TOP VIEW)
20-pin Plastic SSOP (7.62 (300))
KI/O6 KI/O7 S1/LED XOUT RESET
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0
Caution order KI/O numbers reverse that µPD6600A 6124A.
Data Sheet U14474EJ2V0DS00
µPD62A
BLOCK DIAGRAM
Carrier generator core S1/LED 9-bit timer Port KI/O KI/O0-KI/O7 Port KI0-KI3
Port
S1/LED
RESET System control XOUT
LIST FUNCTIONS
Item capacity bits Mask capacity Stack pins bits level (RAM also used input (KI): I/O): extended input (S0, S1): Remote control transmission display output (LED): (alternately functions pin)
µPD62A
1002 bits
µPD6P4B
One-time PROM
Number keys
keys keys (when extended extension input) keys (when extended extension input diode) Ceramic oscillation MHzNote
Clock frequency
Instruction execution time Carrier frequency Timer circuit Supply voltage Operating ambient temperature Package
MHz) fX/8, fX/16, fX/64, fX/96, fX/128, X/192, carrier (high level) 9-bit programmable timer: channel Mask option +85°C 20-pin plastic SSOP (7.62 (300)) Internal MHz) MHz) +85°C +70°C (with circuit) 20-pin plastic (7.62 (300)) 20-pin plastic SSOP (7.62 (300))
Note When supply voltage less than necessary design application circuit make RESET level.
Data Sheet U14474EJ2V0DS00
µPD62A
TABLE CONTENTS FUNCTIONS
List Functions Input/Output Circuits Recommended Connection Unused Pins
INTERNAL FUNCTIONS
Program Counter (PC) Stack Pointer (SP) Address Stack Register (ASR (RF))
Program Memory (ROM) Data Memory (RAM) Data Pointer (DP) Accumulator Arithmetic Logic Unit (ALU) Flags 2.9.1 2.9.2 Status flag Carry flag (CY)
PORT REGISTERS (PX)
KI/O Port (P0) Port/Special Ports (P1) 3.2.1 3.2.2 3.2.3 port (P11: bits port (bit
S1/LED (bit Control Register (P3)
Control Register (P4)
TIMER
Timer Configuration Timer Operation Carrier Output Software Control Timer Output
STANDBY FUNCTION
Outline Standby Function Standby Mode Setting Release Standby Mode Release Timing
RESET CIRCUIT (MASK OPTION)
Functions Circuit Oscillation Check Supply Voltage
SYSTEM CLOCK OSCILLATOR
Data Sheet U14474EJ2V0DS00
µPD62A
INSTRUCTION
Machine Language Output Assembler Circuit Symbol Description Mnemonic to/from Machine Language (Assembler Output) Contrast Table Accumulator Operation Instructions Input/Output Instructions Data Transfer Instruction Branch Instructions Subroutine Instructions
Timer Operation Instructions 9.10 Others
ASSEMBLER RESERVED WORDS
10.1 Mask Option Directives 10.1.1 OPTION ENDOP directives 10.1.2 Mask option definition directive
ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES (REFERENCE VALUES) APPLICATION CIRCUIT EXAMPLE PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX FUNCTIONAL COMPARISON BETWEEN µPD62A OTHER PRODUCTS APPENDIX EXAMPLE REMOTE-CONTROL TRANSMISSION FORMAT
Data Sheet U14474EJ2V0DS00
µPD62A
FUNCTIONS List Functions
Symbol Function Output Format CMOS push-pullNote After Reset High-level output
KI/O0 KI/O7 8-bit input/output port Input/output specified 8-bit units. input mode, pull-down resistor added. output mode, these pins used scan output matrix. Input port also used return input matrix. input mode, pull-down resistor ports specified software 2-bit units. input mode canceled software, this placed mode enters high-impedance state. Input/output port input mode (S1), this also used return input matrix. pull-down resistor ports specified software 2-bit units. output mode (LED), becomes remote control transmission display output (active low). When remote control carrier output from output, this outputs level from output synchronously with signal. Infrared remote control transmission output. output active high. Carrier frequency: fX/8, fX/64, fX/96, high-level, fX/16, fX/128, fX/192 (software supporting) Power supply These pins connected system clock ceramic resonators. Ground Normally, this system reset input. inputting level, reset. When resetting with circuit (mask option) level output. pull-up resistor connected this pin.
High-impedance (OFF mode)
S1/LED
CMOS push-pull
High-level output (LED)
CMOS push-pull
Low-level output
XOUT RESET
level (oscillation stopped)
I3Note 4-bit input port These pins used return input matrix. pull-down resistor specified software 4-bit units.
Input (low-level)
Notes aware that drive capability low-level output side held low. order prevent malfunction, input high level pins (these pins left open) when reset released (when RESET changes from level high level, released supply voltage startup).
Data Sheet U14474EJ2V0DS00
µPD62A
Input/Output Circuits
input/output circuits µPD62A pins shown partially simplified forms below. I/O0 I/O7
Data Output latch
Input buffer
P-ch
mode
Output disable
Selector
N-chNote
Standby release Pull-down flag N-ch
Input buffer
N-ch
S1/LED Note drive capability held low.
Standby release Input buffer
output latch
P-ch
Output disable Standby release Input buffer
N-ch
Pull-down flag
N-ch
Pull-down flag
N-ch
RESET
P-ch
P-ch Data Output latch N-ch
Carrier generator
Input buffer Internal reset signal other than N-ch
circuit
Mask option
Data Sheet U14474EJ2V0DS00
µPD62A
Recommended Connection Unused Pins
following connections recommended unused pins. Table 1-1. Connections Unused Pins
Connection Inside Microcontroller KI/O Input mode Output mode S1/LED RESETNote High-level output Output mode (LED) setting mode setting On-chip circuit Directly connect these pins Leave open Outside Microcontroller Leave open
Note application circuits requiring high reliability, sure design that RESET signal input externally. Caution recommended that mode terminal output level fixed repeating settings each loop program.
Data Sheet U14474EJ2V0DS00
µPD62A
INTERNAL FUNCTIONS Program Counter (PC): Bits
This binary counter that holds address information program memory. Figure 2-1. Program Counter Configuration
program counter contains address instruction that should executed next. Normally, counter contents automatically incremented accordance with instruction length (byte count) each time instruction executed. However, when executing JUMP instructions (JMP, JNC, JNF), program counter contains jump destination address written operand. When executing subroutine call instruction (CALL), call destination address written operand entered after contents time saved address stack register (ASR). return instruction (RET) executed after CALL instruction executed, address saved restored When reset, value program counter becomes "000H".
Stack Pointer (SP):
This 1-bit register which holds status address stack register. stack pointer contents incremented when call instruction (CALL) executed; they decremented when return instruction (RET) executed. When reset, stack pointer contents cleared When stack pointer overflows (stack level more) underflows, hung system reset signal generated, becomes "000H". instruction available value directly stack pointer, possible operate pointer means program.
Address Stack Register (ASR (RF)): Bits
address stack register saves return address program after subroutine call instruction executed. low-order bits configured that also used data memory register holds value even after executed. When reset, holds previous data (undefined power application). Caution accessed data memory, high-order bits become undefined. Figure 2-2. Address Stack Register Configuration
ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 ASR2 ASR1 ASR0
Data Sheet U14474EJ2V0DS00
µPD62A
Program Memory (ROM): steps bits
consists bits step, addressed program counter. program memory stores programs table data, etc. steps from 3EAH 3FFH cannot used test program area. Figure 2-3. Program Memory
bits 000H
0FFH 100H
1FFH 200H
Unmounted areaNote
3E9H 3EAH 3FFH
Test program areaNote
Note unmounted area test program area designed that program data placed either them mistake returned 000H address.
Data Memory (RAM): Bits
data memory, which static consisting bits, used retain processed data. data memory sometimes processed 8-bit units. used data pointer. also used ASR. When reset, cleared "00H" retain previous data (undefined upon power application).
Data Sheet U14474EJ2V0DS00
µPD62A
Figure 2-4. Data Memory Configuration
(high-order bits) (low-order bits) (refer Data Pointer (DP)) (refer Address Stack Register (ASR (RF)))
Data Pointer (DP): Bits
data table referenced setting address data pointer call contents. low-order bits address specified data memory; high-order bits bits register (CR0). When reset, pointer contents become "000H". Figure 2-5. Data Pointer Configuration
register
Accumulator (A): Bits
accumulator, which register consisting bits, plays leading role performing various operations. When reset, accumulator contents become undefined. Figure 2-6. Accumulator Configuration
Data Sheet U14474EJ2V0DS00
µPD62A
Arithmetic Logic Unit (ALU): Bits
arithmetic logic unit (ALU), which arithmetic circuit consisting bits, executes simple manipulations with priority given logical operations.
Flags
2.9.1 Status flag timer statuses checked executing STTS instruction check status flag. status flag following cases. condition specified with operand when STTS instruction been executed When standby mode canceled. When cancelation condition point executing HALT instruction. this case, system placed standby mode.) Conversely, status flag cleared following cases: condition specified with operand when STTS instruction been executed. When status flag been HALT instruction executed, cancelation condition point executing HALT instruction. this case, system placed standby mode.) Table 2-1. Conditions Status Flag STTS Instruction
Operand Value STTS Instruction High level input least pins. High level input least pins. High level input least pins. down counter timer [The following condition added addition above.] High level input least pinsNote.
Condition Status Flag
combination above.
Note pins must input mode (set resister respectively).
Data Sheet U14474EJ2V0DS00
µPD62A
2.9.2 Carry flag (CY) carry flag following cases: instruction instruction executed when accumulator operand "1". instruction instruction executed when accumulator "1". instruction SCAF instruction executed when value accumulator 0FH. carry flag cleared following cases: instruction instruction executed when least either accumulator operand "0". instruction instruction executed when accumulator "0". instruction SCAF instruction executed when value accumulator other than 0FH. instruction executed. When data written accumulator instruction instruction.
Data Sheet U14474EJ2V0DS00
µPD62A
PORT REGISTERS (PX)
KI/O port, port, special ports (S0, S1/LED), control registers treated port registers. port register values after reset shown below. Figure 3-1. Port Register Configuration
Port Register KI/O7 KI/O6 KI/O5 KI/O4 S1/LED TCTL CARY MOD1 MOD0
S1/LED mode KI/O mode
After Reset
KI/O3
KI/O2
KI/O1
KI/O0 FHNote
(Control register
(Control register S0/S1 pull-down pull-down
mode
Note
Refers value based status. Table 3-1. Relationship Between Ports Read/Write
Input Mode Read KI/O S1/LED status status status status Write Output latch Note status Output Mode Read Output latch Write Output latch
Port Name
Note When mode, normally read.
Data Sheet U14474EJ2V0DS00
µPD62A
Port (P0)
KI/O port 8-bit input/output port scan output. Input/output mode register. read instruction executed, state read input mode, whereas output latch contents read output mode. write instruction executed, data written output latch regardless input output mode. When reset, port placed output mode; value output latch (P0) becomes 1111 1111B. KI/O port includes pull-down resistor, allowing pull-down input mode only. Caution double-pressed, high-level output low-level output coincide KI/O port. avoid this, low-level output current KI/O port held low. Therefore, careful when using KI/O port purposes other than scan output. KI/O port designed that, even when connected directly VDD, within normal supply voltage range (VDD problem occur. Table 3-2. KI/O Port (P0)
Name KI/O7 KI/O6 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0
Read: Write:
input mode, KI/O pin's state read. output mode, KI/O pin's output latch contents read. Data written KI/O pin's output latch regardless input output mode.
Data Sheet U14474EJ2V0DS00
µPD62A
Port/Special Ports (P1)
3.2.1 port bits port 4-bit input port entry. status read this port. Software used whether connect pull-down resistor port 4-bit units means register. When reset, pull-down resistor connected. Table 3-3. KI/Special Port Register (P1)
Name S1/LED
(Fixed
input mode, status read (Read only). mode, this fixed status S1/LED read regardless input/output mode (Read only). status read (Read only).
Caution order prevent malfunction, sure input level more than pins when reset released (when RESET changes from level high level, released supply voltage startup). 3.2.2 port (bit port input/OFF mode port. status read setting this port input mode with register. input mode, software used whether connect pull-down resistor S1/LED ports 2-bit units means register. input mode canceled (set mode), becomes high-impedance, through current stopped from flowing internally. mode, read regardless status. When reset, this port mode becomes high-impedance. 3.2.3 1/LED (bit S1/LED port input/output port. This port input output mode means register. status read both input output mode. input mode, software used whether connect pull-down resistor /LED ports 2-bit units means register. output mode, pull-down resistor automatically disconnected, this port becomes remote control transmission display (refer TIMER). When reset, this port placed output mode, high level output.
Data Sheet U14474EJ2V0DS00
µPD62A
Control Register (P3)
Control register consists bits. contents that controlled shown below. When reset, this register becomes 0000 0011B. Table 3-4. Control Register (P3)
Name CARY MOD1 MOD0
(Data pointer) TCTL
value After reset
Fixed
Fixed
Refer Table 3-5.
These bits specify carrier frequency duty ratio output. This specifies availability carrier frequency specified (with carrier); (without carrier; high level) This changes carrier frequency timer clock's frequency division ratio. (carrier frequency: specified value timer clock: fX/64) (carrier frequency: half specified value timer clock: fX/128) Table 3-5. Timer Clock Carrier Frequency Settings
fX/128 Timer Clock fX/64 Carrier Frequency (Duty Ratio) fX/8 (Duty 1/2) fX/64 (Duty 1/2) fX/96 (Duty 1/2) fX/96 (Duty 1/3) Without carrier (high level) fX/16 (Duty 1/2) fX/128 (Duty 1/2) fX/192 (Duty 1/2) fX/192 (Duty 1/3) Without carrier (high level)
These bits specify high-order bits (DP8 DP9) data pointer. Remark don't care
Data Sheet U14474EJ2V0DS00
µPD62A
Control Register (P4)
Control register consists bits. contents that controlled shown below. When reset, this register becomes 0010 0110B. Table 3-6. Control Register (P4)
Name S0/S1 S1/LED mode Fixed KI/O mode mode
Pull-down Pull-down value After reset Fixed Fixed
Specifies input mode port. mode (high impedance); (input mode). Specifies mode KI/O port. (input mode); (output mode). Specifies mode S1/LED port. (input mode); (output mode). Specifies connection pull-down resistor S0/S1 port input mode. (not connected); (connected) Specifies connections pull-down resistor port. (not connected); (connected). Remark output mode mode, pull-down resistors automatically disconnected.
Data Sheet U14474EJ2V0DS00
µPD62A
TIMER Timer Configuration
timer block used creating remote control transmission pattern. shown Figure 4-1, consists 9-bit down counter t0), flag (t9) enabling 1-bit timer output, zero-detection circuit. Figure 4-1. Timer Configuration
9-bit down counter
control register (P3)
Selector
Count clock
fX/64 fX/128
S1/LED
Carrier synchronous circuit
Timer operation signal (HALT release signal) Zero-detection circuit
control register (P3) Carrier signal
Data Sheet U14474EJ2V0DS00
µPD62A
Timer Operation
timer starts (counting down) when value other than down counter with timer operation instruction. timer operation instructions making timer start operation shown below: #data10 down counter decremented (-1) cycle 64/fX 128/fXNote. value down counter becomes zero-detection circuit generates timer operation signal stop timer operation. this time, timer HALT mode (HALT waiting timer stop operation, HALT mode canceled instruction following HALT instruction executed. output timer operation signal continued while down counter timer stopped. There following relational expression between timer's time down counter's value. Timer time (Set value 64/fX 128/fXNote) Note This becomes 128/fX control register setting flag (t9) which enables timer output, timer output operation status from S1/LED pin. also output carrier while timer operation. Table 4-1. Timer Output
1/LED Timer operating Timer halting carrier outputNote)
Note carrier output results control register cleared Figure 4-2. Timer Output (When Carrier Output)
Timer value: (set value 64/fX 128/fX)
Data Sheet U14474EJ2V0DS00
µPD62A
Carrier Output
carrier remote-controlled transmission output from clearing control register shown Figure 4-3, case where timer stops when carrier high level, carrier continues output until next fall then stops function carrier synchronous circuit. When timer starts operation, however, high-level width first carrier shorter than specified width. Figure 4-3. Timer Output (When Carrier Output)
Timer value: (Set value+1) 64/fX 128/fX)
low-level start) Note high-level start)
Note
Notes Error when output ends: Lead "the carrier's low-level width" "the carrier's highlevel width" Error carrier's high-level width: "the carrier's high-level width"
Software Control Timer Output
timer output controlled software. shown Figure 4-4, pulse with minimum width 1instruction cycle (64/fX) output. Figure 4-4. Pulse Output 1-Instruction Cycle Width #0000000000B; low-level output from #1000000000B; high-level output from #0000000000B; low-level output from
64/fX
Data Sheet U14474EJ2V0DS00
µPD62A
STANDBY FUNCTION Outline Standby Function
save current consumption, types standby modes, HALT mode STOP mode, made available. STOP mode, system clock stops oscillation. this time, XOUT pins fixed level. HALT mode, operation halts, while system clock continues oscillating. When HALT mode, timer (including output output) operates. either STOP mode HALT mode, statuses data memory, accumulator, port register, etc. immediately before standby mode retained. Therefore, make sure port status system that current consumption whole system suppressed before standby mode set. Table 5-1. Statuses During Standby Mode
STOP Mode Setting instruction Clock oscillation circuit Data memory Operation statuses Accumulator Flag Port register Timer HALT instruction Oscillation stopped Operation halted Immediately preceding status retained Immediately preceding status retained (When flag placed standby mode.) Immediately preceding status retained Immediately preceding status retained Operation halted Operable (The count value reset "0") Oscillation continues HALT Mode
Cautions Write instruction first instruction after STOP mode canceled. When standby mode canceled, status flag point standby mode been set, cancelation condition met, then system placed standby mode. However, status flag (1).
Data Sheet U14474EJ2V0DS00
µPD62A
Standby Mode Setting Release
standby mode with HALT #b3b 2b1b instruction both STOP mode HALT mode. standby mode set, status flag required have been cleared standby mode released release condition specified reset (RESET input, POC) HALT instruction operand. standby mode released, status flag Even when HALT instruction executed state which status flag been standby mode set. release condition this time, status flag cleared release condition met, status flag remains Even case when release condition already been point that HALT instruction executed, standby mode set. Here, also, status flag Caution Depending status status flag (F), HALT instruction executed. careful about this. example, when setting HALT mode after checking status with STTS instruction, because system does enter HALT mode long status flag remains sometimes unintended operation performed. this case, intended operation realized executing STTS instruction immediately after timer setting clear status flag. Example STTS STTS HALT #03H #0xxH #05H #05H check status. timer clear status flag HALT mode
(During this time, sure execute instruction that status flag.)
Table 5-2. Addresses Executed After Standby Mode Release
Release Condition Reset Release condition shown Table Address Executed After Release address address following HALT instruction
Data Sheet U14474EJ2V0DS00
µPD62A
Table 5-3. Standby Mode Settings (HALT #b3b2b1b0B) Release Conditions
Operand Value HALT Instruction STOP STOP STOPNote STOP KI/O pins high-level output. KI/O pins high-level output. KI/O0 high-level output. High level input least pins. High level input least pins. High level input least pins.
Setting Mode
Setting Precondition
Release Condition
combination b2b1b0 above
[The following condition added addition above.] High level input least pins Note
HALT
When timer's down counter
Notes When setting HALT configure matrix using KI/O0 that internal reset takes effect time program hang-up. least pins (the used releasing standby) must input mode. (Note that internal reset does take effect even when both pins output mode.) Cautions internal reset takes effect when HALT instruction executed with operand value other than that above when precondition been satisfied when executing HALT instruction. STOP mode when timer's down counter (timer operating), system placed STOP mode only after bits timer's down counter timer output permit flag cleared Write instruction first instruction after STOP mode released.
Standby Mode Release Timing
STOP mode release timing Figure 5-1. STOP Mode Cancelation Release Condition
Wait (52/fX
HALT instruction (STOP mode) Standby release signal Operating mode STOP mode Oscillation stopped
HALT mode
Operating mode
Oscillation Clock
Oscillation Oscillation growth time
Caution When release condition established STOP mode, device released from STOP mode, goes into wait state. this time, release condition held, device goes into STOP mode again after wait time elapsed. Therefore, when releasing STOP mode, necessary hold release condition longer than wait time.
Data Sheet U14474EJ2V0DS00
µPD62A
Figure 5-2. STOP Mode Release RESET Input
HALT instruction (STOP mode) RESET Operating mode STOP mode Reset
Wait (246 694)/fX
address start
HALT mode
Operating mode
Oscillation Clock
Oscillation stopped
Oscillation Oscillation growth time
HALT mode release timing Figure 5-3. HALT Mode Release Cancelation Condition
Standby release signal
HALT instruction (HALT mode) Operating mode
HALT mode
Operating mode
Oscillation Clock
Figure 5-4. HALT Mode Release RESET Input
HALT instruction (HALT mode) RESET Operating mode HALT mode Reset Oscillation stopped
Wait (246 694)/fX
address start
HALT mode
Operating mode
Oscillation Clock
Oscillation Oscillation growth time
Data Sheet U14474EJ2V0DS00
µPD62A
RESET
system reset takes effect inputting level RESET pin. While RESET level, system clock oscillator stopped XOUT pins fixed GND. RESET raised from level high level, executes program from address after counting system clock (fX). Figure 6-1. Reset Operation RESET Input
Wait (246 694)/fX RESET Operating mode standby mode Oscillation stopped HALT mode
address start
Operating mode
Oscillation growth time
RESET outputs level when circuit (mask option) operation. Caution When connecting reset RESET pin, sure connect N-ch open drain output type. Table 6-1. Hardware Statuses After Reset
RESET Input During Operation RESET Input Standby Mode Reset Internal Circuit During Operation Reset Internal Circuit Standby Reset Other Factors Note Mode 000H R1-RF 000H Undefined Undefined 000H Control register Previous status retained
Hardware bits) bit) Data memory
Accumulator Status flag Carry flag (CY) Timer bits) Port register
Notes following resets available. Reset when executing HALT instruction (when operand value illegal does satisfy precondition) Reset when executing instruction (when Reset stack pointer's overflow underflow Refers value based status. order prevent malfunction, sure input level more than pins when reset released (when RESET changes from level high level, released supply voltage startup).
Data Sheet U14474EJ2V0DS00
µPD62A
CIRCUIT (MASK OPTION)
circuit monitors power supply voltage applies internal reset microcontroller when battery replaced, etc. application circuit satisfies following conditions, circuit incorporated mask option. High reliability required. Clock frequency Operating ambient temperature +85°C Cautions one-time PROM product (µPD6P4B) already contains circuit. There cases which circuit cannot detect power supply voltage less than Therefore, power supply voltage become period less than circuit malfunction because does generate internal reset signal. Clock oscillation stopped resonator power supply voltage before circuit generates internal reset signal. this case, malfunction result, example when power supply voltage recovered after oscillation stopped. This type phenomenon takes place because circuit does generate internal reset signal (because power supply voltage recovers before power supply voltage detected) even though clock stopped. chance, malfunction taken place, remove battery short time back. most cases, normal operation will resumed. application circuit does satisfy conditions above, design application circuit that reset takes effect without failure within power supply voltage range means external reset circuit. order prevent malfunction, sure input level more than pins when reset released (when RESET changes from level high level, released supply voltage startup). Remarks recommended that circuit incorporated when application circuit infrared remote-control transmitter household appliances. Even when circuit incorporated, externally input RESET valid with condition; therefore, circuit RESET input used same time. However, circuit detects power supply voltage, RESET will forced level; therefore, N-ch open drain output open collector output external reset circuit.
Data Sheet U14474EJ2V0DS00
µPD62A
Functions Circuit
circuit following functions: Generating internal reset signal when VPOC. Canceling internal reset signal when VPOC. Here, VDD: power supply voltage, VPOC: POC-detected voltage.
Clock frequency VPOC (approx.) POC-detected voltage VPOC 1.85 (TYP.)Note Operating ambient temperature +85°C
Internal reset signal Note Operating mode Reset Note
Reset
Notes reality, oscillation stabilization wait time must elapse before circuit switched operating mode. oscillation stabilization wait time about 246/fX 694/fX (about when 3.64 MHz). circuit generate internal reset signal when power supply voltage fallen, necessary power supply voltage kept less than VPOC period more. Therefore, reality, there time until reset takes effect. POC-detected voltage (VPOC) varies between about thus, reset canceled power supply voltage smaller than assured range (VDD However, long conditions operating circuit met, actual lowest operating power supply voltage becomes lower than POC-detected voltage. Therefore, there malfunction occurring shortage power supply voltage. However, malfunction such reasons clock oscillating power supply voltage occur (refer Caution CIRCUIT).
Oscillation Check Supply Voltage
reliable reset operation expected circuit satisfies condition that clock oscillate even power supply voltage (the oscillation start voltage resonator being even lower than POCdetected voltage). Whether this condition checked measuring oscillation status product which actually contains circuit, follows. Connect storage oscilloscope that oscillation status measured. Connect power supply whose output voltage varied then gradually raise power supply voltage from (making sure avoid first (during (approx.)), XOUT regardless VDD. However, point that reaches POC-detected voltage (VPOC 1.85 (TYP.)), voltage XOUT jumps about VDD. Maintain this power supply voltage while measure waveform XOUT pin. chance, oscillation start voltage resonator lower than POC-detected voltage, growing oscillation XOUT confirmed within several after reached VPOC.
Data Sheet U14474EJ2V0DS00
µPD62A
SYSTEM CLOCK OSCILLATOR
system clock oscillator configuration consists ceramic resonator oscillation circuit MHz). Figure 8-1. System Clock
PD62A
XOUT
Ceramic resonator
system clock oscillator stops oscillation when reset STOP mode. Caution When using system clock oscillator, wire follows area enclosed broken lines above figure avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wire near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential ground. ground capacitor ground pattern through which high current flows. fetch signals from oscillator.
Data Sheet U14474EJ2V0DS00
µPD62A
INSTRUCTION Machine Language Output Assembler
length machine language this product bits word. However, machine language that output assembler extended bits word. shown example below, extension made inserting 3-bit extended bits (111) locations. Figure 9-1. Example Assembler Output Bits Extended Bits) case "ANL @R0H"
FAF0
Extended bits
Extended bits
case "OUT #data8"
E6F8
Extended bits
Extended bits
Data Sheet U14474EJ2V0DS00
µPD62A
Circuit Symbol Description
ASR: addr: data4: data8: data10: P0n: P1n: ROMn: R0n: R1n: Accumulator Address Stack Register Program memory address Carry flag 4-bit immediate data 8-bit immediate data 10-bit immediate data Status flag Program Counter Port register pair Port register (low-order bits) Port register (high-order bits) program memory's Register pair Data memory (General-purpose register; Data memory (General-purpose register; Stack Pointer Timer register Timer register (low-order bits) Timer register (high-order bits) Content addressed with
Data Sheet U14474EJ2V0DS00
µPD62A
Mnemonic to/from Machine Language (Assembler Output) Contrast Table
Accumulator Operation Instructions
Instruction Code Word @R0H FBEn FAEn FAF0 Word Word Rmn3 ROM7 @R0L FBF0 ROM3 #data4 FBF1 data4 data43 @R0H FDEn FCEn FCF0 (Rmn) ((P13), (R0))7-4 @R0L FDF0 ((P13), (R0))3-0 #data4 FDF1 data4 data4 @R0H F5En F4En F4F0 (Rmn) Rmn3 ((P13), (R0))7-4 ROM7 @R0L F5F0 ((P13), (R0))3-0 ROM3 #data4 F5F1 data4 data4 data43 F4F3 else FCF3 (An+1) (A3) FEF3 reset else (An+1) (An), (A0)
Mnemonic
Operand
Operation (Rmn)
Instruction Length
Instruction Cycle
Data Sheet U14474EJ2V0DS00
((P13), (R0))7-4
((P13), (R0))
data4
µPD62A
Input/output Instructions
Instruction Code Word P0n, P1n, FFF8 FEF8 E5F8 E4F8 FBF8 FAF8 FDF8 FCF8 F5F8 F4F8 Word Word Pmn3 (Pmn) (Pmn) Pmn3 Instruction Length (Pn) data8 Instruction Cycle (Pmn) (Pmn) Instruction Length Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic
Operand
Instruction Code Word Word data8 Word
#data8 E6F8
Remark
dealt with pairs.
Data Transfer Instruction
Instruction Code Word @R0H FFEn FEEn FEF0 Word Word (Rmn) ((P13), (R0))7-4 @R0L FFF0 ((P13), (R0))3-0 #data4 R0n, R1n, FFF1 E5En E4En data4 data4 (Rmn) Instruction Length Instruction Cycle
Mnemonic
Operand
Mnemonic
Operand #data8 E6En E7En
Instruction Code Word Word data8 Word
(R1n-R0n) data8
(R1n-R0n) ((P13), (R0))
Remark
dealt with pairs.
Data Sheet U14474EJ2V0DS00
(Pmn)
Operation
Operation
Operation
Instruction Length
Instruction Cycle
µPD62A
Branch Instructions
Instruction Code Word addr (Page E8F1 addr (Page E9F1 addr (Page ECF1 addr (Page EAF1 addr (Page EDF1 addr (Page EBF1 addr (Page EEF1 addr (Page F0F1 addr (Page EFF1 addr (Page F1F1 Word addr addr addr addr addr addr addr addr addr addr addr addr addr addr else else else else Word addr Instruction Length Instruction Cycle
Mnemonic
Operand
Operation
Caution which refer PAGE0 written when describing mnemonics. Subroutine Instructions
Instruction Code Word CALL addr (Page E6F2 addr (Page E6F2 E8F2 Word E8F1 E9F1 Word addr addr ASR, addr Instruction Length Instruction Cycle
Mnemonic
Operand
Operation
Caution which refer PAGE0 written when describing mnemonics. Timer Operation Instructions
Instruction Code Word FFFF FEFF E5FF F4FF Word Word (Tn) (Tn) Instruction Code Word #data10 E6FF F4FF Word data10 Word data10 ((P13), (R0)) Instruction Length Instruction Cycle Instruction Length Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic
Operand
Operation
Data Sheet U14474EJ2V0DS00
µPD62A
Others
Instruction Code Word HALT STTS #data4 #data4 E2F1 E3F1 Word data4 data4 Word Standby mode statuses match else E3En Instruction Length Instruction Cycle
Mnemonic
Operand
Operation
statuses match else
SCAF
FAF3
else
E0E0
Data Sheet U14474EJ2V0DS00
µPD62A
Accumulator Operation Instructions
Instruction code: Cycle count: Function:
Rmn3
(Rmn)
accumulator contents register contents ANDed results entered accumulator. @R0H @R0L Instruction code: Cycle count: Function:
((P13), (R0)) case @R0H) ((P13), (R0)) case @R0L)
accumulator contents program memory contents specified with control register register pair R10-R00 ANDed results entered accumulator. specified, take effect. specified, take effect. Program memory (ROM) organization
Valid bits time accumulator operation
#data4 Instruction code: Cycle count: Function:
data4 data43
accumulator contents immediate data ANDed results entered accumulator.
Data Sheet U14474EJ2V0DS00
µPD62A
Instruction code: Cycle count: Function:
(Rmn)
accumulator contents register contents ORed results entered accumulator. @R0H @R0L Instruction code: Cycle count: Function:
(P13), (R0))7-4 case @R0H) (P13), (R0))3-0 case @R0L)
accumulator contents program memory contents specified with control register register pair R10-R00 ORed results entered accumulator. specified, take effect. specified, take effect. #data4 Instruction code: Cycle count: Function:
data4
accumulator contents immediate data exclusive-ORed results entered accumulator. Instruction code: Cycle count: Function:
(Rmn) Rmn3
accumulator contents register contents ORed results entered accumulator.
Data Sheet U14474EJ2V0DS00
µPD62A
@R0H @R0L Instruction code: Cycle count: Function:
((P13), (R0))7-4 case @R0H) ((P13), (R0))3-0 case @R0L)
accumulator contents program memory contents specified with control register register pair R10-R00 exclusive-ORed results entered accumulator. specified, take effect. specified, take effect. #data4 Instruction code: Cycle count: Function:
data4 data43
accumulator contents immediate data exclusive-ORed results entered accumulator. Instruction code: Cycle count: Function:
else
accumulator contents incremented (+1). Instruction code: Cycle count: Function:
(An), (A3)
accumulator contents rotated anticlockwise bit. Instruction code: Cycle count: Function:
reset else (An), (A3)
accumulator contents rotated anticlockwise bit. time command execution, internal reset takes effect.
Data Sheet U14474EJ2V0DS00
µPD62A
Input/Output Instructions
Instruction code: Cycle count: Function:
(Pmn)
port data loaded (read) onto accumulator. P0n, P1n, Instruction code: Cycle count: Function:
(Pmn)
accumulator contents transferred port latched. Instruction code: Cycle count: Function:
(Pmn)
accumulator contents port contents ANDed results entered accumulator. Instruction code: Cycle count: Function:
(Pmn)
accumulator contents port contents ORed results entered accumulator. Instruction code: Cycle count: Function:
(Pmn)
accumulator contents port contents exclusive-ORed results entered accumulator.
Data Sheet U14474EJ2V0DS00
µPD62A
#data8 Instruction code: Cycle count: Function:
(Pn) data8
immediate data transferred port this case, port refers P1n-P operating pairs.
Data Transfer Instruction
Instruction code: Cycle count: Function:
(Rmn)
register contents transferred accumulator. @R0H Instruction code: Cycle count: Function:
((P13), (R0))
high-order bits program memory specified with control register register pair R10-R00 transferred accumulator. ignored. @R0L Instruction code: Cycle count: Function:
((P13), (R0))
low-order bits program memory specified with control register register pair R10-R00 transferred accumulator. ignored. Program memory (ROM) contents
#data4 Instruction code: Cycle count: Function:
data4
immediate data transferred accumulator.
Data Sheet U14474EJ2V0DS00
µPD62A
R0n, R1n, Instruction code: Cycle count: Function:
(Rmn)
accumulator contents transferred register Rmn. #data8 Instruction code: Cycle count: Function: pairs. pair combinations follows: Lower column Higher column Instruction code: Cycle count: Function:
(R1n-R0n) data8
immediate data transferred register. Using this instruction, registers operate register
(R1n-R0n) ((P13), R0))
program memory contents specified with control register register pair R10-R00 transferred register pair R1n-R0n. program memory consists bits following state after transfer register.
Program memory
high-order bits program memory address specified with control register (P13).
Data Sheet U14474EJ2V0DS00
µPD62A
Branch Instructions
program memory consists pages steps (000H 3FFH). However, assembler automatically performs page optimization, unnecessary designate pages. pages allowed each product follows.
µPD62A (ROM: steps): µPD6P4B (PROM: steps)
addr Instruction code: page Cycle count: Function: a0). addr Instruction code: page Cycle count: Function: addr
page page
page
bits (PC9-0) program counter replaced directly specified address addr
page
addr
else
carry flag jump made address specified with addr a0). addr Instruction code: page Cycle count: Function: else addr
page
a1a0
carry flag cleared jump made address specified with addr addr Instruction code: page Cycle count: Function: else addr
page
status flag jump made address specified with addr a0). addr Instruction code: page Cycle count: Function: addr else
page
status flag cleared jump made address specified with addr
Data Sheet U14474EJ2V0DS00
µPD62A
Subroutine Instructions
program memory consists pages steps (000H 3FFH). However, assembler automatically performs page optimization, unnecessary designate pages. pages allowed each product follows.
µPD62A (ROM: steps):
page
µPD6P4B (PROM: steps): page
CALL addr Instruction code:
page Cycle count: Function:
page
addr
stack pointer value incremented (+1) program counter value saved address stack register. Then, address specified with operand addr entered program counter. carry generated when stack pointer value incremented (+1), internal reset takes effect. Instruction code: Cycle count: Function:
value saved address stack register restored program counter. Then, stack pointer decremented (-1) borrow generated when stack pointer value decremented (-1), internal reset takes effect.
Data Sheet U14474EJ2V0DS00
µPD62A
Timer Operation Instructions
Instruction code: Cycle count: Function:
(Tn)
timer contents transferred accumulator. corresponds (t9, t6); corresponds (t5, t2).
#data10 with
Instruction code: Cycle count: Function:
(Tn)
accumulator contents transferred timer register corresponds (t9, t6); corresponds (t5, t2). After executing this instruction, data transferred becomes data transferred becomes #data10 Instruction code: Cycle count: Function:
data10
immediate data transferred timer register (t9-t0). Remark timer time with (set value 64/f 128/fX.
Data Sheet U14474EJ2V0DS00
µPD62A
Instruction code: Cycle count: Function:
((P13), (R0))
program memory contents transferred timer register specified with control register register pair R10-R00. program memory, which consists bits, placed following state after being transferred register.
Program memory
Timer
high-order bits program memory address specified with control register (P13). Caution When setting timer value program memory, sure directive.
9.10 Others
HALT #data4 Instruction code: Cycle count: Function:
Standby mode
Places standby mode. condition having standby mode (HALT/STOP mode) canceled specified with immediate data. STTS Instruction code: Cycle count: Function:
statuses match else
KI/O TIMER statuses compared with register contents. least statuses coincides with bits that have been set, status flag none them coincide, status flag cleared
Data Sheet U14474EJ2V0DS00
µPD62A
STTS #data4 Instruction code: Cycle count: Function:
statuses match else
KI/O, TIMER statuses compared with immediate data contents. least statuses coincides with bits that have been set, status flag none them coincide, status flag cleared SCAF (Set Carry Instruction code: Cycle count: Function:
else
carry flag accumulator contents accumulator values after executing SCAF instruction follows:
Accumulator Value Before execution 0111 1111 After execution 0000 0001 0011 0111 1111 (clear) (clear) (clear) (clear) (set)
Carry Flag
Remark
don't care
Instruction code: Cycle count: Function: operation
Data Sheet U14474EJ2V0DS00
µPD62A
ASSEMBLER RESERVED WORDS 10.1 Mask Option Directives
When creating µPD62A program, necessary mask option directive assembler's source program specify mask option. 10.1.1 OPTION ENDOP directives assembler directives from OPTION directive ENDOP directive called mask option definition block. format mask option definition block follows: Format Symbol field [Label:] Mnemonic field OPTION ENDOP 10.1.2 Mask option definition directive assembler directives that used mask option definition block listed Table 10-1. example mask option definition shown below. Example Symbol field Mnemonic field OPTION USEPOC ENDOP Table 10-1. List Mask Option Definition Directives
File Address Value USEPOC (With circuit) NOUSEPOC (Without circuit) 2044H Data Value
Operand field
Comment field Comment]
Operand field
Comment field circuit incorporated
Name
Mask Option Definition Directive
Data Sheet U14474EJ2V0DS00
µPD62A
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings +25°C)
Parameter Power supply voltage Input voltage Output voltage Output current, high Symbol IOHNote Peak value Peak value KI/O Peak value Total KI/O pins Note Peak value Output current, Peak value Peak value Operating ambient temperature Storage temperature Tstg KI/O, RESET Conditions Rating -0.3 +3.8 -0.3 +0.3 -0.3 +0.3 -7.5 -13.5 +150 Unit
Note value should calculated follows: [rms value] [Peak value]
Duty.
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Power Supply Voltage Range +85°C)
Parameter Power supply voltage Symbol Conditions MIN. TYP. MAX. Unit
Data Sheet U14474EJ2V0DS00
µPD62A
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 Input voltage, VIL1 VIL2 VIL3 Input leakage current, high ILIH2 Input leakage current, ILIL1 ILIL2 ILIL3 Output voltage, high Output voltage, VOH1 VOL1 VOL2 Output current, high IOH1 IOH2 Output current, IOL1 ILIH1 RESET KI/O RESET KI/O VDD, pull-down resistor incorporated VDD, pull-down resistor incorporated KI/O -0.3 On-chip pull-up resistor On-chip pull-down resistor Data retention power supply voltage Supply currentNote VDDDR IDD1 RESET RESET KI/O STOP mode Operating mode IDD2 HALT mode MHz, MHz, MHz, MHz, IDD3 STOP mode 10%, When circuit incorporated mask option 10%, 25°C, When circuit incorporated mask option -2.5 0.75 0.65 Conditions MIN. 0.65 TYP. MAX. 0.15 Unit
REM, LED, KI/O REM, KI/O KI/O KI/O
Note current flowing on-chip pull-up resistors included.
Data Sheet U14474EJ2V0DS00
µPD62A
Characteristics +85°C,
Parameter Symbol Test Conditions MIN. When releasing standby mode RESET low-level width tRSL HALT mode STOP mode Note TYP. MAX. Unit
Instruction execution time high-level width
Note 52/fX oscillation growth time Remark 64/fX (fX: System clock oscillation frequency) Circuit (mask optionNote +85°C)
Parameter POC-detected voltageNote Symbol VPOC Test Conditions MIN. TYP. 1.85 MAX. Unit
Notes Operates effectively under conditions MHz. Refers voltage which circuit cancels internal reset. VPOC VDD, internal reset released. From time VPOC until internal reset takes effect, delay occurs. When period VPOC lasts less than internal reset take effect. System Clock Oscillator Characteristics +85°C,
Parameter Oscillation frequency (ceramic resonator) Symbol Conditions MIN. TYP. 3.64 MAX. Unit
Data Sheet U14474EJ2V0DS00
µPD62A
Recommended Ceramic Resonator +85°C)
Frequency Recommended Constant (MHz) [pF] [pF] 3.52 3.58 3.64 3.84 Unnecessary (C-containing type) Power Supply Voltage MIN. MAX.
Manufacturer
Part Number
Remark
Corp.
FCR3.52MC5 FCR3.58MC5 FCR3.64MC5 FCR3.84MC5 FCR4.0MC5 FCR6.0MC5 FCR8.0MC5
Murata Mfg. Co.,
CSA2.50MG040 CST2.50MG040
Unnecessary (C-containing type) 3.52
CSA3.52MG CST3.52MGW CSTS0352MG03 CSA3.58MG CST3.58MGW CST0358MG03 CSA3.64MG CST3.64MGW CSTS0364MG03 CSA3.84MG CST3.84MGW CST0384MG03 CSA4.00MG CST4.00MGW CSTS0400MG03 CSA6.00MG CST6.00MGW CSTS0600MG03 CSA8.00MTZ CST8.00MTW CSTS0800MG03
Unnecessary (C-containing type) 3.58
Unnecessary (C-containing type) 3.64
Unnecessary (C-containing type) 3.84
Unnecessary (C-containing type)
Unnecessary (C-containing type)
Unnecessary (C-containing type)
Unnecessary (C-containing type)
external circuit example
XOUT
Data Sheet U14474EJ2V0DS00
µPD62A
CHARACTERISTICS CURVES (REFERENCE VALUES)
MHz) 25°C) Power supply current [mA] Power supply current [mA] HALT mode Operating mode HALT mode Operating mode MHz) 25°C)
Power supply voltage
Power supply voltage
(REM, LED) 25°C, High-level output current [mA]
(REM, LED, KI/O) 25°C,
Low-level output current [mA]
Low-level output voltage
High-level output voltage
(KI/O) 25°C, Low-level output current Low-level output voltage
Data Sheet U14474EJ2V0DS00
µPD62A
APPLICATION CIRCUIT EXAMPLE
Example Application System Remote-control transmitter keys; mode selection switch accommodated)
KI/O6 KI/O7 S1/LED XOUT RESET
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 matrix keys Mode selection switch
Remote-control transmitter keys accommodated)
KI/O6 KI/O7 S1/LED XOUT RESET
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 matrix keys
Remark When circuit mask option used effectively, necessary connect capacitor enclosed broken lines.
Data Sheet U14474EJ2V0DS00
µPD62A
PACKAGE DRAWINGS
20-PIN PLASTIC SSOP (7.62 (300))
detail lead
NOTE
ITEM MILLIMETERS 6.65±0.15 0.475 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.1±0.05 1.3±0.1 8.1±0.2 6.1±0.2 1.0±0.2 0.17±0.03 0.13 0.10 0.25 0.6±0.15 S20MC-65-5A4-2
Each lead centerline located within 0.13 true position (T.P.) maximum material condition.
Remark dimensions materials model same those mass production model.
Data Sheet U14474EJ2V0DS00
µPD62A
RECOMMENDED SOLDERING CONDITIONS
µPD62A should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representatives. Table 15-1. Surface Mount Type Soldering Conditions
20-pin plastic SSOP (7.62mm (300))
Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1
Soldering Method Infrared reflow Wave soldering Partial heating
Soldering Conditions Package peak temperature: 235°C; Time: seconds max. 210°C higher); Count: Three times less Package peak temperature: 215°C; Time: seconds. max. 200°C higher); Count: Three times less Solder bath temperature: 260°C max.; Time: seconds max.; Count: once; Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C less; Time: seconds max. (per row)
Caution different soldering methods together (except partial heating).
Data Sheet U14474EJ2V0DS00
µPD62A
APPENDIX DEVELOPMENT TOOLS
emulator provided emulating µPD62A. Hardware Emulator (EB-6133, EB-69)Note Used emulate µPD62A. Note This product made Naito Densei Machida Mfg. Co., Ltd. details, contact Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). Software Assembler (AS6133) This development tool remote control transmitter software. Part Number List AS6133
Host Machine PC-9800 series (CPU: 80386 more) PC/ATand compatibles MS-DOS (Ver. Ver. 6.22) DOS(Ver. Ver. 6.3) 3.5-inch MS-DOS(Ver. Ver. 6.2) Supply Medium 3.5-inch Part Number
µS5A13AS6133 µS7B13AS6133
Caution Although Ver.5.0 later task swap function, this function cannot used with this software.
Data Sheet U14474EJ2V0DS00
µPD62A
APPENDIX FUNCTIONAL COMPARISON BETWEEN µPD62A OTHER PRODUCTS
Item capacity capacity Stack matrix extension input Clock frequency
µPD62
bits bits
µPD62A
bits
µPD64
1002 bits
µPD64A
1002 bits
µPD65
2026 bits
level (also used RAM) keys keys
Ceramic oscillation Ceramic oscillation Ceramic oscillation Ceramic oscillation (with circuit) (with circuit)
Timer
Clock Count start
fX/64, fX/128 Writing count value fX/8, fX/64, fX/96 (timer clock: /64) fX/16, fX/128, fX/192 (timer clock: X/128) carrier
Carrier
Frequency
Output start Instruction execution time "MOV @R0" instruction Standby mode Reset
Synchronized with timer MHz) RESET input,
Release condition HALT mode timer only. (HALT instruction) STOP mode only releasing (KI/O high-level output KI/O0 high-level output)
Relationship between HALT instruction execution status flag circuit
HALT instruction executed when
Mask option level output RESET detection detection voltage VPOC (TYP.) circuit only (with circuit) VPOC 1.85 (TYP.) VPOC (TYP.)
Provided Internal reset signal occurs detection VPOC 1.85 (TYP.)
Mask option Power supply voltage
provided (with circuit)
Operating ambient temperature
+85°C +85°C +85°C +85°C +70°C (with circuit) +70°C (with circuit)
Electrical specifications Recommended soldering conditions Package
Refer each product data sheet.
20-pin plastic SSOP
20-pin plastic 20-pin plastic SSOP
20-pin plastic SSOP
One-time PROM product
µPD6P4B
µPD6P5
Data Sheet U14474EJ2V0DS00
µPD62A
APPENDIX EXAMPLE REMOTE-CONTROL TRANSMISSION FORMAT (NEC transmission format command one-shot transmission mode)
Caution When using transmission format, apply custom code NEC. output waveform (From <2>, output made only when continually pressed.)
output 58.5 76.5
Remark repeatedly pressed, power consumption infrared light-emitting diode (LED) reduced sending reader code stop from second time. Enlarged waveform
output Custom code bits Custom code' bits Data code bits Data code bits Stop
13.5 Leader code
58.5 76.5
Enlarged waveform
output 13.5 0.56 1.125 2.25
Enlarged waveform
output 11.25 Leader code 2.25 0.56 Stop
Data Sheet U14474EJ2V0DS00
µPD62A
Carrier waveform (enlarged waveform each code's high period)
output 8.77 26.3 0.56 Carrier frequency
array each code
Leader code
Custom code
Custom code'
Data code
Data code
Caution prevent malfunction with other systems when receiving data transmission format, only fully decode (make sure check Data code well) total bits 16-bit custom codes (Custom code, Custom code') 16-bit data codes (Data code, Data code) also check make sure that signals exist.
Data Sheet U14474EJ2V0DS00
µPD62A
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U14474EJ2V0DS00
µPD62A
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
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Brasil S.A.
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J00.7
Data Sheet U14474EJ2V0DS00
µPD62A
MS-DOS either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademarks International Business Machines Corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document current August, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

uPD62A

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