| Fulltext Datasheet Results |
1 - 50 of about 10000+ for fifo cross |
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First line: CMTI-67202 QS7201 qs7202 cms1-67203* AM7205* FIFO FIFO Cross Reference Abstract: .. FIFO Cross Reference. AMD AMD Part-Number TEMIC Part-Number Description AM7201-25JC CMS1-67201AL-25 512x9 FIFO PLCC32 25ns LP. AM7201-25RC CM3P-67201AL-25 512x9 FIFO PDIL 28 .3 25ns LP. AM7201 .. Tags: AM7205* cms1-67203* qs7202 CMTI-67202 QS7204 QS7201-80P QS7201-50P QS7201 plcc-32 IDT7203L25J IDT7201SA80SO* IDT7201SA65TP IDT7201LA35J IDT FIFO idt cross datasheet abstract.. |
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First line: Application Note High-Bandwidth Isochronous Traffic NET2890 Document 632-0057-1401 Abstract: .. The interrupt activates when the FIFO crosses a firmware-programmable threshold in register Fn_AFTH while the FIFO is filling. When the interrupt occurs, the firmware responds by clearing .. Tags: NET2890 NET2890 |
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First line: 20Mbps packet Aeroflex Colorado Springs ERRATA ERR-SPW-004-01 Error Packet (EEP) reported properly UT200SpW4RTR SpaceWire Router Product Name: Table Cross Reference Applicable Products Manufacturer Part Number UT200SpW4RTR Device Type Internal PIC* Abstract: .. Table 1: Cross Reference of Applicable Products. Product Name: Manufacturer Part Number SMD .. EEP is not properly written into the receiving FIFO when the router is clocked at less than .. Tags: packet 20Mbps UT200SpW4RTR |
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First line: FPGA Virtex 6 fifo cross XC4VLX15-FF668-10* XC6VLX760-FF1760-1 xilinx fifo generator timing FIFO Generator v5.2 DS317 June 2009 Product Specification Xilinx LogiCORETM FIFO Generator fully verified first-in first-out (FIFO) memory queue applications requiring in-order storage retrieval. core provide Abstract: .. : Built-in FIFO. 23 C_MSGON_VAL Integer. • 0: Does not disable timing violation on cross clock domain registers • 1: Disables timing violation on cross clock domain registers. 24 C_OVERFLOW_LOW .. Tags: xilinx fifo generator timing XC6VLX760-FF1760-1 XC4VLX15-FF668-10* fifo cross xilinx logicore fifo generator 6.2 xc6slx150t The V5.2 synchronous fifo pdf FPGA Virtex 6 fifo generator xilinx datasheet spartan DS317 UG175 |
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First line: 256Kx8 tc551001 cross reference um61256* hynix hy57v281620 um61256 Cross Reference Your Memory Provider Part number µPD4218165 µPD4218165 µPD424260 µPD431000A µPD43256B µPD441000L-B µPD442000L-B µPD442012L-XB µPD444012L-B µPD4504161 28F160S Abstract: .. Cross Reference. Your Memory Provider. Part number Brand AMIC part number Description .. CY7C4205 * CYPRESS FQ215 512 x 18 FlexQ I FIFO Now! CY7C4205 * CYPRESS FQV205 256 x 18 FlexQ I FIFO .. Tags: hynix hy57v281620 256Kx8 WINBOND cross reference UPD4516161 UM62256* um61256* um611024* toshiba 32k*8 sram toshiba 256K sram tc55257 tc551001 cross reference TC551001 TC55100* AT249LV040 LP621024D BS616LV1010 BS616LV2010 BS616LV2012 BS616LV2013 BS616LV2018 BS616LV2020 BS616LV4010 BS616LV4023 BS616LV8011 BS616LV8013 BS616UV1010 BS616UV2011 BS616UV2021 BS616UV4010 BS616UV4023 BS616UV8010 CY61256 CY62126DV CY62128B CY62137CV18 |
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First line: UM611024 NX25P80 um611024* um61256* um61256 Cross Reference Your Memory Provider part number µPD4218165 µPD4218165 µPD424260 µPD431000A µPD43256B µPD441000L-B µPD442000L-B µPD442012L-XB µPD444012L-B µPD4504161 28F160S3/B3/C3 A29F002 AM29DL1 Abstract: .. Cross Reference Your Memory Provider. part number brand AMIC part number Description .. CY7C4205 * CYPRESS FQ215 512 x 18 FlexQ I FIFO Now! CY7C4205 * CYPRESS FQV205 256 x 18 FlexQ I FIFO .. Tags: NX25P80 WINBOND cross reference UM62256* um61256* um611024* toshiba 32k*8 sram toshiba 256K sram Sram serial sram siemens CROSS sharp lcd cross reference samsung ram circuit AT249LV040 LP621024D |
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First line: verilog coding for analog to digital converter testbench of a transmitter in verilog AMBA APB bus i2s specification verilog code for apb Meets Philips Inter-IC Sound Supported modes I2S-APB Abstract: .. Both FIFO buffers are equipped with appropriate cross clock domain logic. Transmitter and Receiver Dual Port RAM. The transmit RAM and Receive RAM component is a dual-port synchronous RAM 1r1w .. Tags: verilog code for apb AMBA APB bus testbench of a transmitter in verilog verilog coding for analog to digital converter philips tsmc i2s specification I2S bus specification datasheet abstract.. |
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First line: 125-Msps Using FIFOs Interface High-Speed Data Converters With TMS320 DSPs Robert Finger ABSTRACT Most high-speed data converters cannot connected directly digital signal processor (DSP). required transfer rates would most DSP's bandwidth. FIFO appropriate solution this problem because buffer large Abstract: .. crossed. This signals the DSP that space is available and the DSP can write new data to the FIFO. The interrupt polarity must be changed for the input FIFO. An interrupt should be generated when enough .. Tags: 125-Msps TMS320C6000 synchronous fifo pdf synchronous FIFO SN74V2x5 |
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First line: Evaluation Report SCMOS1/2 Radiation Tolerant Technology FIFO Family 72Kbit) Tolerance Radiation Thierry CORBIERE Abstract: .. SCMOS1/2 Radiation Tolerant Technology FIFO Family up to 72Kbit Tolerance to Radiation. by .. Flag circuitry and address pointers are less sensitive Let th at 22 MeV/ mg/cm≤ with a cross .. Tags: LINEAR Cross Reference Search cross reference 35CL datasheet abstract.. |
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First line: GMII VLAN Tag AL1032 Product Brief 12-Gigabit 10-Gigabit Switching Processor Supports 12-Gigabit ports 10-Gigabit uplink wirespeed operation, ideal Gigabit ports backplane concentration Gigabit ports support (1000Base-X) GMII (1000Base-T) interfaces Uplink supports XGMII interface 10Gigabit search t Abstract: .. option to cross VLAN boundary Supports frame trapping for CPU processing Full-duplex & half .. For each port, there is a receiving Rx FIFO to interface with the Rx MAC. While the frame is in .. Tags: GMII VLAN Tag AL1032 |
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First line: ADS52xx* vhdl code for digital clock vhdl coding for analog to digital converter ADS52xx VHDL code for high speed ADCs using SPI with FPGA Application Note: Virtex-II, Virtex-II Pro, Spartan-3 Families Connecting Xilinx FPGAs Texas Instruments ADS527x Series ADCs Author: Marc Defossez Abstract: .. run at a clock rate similar, but not referenced, to the sampling clock, and use a FIFO to cross the clock domains between the ADC receiver interface and the application logic. Example designs of .. Tags: VHDL code for high speed ADCs using SPI with FPGA ADS52xx vhdl coding for analog to digital converter vhdl code for digital clock ADS52xx* XC2V250* large* fpga frame by vhdl examples ADS527x |
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First line: SCMOS1/2 SCMOS1/2 Technology FIFO Family 72Kbit) Tolerance Radiation Abstract This paper proposes review data gathered during heavy testing First First manufactured using Radiation Tolerant version 0.85µm SCMOS1/2 technology. Both Upset sensitivity Total Dose tolerance assessed 5.0V typical po Abstract: .. The First In First Out RAMs FIFO manufactured using the radiation tolerant version of the .. address pointers are less sensitive Let th at 22 MeV/ mg/cm2 with a cross section at 9E‐05cm2 .. Tags: technics matra LINEAR Cross Reference Search 9439 35CL datasheet abstract.. |
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First line: smd marking 8K SMD W16 Transistor w16 SMD transistor smd w16 smd transistor w16 Cross Reference Listed below SMDs which Cypress approved source supply. Please contact your local Cypress representative Cypress website (www.cypress.com) latest update. part numbers that have (Preferred Parts List) colu Abstract: .. X 32 R LCC L55 2K x 9 FIFO A. 5962-88669 05YX CY7C429-30DMB 28.3 DIP D22 2K x 9 FIFO A. SMD Cross Reference by SMD Number[1] continued SMD Number. Equivalent Cypress[2] Part Number PPL[3] Package[4 .. Tags: SMD W16 Transistor smd marking 8K W22 sram w16 SMD w12 smd transistor smd w16 smd w16 smd transistor x8 smd transistor w16 smd cross reference PROM OTP PALC22V10-30WMB PALC22V10-25WMB CY6116A-35DMB CY6116A-35LMB CY6116A-45DMB CY6116A-55DMB |
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First line: 7805 ACT FB 3306 Section Functional Cross Reference DEVICE '1G00 '1G04 '1GU04 '1G08 '1G14 '1G2 '1G86 '00 '01 '02 '04 'U04 '05 '06 '07 '08 '09 '10 Abstract: .. FUNCTIONAL CROSS-REFERENCE. Template Release Date: 7‐11‐94. 3‐4 POST OFFICE BOX 655303 DALLAS .. ✔ FIFO. ’225. ✔. ✔ FIFO. ’230. ✔. ’232. ✔. ✔ FIFO. ’233. ✔. ✔ FIFO. ’236. ✔. ✔ FIFO. ’240. ✔. ✔. ✔. ✔. ✔. ✔. ✔. ✔. ✔ ∞ ✔ ∞ ✔. ✔. ✔. ✔. ✔. ✔. ’241. ✔. ✔. ✔. ✔ .. Tags: 29833 hc 7808 7807 LVC 576 hct 241 datasheet hct 138 FB 3306 7805 ACT 7804 7204l "4066" "Cross Reference" datasheet abstract.. |
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First line: 64-Byte FIFOs SN74ALS2232A SN74ALS2233A First-In, First-Out Technology Kittrell Advanced System Logic Semiconductor Group SCAA023A March 1996 Abstract: .. The first word loaded into an empty FIFO propagates directly to the data outputs. Any UNCK .. input levels to cross the transition threshold may be detected as clock pulses by high-speed .. Tags: SN74ALS2233A SN74ALS2232A SN74ALS2233A |
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First line: fifo cross Clocked FIFO MARKETING PART NUMBER CY7C445 CY7C446 CY7C447 CY7C455 CY7C456 CY7C457 DEVICE DESCRIPTION Clocked FIFO Clocked FIFO Clocked FIFO Cascadable Clocked FIFO Cascadable Clocked FIFO Cascadable Clocked FIFO Abstract: .. Fab/Assembly site change: None Cross Licensee/Licensor: None. Other Devices to be qualified .. SIMILARITY Product Family: Clocked FIFO Mfg Division: Cypress Semiconductor. Supplier's .. Tags: fifo cross cross reference clocks cypress CY7C445 CY7C446 CY7C447 CY7C455 CY7C456 CY7C457 |
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First line: XC4VLX40FF1148-10* Application Note: Virtex-4 FPGAs SPI-4.2 Quad SPI-3 Bridge Virtex-4 FPGAs Author: Abstract: .. FIFO. Each SPI-3 channel is eligible for transfer when it has at least one EOP in its burst FIFO or .. SPI-4.2 cores and the user side of the SPI-3 cores causes the bridge logic to cross clock domains .. Tags: XC4VLX40FF1148-10* ug154 SPI-4 SPI-3 |
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First line: BCM8128 MULTI-RATE 10-GBPS SONET/SDH/10GE/FEC FEATURES 10-Gigabit (Multi-Source Agreement) compliant Fully integrated Clock Multiplication Unit (CMU) supports Abstract: .. On-chip 16 x 10 FIFO eliminates system timing issues Serial data polarity invert Bit order .. cross-connects ATM switch backbones SONET test equipment Terabit routers Edge routers. A P P L I .. Tags: mux 8/3 cmos BCM8128 BCM8128 |
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First line: BCM8124 LOW-JITTER 10-GBPS 16:1 WITH CLOCK GENERATION FEATURES FEATURES Supports 10-Gigabit (Multi-Source Agreement) features Enhanced 10-Gbps serial output data: Abstract: .. On-chip 16 x 10 FIFO to eliminate system timing issues Lock detect Core power supply: 1.8V I/O .. transmission equipment SONET/SDH optical modules ADD/DROP multiplexers Digital cross .. Tags: mux 8/3 cmos BCM8124 BCM8124 |
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First line: XR16M2750 1.62V 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AUGUST 2007 REV. 1.0.0 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the M2750 will transmit the programmed .. Tags: XR16V2751 XR16M2750 |
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First line: universal AC Motor soft start XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO POWERSAVE SEPTEMBER 2007 REV. 1.0.1 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the V2751 will transmit the programmed .. Tags: universal AC Motor soft start XR16V2751 |
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First line: XR16M2751 1.62V 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AUGUST 2007 REV. 1.0.0 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the M2751 will transmit the programmed .. Tags: XR16M2751 |
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First line: remote control rx tx LED "IR for Tx, RX Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the V2751 will transmit the programmed .. Tags: LED "IR for Tx, RX remote control rx tx datasheet abstract.. |
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First line: infrared transmitter receiver 555 2/2 XR16C8641* XR16C864 2.97V 5.5V QUAD UART WITH 128-BYTE FIFO Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables A-D . To clear this condition, the 864 will transmit the programmed .. Tags: XR16C8641* infrared transmitter receiver 555 2/2 ST16C654 16C554 XR16C864 |
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First line: XR16V2750 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO SEPTEMBER 2007 REV. 1.0.3 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the V2750 will transmit the programmed .. Tags: XR16V2750IM XR16V2750 |
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First line: XR16V2750 REV. P1.0.0 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the V2750 will transmit the programmed .. Tags: XR16V2750 |
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First line: 16C850 M2752 XR16M2752 1.62V 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AUGUST 2007 REV. 1.0.0 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the M2752 will transmit the programmed .. Tags: M2752 16C850 mcr 6 13 XR16M2752 |
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First line: XR16L2750 2.25V 5.5V DUART WITH 64-BYTE FIFO Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables A-D . To clear this condition, the 2750 will transmit the programmed .. Tags: XR16L2750 |
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First line: XR16V2752 REV. P1.0.0 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the V2752 will transmit the programmed .. Tags: mcr 6 13 XR16V2752 |
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First line: XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO JULY 2007 REV. 1.0.2 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables . To clear this condition, the V2752 will transmit the programmed .. Tags: mcr 6 13 16C854 XR16V2752 |
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First line: XR16L2752 2.25V 5.5V DUART WITH 64-BYTE FIFO Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables A-D . To clear this condition, the 2752 will transmit the programmed .. Tags: pc16c552 mcr 6 13 XR16L2752 |
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First line: XR16L2752 2.25V 5.5V DUART WITH 64-BYTE FIFO Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level for all trigger tables A-D . To clear this condition, the 2752 will transmit the programmed .. Tags: SC 2752 pc16c552 mcr 6 13 MCR ?6 ?313 transistor power 16C2852 XR16L2752 |
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First line: 2716 2k eprom 24 pin w14 smd transistor Cross Reference Listed below SMDs which Cypress approved source supply. Please contact your local Cypress representative Cypress website (www.cypress.com) latest update. part numbers that have date (Preferred Parts List) column will supported Cypress minimum y Abstract: .. x 9 FIFO A. 5962-90555 01LX PLDC20RA10-35DMB 24.3 DIP D14 Asynchronous CMOS OTP PLD A. SMD Cross Reference by SMD Number[1] continued SMD Number. Equivalent Cypress[2] Part Number PPL[3] Package .. Tags: w14 smd transistor 2716 2k eprom 24 pin 99522 PALC22V10B-20WMB 128-Macrocell* UV led diode u208 sram cross reference smd w16 smd transistor w16 smd cross reference PROM OTP PALCE22V10-25LMB* PALCE22V10-15LMB PALCE22V10 PALCE16V8-15DMB PALC22V10-25QMB PALC22V10-25WMB PALC22V10B-20QMB PALC22V10B-20WMB PLDC20G10-30DMB PLDC20G10-30LMB PALC22V10-25LMB PALC22V10-25DMB PALC22V10-30DMB PALC22V10B-20LMB PALC22V10B-20KMB PALC22V10B-20DMB PALC22V10B-15LMB PALC22V10B-15KMB PALC22V10B-15DMB |
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First line: SPARTAN-3e microblaze DS449 Fast Simplex Link (FSL) (v2.11b) DS449 June Abstract: .. FIFO depths can be as low as 1 and as high as 8K. Supports both synchronous and asynchronous FIFO .. 10/1805 1.4.1 Updated to incorporate CR205787; updated cross references. 11/11/05 1.5. In .. Tags: DS449 SPARTAN-3e microblaze DS449 |
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First line: CYPRESS CY7C9689 Compatible Transceiver Second-generation technology AM7968/7969 compatible 8-bit 4B/5B 10-bit 5B/6B NRZI encoded data transport 10-bit 12-bit NRZI pre-encoded (bypass) data transport Synchronous parallel interface Embedded/Bypassable character Transmit Receive FIFOs 50-to-200 MBaud Abstract: .. In this mode all Transmit FIFO writes are synchronized to TXCLK, and all Receive FIFO reads are .. , after 100,000 samples measured at the cross point of differential outputs, time referenced .. Tags: datasheet abstract.. |
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First line: 32-Lead Lead Frame Chip Scale Package LFCSP_VQ sec d 5702 proximity sensor interfacing with microcontroller jedec package MO-220-VHHD-2 IR Sensor transmitter and receiver pair datasheet Programmable Controller Capacitance Touch Sensors AD7142 Programmable capacitance-to-digital converter update rate Abstract: .. internally connected to the CSHIELD signal to help prevent cross coupling. If an input is not .. FIFO is used by the on-chip logic to determine if proximity is detected. The fast FIFO expects to .. Tags: IR Sensor transmitter and receiver pair datasheet jedec package MO-220-VHHD-2 sec d 5702 32-Lead Lead Frame Chip Scale Package LFCSP_VQ proximity sensor interfacing with microcontroller KTC3875 finger print sensor pcb with circuit pdf ELC2000 45 R 15 C AD7142 AD7142-1 |
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First line: AD7147-1 finger print sensor pcb with circuit pdf CapTouchTM Programmable Controller Single-Electrode Capacitance Sensors AD7147 Programmable capacitance-to-digital converter (CDC) Femtofarad resolution capacitance sensor inputs update rate, sensor inputs external components required Automatic conve Abstract: .. Each input can also be internally connected to the BIAS signal to help prevent cross coupling .. FIFO is used by the on-chip logic to determine if proximity is detected. The fast FIFO expects to .. Tags: AD7147-1 KTC3875 finger print sensor pcb with circuit pdf AD7147 AD7142 AD7147-1 |
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First line: CY7C9689 TAXITM Compatible HOTLink® Transceiver Second-generation HOTLink® technology AMDTM AM7968/7969 TAXIchipTM compatible 8-bit 4B/5B 10-bit 5B/6B NRZI encoded data transport 10-bit 12-bit NRZI pre-encoded (bypass) data transport Synchronous parallel interface Embedded/Bypassable charact Abstract: .. tTXRSS Transmit FIFO Reset TXRST Set-Up Time to TXCLK↑ 4 ns. tTXRSH Transmit FIFO Reset TXRST .. , after 100,000 samples measured at the cross point of differential outputs, time referenced .. Tags: AM7968 7969 |
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First line: MEF 0.47 LH543620 FEATURES Fast Cycle Times: 20/25/30 Selectable 36/18/9-Bit Word Width Both Input Port Output Port Byte-Order-Reversal Function (i.e., `Big-Endian' `Little-Endian' Conversion) 16-mA-IOL Three-State Outputs Automatic Byte Parity Checking Selectable Byte Parity Generation Five Status Abstract: .. Cross-connecting the FF output of each FIFO to ENI1 or ENI2 input of the other FIFO. Cross-connecting the EF output of each FIFO to ENO1 or ENO2 input of the other FIFO. The composite status .. Tags: MEF 0.47 synchronous fifo pdf pqfp132* fifo buffer empty full flag error reset CC-131 80286 LH543620 |
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First line: universal AC Motor soft start XR16V654/654D 2.25V 3.6V QUAD UART WITH 64-BYTE FIFO SEPTEMBER 2007 REV. 1.0.2 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level. To clear this condition, the V654 will transmit the programmed Xon-1,2 characters as .. Tags: universal AC Motor soft start QFN "100 pin" PACKAGE thermal resistance XR16V654 654D |
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First line: universal AC Motor soft start General Instrument 312 diode XR16M654/654D 1.62V 3.63V QUAD UART WITH 64-BYTE FIFO 2008 REV. 1.0.0 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level. To clear this condition, the M654 will transmit the programmed Xon-1,2 characters as .. Tags: General Instrument 312 diode universal AC Motor soft start QFN "100 pin" PACKAGE thermal resistance m654 XR16M654 654D |
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First line: 16550 uart timing diagram xr16m554 XR16M554/554D 1.62V 3.63V QUAD UART WITH 16-BYTE FIFO 2008 REV. 1.0.0 Abstract: .. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections. TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION .. Tags: 16550 uart timing diagram xr16m554iv64 XR16M554 554D |
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First line: XR16V554/554D 2.25V 3.6V QUAD UART WITH 16-BYTE FIFO SEPTEMBER 2007 REV. 1.0.2 Abstract: .. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections. TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION .. Tags: xr16v554div XR16V554 554D |
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First line: 16C864 uart 8051 115200 XR18W750 WIRELESS UART CONTROLLER MARCH 2008 REV. 1.0.0 Abstract: .. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections. Note that the receiver and the transmitter .. Tags: uart 8051 115200 LSR THR 16C864 16C854 XR18W750 |
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First line: a7 w 74 IR Sensor transmitter and receiver pair datasheet proximity sensor interfacing with microcontroller proximity switch block diagram Programmable Controller Capacitance Touch Sensors AD7143 Programmable capacitance-to-digital converter update rate maximum sequence length) Better than resolutio Abstract: .. internally connected to the CSHIELD signal to help prevent cross coupling. If an input is not .. Using FF_SKIP_CNT normalizes the frequency of the samples going into the FIFO, regardless of .. Tags: proximity switch block diagram IR Sensor transmitter and receiver pair datasheet a7 w 74 Sensor,Ambient proximity sensor interfacing with microcontroller finger print sensor pcb with circuit pdf AD7143 |
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First line: XR16C2550 2.97V 5.5V DUART WITH 16-BYTE FIFO Abstract: .. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections. 4.6 Line Control Register LCR - Read/Write .. Tags: 16C554 XR16C2550 |
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First line: STAGE10 11-Stage proximity sensor interfacing with microcontroller IR Sensor transmitter and receiver pair datasheet sensor 21E 22B Programmable Capacitance-to-Digital Converter with Environmental Compensation Programmable capacitance-to-digital converter update rate maximum sequence length) Better Abstract: .. internally connected to the CSHIELD signal to help prevent cross coupling. If an input is not .. /W STAGE0_FF_WORD0 STAGE0 Fast FIFO WORD0. 0E2 [15:0] X R/W STAGE0_FF_WORD1 STAGE0 Fast FIFO .. Tags: sensor 21E 22B IR Sensor transmitter and receiver pair datasheet 11-Stage STAGE10 proximity sensor interfacing with microcontroller dev 23d d 5702 AD7142-1 |
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First line: 16c854 3mm ir receiver LED "IR for Tx, RX LED IR for Tx, RX XR16M780 1.62V 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO SEPTEMBER 2008 REV. 1.0.0 Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level. To clear this condition, the M780 will transmit the programmed Xon-1,2 characters as .. Tags: LED IR for Tx, RX LED "IR for Tx, RX 3mm ir receiver 16c854 LED "IR for Tx, RX XR16M780 |
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First line: MCR 92 universal AC Motor soft start ST16C654/654D 2.97V 5.5V QUAD UART WITH 64-BYTE FIFO Abstract: .. two characters at the programmed baud rate after the receive FIFO crosses the programmed trigger level. To clear this condition, the 654 will transmit the programmed Xon-1,2 characters as soon .. Tags: universal AC Motor soft start MCR 92 intel Source Book 2003 ST16C654 654D |
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First line: ST16C554/554D 2.97V 5.5V QUAD UART WITH 16-BYTE FIFO JUNE 2006 REV. 4.0.1 Abstract: .. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections. TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION .. Tags: TL16C554* ST16C554 554D |
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