Z8601/Z8603 Z8611/Z8613 Z8601 Single-Chip with 78603 Prototy
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June 1987
Z8601/Z8603 Z8611/Z8613
Z8601 Single-Chip with
78603 Prototyping Device with EPROM Interface
28611 Single-Chip with
Z8613 Prototyping Device with EPROM Interface
Complete microcomputer, (8601) (8611) bytes ROM, bytes RAM, lines, (8601) (8611) bytes addressable external space each program data memory.
144-byte register file, including general-purpose registers, four port registers, status control registers.
Average instruction execution time maximum fxs.
Vectored, priority interrupts I/O, counter/timers, UART.
Full-duplex UART programmable 8-bit counter/timers, each with 6-bit programmable prescaler.
Register Pointer that short, fast instructions access nine working register groups fis.
On-chip oscillator which accepts crystal external clock drive.
Single power pins compatible.
12.5 MHz.
General microcomputer introduces level
Description sophistication single-chip architecture.
Compared earlier single-chip microcomputers, offers faster execution; more efficient memory; more sophisticated interrupt, input/output bit-manipulation capabilities; easier system expansion.
Under program control, tailored needs user. configured
stand-alone microcomputer with bytes internal ROM, traditional microprocessor that manages 124K bytes external memory, parallel-processing element system with other processors peripheral controllers linked bus. configurations, large number pins remain available I/O.
TIMING CONTROL
PORTO
(nibble programmable)
Ab-A,5
PORT
{byte
programmable)
AD0-ADf
reset xtal1 xtal2 28601/11
Itti
}CLOCK
PORT
(bit programmable)
PORT
SERIAL PARALLEL CONTROL
Figure 40-pin DuaMn-Line Package (DIP), Assignments
Address Strobe (output, active Low),
Description Address Strobe pulsed once beginning each machine cycle. Addresses output Port external program data memory transfers valid trailing edge Under program control, placed high-imp edance state along with Ports Data Strobe Read/Write.
Data Strobe (output, active Low). Data Strobe activated once each external memory transfer.
PO0-PO7, P1q-P17, P2o-P27, P30-P37. Port Lines (input/outputs, TTL-compatible). These lines divided into four 8-bit ports that configured under program control external memory interface.
RESET. Beset (input, active Low). RESET initializes When RESET deactivated,
program execution begins from internal program location OOOCh.
ROMIess. (input, active LOW). This only available version Z8611. When connected disables internal forces part function Z8681 ROMIess When left unconnected pulled high V^the part will function normally Z8611.
R/W. Read/Write (output). when writing external program data memory.
XTAL1, XTAL2. Crystal Crystal2 (time-base input output). These pins connect parallel resonant 12.5 crystal external single-phase 12,5 clock on-chip clock oscillator buffer.
RESET
POfl
ROMIess
Figure 44-pin Chip Carrier, Assignments
Architecture architecture characterized flexible scheme, efficient register address space structure number ancillary features that helpful many applications.
Microcomputer applications demand powerful capabilities. fulfills this with pins dedicated input output. These lines grouped into four ports eight lines each configurable under software control provide timing, status signals, serial parallel with without handshake, address/ data interfacing external memory.
Because multiplexed address/data merged with I/O-oriented ports, assume many different memory configurations. These configurations range from self-contained microcomputer microprocessor that address 124K (Z8601) 120K (Z86I1) bytes external memory.
Three basic address spaces available support this wide range configurations: program memory (internal external), data memory (external) register file (internal). 144-byte random-access register file composed general-purpose registers, four port registers, control status registers.
unburden program from coping with real-time problems such serial data communication counting/timing, asynchronous receiver/transmitter (UART) counter/timers with large number userse-lectable modes offered on-chip. Hardware support UART minimized because on-chip timers supplies rate.
OUTPUT INPUT
PORT
uart
COUNTER/ TIMERS
INTERRUPT CONTROL
PORT
Ifflt
(BIT PROGRAMMABLE)
till UH,,
fugs
REGISTER POINTER
RESET
MACHINE TIMING INSTRUCTION CONTROL
REGISTER FILE 8-BIT
ADDRESS (NIBBLE PROGRAMMABLE)
PROGRAM MEMORY
PROGRAM COUNTER
Z8601 2048 8-BIT
Z8611 4096 8-BtT
PORTO PORT
ADDRESS/DATA (BYTE PROGRAMMABLE)
Figure Functional Block Diagram
Address Spaces
Program Memory. 16-bit program counter addresses bytes program memory space. Program memory located areas: internal other external (Figure first 2048 (Z8601) 4096 (Z8611) bytes consist on-chip mask-programmed ROM. addresses 2048 (Z8601) 4096 (Z8611) greater, executes external program memory fetches.
first bytes program memory reserved interrupt vectors. These locations contain 16-bit vectors that correspond available interrupts.
Data Memory. address (Z8601) (Z8611) bytes external data memory beginning location 2048 (Z8601) 4096 (Z8611) (Figure External data memory
included with separated from external program memory space. optional function that programmed appear P34, used distinguish between data program memory space.
Register File. 144-byte register file includes four port registers (R0-R3), general-purpose registers (R4-R127) .control status registers (R240-R255). These registers assigned address locations shown Figure
instructions access registers directly indirectly with 8-bit address field. also allows short 4-bit register addressing using Register Pointer (one control registers). 4-bit mode, register file
Z6601
2047
Location first byte Inslnjcifon executed after reset
Interrupt Vector
imenuui Vector (Upper Byte)
EXTERNAL
ON-CHIP
IROS
IROS
IRQ4
IRQ4
IRQ3
IRQ3
IR02
IRQ1
IRQ1
IRQ0
IRQ0
4096
Z8A11
12046 2047
EXTERNAL
DATA MEMORY
ADDRESSABLE
4096 4095
28611
Figure Program Memory
Figure Data Memory
LOCATION
STACK POINTER {BUS 7-0)
STACK POINTER (BITS 15-6)
REGISTER POINTER
PROGRAM CONTROL FLAGS
INTERRUPT MASK REGISTER
INTERRUPT REQUEST REGISTER
INTERRUPT PRIORITY REGISTER
PORTS MODE
PORT"3 MODE
PORT MODE
PRESCALER
TIMER/COUNTER
PRESCALER
TIMER/COUNTER
TIMER MODE
SERIAL
IMPLEMENTED
GENERAL-PURPOSE REGISTERS
PORT
PORT
PORTI
PORTO
IDENTIFIERS
FLAGS
P01M
PRE0
PRE1
upper nibble register file address provided register pointer spedfles active working-register group.
SPECIFIED WORKING-REGISTER GROUP
PORTS
lower nibble register file address provided Instruction points specified register.
Figure Register File
Figure Register Pointer
2037-004,005,006,007
divided into nine working-register groups, each occupying continguous locations (Figure Register Pointer addresses starting location active working-register group.
Stacks. Either internal register file external data memory used stack.
16-bit Stack Pointer (R254 R255) used external stack, which reside anywhere data memory between locations 2048 (8601) 4096 (8611) 65535. 8-bit Stack Pointer (R255) used internal stack that resides within general-purpose registers (R4-R127).
Serial Port lines programmed
Input/ serial lines full-duplex serial asynchro-
Output nous receiver/transmitter operation. rate
controlled Counter/Timer MHz.
automatically adds start stop bits transmitted data (Figure parity also available option. Eight data bits always transmitted, regardless parity
Transmitted Data
Parity)
selection. parity enabled, eighth parity bit. interrupt request (IRQ4) generated transmitted characters.
Received data must have start bit, eight data bits least stop bit. parity received data replaced parity error flag. Received characters generate IRQ3 interrupt request.
Received Data
Parity)
Transmitted Data
(With Parity)
START EiQHT DATA BITS STOP BITS
Dj|p,|D,[p0|sf{
START EIGHT DATA BITS STOP
Received Data
(With Parity)
START SEVEN DATA BITS PARITY STOP BITS
START SEVEN DATA BITS PARITY ERROR FLAG STOP
Figure Serial Data
Counter/ contains 8-bit programmable
Timers counter/timers Ti), each driven
6-bit programmable prescaler. prescaler driven internal external clock sources; however, prescaler driven internal clock only.
6-bit prescalers divide input frequency clock source number from Each prescaler drives counter, which decrements value 256) that been loaded into counter. When counter reaches count, timer interrupt (to) IRQ5 generated.
counters started, stopped, restarted continue, restarted from initial value. counters also programmed stop upon reaching zero (single-
pass mode) automatically reload initial value continue counting (modulo-n continuous mode). counters, prescalers, read time without disturbing their value count mode.
clock source user-definable internal microprocessor clock divided four, external signal input Port Timer Mode register configures external timer input external clock, trigger input that retriggerable non-retriggerable, gate input internal clock. counter/timers programmably cascaded connecting output input Port line also serves timer output (Tqut) through which internal clock output.
Ports lines dedicated input
output. These lines grouped into four ports eight lines each configurable input, output address/data. Under software control, ports programmed provide address
outputs, timing, status signals, serial I/O, parallel with without handshake. ports have active pull-ups pull-downs compatible with loads.
Port programmed byte port address/data port interfacing external memory. When used port, Port placed under handshake control. this configuration, Port lines used handshake controls RDYi DAVi (Ready Data Available).
Memory locations greater than 2048 (Z8601) 4096 (Z8611) referenced through Port interface external memory, Port must programmed multiplexed Address/Data mode. more than external locations required, Port must output additional lines.
Port placed high-impedance state along with Port R/W,
allowing share common resources multiprocessor applications. Data transfers controlled assigning Acknowledge input Request output.
(I/O AD^-AD?)
HANDSHAKE CONTROLS DAV, RDY1 '{P3, P3,)
Figure Port
Port programmed nibble port, address port interfacing external memory, When used port, Port placed under handshake con- trol. this configuration, Port lines used handshake controls DAVq RDYq. Handshake signal assignment dictated direction upper nibble PO4-PO7.
external memory references, Port provide address bits As-Aji (lower nibble) Ag-Ais (lower upper nibble) depending required address space. address range requires bits less, upper nibble Port programmed independently while
lower nibble used addressing. When Port nibbles defined address bits, they highimpedance state along with Port control signals R/W,
PORTO (I/O A|-A||)
HANDSHAKE CONTROLS DAVo RDYo (P32
Figuro Port
Port bits programmed independently input output. port always available operations. addition, Port configured provide open-drain outputs.
Like Ports Port also placed under handshake control. this configuration, Port lines andP3gare used handshake controls lines DAV2 RDY2. handshake signal assignment Port lines dictated direction (input output) assigned Port
PORT i(U0)
HMPSHAKE CONTROLS BAV2 RDY2 (P3j P3f)
Figure Port
Port lines configured control lines. either case, direction eight lines fixed four input (P3o-P3a) four output (P34-P37). serial I/O, lines programmed serial serial respectively.
Port also provide following control functions: handshake Ports (DAVand RDY); four external interrupt request signals (IRQ0-IRQ3); timer input output signals (Tin Tqut) Data Memory Select (DM);
PORT
(I/O CONTROL)
Figure Pori
2037-008
Interrupts allows different interrupts from
eight sources: four Port lines P3o-P33, Serial Serial Out, counter/timers. These interrupts both maskable prioritized. Interrupt Mask register globally individually enables disables interrupt requests. When more than interrupt pending, priorities resolved programmable priority encoder that controlled Interrupt Priority register.
interrupts vectored. When interrupt request granted, interrupt machine
cycle entered. This disables subsequent interrupts, saves Program Counter status flags, branches program memory vector location reserved that interrupt. This memory location next byte contain 16-bit address interrupt service routine that particular interrupt request.
Polled interrupt systems also supported. accommodate polled structure, interrupt inputs masked Interrupt Request register polled determine which interrupt requests needs service.
Clock
on-chip oscillator high-gain, parallel-resonant amplifier connection crystal suitable external clock source (XTAL1 Input, XTAL2 Output).
crystal source connected across XTAL1 XTAL2, using recommended capacitors
from each ground. specifications crystal follows:
cut, parallel resonant
Fundamental type, 12.5 maximum
Series resistance,
Z8603/13 Protopack used prototype
Protopack development preproduction mask-Emulator programmed applications. Protopack ROMless version standard Z8601 Z8611 housed pin-compatible 40-pin package (Figure 11).
provide compatibility interchange-ability with standard maskprogrammed device, Protopack carries piggy-back 24-pin socket direct interface program memory (Figure Z8603 24-pin socket equipped with address lines, data lines necessary control lines interface 2716 EPROM first bytes program memory. Z8613 24-pin socket
Figure Microcomputer Protopack Emulator
equipped with address lines, data lines necessary control lines interface 2732 EPROM first bytes program memory.
compatibility allows user design board final 40-pin maskprogrammed and, same time, allows Protopack build prototype pilot production units. When final program established, user then switch over 40-pin mask-programmed large volume production. Protopack also useful small volume applied tions where masked setup time, mask charges, etc., prohibitive program flexibility desired.
Compared conventional EPROM versions single-chip microcomputers, Protopack approach offers main advantages:
Ease developing various programs during prototyping stage. instance, applications where same hardware configuration used with more than program, Protopack allows economical program storage separate EPROMs PROMs), whereas separate EPROM-based single-chip microcomputers more costly.
Elimination long lead time procuring EPROM-based microcomputers.
Instruction
Notation
Addressing Modes. following notation used describe addressing modes instruction operations shown instruction summary.
Indirect register pair indirect working-register pair address
Indirect working-register pair only Indexed address Direct address Relative address Immediate
Register working-register address Working-register address only Indirect-register indirect working-register address
Indirect working-register address only Register pair working register pair address
Symbols, following symbols used describing instruction set. Destination location contents Source location contents Condition code (see list) Indirect address prefix Stack pointer (control registers 254-255) Program counter FLAGS Flag register (control register 252) Register pointer (control register 253) Interrupt mask register (control register 251)
Assignment value indicated symbol example,
indicates that source data added destination data result stored destination location. notation "addr(n)" used refer given location. example,
refers destination operand.
Flags. Control Register R252 contains following flags:
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags indicated
Cleared zero
cleared according operation
Unaffected
Undefined
Condition Codes
Value Mnemonic Meaning Flags
1000 Always true
0111 Carry
1111 carry
0110 Zero
1110 zero
1101 Plus
0101 Minus
0100 Overflow
1100 overflow
0110 Equal
1110 equaL
1001 Greater than equal
0001 Less than
1010 Greater than
0010 Less than equal
1111 Unsigned greater than equal
0111 Unsigned less than
1011 Unsigned greater than
0011 Unsigned less than equal
0000 Never true
Instruction Formats
CCF, IRET, NOP, RCF, RET,
INCr
One-Byte (rue ions
MODE
dit/src
VALUE
MODE
MODE
dst/stc
CLR, CPL, DEC,
dsl/src DECW',NC'INCW' osusrc pusH> fllC( ftRf
RRC, SWAP CALL (indirect)
ADC, ADD, AND, SBC, SUB, TCM,
dsl/src
VALUE
dst/CC OPC_
MODE
MODE
VALUE
MODE
ADC, ADD. AND, SBC, SUB, TCM,
ADC, ADD, AND, SBC, SUB, TCU.
LDE, LDEf, LDC, LDCt
MODE
dst/ire
ADDRESS
OPC"*
DJNZ,
CALL
Two-Byte Instructions
Tbree-Byte Instructions
Figure Instruction Formats
Instruction Summary
Instruction Operation
Addr Mode Opcode Flags Affected
-Byte
(Hex)
d9t(src (Note
dst,src
(Note
dst,ere (Note
CALL
dst,src (Note
DECW
DJNZ r.dst
Range: +127, -128
INCW
IRET ******
FLAGS -SP+
cc,dst
true c=0-F
cc,dst
true,
Range: +127, -128
dst,
dst,
LDCI dst,src
Instruction Addr Mode Opcode Flag's Aiiected Operation czsypH
dst,src
LDEI dst,src
NOP_FF
dst,src (Note -dst src_:_
PUSH
SP-SP-1; @SP-src
^XF^T) ****-
I,_, ****-_
****-
43WIIZ3-1
****_
KZJ-EI^H
dst,arc (Note
dst^^R ***0-
dst,src (Note
SWAP rr^^P-n IR_Fl_
dst,src (Note -(NOT dst) src_
dst, (Note -dst
dst,src (Note
dstXOR
Hotel
These instructions have identical addressing modes, which encoded brevity. first opcode nibble found instruction table above. second nibble expressed symbolically this table, value found following table right applicable addressing mode pair.
example, determine opcode instruction addressing modes (destination) (source). result
Addr Mode
Lower Opcode Nibble
Registers
R240 Sericd Register
(FOh; Read/Write)
R244T0 Counter/Timer Register
(F4h; Read/Write)
SERIAL DATA (0,, LS8)
initial value (when written) -(range: decimal01-00 hex) current value (when read)
R241 Timer Mode Register
(F1h; Read/Write)
R245 PREO Prescaler Register
(F5h; Write Only)
tout modes used
internal cloclj
modes external clock input gate input trigger input -(n0nretr1g0erable)
trigger input (retrigoerable)
IPe|
function load
disable count enablet0count
function loaott
disable count
enablet, count
D4|D,!Dj|DtjD0|
count mode
single-pas!
modulo
-reserved
prescaler modulo (range: 1-64 decimal 01-00 hex)
R242 Counter Timer Register
(F2h; Read/Write)
R246 Port Mode Register
Write Only)
D,|D2|D,[D01
initial value (when written) -(range 1-256 decimal 01-00 hex) current value (when read)
|D,|D,|D6[D4 IPfl
p2q~p2j definition
defines output
defines input
R243 PRE1 Prescaler Register
(F3h; Write Only)
R247 Port Mode Register
(F7h; Write Only)
count mode
single-pass
modulo-n
clock source internal
external timing input
prescaler modulo -{range: 1-64 decimal 01-00 hex)
port pull-ups open drain
port pull-ups active
-reserved
input output
6sv&rdy0 roywdoto
input output -?j}p33 input
input (tin) output (tout)
bav2;rdy2 rdy2,6*v2
input output
serial serial
parity parity
Registers
(Continued)
R248 Port Mode Register
(F8h; Write Only)
R252 FLAGS Flag Register
<FCh; Read/Write)
ESE9E9 E9E9E9
OUTPUT INPUT
external memory thjhnq normal -extended
IODE
POj-POJ MODE
OUTPUT
INPUT A*-*,,
STACK SELECTION
EXTERNAL INTERNAL
l>VP1, MODE BYTE OUTPUT
BYTE INPUT
ADo-AD,
NIQHJMPEDANCE ADo-AD,,
R/W, Aa-An, A12-A,5 SELECTED
E9E9E9E3E3E3
USER FLAG USER FLAG CARRY FLAG DECIMAL ADJUST FLAG OVERFLOW SIGN FLAG FLAG CARRY
H2491PR
Interrupt Priority Register
(F9h; Write Only)
R253 Register Pointer
(FDh; Read/Write)
E3ESE3BICSE3E9E9
reserved
IRQ3, (HQS PRIORITY (GROUP
IRQ5 IR03
IRQ3 IR05
woo, priority (group
irq2 iroo
IROO IRQ2
mOI, IRQ4 PRIORITY (GROUP
irq1 irq4
(roi
INTERRUPT GROUP PRIORITY RESERVED RESERVED
REGISTER POINTER
R250 Interrupt Request Register
(FAh; Read/Write)
R254 Stack Pointer
(FEh; Read/Write)
reserved
|d?jD<|DsjD4|Da|Di|D1}0<,;
IROO INPUT IROO)
IR01 INPUT
1RQ2 INPUT
IR03 INPUT, SERIAL INPUT
IRQ4 SERIAL OUTPUT
STACK POINTER UPPER BYTE (SPj-SPjj)
R2511MR Interrupt Mask Register
(FBh; Read/Write)
ENABLES IROO-IROS IROO}
RESERVED
R255 Stack Pointer
(FFh; Read/Write)
STACK POINTER LOWER BYTE(SP0-SP,)
enables interrupts
Opcode
Lower Nibble (Hex)
ri,Ira 10,5 Ra,Ri 10,5 IRa,Ri 10,5 Ri,IM 10,5 IRi,IM
n,Ira 10,5 Ra.Ri 10,5 IRa,Ri 10,5 Ri,IM 10,5 IRi,IM
ri,ra n,Ira 10,5 Ra,Ri 10,5 lRa,Ri 10,5 Ri,IM 10,5 lRi,IM
IRRi n.Ira 10,5 10,5 IR2,Ri 10,5 Ri,IM 10,5 IRi.IM
ri,lra 10,5 Ra.Ri 10,5 IRa.Ri 10,5 Ri,IM 10,5 lRi,IM
10,5 10,5 ri.ra 10,5 Ra,Ri 10,5 IRa,Ri 10,5 Ri,IM 10,5 IRi,IM
n,ra 10,5 Ra,Ri 10,5 IRa,Ri 10,5 Ri,IM 10,5 1Ri,IM
10/12,1 PUSH 12/14,1 PUSH ri.ra ri,Ir2 10,5 Ra,Rt 10,5 IRa,Rx 10,5 Ri,lM 10,5 IRi,IM
10,5 DECW 10,5 DECW 12,0 ri,Irra 18,0 LDEI Irta
12,0 18,0 LDEI Ira,Irri
10,5 INCW 10,5 INCW ri,ra 10,5 Ra,Ri 10,5 IRa,Ri 10,5 Ri,IM 10,5 IRi,IM
6,5-XOR ri,ra *l,Ira 10,5 Ra,Ri 10,5 IRa,Ri 10,5 Rl,IM 10,5 IRi,lM
12,0 ri,lzi2 18,0 LDCI Iri,Irra 10,5
12,0 ra,Irrx 18,0 LDCI It2,1"1 20,0 CALL* IRRi 20,0 CALL 10,5
10,5 Ra,Ri 10,5 IR2,Ri 10,5 Ri,IM 10,5 IRi,IM
SWAP SWAP Iri, 10,5 Ra.IRi
n,Ra
12/10,5 DJNZ ri,RA
12/10,0
cc,RA
ri.IM
12/10,0
cc,DA
14,0
16,0 IRET
Bytes Instruction
Execution Cycles
Lower Opcode Nibble
Upper Opcode -Nibble
First Operand
Pipeline Cycles
Mnemonic
Second Operand
Legend:
8-Bit Address 4-Bit Address Address Address
Sequence:
Opcode, First Operand, Second Operand Note: blank areas defined.
*2-byte Instruction; fetch cycle appears 3-byte Instruction
6085-002
Absolute Voltages pins
Maximum with respect GND.-0.3 +7.0
Ratings Operating Ambient
Temperature. Ordering Information
Storage Temperature.-65 +150
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; operation device condition above those indicated operational sections these specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
characteristics listed below apply following standard test conditions, unless otherwise noted. voltages referenced GND. Positive current flow's into reference pin.
Standard conditions are:
+4.75 +5,25
FROM OUTPUT UNDER TEST
Figure Test Load
Characteristics
Symbol Parameter Unit Condition
Clock Input High Voltage Driven External Clock Generator
Clock Input Voltage -0.3 Driven External Clock Generator
Input High Voltage
Input Voltage -0.3
Reset Input High Voltage
Reset Input Voltage -0.3
Output High Voltage -250
Output Voltage
Input Leakage +5.25
Output Leakage +5.25
iffi Reset Input Current +5.25
Supply Current
Characteristics
External Memory Head Write Timing
PORT
PORT
PORT
{WRITE)
Figure External Memory Read/Write
Symbol
Parameter
12.5
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TdAz(DS)
TwDSW
TdDSR(DR)
ThDR(DS)
TdDS(A)
TdDS(AS)
TdRAV(AS)
TdDS(B/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)
Address Valid Delay
Address Float Delay
Read Data Required Valid
Width
Address Float
(Read) Width-250-185-
(Write) Width
Read Data Required Valid
Read Data Hold Time
Address Active Delay
Delay
Valid Delay-50-30-
Valid
Write Data Valid (Write) Delay
Write Data Valid Delay
Address Valid Read Data Required Valid
ASTtoDSiDelay
1,2,3 1,2,3
"1,2,3 1,2,3 1,2,3
1,2,3
-NOTES:
When using extended memory timing TpC.
Timing numbers given minimum TpC,
clock cycle time dependent characteristics table.
Test Load!.
timing references logic logic "0". units nanoseconds (ns).
Characteristics
Additional
Timing
Table
CLOCK
Figure Additional Timing
Symbol
Parameter
12.5
Notes*
Input Clock Period
TrC.TfC Clock Input Rise Fall Times
Input Clock Width
TwTinL Time Input Width
TwTinH-Timer Input High Width-
TpTin Timer Input Period
TrTin,TfTin Timer InputRise Fall Times
TwIL Interrupt Request Input Time
TwIL Interrupt Request Input Time
TwIH Interrupt Request Input High Time
-3TpC-8TpC
1000
3TpC 3TpC
3TpC 8TpC
3TpC 3TpC
1000
NOTES:
Clock timing references uses logic logic-0",
Timing reference uses logic logic "0".
Interrupt request Port (P3j -P33).
Interrupt request Port (P3o>. Units nanoseconds (ns).
Memory Port Timing
A0-A1O
Do-Dt
ADDRESS VALID
DONT CARE DATA VALID
Figure Memory Port Timing
Symbol Parameter Notes*
TdA(DI) Address Valid Data Input Delay
ThDI(A) Data Hold time
NOTES:
Test Load
This Clock-Cycle-Dependent parameter. clock frequencies other than maximum, following formula:
4Units nanoseconds unless otherwise specified.
Handshake Timing
DATA
twirn
(output)
DATA INVALID
Figure 18a. Input Handshake
DATA
khjtput)
ttwim
DATA VALID
Figure 18b. Output Handshake
Symbol
Parameter
Notes*
TsDI(DAV)
TwDAV
TdDAVIf(RDY)
5-TdDAVOf (HDY)
TdDAVIr(RDY)
TdDAVOr(RDY)
TdDO(DAV)
TdRDY(DAV)
Data Setup Time Data Hold time Data Available Width Input Delay Output Delay Input Delay Output Delay Data DAVI Delay Input Delay
NOTES: Test load
Input handshake
Output handshake
timing references logic logic "0".
Units nanoseconds (ns).
Clock-
Cycle-Time- Number Symbol Dependent
Equation
Characteristics
TdA(AS) TdAS(A) TdAS(DR) TwAS
-TwDSR-
TwDSW TdDSR(DR) Td(DS)A TdDS(AS) -TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS)
TpC-50 TpC-40 4TpC-110* TpC-30
3TpC-65* -2TpC-55* 3TpC-120*
TpC-40 TpC-30
TpC-55 TpC-50 TpC-50 TpC-40
5TpC-160* TpC-30
2TpC when using extended memory timing.
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