Semiconductor microCMOS Gate Array Family Application Guide
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National July 1985
Semiconductor
microCMOS Gate Array Family Application Guide
TABLE CONTENTS
General Description
Product Features.
2.0.1 Enhanced Product Features.
microCMOS Process Circuit Personalization.
Gate Array Basic Cell.
Power Dissipation.
Absolute Maximum Ratings.
Recommended Operating Conditions.
Electrical Characteristics.
Electrical Characteristics.
Topology Routing Resource Distribution.
SCX6206 (600)
SCX6212 (1.2k).
SCX6218 (1.8k).
SCX6225 (2.5k).
SCX6232 (3.2k).
SCX6244 (4.4k).
On-Chip Test Circuitry.
Macros
Hardware Macros
Peripheral Macros.
Software Macros.
Software Macros (User Generated).
Packaging.
Propagation Delays.
Design Automation System.
Workstation Support.
10.0 Design Example.
10.1 Text Mode.
10.2 Workstation Mode.
10.3 Pattern File.
10.4 Simulator Output.
11.0 Alternative Interfaces.
12.0 Training Technical Services.
13.0 Technology Centers.
006363
registered trademark National Semiconductor Corp.
National Semiconductor Corporation
TL/U/5725
RRD-B30M75/Printed
General Description
National Semiconductor's CMOS gate array Family utilizes dual layer metal technology (microCMOS) achieve operating speeds similar Schottky-TTL with inherent lower power consumption standard CMOS integrated circuits. SCX6200-Series Family available 2-micron drawn geometry with micron effective channel length. range complexity currently from 6000 gates. gates arranged cells. Each cell equivalent three 2-input NAND gates. outputs have ability drive LSTTL loads. inputs have high noise immunity protected from static discharge. National Semiconductor supports gate array designs with variety user/vendor interfaces. This ranges from producing arrays from user's schematic accepting databases mask generation. large dedicated staff gate array professionals available help user determine most efficient cost effective interface given design.
design automation tools include workstation text file entry (for schematic capture), logic timing verifiers substantiate actual design, fault grading analysis gauge testability large selection macros (hardware software) speed simplify design.
Product Features
Latch-up proof, state-of-the-art 2-micron (drawn) dual-metal silicon-gate microCMOS technology
Ultra-high typical gate delays
Available from gates 6000 gates
CMOS power dissipation
inputs l/Os protected from over-voltage latch-up
Full design automation support
Schematic capture
Logic simulator with timing information
Fault grading
Multiple power rail connections
Multiple packaging options ceramic, plastic, leaded leadless
counts
Military performance
Alternately sourced
Complete hardware/software macrocell libraries
On-chip self-test capability (6.0K only)
100% auto-place-and-route utilization
Design automation system supported mainframe workstations
2.0.1 Enhanced Product Features
SCX6200-series gate array family available seven device increments from 6000 gates. initial members 2-micron family consist SCX6212, 6225 6260. Today been enhanced expanded include 6244, 6232, 6218 6206. These enhanced devices contain several features follows:
Flexible Structure buffer been enhanced handle multiple (unctions including:
Low-drive inputs compatible with TTL, CMOS Schmitt Trigger
High-drive (Clock Driver) inputs compatible with TTL, CMOS Schmitt Trigger
Output compatible with CMOS configurable TRI-STATE Open Drain
Outputs selectable drive
Bidirectional inputs/outputs
Oscillator macros drive
Separate power supply traces output drivers improve noise immunity
input capacitance loading output drivers also been reduced enhance overall circuit performance.
Selectable Output Drive Capability enhanced structure makes possible offer variety output drives given location. Through implementation macro options, users select their output drives each output buffer.
Parallel Buffers High Drives means special macros, output drive current excess achieved paralleling buffers without losing input functions. example, achieve buffers need paralleled through special macros, needed implement output which bidirectional while pins still used inputs.
Dedicated Multiplexed D-Flip/Flops Incorporated into internal array core number dedicated multiplexed D-flip/flops. These flip/flops have been designed achieve significant system speed improvement over logically eqivalent macro function while minimizing silicon space implement. They ideal scan path design techniques well registers counters.
Array Name Equivalent 2-lnput Gates (Note Input Cells Cells Signal Pins Test Pins Pins
SCX6206
SCX6212 1260
SCX6218 1806
SCX6225 2430
SCX6232 3162
SCX6244 4380
SCX6260 (Note 6090
Note Input cells considered part internal cell count.
Note Advanced Architecture with additional 2500 gates on-chip self-test capability.
METAL CAPPED CONTACTS
WELl CONTACT
P-CHANNEL WIDTH
AVAILABLE SITES
TL/U/5725-2
FIGURE Cell
microCMOS PROCESS CIRCUIT PERSONALIZATION
microCMOS process developed National based P-type starling material, N-well technology oxide isolation. After basic transistors formed their respective cells), separate layers metalization placed wafers.
processing steps tooling requirements wafers metal layers common fixed. Circuit defined metal layers VIAs. this way, user's design circuit personality) imposed wafer. gate arrays family same basic internal cell. There eight pairs P-type transistors each cell (see Figure power ground lines (Vqd buses, respectively) down celt. This cell repeated four directions form columns rows core array. structure internal core optimized size each family member. National Semiconductor maintains inventory gate array wafers fabricated before metalization. customer's options designed last three patterns finalized, wafers taken inventory fabrication process completed metal layers. this way, National Semiconductor provide gate array users with quick turn-around cost effective designs while maintaining quality, reliability production control in-house 6-inch) wafer line.
GATE ARRAY BASIC CELL
Figure shows basic internal cell. geometries drawn scale exact topology been modified illustration purposes.
POWER DISSIPATION
outstanding feature microCMOS circuits their power dissipation. CMOS circuits draw electrical current basically reasons:
During transition from logic logic vice versa, there exists finite time when P-channel N-channel devices associated with logic element both conducting. CMOS circuit consumes power during this transition.
When signals change statej distributed capacitance circuit (and load) need either charged discharged. electrical current required this purpose increases power consumption.
Thus, power dissipation dependent operating voltage, nodal capacitance frequency circuit operation. Mathematically speaking:
CV2F estimation purposes, value fiW/gate/MHz gate equivalent used elements within array.
fiW/MHz/output buffer load 1500 p.W/ MHz/output load, used output buffers.
Power dissipation CMOS array typically dominated output buffers driving large capacitive loads. Figure will help estimating power consumption particular design.
tl/u/5725-3
FIGURE Power Consumption Frequency
ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Exceeding following absolute maximum ratings Units suit permanent damage device. Vqd. Supply Voltage Supply Voltage -0.5Vto7V Input Output Voltage High Level Output Input Output Voltage -0.5V +0.5V Current Storage Temperature lDD, Current Power Dissipation (Package Dependent) Ambient Operating Lead Temp. (Soldering, seconds) 300"C Temperature ELECTRICAL CHARACTERISTICS 10%, min/max limits apply over recommended operating temperature range unless otherwise specified.
Symbol Parameter Conditions Units
High Level Input Voltage 0.5V
Level Input Voltage 0.5V
High Level Output Voltage VDDorGND, -0.05
Level Output Voltage GND, (j.A 0.05
High Level Output Current GND, 0.8V
Level Output Current GND, 0.4V
VihTTL Min. High Level Voltage (for Input Option) 0.5V
VilTTL Max. Level Voltage (for Input Option) 0.5V
Input Current (Without Pull-Up Resistor)
Supply Current GND, ju.A
ELECTRICAL CHARACTERISTICS 2ju. process.
Symbol Parameter Units
tPLH tPHL Output Buffer (Non-Inverting, non-TRI-STATE) 0V-5V
tPLH tPHL Input Buffer (TTL Type, Non-Inverting) attr 0V-3V 0.75 1.10 2.95
'PLH tPHL Input Buffer (CMOS Type, Inverting) 0V-5V 0.55 0.50 1.75 1.40
tPLH tpHL tpZL tpZH tPLZ tpHZ Output TRI-STATE (Non-Inverting) 0V-5V Delays Measured Point Between Start Target Voltage
<PLH tPHL <PHL tPLH Internal 2-lnput NAND 0V-5V Load Equivalent Fan-Out mils Interconnect Above with 0.20 0.15 1.55 2.30 0.75 0.55
Topology Routing Resource Distribution
specific topology routing resource distribution have been tailored each family member. Architectural considerations include ratio inputs l/Os total cell count, power consumption package inductance pow-
pins (for simultaneous switching outputs) routing resources consistant with automatic place route software. Internal cell utilizations greater than expected. Individual topologies family summary follow.
VSSE VDDE
l/0'S
6206 Structure
6212 Structure
POWER
RESET
l/0'S-
COLUMNS
-1D-F/F
l/0'S-
l/0'S
VDDE VSSE
TL/U/5725-5
6218 Structure
l/0'S
1/0'S-
COLUMNS-
-ID-F/F
l/0'S
l/O-S
POWER
RESET
TL/U/5725-6
6225 Structure
COLUMNS
TL/U/572S-7
6232 Structure
6244 Structure
TL/U/5725-9
On-Chip Test Circuitry
Each gate arrays provided with dedicated on-chip test circuitry. This circuitry forces outputs specific states facilitate output parametric testing. These parametric tests include leakage current sourcing/sink-ing measurements output pins. on-chip test circuitry enabled dedicated test mode control (TMC) pin. This aside testing cannot used other purpose 6212 6225. However, enhanced devices (6244, 6232, 6218 6206), extra avoided means internal decoding circuit user's design. addition, optional internal control signal derived from available. This used, example, reset control signal internal logic.
self-test capability been further expanded enhanced 6k-gate 6260. additional 2,500 gates dedicated provide on-chip maintenance system that includes chip self-test, system interconnect-test, logic analyzer, system check-sum modes. This self-test feature 6260 unique from rest family well industry. this input will activate on-chip test circuitry. When on-chip test circuitry activated, states outputs determined other inputs; these TRI-STATE test control (TSTC) data test (DT). TSTC share input pins with user's design. They only active when enabled. TSTC input precedence over input. input active following discussion. When TSTC input active, output buffers into high impedance mode. When TSTC active, states output buffers determined input. These inputs assigned input pins.
On-Chip Test Circuitry Truth Table
TSTC Output
Active TRI-STATE
Non-Active Non-Active
Active Non-Active
Definition Test Input States
Non-Inverting Inverting
Macros Macros
Non-Active
Active
Macros
Three types macros available designers use: hardware macros, software macros (National Semiconductor standard library), user generated software macros.
HARDWARE MACROS
family gate arrays offers extensive library hardware macros (Table Each macro been fully characterized functionally proven. designer select those macros that most efficiently implement design. electrical performance macros characterized sets conditions: best worst-case. Under each conditions, output loading specified load equivalent fan-out includes mils length metal interconnect. single input load equivalent 0.13 defined load factor
National Semiconductor very tight wafer fabrication guidelines. However, process parameters still vary from wafer-to-wafer, lot-to-lot. electrical specifications macros take into account such variations.
TABLE Table Macros
Function Macro Name
GATES
Triple 2-lnput NAND C001 (S1)
Dual 3-lnput NAND C002 (S2)
Dual 2-lnput NAND/AND C003 (S3)
Triple 2-lnput C004 (S4)
Dual 3-lnput C005 (S5)
Dual 2-lnput NOR/OR C006 (S6)
Single 2-lnput Exclgsive-OR C053 (S53)
2-lnput 2-Wide OR-NAND with Complement C014 (S14)
2-lnput 2-Wide AND-NOR with Complement C015 (S15)
Triple 4-lnput NAND C017 (D1)
Single 5-lnput NAND (2X) C018 (D2)
Triple 3-lnput NAND with Complement C019 (D3)
Triple 4-lnput C020 (D4)
Single 5-lnput (2X) C021 (D5)
Triple 3-lnput with Complement C022 (D6)
4-lnput Exclusive-OR C046 (T2)
3-lnput Exclusive-OR C047 (D10)
Single 2-lnput Exclusive-NOR C048 (S21)
5-lnput NAND-AND C057 (D57)
5-lnput NOR-OR C058 (D58)
3-lnput Exclusive-NOR C800 (D800)
8-lnput AND/NAND C830 (D830)
8-lnput OR/NOR C878 (D878)
BUFFERS
Triple Buffer C007 (S7)
Quad Inverter C008 (S8)
Dual TRI-STATE Inverting Buffer C009 (S9)
Single Non-Inverting TRI-STATE Buffer C010(S10)
Schmitt Trigger C025 (S24)
Quad Inverter Buffer C043 (S20)
Dual Triple Inverter Buffer C044 (S19)
Buffer C045 (S22)
Buffer C061 (S23)
Buffer C049 (S18)
4-lnput Exclusive-OR Buffer (2X) C801(T801)
Quad Pulldown with Common Enable C808 (S808)
Quad Pulldown with 6-lnput Enable Decode C811 (D811)
Quad Pullup with 6-lnput Enable Decode C812 (D812)
Quad Pullup with Common Enable C832 (S832)
Function Macro Name
LATCHES
NAND Latch wilh 2-lnput NAND C012 (S12)
Latch with 2-lnput C013 (S13)
D-Latch with Set/Reset C062 (D11)
-Bit Transparent D-Latch with Reset Enable C026 (D12)
Triple NAND Latch C027 (D7)
Triple Latch C031 (D8)
FLIP-FLOP
Flip-Flop C023 (D9)
Flip-Flop with Reset C024 (T1)
Flip-Flop with Reset Parallel Load C034 (04)
Flip-Flop with Set/Reset Master Slave C051 (T3)
Flip-Flop with Set/Reset Buffered C060 (T60)
Flip-Flop with Reset Output Only) C064 (D64)
Multiplexed Flip-Flop with Reset C035 (Q35)
Flip-Flop with Reset C037 (F37)
Flip-Flop with Set/Reset Master Slave C052 (Q2)
Flip-Flop with Inverter Reset C036 (Q6)
Flip-Flop with Reset C861 (Q861)
REGISTERS COUNTERS
2-Bit Serial In/Out Parallel Shift Register C039 (F1)
2-Bit Serial/Parallel Shift Register C042 (H4)
Universal Shift Register State C194 (F194)
Up-Down Counter Stage with Parallel Load C038 (F2)
4-Bit Binary Counter Control Logic C871 (0871)
MULTIPLEXER DEMULTIPLEXER
2-to-1 Multiplexer with Single Control Input C056 (S56)
4-to-1 TRI-STATE Multiplexer with Enable C028 (T4)
4-to-1 Multiplexer with Complement Output C029 (T5)
-to-4 Decoder with Active Outputs Enable Input C033 (Q3)
3-to-8 Decoder C138 (H138)
8-Channel Digital Multiplexer C151 (H151)
Quad 2-lnput Multiplexer C158 (Q158)
Quad 2-Channel TRI-STATE Multiplexer C257 (Q257)
TABLE Table Macros (Continued)
Function Macro Name
ARITHMETIC FUNCTIONS
4-Bit Parity Checker C030 (T6)
1-Bit Full Adder C032 (T7)
-Bit with Functions C040 (H2)
2-Bit Magnitude Comparator C041 (H3)
Function Macro Name
INPUTS OUTPUTS
Inputs Only (36) Macro Table
Outputs Only Macro Table
Bidirectional (72) Macro Table
Oscillator Macros Macro Table
Notes Macro Name Note Cell Count cell gates) cells gates) cells gates)
cells gates) cells gates) cells gates)
Note 'C000' designator common reference used between National Semiconductor alternate source purpose consistency with users.
TABLE Macro Table
Macro Type
Input Macro
Output Macro
Input Drive
Output Drive
Each Capable
Input Only Macros)
CMOS (INV) CMOS (NINV) Schmitt
Output Only Macros)
NINV Open Drain
Bidirectional Macros)
CMOS (INV) CMOS (NINV) Schmitt
CMOS (INV) CMOS (NINV) Schmitt
NINV NINV NINV NINV
Oscillator Macros)
Pull-Up; Pull-Down; Neither Pull-Up Pull-Down
PERIPHERAL MACROS
Interfacing gate arrays done through peripheral buffers. There types peripheral cells; input only bi-directional cells (Table II). peripheral macros included count internally available cells.
buffers located around periphery exact configuration dependent particular family member under consideration. Reference section specific locations input cells.
Software Macros
addition pre-designed hardware macros, National Semiconductor offers library software macros. These software macros emulate functions popular 7400 4000 logic families. From designer's vantage point, these software macros utilized though they were hardware macros. actual implementation these higher order functions handled design automation tools process that virtually expands software macro into hardware macro primitives.
Since software macros reside design automation system, designer copy software macro into
sign, modify meet some special consideration, rename then reference special software macro. This procedure coordinated with National's Technology Centers.
National Semiconductor adds popular software macros existing library required meet user needs. representative list shown Table III. cell count 'will exceed' number, unused portions cells available unrelated portions design.
SOFTWARE MACROS (USER GENERATED)
user always option generating higher order software macros. This true regardless where user decides interface with design automation system. workstation level, user simply creates desired function from existing hardware macros, stores function under unique identifier name, then recalls block logic required.
text file mode schematic capture user defines higher order function terms basic hardware macros. These higher order (custom) functions then 'called' same manner other software macro.
TABLE III. Software Macros
Cell Cell Cell Cell
Device Count Device Count Device Count Device Count
7400 7495 13.0 74191 22.0 74399 12.0
7402 7496 18.0 74192 23.0 74445
7403 74100 74193 22.0 74490 13.0
7404 74101 74194 20.0 74521 12.0
7405 74102 74195 12.0 74533 12.0
7406 74103 74196 23.0 74534 21.0
7407 74106 74197 41.0 74540
7408 74107 74198 21.0 74541
7409 74108 74199 26.0 74543 27.0
7410 74109 74237 12.0 74544 27.0
7411 74112 74240 74550 57.0
7412 74113 74241 74551 57.0
7414 74114 74242 74563 12.5
7415 74116 17.0 74243 74564 21.0
7416 74125 74244 74568 28.0
7417 74126 74245 74569 26.0
7420 74128 74251 13.0 74573 13.0
7421 74132 74253 74574 21.0
7422 74133 74256 19.0 74589 48.0
7425 74134 74257 74590 57.0
7426 1.33 74135 74258 74592 58.0
7427 74136 74259 14.0 74593 66.0
7428 74137 12.0 74260 74595 37.0
7430 74138 74261 29.0 74597 51.0
7432 74139 74266 74640
7433 74145 74273 25.0 74643 12.5
7437 74147 15.0 74279 74646 12.5
7438 74148 74280 74648
7440 74149 15.5 74283 22.0 7467ff 60.0
7442 74150 15.0 74289 84.0 74688 11.0
7443 74151 74290 17.0 744002
7444 74152 74292 138.0 744017 21.0
7445 74153 74293 17.0 744020 44.0
7446 17.0 74154 13.0 74294 74.0 744024 22.0
7447 17.0 74155 74295 14.0 744040 38.0
7448 17.0 74156 74298 13.0
7451 74157 74299 43.0
7458 74158 74323 48.0
7464 74159 13.0 74350 16.0
7465 74160 22.0 74354 30.0
7470 74161 19.5 74356 30.0
7471 74162 22.0 74363 13.0
7472 74163 20.0 74364 21.0
7473 74164 26.0 74365
7474 74165 23.0 74366
7475 74166 25.0 74367
7476 74168 22.0 74368
7477 74169 20.0 74373 13.0
7478 74170 40.0 74374 21.0
7483 12.0 74172 57.0 74375
7485 12.0 74173 15.0 74377 26.0
7486 74174 19.0 74378 20.0
7489 84.0 74175 19.0 74379 14.0
7490 13.0 74180 74386
7491 17.0 74181 41.7 74390 26.0
7492 13.3 74182 15.0 74393 24.0
7493 13.0 74189 84.0 74395 14.0
7494 13.0 74190 23.0 74398 12.0
Packaging
family microCMOS gate arrays offered very wide variety packages. user provided with many choices terms both package type lead count. package types offered include ceramic grid arrays (PGA), leaded ceramic chip carriers (LDCC), leadless ceramic chip carriers (LCC), plastic leaded chip carriers (PCC), ceramic DIPs, plastic DIPs.
availability such large variety packages gives user flexibility making following choices: versus plastic mount versus surface mount specific packages offered listed Table IVa. Surface mounting multi-lead components rapidly gaining popularity. provide user flexibility, National Semiconductor offers CMOS gate arrays several surface mount package options: leaded leadless ceramic chip carrier plastic leaded chip carrier. Surface mounting refers component attachment, whereby component leads pads rest surface instead traditional approach inserting leads into through-holes which through board. With surface mounting there solder pads which align with leads pads component. resulting solder joint forms both mechanical electrical connections.
primary reason surface mounting allow leads placed closer together than 0.100 inch standard DIPs with through-hole mounting. Through-hole mounting smaller than 0.100 inch space difficult achieve production generally avoided. move 0.050 inch lead spacing offered with current generation surface mounted components, along with switch from dual-in-line format quad format, achieved threefold increase component mounting density. need achieve greater density major driving force today's marketplace.
Learning surface mount components printed circuit boards requires user implement assembly process typically associated with through-hole insertion/wave soldering assembly methods. Surface mounting involves three basic process steps:
Application solder solder paste printed circuit board
Positioning component onto printed circuit
Reflowing solder solder paste.
Table lists manufacturers currently offering sockets each advanced package options listed this data sheet. matrix which manufacturers contact each socket option provided. listing divided into test/ burn-in production categories. There some individual sockets that will cover both requirements.
TABLE IVa. Gate Array Package Options
Package Type Pins 6206 6212 6218 6225 6232 6244 6260
Plastic DIP,
Ceramic DIP,
(Side Braze)
Plastic Leaded
Chip Carrier,
Ceramic Leaded
Chip Carrier, LDCC
Ceramic Leadless
Chip Carrier,
Ceramic
Grid Array,
TABLE IVb. Socket Vendors
Vendor Location Telephone
Package Type Test/Burn-In Production
Ceramic Grid Array Amp, Textool, Yamaichi, Thomas Betts Amp, Yamaichi Thomas Betts
Leaded Ceramic Chip Carrier Yamaichi Yamaichi
Leadless Ceramic Chip Carrier Amp, Plastronics, Textool Amp, Plastronics
Plastic Chip Carrier Textool Amp, Burndy, Robinson/Nugent
Jnc. Textool
Harrisburg, Irving,
<715) 564-0100 (214) 259-2678
Plastronics Thomas Betts
Irving, Raritan,
(214) 258-1906 (210) 469-4000
Robinson/Nugent Yamaichi
Albany, Napenthe Dist.
(812) 945-0211 Palo Alto.
Burndy (415) 856-9332
Norwalk.
(203) 838-4444
Propagation Delays
Propagation delays CMOS arrays function several factors:
Supply voltage
Junction temperature
Process tolerance
Fan-out loading
Interconnection routing
Input signal direction
assist designer evaluating circuit performance under operating conditions, National Semiconductor guarantees parametrics over full voltage temperature range, well best-case worst-case propagation delays. Process tolerance included specifications.
Delays other than three fan-out loading extrapolated loads other than shown.
example: 2-input NAND (Si) drives loads. What worst-case delay? From Table
tpLH 0.75 loads)
tpLH 2.40 loads)
delay load 2.40 0.75)/3 0.55
Total delay base delay load) loads
4.05 0.75 (0.55
What delay power supply maintained junction temperature (approximately ambient)?
0.95
0.91
0.75
0.66
TL/U/5725-10
FIGURE CMOS Propagation Delays Function Temperature
From scaling factors (Table note): Worst-case junction temperature junction temperature
0.3%
Improvement factor
Worst-case voltage voltage 5.0V
4.5V
4.5V)
Improvement factor (5.0V
Derating factor 0.06)(1 0.1) 0.646 Total delay (scaled) 4.05(0.846) 3.43 This form calculation handy making estimates critical paths during initial design phase used guide determine estimated performance NSC's process. actual performance prediction will provided design automation system after designer functionally verified design logic simulator. Propagation delays function temperature supply voltage shown Figures respectively. Utilization these curves will speed estimation performance other than specified values. Representative macro types process (Table presented comparison. Reference family macro library book complete specifications.
4.75 5.25
TL/U/5725-11
FIGURE CMOS Propagation Delays Function Supply Voltage
Best-Case Worst-Case
Temperature Supply Voltage 5.5V Extreme Process Parameters Temperature Supply Voltage 4.5V Extreme Process Parameters
TABLE
Symbol Function Best-Case Worst-Case CLOAD (PF)
lPLH tpHL tpLH JPHL
2-NAND 0.095 0.39 0.19 0.67 0.75 2.40 0.95 4.05
3-NAND 0.09 0.37 0.27 0.92 0.95 2.65 1.65 5.75
2-NOR 0.16 0.62 0.15 0.51 4.15 0.95 2.85
3-NOR 0.23 0.85 0.16 0.52 1.65 1.13 3.05
Clock Buffer 0.07 0.24 0.13 0.33 0.45 1.45 0.55 1.65
Inverter 0.095 0.36 0.16 0.52 2.35 0.75
2-XOR 0.11 0.54 0.16 0.53 5.65
Flip-Flop 0.71 1.02 0.59 0.94 5.12 4.38 6.25
0.35 0.64 0.54 0.98 2.38 5.37 6.62
TRI-STATE Inverter 0.18 0.60 0.18 0.70 4.25 1.35 4.15
TRI-STATE Buffer 0.30 0.53 0.27 0.53
Inverting Input Buffer CMOS 0.23 0.45 0.19 0.39 0.85 2.30 0.70 1.80
Input Buffer 0.33 0.60 0.39 0.78 3.70 2.45 4.80
Short Circuit Input CMOS 0.04 0.15 0.04 0.15 0.07 0.50 0.07 0.50
Input 0.33 0.60 0.39 0.78 2.45
Output* 0.62 1.15 0.78 1.55 5.75 9.75
Input (Inverting) CMOS 0.23 0.45 0.19 0.39 0.85 2.30 0.70 1.80
Output* 0.62 1.15 0.78 1.55 4.40 5.75 9.75
Short Circuit Input CMOS 0.04 0.15 0.04 0.15 0.07 0.50 0.07 0.50
Output* 0.62 1.15 0.78 1.55 4.40 5.75 9.75
Output 0.65 1.17 0.63 1.45 4.75 8.25 8.25
Note: delays nanoseconds. 2-micron. Load Factor.
active mode. Voltage Derate 2.0%/100 from 4.5V. 0.13
Temperature Derate from 100"C.
Design Automation System
design automation system offers user variety interface points techniques. Figure shows standard gate array development flow responsibilities. Alternative flows available presented Section
standard flow consists four major quadrants. They user's site, user's responsibilities, National Semiconductor's technology center, National Semiconductor's responsibility. These represent 'where' 'who' aspects task responsibility location.
User Site
Logic design definition user's responsibility completed his/her site.
design file consists netlist (wiring diagram) test vectors (pattern file). Each generated text file output from 'workstation'. syntax these files 'hardware design language'. evaluation acceptance completed prototypes done user his/her facilities. National Semiconductor offers technical assistance necessary.
USER'S SITE
TECHNOLOGY CENTER
LOGIC DESIGN
TRAINING
DESIGN FILE
NETLIST TEST VECTORS
USER'S RESPONSIBILITY
LOGIC FAULT
SIMULATION 6RADING
TL/U/5725-12
FIGURE Standard Gate Array Development Process Responsibilities
National Semiconductor Technology Center
Training includes actual interaction with design automation system and, depending level user experience, requires from three five days complete. considerations necessary successful completion design covered during training. Topics such hardware (i.e., speed, power, pinouts) software considerations (i.e., logic simulation, fault grading, critical path analysis) tailored meet user's needs. Training provided closest technology center. Contact local sales representative location nearest you. Functional verification logic accomplished submitting netlist pattern files logic simulator. simulator will predict output results specified logic applied vectors. designer then determine specified logic meets design objectives. Simulation under actual 'loaded' conditions occurs after functional verification fault grading. Functional verification responsibility user.
Fault grading measure ability supplied vectors detect induced logic errors (i.e., on-chip shorts). vectors supplied eventually become functional portion final production test tape. important that fault grading figure merit reach 85%. Fault grading responsibility user.
Performance estimation prediction that logic simulator makes considering actual macro loading projection interconnect lengths. This projection based algorithm which relates fan-out probable trace length. Performance estimation responsibility user.
Place route actual implementation user's design file. pieces design automation software used complete routing.
Automatic place route software completes majority interconnects most cases completes entire array.
Interactive graphics software used complete un-routed interconnects.
Place route responsibility National Semiconductor.
Performance verification rerunning 'performance estimation' software with actual cell placements associated trace lengths. Performance verification responsibility user.
Mask generation, wafer fab, assembly test completed National Semiconductor.
Prototype evaluation acceptance responsibility user.
National Semiconductor large staff applications consulting engineers available assist users point array development process.
WORKSTATION SUPPORT
above capabilities, specifically front-end design functions (such schematic capture, netlist entry, logic simulation timing estimation), also available Valid, Daisy, Mentor workstations. Such capabilities will extended other popular design stations such Systems
allow workstation users properly interface with SCX-series gate arrays, National provides workstation software design kit. consists floppy discs containing logic symbols macros, netlist extractor model timing data pre-layout simulation timing estimation. This design developed, distributed, maintained updated solely National. Some more time-consuming tasks such fault grading, auto-place-and-route post-layout logic verification performed mainframe computer. typical design flow between workstation mainframe illustrated Figure Generally, there three design paths follows:
Path capture user's workstation; then transfer unsimulated design files (netlist test vectors) NSC's mainframe logic simulation, fault grading place-and-route.
Path capture, logic simulation timing verification user's workstation; then transfer simulated design files NSC's mainframe resimulation (one pass), fault grading place-and-route.
Path capture, logic simulation, timing verification place-and-route user's workstation; then transfer database file NSC's mainframe resimulation (one pass), fault grading tape generation. (This future capability.)
WORKSTATION MAINFRAME
nonnrn
TL/U/5725-15
FIGURE National's Workstation-to-Mainframe Semi-Custom Design Flow
10.0 Design Example
most popular ways interfacing design automation system alphanumeric text entry workstation output. different example will given each. either case design automation system requires basics files operate.
Network (File): network file 'wiring diagram' design. represents array 'wired'. More specifically, manner which hardware macros interconnected. syntax network file specified hardware design language (HDL). Pattern (File): pattern file represents stimuli sequence signals used exercise design specified network file. pattern file ultimately becomes functional portion final test tape used screen production devices.
logic simulator operates network pattern files predicts logic output function pattern file.
Data Entry
PREDICTED OUTPUT
TL/U/5725-13
simulator modes operation. first mode used verify logical integrity design. second mode considers capacitive circuit loading anticipated wire lengths. result second mode performance that expected after circuit been placed routed.
basic form network file follows: {NETWORK ('BEGIN NETWORK FILE*)
ETC. ('LIST INPUT NAMES') OUTA OUTB ETC. ('LIST OUTPUT NAMES')
macro call syntax following circuit fragment specified.
CLOCK
TL/U/5725-14
SPECIFIES PARTICULAR MACRO TYPE
$$AN0
SPECIFIES HARDWARE MACRO
CIRCUIT NAME ASSOCIATED WITH -ABOVE MACRO
DELIMITER
CLKB CLRB OGBI CLOCK CLKB CLEAR
INPUTS MACRO ELEMENTS OUTPUTS FROM MACRO ELEMENTS
TL/U/5725-18
designer were using alphanumeric text mode data entry, each unique macro macro type would specified above manner until entire network been specified.
workstation mode schematic capture designer would call name each desired macro, then graphically interconnect each macro required fashion. workstation would then 'compile' schematic into network file.
MACRO CALLS
'SPECIFY MACROS INTERCONNECTS*)
COMMENTS ('MAKE COMMENTS')
10.1 TEXT MODE
OUTC
FIGURE Design Four-Bit Latch with TRi-STATE Output Presented.
TL/U/5725-16
Listing
snetwork
sinput clock clear
soutput outa outb outc outd
dm74173 macro
ssubu
ssano
clkb clrb clock clkb clear
ssubu
ssan1
cono
ssubu
ssan2
ssubu
ssan3
ssubu
ssan4
ssubu
ssan5
ssubu
ssan6
coni clrb
ssubu
ssan7
coni clrb
ssubu
ssan8
coni clrb
ssubu
ssan9
coni clrb
ssubu
ssan10
outa outb
ssubu
ssan11
outc outd
10.2 WORKSTATION MODE
FIGURE
Listing
$NETWORK
SINPUT CLEAR CLOCK
SOUTPUT OUTA OUTB OUTC OUTD
SSUBU
SSXCMP
XSIG29 XSIG27 XSIG18 XSIG27
SSUBU
SSXCMP
XSIG33 XSIG41 XSIG34 XSIG20 XSIG21
SSUBU
SSXCMP
OUTA OUTB XSIG41 XSIG22 XSIG40 XSIG22
SSUBU
SSXCMP
OUTC OUTD XSIG39 XSIG22 XSIG38 XSIG22
SSUBU
$$XCMP
XSIG22 XSIG20 XSIG21 XSIG19 XSIG18 XSIG19 CLEAR CLOCK
SSUBU
SSXCMP
OPEN-1 XSIG37 XSIG30 XSIG29 XSIG27
SSUBU
SSXCMP
OPEN-2 XSIG36 XSIG31 XSIG29 XSIG27
SSUBU
SSXCMP
OPEN-3 XSIG35 XSIG32 XSIG29 XSIG27
SSUBU
SSXCMP
OPEN-4 XSIG34 XSIG33 XSIG29 XSIG27
SSUBU
SSXCMP
XSIG30 XSIG38 XSIG37 XSIG20 XSIG21
SSUBU
SSXCMP
XSIG31 XSIG39 XSIG36 XSIG20 XSIG21
SSUBU
SSXCMP
XSIG32 XSIG40 XSIG35 XSIG20 XSIG21
10.3 PATTERN FILE
SCYCLE 1000 1000 REPRESENTS NUMBER INTERVALS CYCLE
PATTERN FILE CODING FOLLOWS
PATTERN FILE TESTING DM74173 TEST SHOULD SWEEP CYCLES CLEAR
INTERVAL PICOSECONDS
_/OD1 ~\0D2
CLOCK
13-14 15-16
11-12 11-12 11-12 11-12
INPUT SIGNALS USED SIMULATE NETWORK
(01: 1-16) SINGLE CLOCK REPEATING THROUGH CYCLE
CIRCUIT INPUTS SPECIFIED CYCLE. OTHER CYCLES
CIRCUIT INPUT SPECIFIED CYCLE. OTHER CYCLES
TL/U/5725-19
10.4 SIMULATOR OUTPUT
OUTPUTS
INPUTS SPECIFIED SPECIFIED PATTERN FILE PATTERN FILE
NNNN
ABCD
1111
*157 1111
0000
1111
0000
1111
1111
0000
1111
0000
0000
*140 0000
0000
1111
1111
0000
*129 0000
0000
0000
0000
oooo uuuu
abcd
xxxx 0000 0000 0000 0000 0000 zzzz zzzz zzzz zzzz zzzz
zzzz zzzz zzzz zzzz
EQUENTIAL NUMBERS REPRESENT TIME CYCLES
ZZZZ HIGH IMPEDANCE STATE 1111= HIGH STATE 0000 STATE "Intermittent numbers represent settling time hundred-picoseconds that occur between time cycles.
11.0 Alternative Interfaces
Flexibility design automation system allows variety user/vendor interfaces. Options include:
User supplies schematic, timing diagrams parametric specifications. National Semiconductor implements array (Turn-Key design).
User 'captures' design facility National Semiconductor technology center. National Semiconductor supports wide range communication protocols interfacing industrial (mainframe) personal computers. These available with without error control communication rates 9600 baud.
User follows basic array development flow specified Figure
User generates logic simulator compatible files from workstation. Completes array using National Semiconductor's design automation system.
User generates compatible design files logic verification his/her simulator, then interfaces design automation system either fault grading, performance estimation, 'place route'.
User supplies completed design files from National Semiconductor's alternate source, effectively entering design automation system just prior digitizing.
User provides design files necessary mask generation, essentially 'customer owned tooling' (COT) approach.
12.0 Training Technical Services
facilitate users design with National's CMOS gate arrays, training offered regular basis National's worldwide technology centers. Santa Clara training/design center, multiple workstations used complement basic training. Additional workstations located private offices also available customers enter, capture verify their designs. part technical services, experienced design consultants from National will available training/design center provide on-the-spot engineering assistance.
training, workstation design other technical services provided National's Training, Layout, Consulting (TLC) Group. Overall technical customer-support services include following:
Customer training
Technical documentation
Design assistance
Simulation support
Workstation support
Turnkey design
Place-and-Route implementation
Mainframe software qualification
Workstation software qualification
technical assistance, contact National's Applications Group (408) 721-4614.
13.0 Technology Centers
National Semiconductor Headquarters,
2900 Semiconductor Drive, Santa Clara, California 95051 (408) 721-4614, TWX: (910) 339-9240
National Semiconductor Corp.
Bedford Street, Suite Burlington, 01803 Telephone: (617) 273-0964
National Semiconductor S.A.
Expansion 1000
Redoute
F-92260 Fontenay-aux-Roses, France
Telephone: 33-1-660-8140
Telex: 842-250959
National Semiconductor GmbH
Industriestrasse
D-8080 Fuerstenfeldbruck, Germany Telephone: 49-8141-103-1 Telex: 841-527649
National Semiconductor
2016
Stensaetravaegen 4/II S-12702 Stockholm, Sweden Telephone: 46-8-970190 Telex: 854-10731
National Semiconductor
Maples Kembrey Park Swindon Wilts, England Telephone: 44-793-614141 Telex: 851-444674
National Semiconductor
Solferino 1-20121 Milan, Italy Telephone: 39-2-3452046 Telex: 332835
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION. used herein:
Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
National Semiconductor Corporation
2900 Semiconductor Drive P.O. 56090 Santa Clara, 95052-6090 Tel: (408) 721-5000 TWX: <910) 339-9240
National Semiconductor GmbH
Westendstrasse 193-195 D-8000 Wesl Germany Tel: (089)5 Telex: 522772
Japan Ltd.
4-403 Ikebukiro. Toshima-ku, Tokyo 171, Japan Tel: (03| 966-2131 FAX: 011-81-3-988-1700
National Semiconductor Hong Kong Ltd. Southeast Asia Marketing
Austin Tower, Floor 22-26 Austin Avenue Tsimshatsui. Kowloon. Tel: 3-7231290. 3-7243645 Cable: NSSEAMKTG Telex: 52996 NSSEA
National Semicondutom Brasi Ltd*
Brig. Faria Lima, Andar
01452 Paulo, Brasil Tel: (55/11) 212-5066 Telex: 391-1131931 NSBR
National Semiconductor Australia) PTY, Ltd.
21/3 High Street Bayswater, Victoria 3153 Tel: (03) 729-6333 Telex: AA32096
National does assume responsibility crcuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications.
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