CMOS 8-Bit Microcomputer TMP88CS42N/F TMP88CS42 high-speed,
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TMP88CS42
CMOS 8-Bit Microcomputer
TMP88CS42N/F
TMP88CS42 high-speed, high-function 8-bit microcomputer built around TLCS-870/X series core incorporating sine wave drive (Programmable Motor Driver: PMD), well 10-bit converter, multifunction timer/counters, synchronous/asynchronous serial interfaces.
Product Package Built-in
TMP88CS42F Kbytes bytes P-QFP64-1420-1.00A TMP88PS42F
TMP88CS42N P-SDIP64-750-1.78 TMP88PS42N
8-bit single-chip microcomputer TLCS-870/X series
Minimum instruction execution time: 0.20 (when operating with 20.0 MHz)
Fundamental machine instruction: kinds, instructions
Interrupt sources external, internal)
Input/Output port: pins
Large-current output: pins (typ. mA),
capable direct drive
Programmable motor driver: channels (PMD)
Sine wave drive circuit (built-in sine wave data-only RAM)
Rotor position detect function
Motor control timer capture function
Overload protective function
Auto commutation, auto position detection start
Watchdog Timer (WDT)
Time Base Timer (TBT)
Divider output function (DVO)
External view package
P-QFP64-1420-1.00A
TMP88CS42F TMP88PS42F
P-SDIP64-750-1.78
TMP88CS42N TMP88PS42N
030519EBP1
information contained herein subject change without notice.
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88CS42-1 2003-06-03
TMP88CS42
16-bit timer/counter: channels (TC1, CTC)
TC1: Timer, external trigger timer, event counter,
window mode, pulse width measurement, PPG1 (Programmable Pulse) output
CTC: Timer, event counter,
PPG2 (Programmable Pulse) output
8-bit timer/counter: channels (TC3, TC4, TC5, TC6)
TC3: Timer, event counter, capture
TC4: Timer, event counter, (Programmable Divider Output), (Pulse Width Modulation),
UART baud rate
TC5, TC6: channels cascaded 16-bit timer
Timer, event counter, (Pulse Width Modulation), (Programmable Pulse) output, (Programmable Divider Output)
10-bit successive approximation type converter (with sample hold)
Analog input: channels
Serial interface: channels (SIO, UART)
8-bit (synchronous): channel
8-bit UART (asynchronous): channel (selectable pins use)
8-bit high-speed PWM: channels
power dissipation mode
STOP mode: Operation halted (battery)
IDLE mode: halted only peripheral hardware operating, returned normal interrupt
Operating voltage: MHz)
88CS42-2
2003-06-03
TMP88CS42
Assignments (Top View)
P-QFP64-1420-1.00A
_(DVO, TC5I)
(PPG1, PD05, PWM5) (PDU2) (PDV2) (PDW2) (CL2) (EMG2) (U2) (V2) (W2) (X2) (Y2) (Z2)
<t<t>CLCLCLO-CLCLCLCLCL
OOlOSNlil^'imfN
ouiossioin'im
QFP64 (Top View)
(AIN6) (AIN5) (AIN4) (AIN3) (AIN2) (AIN1) (AINO) (CTC) (PPG2) (SO,TXD1) (SI, RXD1) (SCK) (PDU1)
tnttttntttttt
QrMfMujfMfnmmmtflmmm^^ >CLCLCOCLCLCLCLCLO-CLCLCLCLCL
luQQ
Illi
88CS42-3
2003-06-03
TMP88CS42
Assignments (Top View)
P-SDIP64-750-1.78
(U2)
(V2)
(W2)
(X2)
(Y2)
(Z2)
XOUT
TEST
(TC3, INT3)
(TC4, INT4, PWM4, PD04)
RESET
(STOP, ijTF5)
(Z1)
(Y1)P31
(X1)
(W1)
(V1)P34
(U1)
(EMGT)
(CLI)
(PDW1)
(PDV1)
(PDU1)
(SCK)
(RXD1,
(TXD1,
(PPG2)
(CTC)
(AINO)
(EMG2)
P50(CL2)
(PDW2)
(PDV2)
(PDU2)
(PD05, PWM5, PPG1)
P13(TC5l,DVO)
(INT2,TC1)
(INT1)
(INTO)
(HPWM1)
(HPWM0)
(PD06, PWM6, PPG6, TXD2)
(TC6I, RXD2)
AVSS
AVDD
VAREF
(AIN1 DBOUT2)
(AIN14)
(AIN13)
(AIN12)
(AIN11)
(AIN10)
(AIN9)
(AIN8)
(AIN7, DBOUT1)
(AIN6)
(AIN5)
(AIN4)
(AIN3)
(AIN2)
(AIN1)
88CS42-4
2003-06-03
TMP88CS42
Block Diagram
(AIN8tO
88CS42-5
2003-06-03
TMP88CS42
Functions (1/2)
Name Function
(TC6I, RXD2) (input, input) 4-bit programmable input/output port, (hysteresis input, tristate output/open-drain output) input output mode bitwise. tristate open-drain output bitwise. When using timer/counter UART input, these pins input mode. When using timer/counter, UART, output, these output mode. Timer/counter input UART input
(output, output) Timer/counter output (PD06, PWM6, PPG6) UART output
(PD06, PWM6, PPG6, TXD2)
(HPWMO) (output) High-speed PWMO output
(HPWM1) High-speed PWM1 output
P1O(TNT0) (input) 8-bit programmable input/output port, (hysteresis input, tristate output) input output mode bitwise. When using external interrupt, timer/counter, position signal input, these pins input mode. When using output PPG1 output TC1, these pins output mode after setting output latch External interrupt input
(INT1) External interrupt input
(INT2, TC1) (input, input) External interrupt input timer/counter input
(TC5I, DVO) (input, output) Timer/counter input divider output
(output, output, output) Timer/counter output (PD05, PWM5) Timer/counter output (PPG
(PD05, PWM5, PPG1)
(PDU2) (input) Motor control position signal input (U2, phases)
(PDV2)
(PDW2)
(INT5, STOP) (input, input) 3-bit input/output port, (hysteresis input, open-drain output) When using these pins timer/counter, external interrupt, STOP mode exiting input, output latch External interrupt input, STOP mode exiting input
(TC3, INT3) Timer/counter input external interrupt input
(TC4, INT4, PWM4, PD04) (input, input output, output) Timer/counter4 input external interrupt input, PWM4 output, PD04 output
(Z1) (output) 8-bit programmable input/output port, (hysteresis input, tristate output/open-drain output) input output mode bitwise. tristate open-drain output bitwise. directly drive with large current. When using motor control output, these pins output mode. Also, output latch When using error detection/overload protective input, these pins input mode. Motor control output (Z1, Y1,X1, phases)
(Y1)
P32(XD
P33(WD
P35(UD
(EMGD (input) Motor control error detection input
(CLT) (input) Motor control overload protective input
(PDWD (input) 8-bit programmable input/output port, (hysteresis input, tristate output/open-drain output) input output mode bitwise. tristate open-drain output bitwise. directly drive with large current. When using timer/counter, SIO, position signal input, these pins input mode. When using SIO, UART output, these pins output mode. Also, output latch Motor control position signal input (W1.V1.U1 phases)
(PDVD
(PDUD
(SCK) clock input/output
(SI, RXDD (input) input, UART data input
(SO, TXDD (output) output, UART data output
P46(PPG2) (output) Compare timer/counter output
P47(CTC) (input) Compare timer/counter input
88CS42-6
2003-06-03
TMP88CS42
Functions (2/2)
Name Function
P50(CL2) (input) 8-bit programmable input/output port, (hysteresis input, tristate output/open-drain output) input output mode bitwise. tristate open-drain output bitwise. directly drive with large current. When using motor control output, these pins output mode. Also, output latch When using error detection/overload protective input, these pins input mode. Motor control overload protective input
(EMG2) Motor control error detection input
(U2) (output) Motor control output (Z2, phases)
(V2)
(W2)
(X2)
(Y2)
P57(Z2)
(input) 8-bit programmable input/output port, (tristate output) input output mode bitwise. When using analog input, these pins input mode. Also, output latch When using motor control output, these pins output mode. Also, output latch converter analog input
(AIN2)
(AIN3)
(AIN5)
(AIN7, DBOUT1) (input, output) converter analog input, Motor control output
P70(AIN8) (input) 8-bit programmable input/output port, (tristate output) input output mode bitwise. When using analog input, these pins input mode. Also, output latch When using motor control output, these pins output mode. Also, output latch converter analog input
P71(AIN9)
(AIN10)
(AIN11)
(AIN12)
(AIN13)
(AIN14)
(AIN15, DBOUT2) (input, output) converter analog input, Motor control output
TEST Input Used shipping test. this low.
RESET Input Reset signal input
Input High-frequency resonator connecting pins. When using external clock input, feed leave XOUT open.
XOUT Output
Input
Power supply
AVSS conversion circuit
AVDD Power supply conversion circuit
VAREF Analog reference voltage conversion
88CS42-7
2003-06-03
TMP88CS42
Functional Description Functions Core
core consists mainly CPU, system clock control circuit, interrupt control circuit. This chapter describes core, program memory, data memory, reset circuit TMP88CS42.
Memory Address
memory TMP88CS42 consists four blocks: ROM, RAM, (Special Function Registers), (Data Buffer Registers), which mapped into 1-Mbyte address space. general-purpose registers consist banks, which mapped into address space. Figure shows memory address TMP88CS42.
00000H 0003Fh 000BFh bytes Special Function Register
(128 bytes) bytes General-purpose Register Bank registers banks)
Kbytes) OOOCOH 008BFh 2048 bytes Random-Access Memory
01F80H 01FFFh bytes Data Buffer Register (Peripheral hardware control register/ status register)
Kbytes) 04000h 13EFFh 65280 bytes Program Memory
FFFOOH FFF3Fh FFF7FH bytes Interrupt Vector Table
bytes Vector Table Vector Call Instructions
FFF80H FFFFFH bytes Interrupt Vector Table
TMP88CS42 ROM: Read-only Memory SFR: Special Function Registers DBR: Data Buffer Registers Program memory Input/output port Input/output port Vectortable Peripheral hardware control register Peripheral hardware control register RAM: Random Access Memory Peripheral hardware status register Peripheral hardware status register Data memory System control register Stack Interrupt control register General-purpose register bank Program status word
Figure 1-1. Memory Address
88CS42-8
2003-06-03
TMP88CS42
Program Memory (ROM)
TMP88CS42 contains 64-Kbyte program memory (mask ROM) located addresses 04000h 13EFFh addresses FFFOOh FFFFFH.
Data Memory (RAM)
TMP88CS42 contains 2-Kbytes 128-byte RAM. first 128-byte location (00040 000BFH) internal shared with general-purpose register bank.
content data memory indeterminate power-on, sure initialize initialize routine.
Example: Clearing internal TMP88CS42 (clear addresses except bankO).
0048H
877H
start address. initialization data (00h)-; byte counts (-1).
SRAMCLR
SRAMCLR
Note: Because general-purpose registers exist RAM, never clear current bank address RAM. above example, cleared except bank
88CS42-9
2003-06-03
TMP88CS42
System Clock Control Circuit
System Clock Control Circuit consists clock generator, timing generator, standby control circuit.
Timing Generator Control Register
TBTCR
Clock Generator
00036h
XOUT
High-frequency Clock Oscillator Circuit
Timing Generator
Standby Control Circuit
System Clocks
00038
00039
SYSCR1
SYSCR2
System Control Register
Figure 1-2. System Clock Control Circuit
1.4.1 Clock Generator
Clock Generator generates fundamental clock which serves reference system clocks supplied core peripheral hardware units.
high-frequency clock (frequency obtained easily connecting resonator XOUT pins. clock generated external oscillator also used. this case, enter external clock from leave XOUT open. TMP88CS42 does support network that produces time constant.
High-frequency Clock
XOUT
Using crystal ceramic resonator
XOUT
(Open)
Using external oscillator
Figure 1-3. Example Connecting Resonator Adjusting oscillation frequency
Note: Although hardware functions provided that allow fundamental clock monitored directly from outside, oscillation frequency adjusted forwarding pulse fixed frequency (e.g., clock output) port monitoring program while interrupts watchdog timer disabled. systems that require adjusting oscillation frequency, adjustment program must created beforehand.
88CS42-10
2003-06-03
TMP88CS42
1.4.2 Timing Generator
Timing Generator generates various system clocks from fundamental clock that supplied core peripheral hardware units. timing generator following functions:
Generate main system clock Generate divider output (DVO) pulse Generate source clock time base timer Generate source clock watchdog timer Generate internal source clock timer counter Generate warm-up clock when exiting STOP mode
Configuration Timing Generator
timing generator 3-stage prescaler, 21-stage dividers, machine cycle counter. When reset when entering/exiting STOP mode, prescaler dividers cleared
Figure 1-4. Configuration Timing Generator
88CS42-11
2003-06-03
TMP88CS42
CGCR (0030h)
DV1CK
(Initial value: 000**000)
DV1CK Selects input clock first fc/4
divider stage fc/8
Note high-frequency clock [Hz], Don't care
Note CGCR Register bits show indeterminate value when read. Note sure write bits
Figure 1-5. Divider Control Register
Timing Generator Control Register
TBTCR (00036h) (Initial value: 0000 0000)
DVOEN DVOCK TBTEN TBTCK
Note Don't care
Note sure write
Figure 1-6. Timing Generator Control Register
Machine cycle
Instruction execution internal hardware operations synchronized system clocks. minimum unit instruction execution referred "machine cycle". TLCS-870/X series types instructions, from 1-cycle instructions which executed machine cycle 15-cycle instructions that require maximum machine cycles.
machine cycle consists four states S3), with each state comprised main system clock cycle.
Main
System Clock States
-Machine cycle-
(0.20 MHz)
Figure 1-7. Machine Cycles
88CS42-12
2003-06-03
TMP88CS42
1.4.3 Standby Control Circuit
Standby Control Circuit starts/stops high-frequency clock oscillator circuit selects main system clock. System Control Registers (SYSCR1, SYSCR2) used control operation modes this circuit. Figure shows operation mode transition diagram. Figure shows System Control Registers.
Single clock mode
Only high-frequency clock oscillator circuit used. Because main system clock generated from high-frequency clock, machine cycle time single clock mode 4/fc [s].
NORMAL mode
this mode, core peripheral hardware units operated with high-frequency clock. TMP88CS42 enters this NORMAL mode after reset.
IDLE mode
this mode, watchdog timer turned while peripheral hardware units operated with high-frequency clock. IDLE mode entered into using System Control Register device placed this mode back into NORMAL mode interrupt from peripheral hardware external interrupt. When (interrupt master enable flag) (interrupt enabled), device returns normal operation after interrupt been serviced. When (interrupt disabled), device restarts execution beginning with instruction next that placed IDLE mode.
STOP mode
entire system operation including oscillator circuit halted, retaining internal state immediately before being stopped, with minimal amount power consumed. STOP mode entered into using System Control Register exited STOP input (level edge selectable). After elapse warm-up time, device restarts execution beginning with instruction next that placed STOP mode.
releasing mode
STOP Mode
Oscillator Circuit Peripheral Circuit Machine Cycle Time
Operation Mode High Frequency Frequency Core
RESET Reset Reset
NORMAL Oscillate Operate Operate 4/fc
IDLE Stop
STOP Stop Stop
Figure 1-8. Operation Mode Transition Diagram
88CS42-13
2003-06-03
TMP88CS42
System Control Register
STOP RELM REOUTEN
(Initial value: 0000 00**)
STOP Place device STOP mode Keep core peripheral hardware operating Stop core peripheral hardware (placed STOP mode)
RELM Select method which device released from STOP mode Released rising edge STOP input Released high level STOP input
RESelect operation mode after exiting STOP mode Returns NORMAL mode Reserved
OUTEN Select port output state during STOP mode High-impedance state Hold output
When Returning NORMAL Mode
Unit warm-up time when exiting STOP mode DV1CK DV1CK=
216/fc 216/fc 214/fc Reserved 217/fc 217/fc 215/fc Reserved
Note When entering from NORMAL mode into STOP mode, always sure REto
Note When device released from STOP mode RESET input, always returns NORMAL mode
regardless REis set. Note high-frequency clock [Hz], Don't care
Note values SYSCR1 Register bits indeterminate when read.
Note Releasing device from STOP mode causes STOP automatically cleared "0".
Note Select appropriate value warm-uptime according characteristic resonator used.
System Control Register
SYSCK IDLE (Initial value: 1000 ****)
Control high-frequency oscillator Stop oscillation Continue start oscillating
SYSCK Select (write)/monitor (read) system clock High-frequency clock (NORMAL/IDLE) Reserved
IDLE Place device IDLE mode Keep operating Stop (IDLE mode entered)
Note When exiting STOP mode, SYSCK automatically rewritten according RE(SYSCR1 Register
REOperation Mode after Releasing STOP Mode SYSCK
NORMAL mode operation
Note When cleared when cleared while SYSCK device reset. Note WDT: Watchdog timer, Don't care
Note values SYSCR2 Register bits indeterminate when read.
Note Change operation mode after disabling external interrupts. interrupts enabled after changing
operation mode, clear interrupt latches appropriate advance. Note sure write
Figure 1-9. System Control Registers
88CS42-14
2003-06-03
TMP88CS42
1.4.4 Controlling Operation Modes
STOP mode
STOP mode controlled System Control Register (SYSCR1) STOP input. STOP shared with port INT5 (external interrupt input STOP mode entered into setting STOP (SYSCR1 Register During STOP mode, device retains following state.
Stop oscillation, thereby stopping operation internal circuits.
data memory, register, program status word, port output latch hold state which they were immediately before entering STOP mode.
Clear prescaler divider timing generator
program counter holds instruction address instructions ahead that placed device STOP mode (e.g., "SET (SYSCR1).7").
device released from STOP mode active level edge STOP input selected RELM (SYSCR1 Register
Note: Before entering STOP mode, sure disable interrupts. This because signal external interrupt changes state during STOP (from entering STOP mode till completion warm-up) interrupt latch that device accept interrupt immediately after exiting STOP mode. Also, when reenabling interrupts after exiting STOP mode, sure clear unnecessary interrupt latches beforehand.
Released level (when RELM
device released from STOP mode high level STOP input.
instruction place device STOP mode ignored when executed while STOP input level high, device immediately goes release sequence (warm-up) without entering STOP mode. Therefore, before STOP mode entered while RELM 1,the STOP input must verified program. There following methods this verification.
Testing port status
INT5 interrupt (interrupt generated falling edge INT5 input)
Example Entering STOP mode from NORMAL mode testing port
(SYSCR1), 01010000B Select released from STOP mode
level
SSTOPH: TEST (P2DR).
Wait until STOP input goes
SSTOPH
(SYSCR1).
Place device STOP mode
88CS42-15
2003-06-03
TMP88CS42
Example Entering STOP mode from NORMAL mode INT5 interrupt
PINT5: TEST (P2DR). enter STOP mode port
SINT5 input level high, eliminate noise
(SYSCR1), 01010000B Select released from STOP mode
level
<r-0
(SYSCR1). Place device STOP mode
SINT5: RETI
STOP XOUTpin
NORMAL operation
STOP mode
Detect STOP input program before entering STOP mode
Warm-up
NORMAL operation
Released from STOP mode hardware iAlways released high level STOP input
Figure 1-10. Released from STOP Mode Level
Note Once warm-up starts, device does return STOP mode even when STOP
input pulled again. Note RELM changed (level mode) after being setto (edge mode), STOP mode remains unchanged unless rising edge STOP input detected.
Released edge (when RELM
device released from STOP mode rising edge STOP input. This method used applications where relatively short time program processing repeated certain fixed intervals. Apply fixed-period signal (e.g., clock from low-power oscillating source) STOP pin. When RELM (edge mode), device placed STOP mode even when STOP input level high.
Example: Entering STOP mode from NORMAL mode
(SYSCR1), 10010000B Setto released edge when entering STOP mode
STOP
iViH
XOUTpin
NORMAL operation
Placed into STOP mode program
STOP mode
Warm-up
NORMAL operation
STOP mode
Released from STOP mode hardware rising edge STOP input.
Figure 1-11. Released from STOP Mode Edge
88CS42-16
2003-06-03
TMP88CS42
device released from STOP mode following sequence described below.
Only high-frequency oscillator oscillating.
warm-up time inserted order allow clock oscillation stabilize. During warm-up, internal circuits remain idle. warm-up time selected from three choices according oscillator characteristics using (SYSCR1 Register bits
After elapse warm-up time, device restarts normal operation beginning with instruction next that placed STOP mode. this time, prescaler divider timing generator start from zero-cleared state.
Table 1-1. Warm-up Time (Example: MHz)
Warm-up Time [ms]
When Returning NORMAL Mode
DV1CK DV1CK=
9.830 19.661
3.277 6.554
0.819 1.638
Reserved Reserved
Note: Because warm-up time obtained from fundamental clock dividing oscillation frequency fluctuates while exiting STOP mode, warm-up time becomes have some error. Therefore, warm-up time must handled approximate value.
device also released from STOP mode pulling RESET input low, which case device immediately reset normally reset RESET. After reset, device starts operating from NORMAL mode.
Note: When exiting STOP mode while device retained voltage, following caution required.
Before exiting STOP mode, power supply voltage must raised operating voltage. this time, RESET level also high rises along with power supply voltage. device time-constant circuit added external chip, voltage RESET input does rise fast power supply voltage. Therefore, voltage level RESET input below RESET pin's noninverted, high-level input voltage (hysteresis input), device reset.
88CS42-17
2003-06-03
Oscillator' circuit
Oscillation
Stop
Main system clock
:nJiJTJ~iJiJ~iJTJiJiJi_riJ^^
Program counter
Instruction execution
Divider
(SYSCR1).
Entering STOP mode (Example: Entered into SET(SYSCR1).7 instruction placed address
Stop
STOP input
Oscillator circuit
Main system clock
Program counter
InstructionStop execution
Divider
Warm-up
Oscillation
Instruction address Instruction address lnstruction address
Count
Exiting STOP mode Figure 1-12. Entering Exiting STOP Mode (when DV1CK
TMP88CS42
IDLE mode
IDLE mode controlled System Control Register (SYSCR2) maskable interrupt. During IDLE mode, device retains following state.
watchdog timer stop operating.
peripheral hardware continues operating, data memory, register, program status word, port output latch hold state which they
were immediately before entering IDLE mode. program counter holds instruction address instructions ahead that placed device IDLE mode.
Example: Placing device IDLE mode
(SYSCR2).
(Released normally)
Figure 1-13. IDLE Mode
88CS42-19
2003-06-03
TMP88CS42
device released from IDLE mode normally interrupt selected with interrupt master enable flag (IMF).
Released normally (when
device released from IDLE mode interrupt source enabled interrupt individual enable flag (EF), restarts execution beginning with instruction next that placed IDLE mode. interrupt latch (IL) interrupt source used exit IDLE mode normally needs cleared using load instruction.
Released interrupt (when
device released from IDLE mode interrupt source enabled interrupt individual enable flag (EF), enters interrupt handling. After interrupt handling, device returns instruction next that placed IDLE mode.
device also released from IDLE mode pulling RESET input low, which case device immediately reset normally reset RESET. After reset, device starts operating from NORMAL mode.
Note: watchdog timer interrupt occurs immediately before entering IDLE mode, device processes watchdog timer interrupt without entering IDLE mode.
88CS42-20
2003-06-03
Main
system
Interrupt
request
Program
counter
Instruction execution
Watchdog timer
Idle
(SYSCR2).4
Operating
Entering IDLE mode (Example: Entered into instruction placed address
Main
njTJTxunxmJiJn-rijnjn_rirLr
Interrupt request
Program counter
Instruction execution
timer
Main
system
clock
Idle Instruction address
Idle
Released normally
njnj^JiJ~LrmjTJTJTJiJT_rLru~
Interrupt r-request
Program counter
Instruction execution-
Watchdog timer
idle
Idle
Interrupt accepted
Operating
Released interrupt
Exiting IDLE mode
Figure 1-14. Entering Exiting IDLE Mode
TMP88CS42
Interrupt Control Circuit
TMP88CS42 total interrupt sources including reset. internal interrupt sources, pseudo-nonmaskable interrupts others maskable interrupts. Table lists interrupt sources TMP88CS42.
Table 1-2. Interrupt Sources
Interrupt Source Enable Condition Interrupt Latch Vector Address Priority
Internal/ External (Reset) Nonmaskable FFFFCH HighO
Internal INTSW (Software interrupt) Pseudo-nonmaskable FFFF8h
Internal INTWDT (WDT interrupt) FFFF4|_|
External INTO (External interrupt IMF- INT0EN FFFFOH
Reserved EF4= FFFECh
External INT1 (External interrupt FFFE8h
Internal INTTBT (Time base timer) EF6= FFFE4H
Reserved FFFEOH
Internal INTEMG1 (chi error detection) EF8= FFFDCH
Internal INTEMG2 (ch2 error detection) IMF- EFg= FFFD8h
Internal INTCLM1 (chi overload protection) EF-,0 11-10 FFFD4H
Internal INTCLM2 (ch2 overload protection) IMF- FFFDOH
Internal INTTMR31 (chi timer EF-,2 "-12 FFFCCH
Internal INTTMR32 (ch2timer3) EF-,3 "-13 FFFC8h
Reserved IMF- EF14= "-14 FFFC4H
External INT5 (External interrupt IMF- EF15= "Lis FFFCOH
Internal INTPDC1 (chi position detection) EF16= "Lie FFFBCH
Internal INTPDC2 (ch2 position detection) EF-,7 "-17 FFFB8h
Internal INTPWM1 (chi waveform generator) IMF- EF18= "-18 FFFB4H
Internal INTPWM2 (ch2 waveform generator) EF-,9 "-19 FFFBOH
Internal INTEDT1 (chi electrical angle timer) EF20 "-20 FFFACH
Internal INTEDT2 (ch2 electrical angle timer) IMF- EF21 "-21 FFFA8h
Internal INTTMR11 (chi timer EF22 "-22 FFFA4H
Internal INTTMR12 (ch2 timer EF23 "-23 FFFAOH
Internal INTTMR21 (chi timer IMF- EF24= "-24 FFF9Ch
Internal INTTMR22 (ch2timer2) EF25 "-25 FFF98H
Internal INTTC1 (TC1 16-bit mer/counter EF26= "-26 FFF94H
Internal INTCTC (CTC: 16-bit compare timer/counter) EF27 "-27 FFF90H
Internal INTTC6 (TC6: 8-bit timer/counter EF28= "-28 FFF8Ch
External INT2 (External interrupt EF29 "-29 FFF88h
External INT3 (External interrupt EF30 "-30 FFF84H
External INT4 (External interrupt IMF- EF31 "-31 FFF80H
Internal INTRX (UART reception) EF32 "-32 FFF3Ch
Internal INTTX (UART transmission) EF33 "-33 FFF38H
Internal INTSIO (SIO interrupt) IMF- EF34= "-34 FFF34H
Internal INTTC3 (TC3: 8-bit timer/counter EF35 "-35 FFF30H
Internal INTTC4 (TC4: 8-bit timer/counter IMF-EF36= "-36 FFF2Ch
Internal INTTC5 (TC5: 8-bit mer/cou nter EF37 "-37 FFF28H
Internal INTADC (AD) EF38= "-38 FFF24H
88CS42-22
2003-06-03
INTSW >-INTWDT>-
Interrupt Latch
lNT0P-[^>O-
reserved
INTADC
INTOEN
Noise Rejection Circuit
Edge Select, Noise Rejection Circuit
INT1NC, INT1ES
EINTCR
External Interrupt Control Register
Write data IL3810
Write strobe
IL3a
IL38 readout
EF58toEF,
Priority Resolution Circuit
Vector Table Address Generation Circuit
Vector table address
Nonmaskable interrupt request
Maskable interrupt request
[DI] instruction Instruction
Interrupt request
IDLE mode release request
Interrupt individual enable flag
Internal reset
Figure 1-15. Interrupt Control Circuit
Interrupt accepted
Interrupt master enable flag
_([RETIJ instruction
only when return from maskable interrupt) <[RETN] instruction only when before accepting interrupt) [Ell instruction
Instruction
TMP88CS42
Interrupt latches (IL38 il2)
interrupt latches provided each interrupt source except software interrupts, when interrupt request generated. When interrupt been enabled acceptance, interrupt controller requests accept interrupt. interrupt latch cleared immediately after interrupt accepted. When reset, interrupt latches initialized toO.
interrupt latches allocated addresses 0003C 0003D|_|, 0002E|_|, 0002F|_|, 0002B|_| area, interrupt latches except individually cleared instruction. (However, read-modify-write instructions such those used manipulation arithmetic operation cannot used. This because interrupt request generated while executing read-modify-write instruction happen cleared.) Interrupt requests canceled initialized program. interrupt latches cannot directly instruction. Because contents interrupt latches read out, interrupt requests tested software.
Note Before change each enable flag (EF) and/or each interrupt latch (IL) sure clear interrupt master enable flag (IMF) disable interrupts).
After instruction executed, automatically cleared when interrupt accepted.
nested interrupt processing accepted, each interrupt enable flag (EF) interrupt latch (IL) manipulate before interrupt master enable flag (IMF) enable interrupts). each enable flags (EF) interrupt laches (IL) under conditions otherthan above, proper operation cannot guaranteed.
Note interrupt latch read (undefined) while being applied external interrupt into, INT2, INT3, INT4 TnT5.
Note When testing whether interrupt requests pending software, make sure that signal applied external interrupt remains stable.
Example Clearing interrupt latches
(ILL), 00000000B
(ILH), 00000000B
(ILE), 00000000B
(ILD), 00000000B
(ILC), 00000000B
Example Reading interrupt latches (ILL) (ILE)
(ILC)
Example Testing interrupt latches TEST (ILL). SSET
SSET:
Disable interrupt (IMF
IL2<-0
IL8tolL15<-0
IL16tolL23<-0
il24 IL31
il32 tolL38<-0
Enable interrupt (IMF
(ILH), (ILL) (ILD), (ILE) D<-(ILC)
Jump
88CS42-24
2003-06-03
TMP88CS42
Interrupt enable register (EIR)
This register enables disables interrupt sources except pseudo-nonmaskable interrupts (software watchdog timer interrupts) against acceptance. pseudo-nonmaskable interrupts always accepted matter this register set. However, pseudo-nonmaskable interrupts cannot themselves nested another.
Interrupt Enable Register consists interrupt master enable flag (IMF) interrupt individual enable flags (EF). Interrupt Enable Register allocated addresses 0003A, 0003B, 0002C, 0002D 0002Ah area, read written instruction (including manipulating other read-modify-write instructions).
Note: However, execute read-mod ify-write instruction EIRL (address 0003AH) while servicing pseudo-nonmaskable interrupt. such instruction executed, flag cannot after RETN.
Interrupt master enable flag (IMF)
This flag enables disables maskable interrupts against acceptance. maskable interrupts disabled against acceptance when this flag cleared enabled acceptance when flag
When interrupt accepted, interrupt master enable flag cleared thereby temporarily disabling subsequent maskable interrupts against acceptance. flag then maskable interrupt return instruction [RETI] after executing interrupt service routine, thereby reenabling maskable interrupts acceptance. Therefore, interrupt request already been received, interrupt accepted serviced immediately after executing [RETI] instruction.
pseudo-nonmaskable interrupts, nonmaskable interrupt return instruction [RETN] used return from interrupt main program. this case, interrupt master enable flag only when pseudo-nonmaskable interrupt processing entered into while interrupts enabled acceptance (IMF However, interrupt master enable flag cleared interrupt service routine, remains cleared.
interrupt master enable flag assigned EIRL (address 0003AH SFR) read written instruction. interrupt master enable flag normally cleared using [El] [Dl] instructions. Note that when reset, interrupt master enable flag initialized
Interrupt individual enable flags (EF38to EF3)
These flags used individually enable disable each maskable interrupt source, against acceptance. interrupt enabled acceptance when corresponding interrupt individual enable flag 1,and disabled against acceptance when flag isO.
Before change each enable flag (EF) and/or each interrupt latch (IL) sure clear interrupt master enable flag (IMF) disable interrupts).
After instruction executed, automatically cleared when interrupt accepted. nested interrupt processing accepted, each interrupt enable flag (EF) interrupt latch (IL) manipulate before interrupt master enable flag (IMF) enable interrupts). each enable flags (EF) interrupt laches (IL) under conditions other than above, proper operation cannot guaranteed.
Example:
Disable interrupts (IMF
(EIRL). ;EF5<-1
(EIRL). ;EF6<-0
(EIRH). ;EF12<-0
(EIRD).O ;EF24<-0
Enable interrupts (IMF
88CS42-25
2003-06-03
TMP88CS42
Interrupt Latch
(0002BH)
(0002FH)
(0002Eh)
(0003Dh)
(0003Ch)
il38 il37 IL36 IL35 "-34 "-33 "-32
IL31 IL30 il29 11-28 il27 "-26 "-25 "-24
IL23 IL22 11-21 "-20 "-19 "-18 "-17 "Lie
11-15 "-14 "-13 11-12 "-11 "-10
(Initial value: *000 0000) (Initial value: 0000 0000) (Initial value: 0000 0000) (Initial value: 0000 0000) (Initial value: 0000 0000)
Reads Writes
IL3a Interrupt latch interrupt request Interrupt request generated Clear interrupt request (Note write these bits ignored.
Interrupt nesting flag servicing interrupt Servicing interrupt nested level Servicing interrupts nested more levels Servicing interrupts nested more levels Retain counter value Clear nesting counter Decrement nesting counter (Note Reserved
Notel: cannot alone cleared.
Note Counter underflow cannot recognized.
Note nesting counter cleared initial state counts each time interrupt accepted
counts down each time interrupt return executed. Note Before change each enable flag (EF) and/or each interrupt latch (IL) sure clear interrupt master enable flag (IMF) disable interrupts).
After instruction executed, automatically cleared when interrupt accepted.
nested interrupt processing accepted, each interrupt enable flag (EF) interrupt latch (IL) manipulate
before interrupt master enable flag (IMF) enable interrupts).
each enable flags (EF) interrupt laches (IL) under conditions other than above, proper operation cannot guaranteed. Note When setting nesting flag "00", nesting counter value retained. Note manipulating other read-modify-write instructions clear
Interrupt Enable Register
EIRC (0002Ah) ef38 EF37 EF36 EF35 EF34 EF33 EF32 (Initial value: *000 0000)
EIRD (0002Dh) EF31 EF30 EF29 ef28 EF27 ef26 EF25 EF24 (Initial value: 0000 0000)
EIRE (0002Ch) EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16 (Initial value: 0000 0000)
EIRH (0003BH) EF15 EF14 EF13 EF12 EF11 EF10 (Initial value: 0000 0000)
EIRL (0003Ah) (Initial value: 0000 0000)
Note interrupt master enable flag nonmaskable interrupt service routine. Note Before change each enable flag (EF) and/or each interrupt latch (IL) sure clear interrupt master enable flag (IMF) disable interrupts).
After instruction executed, automatically cleared when interrupt accepted.
nested interrupt processing accepted, each interrupt enable flag (EF) interrupt latch (IL) manipulate
before interrupt master enable flag (IMF) enable interrupts).
each enable flags (EF) interrupt laches (IL) under conditions other than above, proper operation cannot guaranteed. Note simulataneously with
Figure 1-16. Interrupt Latches (IL) Interrupt Enable Register (EIR)
88CS42-26
2003-06-03
TMP88CS42
1.5.1 Interrupt Handling
interrupt request retained until interrupt latch cleared accepting interrupt reset instruction. Interrupt acceptance processing executed machine cycles (2.4 20.0 MHz) after instruction being executed finished. interrupt service task finished executing interrupt return instruction [RETI] (for maskable interrupts) [RETN] (for pseudo-nonmaskable interrupts). Figure 1-17 shows timing chart interrupt acceptance processing.
Interrupt acceptance processing
interrupt acceptance processing, following operations performed automatically.
Clear interrupt master enable flag (IMF) thereby temporarily disabling subsequent maskable interrupts against acceptance. interrupt being accepted nonmaskable interrupt, this operation also temporarily disables subsequent nonmaskable interrupts against acceptance.
Clear interrupt latch accepted interrupt source
Save contents Program Counter (PC) Program Status Word (PSW) stack. (Pushed down order PSW|_|, PSW|_, PCg, PC|-|, PC|_.) Stack Pointer (SP) decremented five times.
From vector table address corresponding accepted interrupt source, read entry address (interrupt vector) interrupt service routine program counter.
Read control code from vector table low-order bits Register Bank Selector (RBS).
interrupt nesting counter count
Proceed execute instruction stored interrupt service routine entry address.
88CS42-27
2003-06-03
TMP88CS42
1-machine cycle
Interrupt service task
Instruction
Instruction execution
Interrupt acceptance processing
Address
yzjczx
Instruction execution
DCDCIX
)CDGDCDCDC
XHXHXHXHX
(FFFE7h).
Interrupt acceptance processing
Instruction execution
Instruction execution
Address
ZXHXEX
XIXHXHX
XHXHXHXHX
Interrupt return instruction timing chart
Note letter denotes return address, denotes entry address, denotes address which RETI instruction stored.
Note time from when interrupt latch till when interrupt acceptance processing starts, 62/fc maximum cases when interrupts have been enabled (and other interrupt requests generated).
Figure 1-17. Interrupt Acceptance Processing Interrupt Return Instruction Timing Chart
88CS42-28
2003-06-03
TMP88CS42
Even when maskable interrupt occurs which higher priority than interrupt being serviced, accepted until interrupt master enable flag Therefore, multiple interrupts need handled, interrupt master enable flag interrupt service routine. this time, sure selectively enable interrupt sources that accepted using interrupt individual enable flags. However, execute read-modify-write instruction EIRL (address 0003A|_|) during pseudo-nonmaskable interrupt service task.
Note: stack pointer must specified before interrupt enabled.
Example: Relationship between vector table addresses interrupt service routine entry addresses INTTBT acceptance processing
Vector table address
FFFE4
FFFE5
FFFE6
FFFE7
Vector
control code
Entry address
05243
05244
05245
05246
Interrupt service routine
Saving restoring general-purpose registers
interrupt acceptance processing, program counter program status word automatically saved stack, accumulator other registers automatically saved. these registers need saved, program. However, handling multiple interrupts desired, make sure data memory areas which register contents saved will overlap.
There following four methods save general-purpose registers.
Saving restoring general-purpose registers automatic register bank switchover
Automatic register bank switchover individual interrupt sources separately. increment value specified address next interrupt vector address, added automatically current value during interrupt acceptance processing.
general-purpose registers saved high speed switching them unused register bank. Assign bank main task banks each interrupt service task. increase efficiency data memory usage, assign common bank interrupt sources which nested, e.g., accepted while servicing another.
switched register banks automatically restored executing interrupt return instruction [RETI] [RETN], Therefore, there need save program.
Example: Register bank switchover
PINTxx:
Interrupt processing RETI
VINTxx:
PINTxx INTxx interrupt routine entry address
INTxx interrupt increment value
88CS42-29
2003-06-03
TMP88CS42
Saving restoring general-purpose registers register bank switchover Specifying value program enables register bank switchover.
general-purpose registers saved high speed switching them unused register bank. bank main task banks interrupt service task. switched register banks automatically restored executing interrupt return instruction [RETI] [RETN], Therefore, there need save program.
Example: Register bank switchover
PINTxx: RBS, Switch bank
Interrupt processing
RETI Restore bank return from interrupt
VINTxx: PINTxx Interrupt service routine entry address
Entry address
Saving restoring general-purpose registers push/pop instructions
When saving only specific registers nesting interrupts from same interrupt source, push/pop instructions save restore general-purpose registers.
Example: Saving restoring registers push/pop instructions
PINTxx: PUSH Save register pair stack
Interrupt processing
Restore register pair from stack
RETI Return
(Address
(example) 0023Ah
0023B
0023C
0023D
0023E
0023F
PSWL PSWl PSWl 00240
PSWH PSWh PSWh 00241
After accepting After pushing After popping czj> After return
interrupt register pair register pair
Saving restoring general-purpose registers transfer instruction
When saving only specific registers interrupt processing where interrupts nested, instruction transfer from data memory save restore general-purpose registers.
Example: Saving restoring registers data memory (GSAVA) transfer instruction
PINTxx: (GSA\/A), Save register
Interrupt processing
(GSAVA) Restore register
RETI Return
88CS42-30
2003-06-03
TMP88CS42
Main task
Bank
Interrupt accepted
Interrupt service task
Interrupt return
Switching bank with RBS,
instruction automatic bank switchover
Control automatically returns original bank executing interrupt return instruction.
Main task Bank
Interrupt accepted
Interrupt service task
Interrupt return
Saving restoring general-purpose registers register Saving restoring general-purpose registers push/pop bank switchover transfer instructions
Figure 1-18. Saving Restoring General-purpose Registers Interrupt Processing Interrupt return
interrupt return instructions perform following operations.
[RETI] maskable interrupt return [RETN] nonmaskable interrupt return
Restore content program counter that program status word from stack. Increment stack pointer times. interrupt master enable flag interrupt nesting counter decremented interrupt nesting flag changes state. Restore content program counter that program status word from stack. Increment stack pointer times. interrupt master enable flag only when nonmaskable interrupt accepted while interrupts were enabled. However, interrupt master enable flag cleared interrupt service routine, flag remains cleared. interrupt nesting counter (INF) decremented interrupt nesting flag changes state.
Interrupt requests sampled last cycle instruction being executed. Therefore, next interrupt processed immediately after executing interrupt return instruction.
Note: interrupt processing takes longer time than duration which interrupt request generated, only interrupt service task executed, main task executed.
88CS42-31
2003-06-03
TMP88CS42
1.5.2 Software Interrupt (INTSW)
software interrupt generated executing instruction, interrupt processing immediately entered into (highest priority interrupt). However, nonmaskable interrupt processing already been entered into, software interrupts generated even executing instruction, which case instruction works same instruction. instruction only used address error detection debugging described below, cannot used other purposes.
Address error detection
fetches instructions from address that does exist memory some reasons (e.g., noise), FF|_| read out. Because code FF|_| instruction, software interrupt generated, thereby making possible detect address errors. Also, address error detection range further expanded filling unused areas program memory with FF|_|. RAM, SFR, area accessed instruction fetch, address trap reset generated.
Debugging
Debugging efficiency increased placing instruction addresses where software breakpoints set.
1.5.3 External Interrupts
TMP88CS42 external interrupt inputs, which have digital noise rejection circuit (which rejects input pulses shorter than certain time noise). Also, INT1 INT4 pins allow active edge selected.
INT0/P10 used external interrupt input input/output port selected. When reset, this input mode.
External Interrupt Control Register used select active edge, control noise rejection,
select INT0/P10 function.
Table 1-3. External Interrupts
Source Name Shared Enable Condition Edge Digital Noise Rejection Circuit
Pulses less than 2/fc duration
INTO TnTo Falling edge rejected noise. Those greater than 6/fc
INTOEN duration always recognized signal. (When DV1CK
Pulses less than 15/fcor 63/fc
duration rejected noise. Those
INT1 INT1 Falling edge greater than 48/fc 192/fc duration always recognized signal. (When DV1CK
INT2 INT2 P12/TC1 EF29 rising edge Pulses less than 7/fc duration
INT3 INT3 P21/TC3 EF30 rejected noise. Those greater than 24/fc duration always recognized signal. (When DV1CK
INT4 INT4 P22/TC4 EF31
Pulses less than 2/fc duration
INT5 TNT5 P2Q/STOP EF15 Falling edge rejected noise. Those greater than 6/fc duration always recognized signal. (When DV1CK
88CS42-32
2003-06-03
TMP88CS42
Note When noise-free signal applied external interrupt input during NORMAL IDLE mode, maximum time before interrupt latch after active edge input signal follows.
INT1 49/fc (when INT1NC 193/fc (when INT1NC
INT2 pins 25/fc
Note When INTOEN interrupt latch even detecting falling edge INTO input.
Note When using shared output port data changes state direction switched between input output, unsolicited interrupt request signal generated. Therefore, some corrective measure must taken example, disabling interrupt enable flag.
Note Before switching operation mode changing value External Interrupt Control Register (EINTCR), sure disable external interrupts. When enabling interrupts after switching operation mode changing value EINTCR, sure clear unwanted interrupt latches advance.
INT1 INTO INT4 INT3 INT2 INT1 nnn^ (Initial value: 0000 000*)
INT1NC Select INT1 noise rejection time Reject pulses less than 63/fc noise Reject pulses less than 15/fc noise
INTOEN Select P10/INT0 function input/output port INTO (P10 port must input mode)
INT4ES Select INT4 edge Generate interrupt request rising edge Generate interrupt request falling edge Generate interrupt request both rising falling edges Generate interrupt request high level
INT3 INT2 INT1 Select INT3 INT1 edge Generate interrupt request rising edge Generate interrupt request falling edge
Note: High-frequency clock [Hz], Don't care
Figure 1-19. External Interrupt Control Register
88CS42-33
2003-06-03
TMP88CS42
Reset Circuit
TMP88CS42 four ways generate reset: external reset input, address trap reset, watchdog timer reset, system clock reset.
Table shows internal hardware initialized reset operation.
power-on time, internal cause reset circuits (watchdog timer reset, address trap reset, system clock reset) initialized.
Table 1-4. Internal Hardware Initialization Reset Operation
Internal Hardware Initial Value Internal Hardware Initial Value
Program Counter (PC) (FFFFEh FFFFCh)
Stack Pointer (SP) initialized Prescalerand divider timing
General-purpose Registers initialized generator
H,L)
Register Bank Selector (RBS) Watchdog timer Enable
Jump Status Flag (JF)
Zero Flag (ZF) initialized
Carry Flag (CF) initialized description each input/output port.
Half Carry Flag (HF) initialized Output latch input/output port
Sign Flag (SF) initialized
Overflow Flag (VF) initialized
Interrupt Master Enable Flag (IMF)
Interrupt Individual Enable Flag (EF) Control register description each control register.
Interrupt Latch (IL)
Interrupt Nesting Flag (INF) initialized
1.6.1 External Reset Input
RESET hysteresis input with pull-up resistor included. holding RESET least three machine cycles (12/fc [s]) more while power supply voltage within rated operating voltage range oscillator oscillating stably, device reset internal state initialized.
When RESET input released back high, device freed from reset starts executing program beginning with vector address stored addresses FFFFC FFFFE|_|.
RESET -Reset input
Figure 1-20. ResetCircuit
88CS42-34
2003-06-03
TMP88CS42
1.6.2 Address Trap Reset
goes wild reasons noise, etc. attempts fetch instructions from internal RAM, DBR, area, device internally generates reset.
address trap control registers (ATAS, ATKEY) used enable/disable address trap. Address trap enabled default, attempts fetch instructions from internal RAM, DBR, area, internal reset generated. When address trap disabled, instructions internal area executed.
Address Trap Control Register
ATAS ;.;.;.
(01F94h)
ATAS
(Initial value: **** ***0)
ATAS Enable/Disable address trap Enable address trap Disable address trap (Effective when control code written ATKEY) Write only
Address Trap Control Code Register
ATKEY (01F95h)
(Initial value: ********)
ATKEY Write control code disable address trap D2h: Address trap disable code Others: Ineffective Write only
Note: Read-modify-write instructions, such manipulation instruction, cannot access ATAS ATKEY register because these registers write only.
Figure 1-21. Address Trap Control Registerand Address Trap Control Code Register
Notel: While instruction address immediately before address trap area executing, program counter incremented point next address address trap area; address trap therefore taken immediately.
Note development tools, address trap cannot disabled internal RAM, DBR, area with address trap control registers. When using development tools, even address trap enable/disable setting changed user program, this change ineffective. execute instructions from area, development tools must accordingly.
Development Tools
disable address trap:
memory window, change iram (mapping attribute) area 0x00040 OxOOObf.
0x000c0 "address trap disable area" neweram (mapping attribute) area.
Load user program.
Execute address trap disable code user program.
1.6.3 Watchdog Timer Reset
Referto Section 2.4, "Watchdog Timer."
1.6.4 System Clock Reset
When (SYSCR2 Register cleared when cleared while SYSCK system clock turned off, causing become locked prevent this problem, upon detecting SYSCK SYSCK= device automatically generates internal reset signal system clock continue oscillating.
88CS42-35
2003-06-03
TMP88CS42
Peripheral Hardware Functions
Special Function Registers (SFR) Data Buffer Registers (DBR)
TLCS-870/X series uses memory-mapped method, peripheral hardware control signal data transfers performed Special Function Registers (SFR) Data Buffer Registers (DBR).
Figure lists Special Function Registers (SFR). Figure lists Data Buffer Registers (DBR).
Address Read Write Address Read Write
00000 PODR Port) 00020 TC5CR (Timer Control)
00001 P1DR(P1 Port) 00021 TC6CR (Timer Control)
00002 P2DR Port) 00022 TTREG5 (Timer Period Register)
00003 P3DR Port) 00023 TTREG6 (Timer Period Register)
00004 P4DR Port) 00024 PWREG5 (Timer Pulse Width Register)
00005 P5DR Port) 00025 PWREG6 (Timer Pulse Width Register)
00006 P6DR Port) 00026 ADCCRA Control
00007 P7DR Port) 00027 ADCCRB Control
00008 Reserved 00028 ADCDRL Conversion Value, Low-order Bits)
00009 Reserved 00029 ADCDRH Conversion Value, High-order Bits)
0000A P0CR Input/Output Control) 0002A EIRC (Extended Interrupt Enable, High)
0000B P1CR Input/Output Control) 0002B (Extended Interrupt Latch, High)
OOOOC HPWMCR (HPWM Control) 0002C EIRE (Extended Interrupt Enable, Low)
0000D HPWMDR0 (HPWM0 Data) 0002D EIRD (Extended Interrupt Enable, Middle)
0000E HPWMDR1 (HPWM1 Data) 0002E (Extended Interrupt Latch, Low)
0000F (Timer Control) 0002F (Extended Interrupt Latch, Middle)
00010 TC1DRAL (Timer Register Lower) 00030 CGCR (First Divider Stage Input Clock Select)
00011 TD1DRAH (Timer Register Upper) 00031 Reserved
00012 TC1DRBL (Timer Register Lower) 00032 Reserved
00013 TC1DRBH (Timer Register Upper) 00033 Reserved
00014 CTC1CR1 (CTC1 Control, Lower) 00034 WDTCT1 (WDT Control
00015 CTC1CR2 (CTC1 Control, Upper) 00035 WDTCT2 (WDT Control
00016 CTC1DR1 (CTC Compare Timer Register Lower) 00036 TBTCR (TBT/TG/Divider Output Control)
00017 CTC1DR2 (CTC Compare Timer Register Upper) 00037 EINTCR (External Interrupt Input Control)
00018 Reserved 00038 SYSCR1 (System Control
00019 Reserved 00039 SYSCR2 (System Control
0001A TC4CR (Timer Control) 0003A EIRL (Interrupt Enable, Lower)
0001B TC4DR (Timer Register) 0003B EIRH (Interrupt Enable, Upper)
0001C TC3DRA (Timer Register 0003C (Interrupt Latch, Lower)
0001D TC3DRB (Timer Register TC3C)| 0003D (Interrupt Latch, Upper)
0001E TC3CR (Timer Control) 0003E PSWL (Program Status Word, Lower)
0001F Reserved 0003F PSWH (Program Status Word, Upper)
Note access reserved addresses program. Note Cannot accessed. Note When defining address 0003FH with symbol, define GPSW/GRBS. Note write-only registers interrupt latches cannot operated using read -modify-write instructions
(bit manipulating instructions such CLR, arithmetic instructions such OR).
Figure 2-1. Special Function Registers (SFR)
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2003-06-03
TMP88CS42
Address Read Write Address Read Write
01F80 POODE Open-drain Control) 01F90 ARTS (Set UARTpin)
01F81 Reserved 01F91 UARTSR (UART Status) UARTCRA (UART Control
01F82 Reserved 01F92 UARTCRB (UART Control
01F83 P30DE Open-drain Control) 01F93 RDBUF (UART Receive Buffer) TDBUF (UART Transmit Buffer)
01F84 P40DE Open-drain Control) 01F94 (Address Trap Control)
01F85 P50DE Open-drain Control) 01F95 ATKEY (Address Trap Register)
01F86 Reserved 01F96 SIOCR1 (SIO Control Register
01F87 Reserved 01F97 SIOSR(SIO Status) SIOCR2 (SIO Control Register
01F88 Reserved 01F98
01F89 P3CR Input/output Control) 01F99
01F8A P4CR Input/output Control) 01F9A
01F8B P5CR Input/output Control) 01F9B Receive Buffer Transmit Buffer
01F8C P6CR Input/output Control) 01F9C
01F8D P7CR Input/output Control) 01F9D
01F8E Reserved 01F9E
01F8F Reserved 01F9F
Figure 2-2. Data Buffer Registers (DBRs) (1/2)
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TMP88CS42
Related Read Write Related Read Write
01FA0 PDCRA (Position Detection Control 01FD0 PDCRA (Position Detection Control
01FA1 PDCRB (Position Detection Control 01FD1 PDCRB (Position Detection Control
01FA2 PDCRC (Position Detection Control 01FD2 PDCRC (Position Detection Control
01FA3 SDREG (Sampling Delay Control) 01FD3 SDREG (Sampling Delay Control)
MTCRA (Mode Timer Control 01FD4 MTCRA (Mode Timer Control
01FA5 MTCRB (Mode Timer Control 01FD5 MTCRB (Mode Timer Control
01FA6 MCAPL (Mode Capture 01FD6 MCAPL (Mode Capture
01FA7 MCAPH (Mode Capture 01FD7 MCAPH (Mode Capture
01FA8 CMP1L (Compare Register 01FD8 CMP1L (Compare Register
01FA9 CMP1H (Compare Register 01FD9 CMP1H (Compare Register
01FAA CMP2L (Compare Register CMP2L (Compare Register
CMP2H (Compare Register 01FDB CMP2H (Compare Register
01FAC CMP3L (Compare Register 01FDC CMP3L (Compare Register
CMP3H (Compare Register CMP3H (Compare Register
01FAE MDCRA (PMD Control 01FDE MDCRA (PMD Control
01FAF MDCRB (PMD Control 01FDF MDCRB (PMD Control
01FB0 EMGCRA (EMG Control EMGCRA (EMG Control
01FB1 EMGCRB (EMG Control 01FE1 EMGCRB (EMG Control
01FB2 MDOUTL (PMD Output Register 01FE2 MDOUTL (PMD Output Register
01FB3 MDOUTH (PMD Output Register 01FE3 MDOUTH (PMD Output Register
01FB4 MDCNTL (PWM Counter 01FE4 MDCNTL (PWM Counter
01FB5 MDCNTH (PWM Counter 01FE5 MDCNTH (PWM Counter
01FB6 MDPRDL (PMD Period Register 01FE6 MDPRDL (PMD Period Register
01FB7 MDPRDH (PMD Period Register 01FE7 MDPRDH (PMD Period Register
01FB8 CMPUL (PMD Compare Register 01FE8 CMPUL (PMD Compare Register
01FB9 CMPUH (PMD Compare Register 01FE9 CMPUH (PMD Compare Register
01FBA CMPVL (PMD Compare Register 01FEA CMPVL (PMD Compare Register
01FBB CMPVH (PMD Compare Register CMPVH (PMD Compare Register
01FBC CMPWL (PMD Compare Register 01FEC CMPWL (PMD Compare Register
01FBD CMPWH (PMD Compare Register CMPWH (PMD Compare Register
01FBE (Dead Time) (Dead Time)
01FBF EMGREL (EMG disable code) 01FEF EMGREL (EMG disable code)
EDCRA (Waveform Calculation Control 01FF0 EDCRA (Waveform Calculation Control
01FC1 EDCRB (Waveform Calculation Control 01FF1 EDCRB (Waveform Calculation Control
01FC2 EDSETL (Waveform Calculation Period Control 01FF2 EDSETL (Waveform Calculation Period Control
01FC3 EDSETH (Waveform Calculation Period Control 01FF3 EDSETH (Waveform Calculation Period Control
01FC4 ELDEGL (Electrical Angle 01FF4 ELDEGL (Electrical Angle
01FC5 ELDEGH (Electrical Angle 01FF5 ELDEGH (Electrical Angle
01FC6 (Voltage 01FF6 AMPL (Voltage
01FC7 AMPH (Voltage 01FF7 AMPH (Voltage
01FC8 EDCAPL 01FF8 EDCAPL
(Electrical Angle Capture Value (Electrical Angle Capture Value
01FC9 EDCAPH 01FF9 EDCAPH
(Electrical Angle Capture Value (Electrical Angle Capture Value
01FCA (Sine Wave Access) 01FFA WFMDR (Sine Wave Access)
01FCB Reserved 01FFB Reserved
Shows registers associated with electrical angle timer waveform calculation.
Figure 2-2. Data Buffer Registers (DBRs) (2/2)
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TMP88CS42
Input/Output Ports
TMP88CS42 contains input/output ports comprised pins.
Port 4-bit input/output port (timer/counter input, serial interface input/output, high-speed
output)
PortPI: 8-bit input/output port (external interrupt input, timer/counter input/output, divider
output, motor control circuit input) PortP2: 3-bit input/output port (external interrupt input, timer/counter input/output, STOP
mode release signal input) PortP3: 8-bit input/output port (motor control input/output)
Port 8-bit input/output port (timer/counter output, serial interface input/output, motor control
circuit input)
Port 8-bit input/output port (motor control circuit input/output) Port 8-bit input/output port (analog input motor control circuit output) Port 8-bit input/output port (analog input motor control circuit output)
output ports contain latch, output data therefore retained latch. none input ports have latch, desirable that input data retained externally until read out, read several times before being processed. Figure shows input/output timing. timing which external data read from input/output ports state read cycle instruction execution. Because this timing cannot recognized from outside, transient input data such chattering needs dealt with program. timing which data forwarded input/output ports state write cycle instruction execution.
Instruction execution cycle
Input strobe Data input
Instruction execution cycle
Output latch pulse Data output
Fetch cycle Fetch cycle Read cycle
Example:
j_i_i_i_i_i_i_i_i_i_l
")(;
Inputtiming Fetch cycle Fetch cycle Write cycle
Example: (x),
j_i_i_i_i_i_i_i_i_i_l
Output timing Note: read/write cycle positions vary depending instructions.
Figure 2-3. Example Input/Output Timing
When operation performed read from input/output port except programmable input/output ports, whether input value content output latch read depends instruction executed, shown below.
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2003-06-03
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Instructions which read content output latch
(src) SET/CLR/CPL (src).b SET/CLR/CPL (pp).g (src).b, (pp).b,CF (src),
ADD/ADDC/SUB/SUBB/AND/OR/XOR ADD/ADDC/SUB/SUBB/AND/OR/XOR MXOR (src),
(src),
(src),(HL) instructions, (src) side thereof
Instructions which read input value
instructions other than those listed above ADD/ADDC/SUB/SUBB/AND/OR/XOR (src),(HL) instructions, (HL) side thereof
2.2.1 Port (P03 POO)
Port 4-bit input/output port shared with serial interface input/output. This port switched between input output modes using port input/output control register (POCR). When reset, POCR register initialized with port input mode. Also, output latch (PODR) initialized when reset.
port contains bitwise programmable open-drain control. port open-drain control register (POODE) used select open-drain tri-state mode port. When reset, POODE register initialized with tri-state mode selected port.
POCRi Data input
Data output Control output
Output latch
External input
Control input values
PODR (00000H)
POCR (OOOOAh)
POODE (01F80h)
HPWM1 HPWM0 TC60 TXD2 TC6I RXD2
3to0, Don't care
Read/Write
(Initial value: **** 0000)
TC60: PD06, PWM6, PPG6 (Initial value: **** 0000)
POCR port input/output cont (Specify bitwise) Input mode Output mode
(Initial value: **** 0000)
POODE port open-drain control (Specify bitwise) Tri-state Open drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore,
apply voltages exceeding VDD. Note Read-Modify-Write (RMW) operation executes open-drain mode selected, read output latch states. When other instruction executed, external states read out.
Figure 2-4. Port Port Input/Output Registers
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2003-06-03
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2.2.2 Port (P17 P10)
Port 8-bit input/output port shared with external interrupt input, timer/counter input/output, divider output. This port switched between input output modes using port input/output control register (P1CR). When reset, P1CR register initialized with port input mode. Also, output latch initialized when reset.
P1DR (00001H)
P1CR (OOOOBh)
Data input
Data output
Control output Control input
Output latch
External input
7to0
Control input values
PDW2 PDV2 PDU2 PPG1 INT2 INT1 INTO
TC50 TC5I
Read/Write
(Initial value: 0000 0000) TC50: PD05, PWM5
(Initial value: 0000 0000)
P1CR port input/output control (Specify bitwise) Input mode Output mode
Figure 2-5. Port Port Input/Output Register
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2003-06-03
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2.2.3 Port (P22 P20)
Port 3-bit input/output port shared with external interrupt input STOP mode release signal. When using this port these functional pins input port, output latch When reset, output latch initialized
recommend using external interrupt input, STOP mode release signal input, input port. When using this port output port, note that interrupt latch falling edge output pulse. Note also that outputs this port during STOP mode high-impedance state. When read instruction executed port, indeterminate values read from bits When read-modify-write instruction executed port, content output latch read out. When other instruction executed, external state read out.
P2DR (00002h)
INT5
INT4 INT3 STOP
PWM4
PD04
Read/Write
(Initial value: *****111) Don't care
Note When read instruction executed port, indeterminate values read from bits Note Port used STOP pin. Therefore, when stop mode started, OUTEN does affect P20, becomes High-Z mode.
Figure 2-6. Port Port Input/Output Register
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2003-06-03
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2.2.4 Port (P37 P30)
Port 8-bit input/output port. This port switched between input output modes using port Input/output control register (P3CR). When reset, P3CR register initialized with port input mode. Also, output latch (P3DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P30DE) used select open-drain tri-state mode port. When reset, P30DE register initialized with tri-state mode selected port.
P3DR (00003h)
P3CR (01F89h)
P30DE (01F83h)
External input
Control input values
Read/Write (Initial value:
EMG1 uuuu UUUUJ
(Initial value: 0000 0000)
P3CR port input/output control (Specify bitwise) Input mode Output mode
(Initial value: 0000 0000)
P30DE port open-drain control (Specify bitwise) Tri-state Open drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore,
apply voltages exceeding VDD. Note Read-modify-write (RMW) operation executes open-drain mode selected, read output
latch states. When other instruction executed, external states read out. Note circuit output, P3DR output latch Note When using port input/output port, disable EMG1 circuit.
Figure 2-7. Port Port Input/Output Registers
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2003-06-03
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2.2.5 Port (P47 P40)
Port 8-bit input/output port shared with serial interface input/output. This port switched between input output modes using port input/output control register (P4CR). When reset, P4CR register initialized with port input mode. Also, output latch (P4DR) initialized when reset.
port contains bitwise programmable open-drain control. port open-drain control register (P40DE) used select open-drain tri-state mode port. When reset, P40DE register initialized with tri-state mode selected port.
External input
Control input values
P4DR (00004h)
PPG2 PDU1 PDV1 PDW1
TXD1 RXD1
(Initial value: 0000 0000)
P4CR F8Ah)
P40DE (01F84h)
(Initial value: 0000 0000)
P4CR port input/output control (Specify bitwise) Input mode Output mode
(Initial value: 0000 0000)
P40DE port open-drain control (Specify bitwise) Tri-state Open drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore,
apply voltages exceeding VDD. Note Read-modify-write (RMW) operation executes open-drain mode selected, read output
latch states. When other instruction executed, external states read out. Note When using 16-bit timer ordinary timer, (CTC) output mode.
Figure 2-8. Port Port Input/Output Registers
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2.2.6 Port (P57 P50)
Port 8-bit input/output port. This port switched between input output modes using port input/output control register (P5CR). When reset, P5CR register initialized with port input mode. Also, output latch (P5DR) initialized when reset. port contains bitwise programmable open-drain control. port open-drain control register (P50DE) used select open-drain tri-state mode port. When reset, P50DE register initialized with tri-state mode selected port.
P5DR (00005h)
P5CR (01F8Bh)
P50DE (01F85h)
Data input
Data output
Control output Control input
Output latch
External input
Control input value
Read/Write
(Initial value: 0000 0000)
EMG2
(Initial value: 0000 0000)
P5CR port input/output control (Specify bitwise) Input mode Output mode
(Initial value: 0000 0000)
P50DE port open-drain control (Specify bitwise) Tri-state Open drain
Note Even when open-drain mode selected, protective diode remains connected. Therefore, apply voltages exceeding VDD.
Note Read-modify-write (RMW) operation executes open-drain mode selected, read output latch
states. When other instruction executed, external states read out. Note circuit output, P5DR output latch Note When using port input/output port, disable EMG2 circuit.
Figure 2-9. Port Port Input/Output Registers
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2003-06-03
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2.2.7 Port (P67 P60)
Port 8-bit input/output port shared with converter analog input. This port switched between input output modes using port input/output control register (P6CR), port output latch (P6DR), AINDS (ADCCRA Register When reset, P6CR Register P6DR output latch initialized while AINDS that have their inputs fixed When using port input port, corresponding bits input mode (P6CR P6DR reason output latch because necessary prevent current from flowing into shared data input circuit. When using port output port, P6CR Register's corresponding bits When using port analog input, corresponding bits analog input (P6CR P6DR Then AINDS conversion will start. ports used analog input must have their output latches beforehand. actual input channels conversion selected using SAIN (ADCCRA Register bits Although bits port used analog input used input/output ports, execute output instructions these ports during conversion. This necessary maintain accuracy conversion. Also, apply rapidly changing signals ports adjacent analog input during conversion.
input instruction executed while P6DR output latch cleared data read from said bits.
Analog input AINDS SAIN
input Data input (P6)
Data output (P6) STOP
Note
Note STOP exists SYSCR1 register Note SAIN selects input channels.
P6DR
(00006h) AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0
DBOUT1
Read/Write (Initial value:
0000 0000)
P6CR (01F8Ch)
(Initial value: 0000 0000)
P6CR port input/output control (Specify bitwise) AINDS (when using AINDS (when using
P6DR P6DR P6DR P6DR
Inputs fixed Input mode Analog input mode (Note Input mode
Output mode Output mode
Note pins used analog input cannot output mode (P6CR because they become shorted with external signals.
Note When read instruction executed bits this port which analog input mode, data read
Note DBOUT output, P6DR.7 output latch
Figure 2-10. Port Port Input/Output Registers
Note: When using this port input mode (including analog input), manipulating other read-mod ify-write instructions. When read instruction executed bits this port that input, contents pins read that read-mod ify-write instruction executed, their output latches rewritten, making pins unable accept input. read-mod ify-write instruction first reads data from eight bits after modifying them (bit manipulation), writes data eight bits output latches.)
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2.2.8 Port (P77 P70)
Port 8-bit input/output port shared with converter analog input. This port switched between input output modes using port input/output control register (P7CR), port output latch (P7DR), AINDS (ADCCRA Register When reset, P7CR register P7DR output latch initialized while AINDS that have their inputs fixed When using port input port, corresponding bits input mode (P7CR P7DR reason output latch because necessary prevent current from flowing into shared data input circuit. When using port output port, P7CR Register's corresponding bits When using port analog input, corresponding bits analog input (P7CR P7DR Then AINDS conversion will start. ports used analog input must have their output latches beforehand. actual input channels conversion selected using SAIN (ADCCRA Register bits Although bits port used analog input used input/output ports, execute output instructions these ports during conversion. This necessary maintain accuracy conversion. Also, apply rapidly changing signals ports adjacent analog input during conversion.
input instruction executed while P7DR output latch cleared data read from said bits.
Analog input AINDS SAIN
input Data input (P7)
Data output (P7) STOP
Note
Note STOP exists SYSCR1 register Note SAIN selects input channels.
P7DR
(00007h) AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8
DBOUT2
Read/Write (Initial value:
0000 0000)
P7CR (01F8Dh)
(Initial value: 0000 0000)
P7CR port input/output control (Specify bitwise) AINDS (when using AINDS (when using
P7DR P7DR P7DR P7DR
Inputs fixed Input mode Analog input mode (Note Input mode
Output mode Output mode
Note pins used analog input cannot output mode (P7CR because they become shorted with external signals.
Note When read instruction executed bits this port which analog input mode, data read
Note DBOUT output, P5DR output latch
Figure 2-11. Port Port Input/Output Registers
Note: When using this port input mode (including analog input), manipulating other read-modify-write instructions. When read instruction executed bits this port that input, contents pins read that read-mod ify-write instruction executed, their output latches rewritten, making pins unable accept input. read-mod ify-write instruction first reads data from eight bits after modifying them (bit manipulation), writes data bits output latches.)
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Time Base Timer (TBT)
time base timer used produce reference time scan dynamic display processing this purpose generates time base timer interrupt (INTTBT) fixed intervals. time base timer interrupt generated beginning with first falling edge source clock (the timing generator's divider output selected TBTCK) after enabling time base timer. Because divider cleared program, first INTTBT interrupt, only first though, generated earlier than interrupt interval. (See Figure 2-12.)
When selecting interrupt frequency, make sure time base timer disabled. change interrupt frequency when disabling time base timer while active.) possible select interrupt frequency while same time enabling time base timer.
INTTBT interrupt
request
Time Base Timer Control Register Configuration Time Base Timer
Source clock
TBTEN
INTTBT
Interrupt interval Enabling Time Base Timer
Time Base Timer interrupt
Figure 2-12. Time Base Timer
Example: Setting time base timer interrupt frequency fc/216 [Hz] enabling INTTBT interrupt
(TBTCR), 0000001 TBTCK<-010 (TBTCR), 00001010B TBTEN
(EIRL).
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TMP88CS42
TBTCR (00036h)
(DVOEN) (DVOCK) TBTEN TBTCK
(Initial value: 0000 0000)
TBTEN Enable/disable time base timer Disable Enable
TBTCK Select time base timer interrupt frequency Unit: NORMAL IDLE Modes
DV1CK DV1CK=
fc/223 fc/221 fc/216 fc/214 fc/213 fc/212 fc/211 fc/29 fc/224 fc/222 fc/217 fc/215 fc/214 fc/213 fc/212 fc/210
Note High-frequency clock [Hz] Note sure write
Figure 2-13. Time Base Timer Control Register Table 2-1. Time Base Timer Interrupt Frequency (Example: MHz)
TBTCK Time Base Timer Interrupt Frequency [Hz]
NORMAL IDLE Modes
DV1CK DV1CK=
2.38 1.19
9.54 4.77
305.18 152.59
1220.70 610.35
2441.41 1220.70
4882.81 2441.41
9765.63 4882.81
39062.50 19531.25
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2003-06-03
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Watchdog Timer (WDT)
watchdog timer fail-safe function which when operates erratically runs control) becomes locked reasons noise, etc., detects fault condition soon possible returns normal condition.
runway detection signal output watchdog timer reset output pseudo-nonmaskable interrupt request selected program. However, this setting effective only once. When reset, this setting initialized reset output selected.
When using watchdog timer runway detection, used timer generate interrupt request fixed intervals.
Note: Care must given system design protect Watchdog timer from disturbing noise. Otherwise Watchdog Timer fully exhibit functionality.
2.4.1 Configuration Watchdog Timer
Figure 2-14. Configuration Watchdog Timer
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2.4.2 Controlling Watchdog Timer
watchdog timer control registers shown Figure 2-15. After reset, watchdog timer enabled.
affected disturbing noise, etc., watchdog timer able display full function. Take this into consideration when designing your application system.
Detecting runway condition using watchdog timer
detect runway condition CPU, follow procedure described below.
detection time, select output, clear binary counter.
Repeatedly clear binary counter within every detection time that set.
runs control locks some reason binary counter cannot cleared, overflow signal from binary counter activates watchdog timer output. WDTOUT= this time, internal hardware reset. WDTOUT watchdog timer interrupt (INTWDT) generated.
During STOP mode (including warm-up) IDLE mode, watchdog timer temporarily stops counting after exiting STOP IDLE mode, automatically restarts (continues counting up).
Example: Setting watchdog timer detection time 221/fc resetting runway detection
Within detection time
Within detection time
(WDTCR2), (WDTCR1), 00001101B (WDTCR2),
(WDTCR2),
(WDTCR2),
Clearthe binary counter WDTT WDTOUT Clearthe binary counter (Always clear immediately before after changing WDTT)
Clearthe binary counter
Clearthe binary counter
Note: watchdog timer consists internal divider two-stage binary counter. When clear code written, only binary counter cleared, internal divider. Depending timing which clear code written WDTCR2 register, overflow time binary counter minimum time WDTCR1 <WDTT>. Thus, write clear code using shorter cycle than time WDTCR1 <WDTT>.
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2003-06-03
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Watchdog Timer Control Register
WDTCR1 (00034h)
(Initial value: ****1001)
WDTEN Enable/Disable watchdog timer Disable (necessary write disable code WDTCR2) Enable
NORMAL Mode
watchdog timer DV1CK DV1CK= Write only
WDTT detection time Unit: seconds 225/fc 223/fc 221/fc 219/fc 226/fc 224/fc 222/fc 220/fc
WDTOUT Select watchdog timer output Interrupt request Reset output
Note Note Note
Note
Note
Note Note
Once WDTOUT cleared toO, cannot back again program, high-frequency clock [Hz], Don't care
Because WDTCR1 Register write only register, cannot accessed with manipulating other read-modify-write instructions. This because register read, indeterminate value read
When placing device STOP mode, disable Watchdog Timer clear counter immediately. Also, counter cleared before entering STOP mode, clear counter more time immediately after exiting STOP mode.
disable watchdog timer, always write "4EH" (clear code) WDTCR2 clearing binary counter before writing toWDTEN,and then write "B1H" (disable code) toWDTCR2. Also, immediately before these procedure, disable interrupt mater flag (IMF) instruction. Clear binary counter before after changing WDTT field.
watchdog timer consists internal divider two-stage binary counter. When clear code written, onlythe binary counter iscleared, internal divider.
Depending timing which clear code written WDTCR2 register, overflow time binary counter minimum time WDTCR1 <WDTT>. Thus, write clear code using shorter cycle than time WDTCR1 <WDTT>.
Watchdog Timer Control Register
WDTCR2 (00035h)
(Initial value: ********)
WDTCR2
Write watchdog timer control code
4Eh: Clear watchdog timer's binary counter (clear code)
B1H: Disable watchdog timer (disable code) Other: effect
Write only
Note disable code effect unless written when WDTEN Note Don't care
Note clear Watchdog Timer's binary counter interrupt task. Note Write clear code within time WDTCR1 <WDTT>.
Note Read-modify-write instructions, such manipulation instruction, cannot access WDTCR2 register because this register write only.
Figure 2-15. Watchdog Timer Control Registers Enabling watchdog timer
WDTEN (WDTCR1 Register enable watchdog timer. When reset, WDTEN initialized that watchdog timer starts operating immediately after reset.
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Disabling watchdog timer
After clearing WDTEN (WDTCR1 Register write disable code WDTCR2 register disable watchdog timer. Conversely, watchdog timer cannot disabled writing disable code (B1H) WDTCR2 register before clearing WDTEN While watchdog timer disabled, binary counter remains cleared.
Note: Just right before disabling watchdog timer, disable acceptance interrupts (DI) clear wathcdog timer.
watchdog timer disabled under conditions other than above, proper operation cannot guaranteed.
Example: Disables interrupt acceptance
(WDTCR2), Clears watchdog timer.
(WDTCR1), B100H Disables watchdog timer.
Enables interrupt acceptance.
Table 2-2. Watchdog Timer Detection Time (Example: MHz)
WDTT Watchdog Timer Detection Time
NORMAL Mode
DV1CK DV1CK
1.678 3.355
419.430 838.861
104.858 209.715
26.214 52.429
Note: watchdog timer disabled during watchdog timer interrupt processing, watchdog timer interrupt will never cleared. Therefore, clear watchdog timer before disabling disable watchdog timer sufficient time before overflows.
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2003-06-03
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2.4.3 Watchdog Timer Interrupt (INTWDT)
This pseudo-nonmaskable interrupt which always accepted matter interrupt enable register set. However, this interrupt occurs while preceding watchdog timer interrupt software interrupt already being serviced, kept waiting acceptance until processing under finished (RETN instruction execution finished).
Note that before watchdog timer output selected interrupt request with WDTOUT, stack pointer must first set.
Example: Setting watchdog timer interrupt 0023FH SetSP
(WDTCR1), 00001000B WDTOUT<-0
2.4.4 Watchdog Timer Reset
This signal resets internal hardware. reset time is8/fcto 24/fc (0.4 atfc MHz).
219/fc
Clock
Binary counter
Overflow INTWDT interrupt
Internal reset
217/fc
(When WDTT
TXZ^ZXDQC
reset occurs.
Writing WDTCR2
Figure 2-16. Watchdog Timer Interrupt Reset
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2003-06-03
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Divider Output (DVO)
using divider timing generator, possible produce approximately duty cycle pulse which used piezoelectric buzzer drive, etc. divider output outside from (DVO) pin.
DVOEN (TBTEN) (TBTCK)
TBTCR (00036h)
(Initial value: 0000 0000)
DVOEN Enable/disable divider Disable
output Enable
NORMAL IDLE Modes
Select divider output (DVO pin) frequency Unit: DV1CK DV1CK=
DVOCK fc/213 fc/212 fc/211 fc/210 fc/214 fc/213 fc/212 fc/211
Note High-frequency clock [Hz]
Note When selecting divider output frequency, make sure divider output disabled. change divider output frequency when disabling divider output while active.) Note sure write
Figure 2-17. Divider Output Control Register Example: When producing 2.44 pulse (when MHz)
(PI).
(P1CR), 00001000B
(TBTCR), 00000000B
(TBTCR), 10000000B
output latch output mode DVOCK
Table 2-3. Divider Output Frequency (Example: MHz)
DVOCK Divider Output Frequency [Hz]
NORMAL IDLE Modes
DV1CK DV1CK
2.4414 1.2207
4.8828 2.4414
9.7656 4.8828
19.5313 9.7656
Output latch
Output data
fc/213, fc/214 fc/212, fc/213 fc/211, fc/212 fc/210, fc/211
Output mode (DVO)
DVOCK
Divider Output Control Register Configuration divider output circuit
output latch_J"
DVOEN
-TTUUin
Divider output timing chart
Figure 2-18. Divider Output
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2003-06-03
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16-Bit Timer/Counter (TC1) 2.6.1 Configuration
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2.6.2 Control
Timer/counter controlled using timer/counter control register (TC1CR) 16-bit timer registers (TC1DRA TC1DRB).
Timer Register
TC1DRA (00011,00010H) DRAh (00011H)
(Initial value: 1111111111111111) Read/Write
TC1DRB (00013, 00012H) TC1DRBh (00013H) TCIDRBl, (00012h)
(Initial value: 1111111111111111) Read/Write (Can written only during output mode)
Timer/Counter Control Register
TC1CR ACAP1
(0000FH) TFF1 MCAP1 METT1 MPPG1 TC1S TC1CK TC1M (Initial value: 0000 0000)
TC1M Select operation mode Timer/Counter Timer/external trigger timer/event counter modes Window mode Pulse width measurement mode (Programmable Pulse Generate) output mode
TC1CK Select source clock Timer/Counter Unit: NORMAL IDLE Modes
DV1CK DV1CK=
fc/211 fc/27 fc/23 fc/212 fc/28 fc/24
External clock (TC1 DUt)
TC1S Control start Timer/Counter Timer External Event Window Pulse
Stop clear counter
Command start
External trigger rising edge start
External trigger falling edge start
ACAP1 Control soft capture Disable automatic capture Enable capture
MCAP1 Control pulse width measurement mode Capture both edges Capture edge
METT1 Control external trigger timer mode Trigger start Trigger start stop
MPPG1 Control output Successive shot
TFF1 Control timer F/F1 Clear
Note Clock [Hz]
Note When writing timer registers, write first lower byte then upper byte continuously. recommended that 16-bit access instruction used write.
timer registers configured 2-stage shift registers, timer register value becomes valid next rising edge source clock after data written upper byte (TC1DRAH, TC1DRBH). Note that writing only lower byte (TC1DRAL, TC1DRBL) does make register value valid. Note Make sure timer/counter idle (TC1S before setting operation mode, source clock, output control, timer F/F1 control.
Note Automatic capture only used timer, event counter, window modes. Note values timer registers must meet conditions shown below.
(PPG output mode) (other than output mode) Note SetTFFI mode other than output mode.
Note Register cannot written unless output mode operation mode.
Note When STOP mode entered, start control (TC1S) cleared timer stopped. this time, other registers held data before then. After returned from STOP mode, setting toTCIS, timer restarted.
Figure 2-20. Timer Registers Control Register Timer/Counter
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2.6.3 Function
Timer/counter operation modes: Timer, external trigger timer, event counter, window, pulse width measurement, (programmable pulse generate) output modes.
Timer mode
this mode, timer/counter counts synchronously with internal clock. When counter value value Timer Register (TC1DRA) match, INTTC1 interrupt request generated counter cleared. timer/counter continues counting even after counter cleared. setting ACAP1 (TC1CR Register content counter that point time latched into Timer Register (TC1DRB) (automatic capture function).
Table 2-4. Internal Source Clock Timer/Counter (Example: MHz)
TC1CK NORMAL IDLE Modes
DV1CK DV1CK=
Resolution [us] Maximum Setting Time Resolution [us] Maximum Setting Time
102.4 6.7108 204.8 13.4216
0.4194 12.8 0.8388
26.214 52.428
Example Sets timer mode with source clock fc/211 [Hz] generates interrupt second later MHz, DV1CK
(TC1DRAL), 2625H Sets timer register 211/fc 2625H)
(EIRD).
(TC1CR), 00000000B (TC1CR), 00010000B
Esample2: Auto-capture
(TC1CR), 01010000B
(TC1DRBL)
Enable INTTC1
Select source clock operating mode Starts
ACAP1<-1 (Capture) Reads capture value
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2003-06-03
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Command start
Source clock
Counter
jxitummi^
XDGDGXDC
Timer Register
INTTC1 interrupt request Coincidence detection Counter clear
Timer mode
Source clock
Counter
Timer Register
Capture
X_liiJCI||IIX
Capture
ACAP1
Automatic capture
Figure 2-21. Timer Mode Timing Chart
External trigger timer mode
this mode, counting started external trigger. This trigger edge theTCI input. Either rising falling edge selected with TC1S. Source clock internal clock. contents TC1DRA compared with contents counter. match found, INTTC1 interrupt request generated, counter cleared halted. counter restarted selected edge theTCI input.
When METT1 (bit TC1CR) "1", inputting edge reverse direction trigger edge start counting clears counter, counter stopped. Inputting constant pulse width generate interrupts. When METT1 "0", reverse directive edge input ignored. input edge before match detection also ignored.
input noise rejection; therefore, pulses 4/fc less rejected noise. pulse width 12/fc more required edge detection NORMAL IDLE mode.
Example Detects rising edge input generates interrupt later, MHz, DV1CK "0")
23/fc
Example
(TC1DRAL), 00FAH
(EIRD).
(TC1CR), 00001000B
(TC1CR), 00101000B
Generates interrupt, inputting pin. MHz, DV1CK "0") (TC1 DRAL), 0270H
(EIRD).
(TC1CR), 01000100B (TC1CR), 01110100B
INTTC1 enable
Select source clock operating mode external trigger start, METT1
level pulse (pulse width: more) 27/fc 0270 INTTC1 interrupt enable
Select source clock operating mode, METT1 external trigger start
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INTTC1 interrupt
Count start
input
Internal clock
counter
Count start
TC1S rising edge
JUUUUIJUI-JUUUUUUUUUUU^
Match detect Counter clear
INTTC1 interrupt
input
Internal clock
counter
Count start
Trigger start (METT1
Counter clear Count start
TC1S rising edge
mmnm thhihi IFYY
Match detect
Counter clear
Trigger start stop (METT1
Note:
Figure 2-22. External TriggerTimer Mode Timing Chart
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2003-06-03
TMP88CS42
Event counter mode
this mode, events counted edge input. Either rising falling edge selected with TC1S. contents TC1DRA compared with contents counter. match found, INTTC1 interrupt generated, counter cleared. more machine cycles required both levels pulse width.
Match detect executed other edge count match detected INTTC1 generated when pulse still same state.
Setting ACAP1 transfers current contents counter TC1DRB (Auto-capture function).
Count start
Figure 2-23. Event Counter Mode Timing Chart Table 2-5. Input Pulse Width Timer/Counter External Clock Source
Minimum pulse width
NORMAL IDLE Modes
width 23/fc
width 23/fc
88CS42-61
2003-06-03
TMP88CS42
Window mode
timer/counter counts rising edge AND'ed pulses input (window clock) internal clock. When counter value value TC1DRA Register match, INTTC1 interrupt generated counter cleared. input chosen active-high active-low using TC1CR Register bits which provided selecting external trigger edge.
maximum applied frequency must sufficient count value analyzed program. Namely, must sufficiently slower than internal clock.
input
Internal clock
Counter
Command start
irmiirirLJiJW
STTTYTYTX XTyTWTYTYTX-
Timer Register INTTC1 interrupt
Coincidence detection
Counter clear
Command start
When active-high (TC1S
input
Internal clock
Counter
irmnnjiji^
rncrrjicTYTY
Timer Register INTTC1 interrupt
Coincidence detection
When active-low (TC1S=
Figure 2-24. Window Mode Timing Chart
88CS42-62
2003-06-03
TMP88CS42
Pulse width measurement mode
Counting started external trigger, which edge pulse input (set external trigger start TC1CR). trigger selected TC1CR<TC1S> either rising falling edge input. source clock selected TC1CR<TC1CK>. When start external trigger TC1CR, rising (falling) edge input triggers start counting. (For source clock, select internal clock.) next falling (rising) edge, counter value loaded TC1DRB INTTC1 request generated.
one-edge capture operation, capture values from capture onward increase compared with capture value immediately after count start (See figure below). both-edge capture set, counter continues counting counter value loaded again next rising (falling) edge.
Single edge double edge selected with TC1CR<MCAPI
Note sure read capture value from timer register before next trigger edge
detected. capture value cannot read, becomes undefined. Note capture value timer register read 16-bit access instruction.
Example: Duty measurement (resolution fc/27 [Hz]; atDV1CK
(INTTC1SW). INTTC1 service switch initial setting
(TC1CR), 0000011 Sets mode source clock, MCAP1
(EIRD). Enables INTTC1
(TC1CR), 00100110B Starts with external trigger
PINTTC1 (INTTCISW).O
SINTTC1
(TC1DRBL)
(HPULSE), RETI
SINTTC1 (TC1DRBL)
(WIDTH),
RETI
Complements INTTC1 service switch Reads ("H" level pulse width)
Reads (Period) Duty calculation
VINTTC1 PINTTC1
INTTC1 vector setting
WIDTH
HPULSE
INTTC1
INTTC1SW
88CS42-63
2003-06-03
Count start
Count start
input
Internal clock
juuiTLJLrLrL.JiJirL^^
counter fr-^bM
Capture Capture
TC1DRB
INTTC1 interrupt
Single edge capture {MCAP1
[Application] "H"or"L" level pulse width measurement
Count start Count start
input
Internal clock juinjijWLj^ .jirLrLarLiL.juirLrL
counter Xn-lX Xn+lXn+2X Xn'+iXn'+2
Capture Capture Capture
TC1DRB
INTTC1 interrupt
[Application] Period/Frequency measuremnt Duty measuremnt
Double edge capture (MCAP1
Figure 2-25. Pulse Measurement Mode Timing Chart
TMP88CS42
Programmable pulse generate (PPG) output mode
this mode, random duty pulse generated output.
Counting started edge input (either rising falling edge selected). source clock selected TC1CR<TC1CK>. First, contents TC1DRB compared with contents counter. match between counter value value TC1DRB inverts timer F/F1, same time generates INTTC1. next match between counter value value TC1DRA inverts timer F/F1 again, clear counter, generates INTTC1. case single output (MPPG 1),TC1CS automatically cleared "00" timer stops counting. Writing "00" TC1CS, while timer counting, stops timer operation clears counter. this case output keeps same level just before timer stopped. Timer F/F1 output connected (PPG) pin. case output, output latch configure output with P1CR4. timer F/F1 cleared during reset. Since timer F/F1 value TC1CRCTFF1 either positive negative since pulse output. Also, writing TC1DRB possible unless timer/counter output mode.
Note change time F/F1 TFF1 while operating. timer F/F1 value cleared only initial setting. Setting clearing timer F/F1 value, while counting after stops counting, inverts output. After stops, necessary initialize timer F/F1 change output desired level. initialize F/F1, change timer mode once (the timer mode need started) then output mode also TFF1 again.
Note restart output mode, necessary initialize timer F/F1. initialize timer F/F1, change timer mode once (the timer mode need started), then output mode, also setTFFI again.
Note timer register change should done while disabled (TC1S 00). When changing timer register value while counting, sufficiently larger value than count value counter.
smaller value than count value counter timer register, comparison performed makes counter overflow.
Example: Pulse output level level MHz, DV1CK "0")
(P1DR). (P1CR), 00010000B (TC1CR), 10001011B (TC1DRAL), 9C4H (TC1DRBL), 1F4H
output latch
Sets output mode
Sets output mode
Sets period 23/fc 9C4H)
Sets level pulse width
(200 23/fc 1F4H)
(TC1CR), 10011011B
Starts
88CS42-65
2003-06-03
TMP88CS42
P14(PPG)
Timer F/F1
Figure 2-26. Output
88CS42-66
2003-06-03
TMP88CS42
Internal clock
Command start
Successive
Count start
input ^Trigger
Note:
External trigger start
Internal clock
JUlAArLAAJlJW
counter
TC1DRB
Match
DRa"X output
INTTC1 interrupt request
Note:
shot
[Application] shot pulse output
Figure 2-27. Output Mode Timing Chart
88CS42-67
2003-06-03
TMP88CS42
16-Bit Timer 2.7.1 Configuration
88CS42-68
2003-06-03
TMP88CS42
2.7.2 Control
Compare timer/counter controlled using Compare timer/counter Control Registers (CTC1CR1 CTC1CR2), well three 16-bit Timer Registers (CTC1DRA, CTC1 DRB, CTC1DRC).
Compare Timer Registers (CTC1 DRH:00017H CTC1DRL00016H)
CTC1 Write Only
CTC1DRAH CTC1DRAL (Initial value: ******** ********)
Write Only
CTC1DRBH CTC1DRBL (Initial value: ******** ********)
CTC1 Write Only
CTC1DRCH CTC1DRCL (Initial value: ******** ********)
Note: CTC1 DRA, CTC1 DRB, CTC1 write-only registers must used with read-modify-write instructions such SET, CLR, etc.
Compare Timer/Counter Control Registers (CTC1CR2:00015H CTC1CR1:00014H)
CTC1CR1
lower address CTC1RES PPGFFO CTC1M CTC1CY CTC1SE CTC1E CTC1SM CTC1S (Initial value: 00000000)
CTC1CR2
upper address EXTRGDIS CTC1REG CTC1CK CTC1FF0 (Initial value: *0000000)
Note Don't care Note CTC1CR1 Register (CTC1 RES) when read. Note instruction write CTC1 Registers. value equal greater than Note Write CTC1 Registers many with CTC1CR2 Register CTC1 bit. Note Data written CTC1 Registers order CTC1 DRA, CTC1 DRB, CTC1 DRC.
Figure 2-29. Control Registers
88CS42-69
2003-06-03
TMP88CS42
Setting-up CTC1CR1 Register
CTC1S Control start Timer Event
Stop clear counter Command start
CTC1SM Select start Software start External trigger start
CTC1E Select external trigger edge Enable edge Enable both edges
CTC1SE Select external trigger start edge Rising edge Falling edge
CTC1CY Select cycle Successive shot
CTC1M operation mode Timer/event counter mode (programmable pulse generator) output mode
PPGFF0 Select output Forward output immediately after start Reverse output immediately after start
CTC1RES Reset Normal operation CTC1 reset
Setting-up CTC1CR2 Register
CTC1FF0 Control timer output F/F0 Clear
NORMAL IDLE Modes
DV1CK DV1CK=
CTC1CK Select timer/counter clock source Unit: fc/211 fc/27 fc/25 fc/23 fc/22 fc/2 fc/212 fc/28 fc/26 fc/24 fc/23 fc/22 fc/2
External clock input (CTC1 input)
CTC1REG registers used timer/counter CTC1DRA CTC1DRA CTC1 CTC1 CTC1 CTC1 Reserved 2REG 3REG
EXTRGDIS External trigger input Enable external trigger input Disable external trigger input
Clock [Hz]
Note Make sure timer/counter idle (CTC1S CTC1SM before setting operation mode, edge, start,
source clock, external trigger timer mode control, output control. Note number registers values timer registers must meet conditions shown below.
Timer Register Value Condition
CTC1CT 16-bit counter Register CTC1
Register CTC1 CTC1 CTC1
Register CTC1 CTC1 CTC1 CTC1 CTC1
Note CTC1DRB CTC1DRC Registers cannot accessed write unless they output mode specified with CTC1 REG.
Note Data must written many data registers with CTC1 REG.
Note write data toCTO DRA/B/C, instruction, instruction writing order
Note Data register values must written respective registers before starting. modify values after starting, write data within interval from INTCTC1 interrupt next INTCTC1.
Note7: Specifying CTC1 causes conditions reset. Even when device operating, they reset, output becomes "0". However, only CTC1 signal reset signal being generated.
Note event counter mode (when CTC1 input selected timer mode), active edge external trigger count selected with CTC1SE.
Note Disabling external trigger input with EXTRGDIS creates input state.
Note CTC1E effective only when using external clock trigger.
Note stop counter software trigger start, CTC1SM CTC1S
Figure 2-30. Functions Control Registers
88CS42-70
2003-06-03
TMP88CS42
2.7.3 Function
Compare timer/counter three modes: timer, event counter, programmable pulse generator output modes.
Timer mode with software start
this mode, timer/counter (16-bit counter) counts synchronously with internal clock. When counter value value Compare Timer Register (CTC1DRA) match, INTCTC1 interrupt generated counter cleared. After counter cleared, restarts continues counting
Table 2-6. Internal Clock Source Compare Timer/Counter (Example: MHz)
CTC1CK NORMAL IDLE Modes
DV1CK DV1CK=
Resolution [us] Maximum Setting Time Resolution [//s] Maximum Setting Time
102.4 6.71 204.8 13.42
0.419 12.8 0.839
0.105 0.210
26.21 52.43
13.11 26.21
6.55 13.11
0.05 3.28 6.55
Note: input port (P47) input mode, timer/counter reset input edge port. When using timer/counter ordinary timer, EXTRGDIS output mode.
88CS42-71
2003-06-03
TMP88CS42
Timer mode with external trigger start
this timer mode, timer/counter starts counting triggered input CTC1 (rising falling edge selected with CTC1SE). source clock internal clock. successive cycles, when counter value value CTC1DRA Register match, INTCTC1 interrupt generated counter cleared then restarted. counter stopped trigger input CTC1 restarted next trigger input. one-shot cycle, when counter value value CTC1DRA Register match, INTCTC1 interrupt generated counter cleared stopped. counter restarts counting input CTC1 pin. When CTC1E (CTC1CR2 Register counter cleared stops counting edge CTC1 input opposite active edge that triggers counter start counting. this mode, interrupt generated entering pulse which certain width. When CTC1E opposite edges CTC1 input ignored.
When rising edge start selected, with counting enabled edge (CTC1SE CTC1E
Count start
Stop
Count start
CTC1 input Internal clock Counter
^Trigger
^Trigger
^Trigger
Timer
Register )(~n'
Clear_
xixz
INTCTC1 interrupt
CTC1 input Internal clock Counter
Successive
Count start
Count start
^Trigger
^Trigger
ruuiA
IXZJCZXjXEXjX
xixdcbcdcdg:
Timer
Register )(~n'
INTCTC1 interrupt
shot
Figure 2-32. External Trigger Mode Timing Chart
88CS42-72
2003-06-03
TMP88CS42
(II) When rising start edge selected, with counting enabled both edges (CTC1SE CTC1E
Count start
CTC1 input Internal clock Counter
^Trigger
Count stop
Count start
Trigger
^Trigger
Timer
Register
INTCTC1 interrupt
CTC1 input
n_riJ~LJViJ~LJiJiJ~Lrv^
xixt
Count start
Successive Count start
Note:
Count clear
^Trigger
Trigger
^Trigger
Internal clock Counter
Timer Register )(~n
INTCTC1 interrupt
FLTLTLA XZXDC^GX
shot
Figure 2-33. External Trigger Mode Timing Chart
Event counter mode
this mode, timer/counter counts active edge CTC1 input (rising falling edge selected with CTC1CR1 Register which provided selecting external trigger edge). When counter value value CTC1DRA Register match, INTCTC1 interrupt generated counter cleared. After counter cleared, restarts continues counting each edge CTC1 input. maximum applied frequency shown table below. Because coincidence detection made edge opposite selected edge, external clock signal must always entered.
Figure 2-34. Event Counter Mode Timing Chart Table 2-7. External Clock Source Compare Timer/Counter
NORMAL IDLE Modes
Maximum applied frequency [Hz] fc/22
Minimum pulse width 22/fc over
88CS42-73
2003-06-03
TMP88CS42
Programmable pulse generate (PPG) output mode
timer/counter starts counting triggered rising falling edge CTC1 input (with active edge one/both edges respectively selected with CTC1SE (CTC1CR1 Register CTC1E (CTC1CR1 Register command. source clock internal clock. When matched with CTC1DR A/B/C Registers, timer output corresponding each mode inverted. When matched with CTC1DR A/B/C Registers next time, timer output inverted again. INTCTC1 interrupt request generated when counter value matches maximum register value CTCREG (CTC1CR2 Register bits timer output cleared when reset. Because CTC1FF0 (CTC1CR2 Register used initial value timer output F/F, active-high active-low pulse whichever desired output. CTC1DRB CTC1DRC Registers cannot accessed write unless they output mode registers used selected with CTC1REG (CTC1CR2 Register bits number registers altered during operation. this case, however, sure number registers used write values data registers before next CTC1INIT1 output after first CTC1INIT1 output. Even when only altering data register values while leaving number registers unchanged, sure this within same period time.
Table 2-8. Internal Clock Source Compare Timer/Counter (Example: MHz)
CTC1CK NORMAL IDLE Modes
DV1CK DV1CK=
Resolution [us] Maximum Setting Time Resolutio
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