Samar Al-Khairi APCD Design Engineering Abstract Power manag

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Power Management Features Embedded Ultra Low-Power Processor
Samar Al-Khairi APCD Design Engineering
Abstract
Power management features becoming essential embedded market segment. ultra low-power embedded processor contains power saving features offered Intel486 enhanced processors plus additional ones. These power saving features include mode, Stop Clock mode, Auto Halt Power down mode, enhanced auto clock freeze mode. enhanced auto clock freeze control completely transparent external chip designed affect operation way. Auto clock freeze consists parts: Global clock freeze (clock throttle) control local clock freeze control. This paper discusses power saving features offered ultra low-power embedded Intel486 processor with emphasis auto freeze features providing timing diagrams illustrations when applicable.
With push towards power applications, power consumption become important consideration design embedded processors. complexity processors target frequency grows, power management features start play important role. power essential embedded applications since battery life directly related power consumed. Intel486 embedded processor offers aggressive power saving techniques dynamically manage power consumption chip. These techniques classified into major categories: macro level software system controlled power management methods micro level dynamic software system transparent methods.
first category, embedded Intel486 processor provides software hardware controllability operating system system hardware allowing them power down processor when needed. means which this achieved hardware interrupt pin, STPCLK#, that allows system hardware control power consumption processor adjusting input controlled sequence. Another achieving power state executing HALT instruction. Upon execution HALT, processor will automatically enter power state called auto halt powerdown state. second category, embedded Intel486 processor provides dynamic local
power management features where idle parts processor shut down their clocks save power. example Kcache Unit freezes clocks processor determines that cache access cycle will run.
Enhanced Auto Clock Freeze Mode
Auto Clock freeze feature embedded Intel486 processor consists parts: local clock freeze control global clock freeze control. Local clock freeze controls clocks used local unit (Bunit, Cunit,.) while global clock freeze "Clock Throttle" controls global clock distribution ph2. Auto clock freeze control features designed decline processor performance completely transparent external system.
Figure shows clock distribution embedded Intel486 processor. global clock freeze controlled circuitry within clock unit. circuitry checks several internal pipeline status based that gates clock output from clock generator unit. internal pipeline empty stalled then clocks frozen. During memory wait cycles, HOLD/HLDA cycles, AHOLD cycles BOFF# cycles, clocks frozen clock unit causing significant power savings. freeze break conditions such RDY#, INTR, BOFF# will restart clocks when asserted. total power consumption that saved from global clock freeze feature order 10mA 3.3V MHz.
Local clock freeze relies control signals within embedded processor indicate clocks particular block frozen. These control signals gate clocks local units once activated clocks local blocks frozen causing significant power savings. total power consumption that saved from local clock freeze order 25mA 3.3V MHz.
STPCLK# Auto Halt Powerdown
Intel486 embedded processor implements software system power management strategies form STPCLK# HALT instruction. STPCLK# implemented priority level interrupt. Upon recognition interrupt, embedded processor executes microcode sequence which stops execution next instruction boundary, stops prefetch unit, empties internal pipelines write buffers, generates Stop Grant cycle, stops internal clock. processor will
acknowledge Stop Grant state when RDY# BRDY# been returned active. During Stop Grant state processor power consumption drops 15-25 (depending input frequency). input completely stopped, processors enters into Stop Clock state where power consumption drops 35-45
Power management using HALT instruction essentially similar Stop Clock mechanism. Upon execution HALT instruction, processor will automatically enter power state called Auto Halt
Powerdown State. processor will issue normal HALT cycle when entering this state. system generate STPCLK# while processor Auto Halt powerdown state. this occurs, processor will generate Stop Grant cycle enter Stop Grant State from Auto Halt Powerdown state. Upon de-asserting STPCLK# processor returns Auto Halt powerdown state. Figure illustrates state transitions between Stop Clock Auto Halt Power down states.
Clock Unit
Global clock freeze control circuitry
phl/2
Bunit bphl/2
freeze- bunit
Punit phl/2
freeze- punit
Figure Clock Distribution Diagram
System Management Mode (SMM)
This mode composed special purpose interrupt (SMI#) that serves hardware interface secure memory address space that stores processor status handlers. handlers special software routines that perform various system management functions including system power control. When SMI# asserted Intel486 embedded processor will respond interrupt
asserting SMIACT#. processor then saves state into SMRAM area will start executing handlers. last instruction handler instruction which will restore processor state from SMRAM, de-assert SMIACT#, return control interrupted program. processor most active component system. Therefore, clock control mode allows saving processor power.
syste^n change input frequency within specified range completely stop input frequency.
Figure Processor Stop Clock State Diagram
Save state processor
Handler
SMI#
SMIACT#
State Restore
Figure Basic SMI# Interrupt Service
Conclusion
technology advances faster processor operation required, efficient power management techniques become crucial meeting low-power high speed computing demands. Power management done both system level processor level. Intel486 embedded processor implements aggressive techniques
References
achieving this goal. operating system system hardware provided with hooks allow them control power activity processor. addition, auto clock freeze feature allows significant power savings without significant degradation processor performance.
Microprocessors Related Products, Intel Corporation, Santa Clara, California, 1995.
P24D Processor External Design Specification, Intel Corporation, 1994.
Embedded Ultra Low-Power Processor EDS, Intel Corporation, 1995.
Desmond Yuen, "Intel's Architecture", McGraw-Hill series, 1993.
Masaru Ishigami, Processor Design Consideration Mobile Systems", Intel Corporation, 1994.
Intel Reference Numbers
World Wide Address: FaxBack Systems
Application Bulletin Board System: Intel Literature Centers Retail Network Products: General Information Hotline:
p://w ntel.com (800) 525-3019 (503) 264-6835 (503) 264-7998
(800) 548-4725 a.m. p.m. (800) 538-3373 (503) 629-7000 a.m. p.m. (800) 628-8686 (916) 356-3104 a.m. p.m.
Intel Corporation assumes responsibility circuitry other than circuitry embodied Intel produci other circuit patent licenses implied Information contained herein supercedes previously published specifications these devices fiom Intel. Other brands names property their respective owners. Corporation 1996
UNITED STATES Intel Corporation 2200 Mission College Blvd. Santa Clara, 95052-8119
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