CMOS 8-BIT MICROCONTROLLER TMP87CC31N, TMP87CH31N 87CC31/H31
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TMP87CC31/H31
CMOS 8-BIT MICROCONTROLLER
TMP87CC31N, TMP87CH31N
87CC31/H31 high speed high performance 8-bit single chip microcomputer. This contains core, ROM, RAM, input output ports, multi-function timer counters, on-screen display, PWM, 6-bit conversion inputs remote control signal preprocessor chip.
PART PACKAGE
TMP87CC31N Kbytes bytes SDIP42-P-600-1.78 TMP87PM36N
TMP87CH31N Kbytes
8-bit single chip microcomputer TLCS-870 Series
instruction execution time MHz) basic instructions
Multiplication Division bits bits, bits bits)
manipulations (Set/ Clear/ Complement/ Move /Test/ Exclusive
16-bit data operations
1-byte jump/subroutine-call (Short relative jump/Vector call)
interrupt sources (External Internal:
sources have independent latches each, nested interrupt control available.
Edge-selectable external interruptswith noise reject
High-speed task switching register bank changeover
Input/Output ports pins)
High current output: pins (typ. 16-bit Timers 8-bit Timer Counters
Timer, Event counter, Capture (Pulse width duty measurement) modes Base Timer (Interrupt frequency 16384 Timer
Interrupt source reset output (programmable) display circuit
SDIP42-P-600-1.78
TMP87CC31N
TMP87CH31N
characters
24colurrmsx4 lines
dots
kinds (line line)
kinds (character character)
Horizontal steps, Vertical steps
Character patterns
Characters displayed
Composition
Size character
Color character
Variable display position
Fringing, Smoothing function
conversion (Pulse Width Modulation) outputs
14-bit resolution channel)
7-bit resolution channels) conversion input channels)
Pulse output (Clock
Remote control signal preprocessor Power saving operating modes
STOP mode Oscillation stops. Battery/Capacitor back-up. Port output hold/high-impedance.
IDLE mode stops, Peripherals operate. Release interrupts. voltage
Emulation BM87CM37N0A
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TMP87CC31/H31
ASSIGNMENTS (TOP VIEW)
SDIP42-P-600-1.78
BLOCK DIAGRAM
^P34 ^P33 (TC4) ^P31 (TC3) (INT3/RXIN)
}<-^P20(INT5/STOP)
PRESET
'-XIN
]-*"OSC2
(VD) (HD) (Y/BL) >^-P65
Ports
Ose. connecting pins OSC1" on-screen OSC2-display
Power VDD" Supply VSS-
Display Memory
Character
Y/BL B,G,R
On-screen display circuit
Flags
Reset RESET -Test TEST
Resonator XIN" Connecting \XOUT~' Pins
Systerr Controller
Standby Controller
Timing Generator
High Clock
frequ. Generator
Stack Pointer
Data Memory (RAM)
Register Banks
Interrupt Controller
Time Base Timer
Watchdog Timer
16-bit Timer
8-bit Timer/Counter
Converter (PWM)
6-bit Converter
Pulse Generator
Program Counter
Program Memory (ROM)
Inst.Register
Inst. Decoder
Remote control signal preprocessor
Ports
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TMP87CC31/H31
FUNCTION
NAME Input/Output Function
(INT5/STOP) (Input) 1-bit input output port with latch. When used input port, latch must External interrupt input STOP mode release signal input
(I/O) 7-bit input/output port with latch. When used input port, timer counter input, remote control signal preprocessor input, external interrupt input, latch must "1".
(I/O)
(I/O)
(TC4) (Input) Timer/Counter input
(INT4) External interrupt input
(TC3) Timer/Counter input
(INT3/RXIN) (Input/Input) External interrupt input remote control signal preprocessor input
(PWM7) (PWM1) (Output) 8-bit programmable input output port (tri-state). Each this port individually configured input output under software control. During reset, bits configured inputs. When used output, latch must 7-bit conversion (PWM) outputs
(PWMO) 14-bit conversion (PWM) output
(CIN3) (CINO) (Input) 8-bit input/output port with latch. When used input port, comparator input, output, pulse output, latch must 6-bit conversion (Comparator) inputs
(PULSE) (Output) Pulse output (Clock
(PWM9) 7-bit conversion (PWM) outputs
(PWM8)
(Y/BL) (Output) 8-bit programmable input output port (P67 tri-state, High current output). Each this port individually configured input output under software control. During reset, bits configured inputs. When used outputs on-screen display circuit, each port data selection register (bits address 0F91H) must Focus signal output Background blanking control signal output
P66(B) output
High current output.
(VD) (Input) 2-bit input output port with latch. When used input ports, vertical synchronous signal input horizontal synchronous signal input, latch must setto Vertical synchronous signal input
(HD) Horizontal synchronous signal input
OSC1, OSC2 Input, Output Resonator connecting pins on-screen display circuitry.
XIN, XOUT Resonator connecting pins. inputting external clock, used XOUT opened.
Reset signal input watchdog timer output/address-trap- reset output/system-clock-reset output.
RESET
TEST Input Test out-going test. tied low.
VDD, Power Supply OV(GND)
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TMP87CC31/H31
OPERATIONAL DESCRIPTION
CORE FUNCTIONS
core consists CPU, system clock controller, interrupt controller, watchdog timer. This section provides description core, program memory (ROM), data memory (RAM), reset circuit.
Memory Address
TLCS-870 Series capable addressing bytes memory. Figure shows memory address maps 87CC31/H31. TLCS-870 Series, memory organized address spaces (ROM, RAM, SFR, DBR). uses memory mapped system, registers mapped address spaces. There banks general-purpose registers. register banks also assigned first bytes address space.
Character
0000H
003F 0040
00BF 00C0
013F 0F80
OFFF 4000
57FF C000
FFFF
bytes
bytes
bytes
Register banks
registers banks) Note Read Only Memory includes:
Program memory RAM; Random Access Memory includes: Data memory Stack
General-purpose register banks SFR; Special Function Register includes: ports
Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word DBR; Data Buffer Register includes:
On-Screen-Display (OSD) control registers
Remote-Control signal preprocessor control status registers
Figure 1-1. Memory Address
COOOH
FF00
FFBF FFC0 FFDF FFE0
FFFF
16128 bytes
bytes
bytes bytes
87CH31
DOOOH
12032 bytes
bytes
bytes bytes
87CC31
COOOH
Vector table vector call instructions vectors) Vector table interrupts/ reset vectors)
Entry area page call instructions
Figure 1-2. Address Maps
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TMP87CC31/H31
Program Memory (ROM)
87CC31 Kbytes (addresses DOOOh FFFFH) 87CH31 Kbytes (addresses COOOh FFFFh) program memory (mask programmed ROM). Addresses FFOOh FFFFh program memory also used special purposes. Figure shows address maps 87CC31/H31.
Interrupt Reset vector table (addresses FFEOh FFFFh)
This table consists reset vector interrupt vectors bytes vector). These vectors store reset start address interrupt service routine entry addresses.
Vector table vector call instructions (addresses FFCOh FFDFh)
This table stores call vectors (subroutine entry address, bytes/vector) vector call instructions [CALLV There vectors. CALLV instruction increases memory efficiency when utilized frequently used subroutine calls (called from more locations).
Entry area (addresses FFOOh FFFFh) page call instructions
This subroutine entry address area page call instructions [CALLP Addresses FFOOh FFBFh normally used because address FFCOh FFFFh used vector tables.
Programs fixed data stored program memory. instruction executed next read from address indicated current contents program counter (PC). There relative jump absolute jump instructions. concepts page bank boundaries used program memory concerning jump instruction.
Example relationship between jump instructions
5-bit PC-relative jump [JRS E8C4H: When jump made E8CEh, which added contents (The contains address instruction being executed+ therefore, this case, contents E8C4H E8C6h-)
8-bit PC-relative jump E8C4H When jump made E846h, which FF80h (-128) added current contents
16-bit absolute jump E8C4H 0C235H unconditional jump made address C235h- absolute jump instruction jump anywhere within entire 64K-byte space.
Address
COOOu
FFOO
FF7B
FFBF FFCO FFC1 FFC2
FFDF FFEO FFE1 FFE2
FFFD FFFE FFFF
call vector
call vector
interrupt vector
nterrupt vector
reset vector reset vector
contents
Example
relationship between Contents Call group instructions/ Interrupt/ Reset
CALLP
CALLV
INT5
RESET
FF7B
C856h
D368
C03E
Figure 1-3. Program Memory
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theTLCS-870 Series, same instruction used access data memory (e.g. (HL)]) also used read fixed data (ROM data) stored program memory. register-offset PC-relative addressing instructions also used, code conversion, table look-up n-way multiple jump processing easily programmed.
Example Loads contents address specified register pair contents into accumulator (HL^ C000Hfor 87CC31/H31): (HL) (HL)
Example Converts 7-segment code (common anode LED). portP5 after executing following program: TABLE-$-4 (TABLE (P5), (PC+A) SNEXT TABLE OCOH, 0F9H, 0A4H, OBOH, 99H, 92H, 0D8H, 80H,
SNEXT
Notes header address instruction. byte data difinition instruction.
Example N-way multiple jump accordance with contents accumulator SHLC then PC<-C234H (PC+A) then PC<-C378H then PC<-DA37H then PC<-E1B0H 0C234H, 0C378H, 0DA37H, 0E1B0H
Note DWis word data definition instruction.
Program Counter (PC)
program counter (PC) 16-bit register which indicates program memory address where instruction executed next stored. After reset, user defined reset vector stored vector table (addresses FFFFh FFFEh) loaded into therefore, program execution possible from desired address. example, when stored addresses FFFFh FFFEh, respectively, execution starts from address C03Eh after reset.
TLCS-870 Series utilizes pipelined processing (instruction pre-fetch); therefore, always indicates addresses advance. example, while 1-byte instruction stored address C123h being executed, contains 25h-
Contents
Program Counter (PC)
Instruction Execution
Configuration Timing chart Contents Instruction Execution
Figure 1-4. Program Counter
When 05h, output
SHLC
_34_
_7_8_
_3_7_
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TMP87CC31/H31
Data Memory (RAM)
87CC31/H31 have bytes (addresses 0040h-013Fh) data memory (static RAM). Figure shows data memory map.
Addresses OOOOh-OOFFh used direct addressing area enhance instructions which utilize this addressing mode; therefore, addresses 0040h-00FFh data memory also used user flags user counters. General-purpose register banks registers banks) also assigned bytes addresses 0040h-00BFh- Access data memory still possible even when being used registers. example, when contents data memory address 0040h read out, contents accumulator bank also read out. stack located anywhere within data memory except register bank area. stack depth limited only free data memory size. more details stack, section "1.7 Stack Stack Pointer".
TLCS-870 Series cannot execute programs placed data memory. When program counter indicates data memory address, error occurs address-trap-reset applies. RESET goes during address-trap-reset.
Example data memory address OOCOh "1", written data memory address 00E3h; otherwise, written data memory address 00E3h: TEST (OOCOH). (00C0H) then jump T.SZERO
(00E3H) (00E3H)<-00H T.SNEXT SZERO (00E3H), OFFH (00E3H)<-FFH SNEXT
Example Increments contents data memory address 00F5h, clears when exceeded:
(00F5H) (00F5H) <-(00F5H)
(00F5H), (00F5H) (00F5H)A0FH
data memory contents become unstable when power supply turned therefore, data memory should initialized initialization routine. Note that general-purpose registers mapped therefore, dear current bank addresses.
Example Clears "00h" except bank
0048H Sets start address register pair Sets initial data (00h) register
03F7H Sets number byte register pair SRAMCLR (HL+),
SRAMCLR
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TMP87CC31/H31
Address 0040h 0050 0060 0070 0080 0090 00A0 00B0 00C0 00D0 OOEO OOFO 0100 0110 0120 0130
Register bank Register bank
Register bank Register bank
Register bank Register bank
Register bank Register bank
Register bank Register bank
Register bank Register bank
Register bank Register bank
ster Register
Direct addressing area
Figure 1-5. Data Memory
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TMP87CC31/H31
General-purpose Register Banks
General-purpose registers mapped into addresses 0040h OOBFh data memory shown Figure 1-5. There register banks, each bank contains eight 8-bit registers Figure shows general-purpose register bank configuration.
bank (00B8 OOBFh) bank (00B0to00B7H) bank (00A8 00AFH) bank (00A0 00A7H)
bank (0060 0067H) bank (0058 005FH) bank (0050to0057H) bank (0048 004FH) bankO (0040 0047H) Configuration
Example BankO
(0041H) (0040h)
(0043h) (0042h)
(0045h) (0044h)
(0047h) (0046h)
Address assignments registers
Figure 1-6. General-purpose Register Banks
addition access 8-bit units, registers also accessed 16-bit units register pairs Besides function general-purpose register, register also following functions:
register functions 8-bit accumulator register pair functions 16-bit accumulator high byte byte). Registers other than also used accumulators 8-bit operations.
Examples
1234H
Adds contents contents stores result into Subtracts 1234h from contents stores result into
Subtracts contents from contents, stores result into
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TMP87CC31/H31
specify memory address. register pair functions data pointer (HL) index register base register register pair function data pointer (DE). also auto-post- increment auto-pre-decrement functions. This function simplifies multiple digit data processing, software LIFO (last-in first-out) processing, etc.
Example
(HL)
52H)
Loads memory contents address specified into
Loads memory contents address specified value obtained adding contents into Loads memory contents address specified value obtained adding register contents contents into
Loads memory contents address specified into Then increments
Decrements Then loads memory contents address specified into
TLCS-870 Series transfer data directly memory memory, operate directly between memory data memory data. This facilitates programming block processing.
Example Block transfer DSTA SRCA SLOOP (HL), (DE)
SLOOP
Sets (number bytes transfer)
Sets destination address
Sets source address
(HL)MDE)
HL<-HL+
DE<-DE
then loop
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TMP87CC31/H31
Registers used 8-bit buffers counters, register pair used 16-bit buffer counter. register functions offset register register-offset index addressing (refer example above) divisor register division instruction [DIV
Example
SREPEAT
Repeat processing
processing
SREPEAT
Sets number repetitions times processing)
Example Unsigned integer division (16-bit 8-bit)
Divides contents Ccontents, places quotient Aand remainder
general-purpose register banks selected 4-bit register bank selector (RBS). During reset, initialized "0". bank selected called current bank. Together with flag, assigned address 003Fh program status word (PSW). There instructions RBS, [PUSH PSW] [POP PSW] access PSW. also operated memory access instruction.
Example Incrementing
(003FH) RBSRBS
Example Reading
(003FH) A<-PSW(A3.0<-RBS,A7-4<-Flags)
Highly efficient programming high-speed task switching possible using bank changeover save registers during interrupt transfer parameters during subroutine processing. During interrupt, automatically saved onto stack. bank used before interrupt accepted restored automatically executing interrupt return instruction [RETI] [RETN] therefore, there need save/restore software processing.
TLCS-870 Series supports maximum interrupt sources. bank assigned main program, bank assigned each source. Also, increase efficiency data memory usage, assign same bank interrupt sources which nested.
Example Saving restoring registers during interrupt task using bank changeover.
PINTI RBS, (Bankchangeover) Interrupt processing RETI Maskable interrupt return (Bank restoring)
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TMP87CC31/H31
Program Status Word (PSW)
program status word (PSW) consists register bank selector (RBS) four flags, assigned address 003Fh SFR.
read written using memory access instruction (003FH)], (003FH), however flags only read. When writing PSW, change specified instruction
made without writing data flags. example, when instruction (003FH), 05H] executed, written "1", other flags affected. [PUSH PSW] [POP PSW] access instructions.
1.6.1 Register Bank Selector (RBS)
register bank selector (RBS) 4-bit register used select general-purpose register banks. example, when bank currently selected. During reset, initialized
Figure 1-7. (Flags, RBS) Configuration
1.6.2 Flags
flags configured with upper bits zero flag, carry flag, half carry flag jump status flag. flags cleared under conditions specified instruction. These flags except half carry flag used jump condition "cc" conditional jump instructions [JRS After reset, jump status flag initialized "1", other flags affected.
Zero flag (ZF)
operation result transfer data (for 8-bit operations data transfers)/OOOOh (for 16-bit operations); otherwise cleared "0".
During manipulation instructions [SET, CLR, CPL], contents specified "0"; otherwise cleared "0".
This flag when upper bits product during multiplication instruction [MUL], when remainder during division instruction [DIV]; otherwise cleared "0".
Carry flag (CF)
when carry (most significant bit) result occurred during addition when borrow into result occurred during subtraction; otherwise cleared "0". During division, this flag when divisor (divided zero error), when quotient 100h higher (quotient overflow error); otherwise cleared. also affected during shift rotate instructions [SHLC, SHRC, ROLC, RORC]. data shifted from register
This flag isalsoa 1-bit register(a boolean accumulator) manipulation instructions. Set/clear/complementare possible with manipulation instructions.
Examplel manipulation
(0007H)
(009AH)
(0001H)
(0001 (0007h)5 (009AH)0
Example2 Arithmetic right shift RORC
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TMP87CC31/H31
Half carry flag (HF)
when carry occurred between bits operation result during 8-bit addition, when borrow occurred from into result during 8-bit subtraction; otherwise cleared "0". This flag useful decimal adjustment operations (adjustments using [DAA [DAS instructions). Example operation
(The becomes after executing following program when 19h, 28h) A<-41H, HF<-1 A<-41H (decimal-adjust)
Jump status flag (JF)
Zero carry information after operation INC, ADD, CMP, TEST). provides jump condition conditional jump instructions [JRS T/F, 2+d], T/F, (Tor condition code). Jump performed true condition (T), false condition (F).
after executing load exchange/swap/nibble rotate/jump instruction, that [JRS regarded unconditional jump instruction.
Example Jump status flag conditional jump instruction
Example
SLABLE1
(HL) SLABLE2
Jump when carry caused immediately preceding operation instruction.
immediately preceding instruction, making unconditional jump instruction.
accumulator flags become shown below after executing following instructions when register pair, register pair, data memory address 00C5h, carry flag half carry flag contents being "219AH", "00C5h", "D7h", "0", respectively.
Instruction Acc. after execution Flag after execution
ADDC (HL)
SUBB (HL)
(HL)
(HL)
(HL)
Instruction Acc. after execution Flag after execution
ROLC
RORC
0F508H 16A2
13DA
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TMP87CC31/H31
Stack Stack Pointer
1.7.1 Stack
stack provides area which return address status, etc. saved before jump performed processing routine during execution subroutine call instruction acceptance interrupt. subroutine call instruction [CALL [CALLP [CALLV contents (the return address) saved; interrupt acceptance, contents saved (the pushed first, followed PC|_). Therefore, subroutine call occupies bytes stack; interrupt occupies three bytes.
When returning from processing routine, executing subroutine return instruction [RET] restores contents from stack; executing interrupt return instruction [RETI] [RETN] restores contents (the popped first, followed PSW). stack located anywhere within data memory space except register bank area, therefore stack depth limited only free data memory size.
1.7.2 Stack Pointer (SP)
stack pointer (SP) 16-bit register containing address next free locations stack.
post-decremented when subroutine call push instruction executed, when interrupt accepted; pre-incremented when return instruction executed. Figure shows stacking order. initialized hardware-wise requires initialization initialize routine (sets highest stack address). mn], access instructions 16-bit immediate data, register pair).
Example initialize
043FH SP<-043FH Example read
HL<-SP
Figure 1-9. Stack
Stack Pointer (SP)
Figure 1-8. Stack Pointer
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TMP87CC31/H31
System Clock Controller
system clock controller consists clock generator, timing generator, stand-by controller.
Timing generator control register
Clock generator
TBTCR
0036h
XOUT
High-frequency clock oscillator
Timing generator
System locks
Stand-by controller
0038h
0039h
SYSCR1
SYSCR2
Clock generator control
System control registers
Figure 1-10. System Clock Controller
1.8.1 Clock Generator
clock generator generates basic clock which provides system clocks supplied core peripheral hardware. contains oscillation circuit high-frequency clock. high-frequency (fc) clock easily obtained connecting resonator between XOUT pins, respectively. Clock input from external oscillator also possible. this case, external clock applied with XOUT connected. 87CC31/H31 provided oscillation.
High-frequency clock XOUT
Crystal/Ceramic resonator
XOUT
(open)
External oscillator
Figure 1-11. Examples Resonator Connection
Note Accurate Adjustment Oscillation Frequency:
Although hardware externally directly monitor basic clock pulse provided, oscillation frequency adjusted providing program output fixed frequency pulses port while disabling interrupts monitoring this pulse. With system requiring adjustment oscillation frequency, adjusting program must created beforehand.
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TMP87CC31/H31
1.8.2 Timing Generator
timing generator generates from basic clock various system clocks supplied core peripheral hardware. timing generator provides following functions
Generation main system clock
Generation source clocks time base timer
Generation source clocks watchdog timer
Generation internal source clocks timer/counters -TC4
Generation warm-up clocks releasing STOP mode
Generation clock releasing reset output
Configuration Timing Generator
timing generator consists 21-stage divider with divided-by-4 prescaler, main system clock generator, machine cycle counters, shown Figure 1-12 follows. During reset upon releasing STOP mode, divider cleared "0", however, prescaler cleared.
machine cycle counters
Hiqh-frequencvv clock
Timer/ Counters
prescaler divider
divider
fc/4
fc/28
Reset circuit
Stand-by controller
Watchdog Timer
Time Base Timer
Figure 1-12. Configuration Timing Generator
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TMP87CC31/H31
Machine Cycle
Instruction execution peripherals hardware operation synchronized with main system clock. minimum instruction execution unit called "machine cycle". There total different types instructions TLCS-870 Series: ranging from 1-cycle instructions which require machine cycle execution 10-cycle instructions which require machine cycles execution.
machine cycle consists states S3), each state consists main system clock.
1/fc
Main System Clock (fm)
State
-Machine cycle-
(0.5/A MHz)
Figure 1-13. Machine Cycle
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TMP87CC31/H31
1.8.3 Stand-by Controller
stand-by controller starts stops oscillation circuit high-frequency clock. Operating modes controlled system control registers (SYSCR1, SYSCR2).
Figure 1-14 shows operating mode transition diagram Figure 1-15 shows system control registers.
Operating mode
NORMAL mode
this mode, both core on-chip peripherals operate. IDLE mode
this mode, internal oscillation circuit remains active. watchdog timer halted; however, on-chip peripherals remain active. IDLE mode started setting IDLE system control register (SYSCR2), IDLE mode released NORMAL mode interrupt request from on-chip peripherals external interrupt inputs. When (interrupt master enable flag) (interrupt enable), execution will resume upon acceptance interrupt, operation will return normal after interrupt service completed. When (interrupt disable), execution will resume with next instruction which follows IDLE mode start instruction. STOP mode
this mode, internal oscillation circuit turned off, causing system operations halted. internal status immediately prior halt held with lowest power consumption during this mode. output status output ports either output hold high-impedance under software control.
STOP mode started setting STOP system control register (SYSCR1), STOP mode released input (either level-sensitive edge-sensitive programmably selected) STOP pin. After warming-up period completed, execution resumes with next instruction which follows STOP mode start instruction.
IDLE mode
software
interrupt
Operating mode Frequency core On-chip Peripherals Machine cycle time
High-frequency
RESET turning oscillation reset reset 4/fc
NORMAL operate operate
IDLE halt
STOP turning oscillation halt
Figure 1-14. Operating Mode Transition Diagram
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TMP87CC31/H31
System Control Register
syscr1
(0038h)
STOP RELM REOUTEN
(Initial value: 0000 00**)
STOP STOP mode start core peripherals remain active core peripherals halted (start STOP mode)
RELM Release method STOP mode Edge-sensitive release Level-sensitive release
REOperating mode after STOP mode Return NORMAL mode Reserved
OUTEN Port output control during STOP mode High-impedance Remain unchanged
Warming-uptime releasing STOP mode 3x219/fc 219/fc Reserved
Note Always REto when transiting from NORMAL mode STOP mode.
Note moved STOP mode while OUTEN internal inputs Then there possibility interrupt falling edge.
Note Bits SYSCR1 read undefined data when read instruction executed.
Note high-frequency clock [Hz] don't care
Note returns NORMAL mode without value RETM, when STOP mode retuned input RESET pin.
System Control Register
syscr2
(0039H)
IDLE
(Initial value: 1000 ****)
IDLE IDLE mode start watchdog timer remain active watchdog timer stopped (start IDLE mode)
Note Note Note Note
reset applied (RESET output goes low) SYSCR2 cleared "0". clear SYSCR2 "0", bits SYSCR2 don't care
Bits 3to0 SYSCR2 always read when read instruction executed.
Figure 1-15. System Control Registers
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TMP87CC31/H31
1.8.4 Operating Mode Control
STOP mode
STOP mode controlled system control register (SYSCR1) STOP input. STOP also used both port INT5 (external interrupt input pin. STOP mode started setting STOP (bit SYSCR1 "1". During STOP mode, following status maintained. Oscillation turned off, internal operations halted.
data memory, registers port output latches held status effect before STOP mode entered. port output select either output hold high-impedance setting OUTEN SYSCR1). divider timing generator cleared "0".
program counter holds address instruction following instruction which started STOP mode.
STOP mode includes level-sensitive release mode edge-sensitive release mode, either which selected with RELM (bit SYSCR1). Level-sensitive release mode (RELM this mode, STOP mode released setting STOP high. This mode used capacitor back-up when main power supply long term battery back-up. When STOP input high, executing instruction which starts STOP mode will place STOP mode instead will immediately start release sequence (warm-up). Thus, start STOP mode level-sensitive release mode, necessary program first confirm that STOP input low. following method used confirmation Using external interrupt input INT5 (INT5 falling edge-sensitive input).
Example Starting STOP mode with INT5 interrupt. (TMP87CC31/H31)
PINT5 TEST (P2)
SINT5 (SYSCR1), 01000000B
reject noise, STOP mode does start portP20 high
Sets level-sensitive release mode.
SINT5 RETI
(SYSCR1) Starts STOP mode
(IL), 1110011111111111B IL12,11
(clears interrupt latches)
STOP XOUTpin
NORMAL operation
-fS-
jfvn
STOP
operation
Confirm program that STOP input start STOP mode.
Warm-up
NORMAL operation
STOP mode released hardware. Always released STOP input high
Figure 1-16. Level-sensitive Release Mode
Notel After warming started, when STOP input changed level, STOP mode placed.
Note2 When changing level-sensitive release mode from edge-sensitive release mode, release mode switched until rising edge STOP input detected.
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TMP87CC31/H31
Edge-sensitive release mode (RELM this mode, STOP mode released rising edge STOP input. This used applications where relatively short program executed repeatedly periodic intervals. This periodic signal (for example, clock from low-power consumption oscillator) input STOP pin.
edge-sensitive release mode, STOP mode started even when STOP input high.
Example Starting STOP mode operation edge-sensitive release mode (TMP87CM36)
(SYSCR1), 00000000B
(SYSCR1). STOP
(IL), 1110011111111111B
OUTEN (specifies high-impedance) (disables interrupt service) STOP (activates stop mode) IL12,11
(clears interrupt latches)
(enables interrupt service)
STOP XOUTpin
-ii-
NORMAL operation
STOP mode started program.
STOP operation
Warm-up
NORMAL operation
STOP operation
STOP mode released hardware rising edge STOP input.
Figure 1-17. Edge-sensitive Release Mode
STOP mode released following sequence:
high-frequency clock oscillator turned
warming-up period inserted allow oscillation time stabilize. During warm-up, internal operations remain halted. different warming-up times selected with (bits SYSCR1) determined resonator characteristics.
When warming-up time elapsed, normal operation resumes with instruction following STOP mode start instruction (e.g. [SET (SYSCR1). 7]). start made after divider timing generator cleared "0".
Table 1-1. Warming-up Time example
4.194304
3x219/fc 219/fc [ms] 196.6 [ms] 65.5
Note warming-up time obtained dividing basic dock divider: therefore, warming-up time include certain amount error there fluctuation oscillation frequency when STOP mode released. Thus, warming-up time must considered approximate value.
STOP mode also released setting RESET low, which immediately performs normal reset operation.
3-31-21
Oscillator circuit
Main
system
clock
turn
Program counter
Port output_
Divider
turn
(when OUTEN
STOP Mode Start (Example Start with SET(SYSCRI). instruction located address
STOP input
Main
system
clock
Program counter
Instruction, execution
halt
Hi-Z
Port output
Divider
Warming
Ose'1 atorturn offt-V
circuit
count
yijnjnjn^ijnLn^ijnjn^LrmjnjiJ^
Instruction address
Instruction address Xlnstruction address
STOP Mode Release
Figure 1-18. STOP Mode Start/Release
TMP87CC31/H31
Note When STOP mode released with hold voltage, following cautions must observed.
power supply voltage must operating voltage level before releasing STOP mode. RESET input must also high, rising together with power supply voltage. this case, external time constant circuit been connected, RESET input voltage will increase slower rate than power supply voltage. this time, there danger that reset occur input voltage level RESET drops below non-inverting high-level input voltage (hysteresis input).
IDLE mode
IDLE mode controlled system control register maskable interrupts. following status maintained during IDLE mode.
Operation watchdog timer halted. On-chip peripherals continue operate.
data memory, registers port output latches held status effect before IDLE mode entered.
program counter holds address instruction following instruction which started IDLE mode.
Example Starting IDLE mode.
(SYSCR2) IDLE<-1
IDLE mode includes normal release mode interrupt release mode. Selection made with interrupt master enable flag (IMF). Releasing IDLE mode returns NORMAL mode.
Normal release mode (IMF "0") IDLE mode released interrupt source enabled individual interrupt enable flag (EF). Execution resumes with instruction following IDLE mode start instruction (e.g. [SET (SYSCR2).4])_ Normally, (Interrupt Latch) interrupt source release IDLE mode must cleared load instructions.
Interrupt release mode (IMF "1") IDLE mode released interrupt processing started interrupt source enabled with individual interrupt enable flag (EF). After interrupt processed, execution resumes from instruction following instruction which started IDLE mode.
IDLE mode also released setting RESET low, which immediately performs reset operation. After reset, 87CC31/H31 placed NORMAL mode.
Note When watchdog timer interrupt generated immediately before IDLE mode started, watchdog timer interrupt will processed IDLE mode will started.
Figure 1-19. IDLE Mode
3-31-23
Watchdog timer
Main
system
clock
Interrupt
request
Program counter
halt
IDLE Mode Start (Example: starting with instruction located address
Instruction address
Watchdog timer
Main
system
clock
Interrupt request
Watchdog timer
halt
halt
halt
Normal Release Mode
operate
acceptance interrupt
operate
Interrupt Release Mode IDLE Moris Release
Figure 1-20. IDLE Mode Start/Release
TMP87CC31/H31
Interrupt Controller
87CC31/H31 total interrupt sources: externals internals. Nested interrupt control with priorities also possible. internal sources pseudo non-maskable interrupts; remainder maskable interrupts.
Interrupt latches (IL) that hold interrupt requests provided interrupt sources. Each interrupt vector independent.
interrupt latch when interrupt request generated requests accept interrupt. acceptance maskable interrupts selectively enabled disabled program using interrupt master enable flag (IMF) individual interrupt enable flags (EF). When more interrupts generated simultaneously, interrupt accepted highest priority order determined hardware. Figure 1-21 shows interrupt controller.
Table 1-2. Interrupt Sources
Interrupt Source Enable Condition Interrupt Latch Vector Table Address Priority
Internal/ External (Reset) Non-Maskable FFFEh High
Internal INTSW (Software interrupt) Pseudo non-maskable FFFCh
Internal INTWDT (Watchdog Timer interrupt) FFFAh
reserved INTOEN FFF8h
Internal INTTC1 (16-bit interrupt) EF4= FFF6h
reserved EF5= FFF4H
Internal INTTBT (Time Base Timer interrupt) EF6= FFF2H
reserved EF7= FFFOh
Internal INTTC3 (8-bit interrupt) IMF- EF8= FFEEh
reserved IMF- EFg= FFECh
Internal INTTC4 (8-bit nterrupt) IMF- EF10= ILlO FFEAh
External INT3 (External interrupt Remote control receive interrupt) IMF- ILll FFE8h
External INT4 (External interrupt EF-,2 11-12 FFE6h
Internal INTOSD (OSD interrupt) EF-,3 IL13 FFE4H
Internal INTTC2 (16-bit interrupt) IMF* EF14= IL14 FFE2H
External INT5 (External interrupt EF15 IL15 FFEOh
3-31-25
IMTSW>-INTWDT>-
INTTC1>-
INTTBT>-
1NTTC3>-
INT3
INTOSD>-
Edge selection,
Digital noise reject circuit
Remote control signal preprocessor
Edge selection, Digital noise reject circuit
iQ-^-
External interrupts control Register
IL1S_0 write data
write strobe
Vector table address
internal reset
Interrupt request
Release IDLE mode
request
Interrupt acceptance
Interrupt Master Enable Flag
[RETI] instruction during maskble interrupt service [RETIM] instruction only when before interrupt accepted. [El] instruction
instruction which sets
Figure 1-21. Interrupt Controller Block Diagram
TMP87CC31/H31
Interrupt Latches
Interrupt latches provided each source, except software interrupt. latch when interrupt request generated, requests accept interrupt. latch cleared just after interrupt accepted. interrupt latches initialized during reset.
interrupt latches assigned addresses 003Ch 003Dh SFR. Each latch cleared individually instruction; however, read-modify-write instruction such manipulation operation instructions cannot used clear watchdog timer interrupt "0"). Thus, interrupt requests cancelled initialized program. Note that interrupt latches cannot instruction.
contents interrupt latches read instruction. Therefore, testing interrupt requests software possible.
Example Clears interrupt latches
(IL), 1110101010111111B IL12, IL10, IL8, IL6<-0
Example Reads interrupt latches
(IL) W<-ILH, A<-ILl
Example Tests interrupt latch
TEST (ILH). IL12 then jump
SSET
Interrupt Enable Register (EIR)
interrupt enable registers (EIR) enable disable acceptance interrupts, except pseudo non-maskable interrupts (software watchdog timer interrupts). Pseudo non-maskable interrupts accepted regardless contents EIR; however, pseudo non-maskable interrupts cannot nested more than once same time. example, watchdog timer interrupt accepted during software interrupt service.
consists interrupt master enable flag (IMF) individual interrupt enable flags (EF). These registers assigned addresses 003Ah 003Bh SFR, read written instruction (including read-mod ify-write instructions such manipulation instructions). Interrupt Master enable Flag (IMF)
interrupt master enable flag (IMF) enables disables acceptance interrupts, except pseudo non-maskable interrupts. Clearing this flag disables acceptance maskable interrupts. Setting enables acceptance interrupts. When interrupt accepted, this flag cleared temporarily disable acceptance maskable interrupts. After execution interrupt service program, this flag maskable interrupt return instruction [RETI] again enable acceptance interrupts. interrupt request already been occurred, interrupt service starts immediately after execution [RETI] instruction.
Pseudo non-maskable interrupts returned [RETN] instruction. this case, only when pseudo non-maskable interrupt service started with interrupt acceptance enabled (IMF Note that remains when cleared interrupt service program.
assigned address 003Ah SFR, read written instruction. normally cleared [El] [Dl] instructions, initialized during reset.
3-31-27
TMP87CC31/H31
Individual interrupt Enable Flags (EFi5 EF4)
These flags enable disable acceptance individual maskable interrupts. Setting corresponding individual interrupt enable flag enables acceptance interrupt, setting disables acceptance.
Example Sets EFfor individual interrupt enable, sets "1".
(EIR), 1110100000000001B EF15toEF13, EF11f IMF<-1
Example Sets individual interrupt enable flag "1".
(EIRH) EF12<-1
(003C, 003Dh)
(003A, 003Bh)
il15 il14 "-13 il12 1l10
(003Dh) ill(003Ch) (Initial Value 00000000 000000**)
ef15 ef14 ef13 ef12 ef11 ef10
EIRH (003BH)
EIRl (003AH) (Initial Value 00000000 0000***0)
Note read-modify-write instruction such manipulation clearing Note2: clear instruction.
Note3: during non-maskable interrupt service program.
Figure 1-22. Interrupt Latch (IL) Interrupt Enable Register (EIR)
3-31-28
TMP87CC31/H31
1.9.1 Interrupt Sequence
interrupt request held until interrupt accepted interrupt latch cleared reset instruction. Interrupt acceptance sequence requires machine cycles NORMAL mode) after completion current instruction execution. interrupt service task terminates upon execution interrupt return instruction [RETI] (for maskable interrupts) [RETN] (for pseudo non-maskable interrupts).
Interrupt acceptance processing follows:
interrupt master enable flag (IMF) cleared temporarily disable acceptance following maskable interrupts. When non-maskable interrupt accepted, acceptance following interrupts temporarily disabled.
interrupt latch (IL) interrupt source accepted cleared "0".
contents program counter (return address) program status word saved (pushed) onto stack. stack pointer decremented times.
entry address interrupt service program read from vector table address, entry address loaded program counter.
instruction stored entry address interrupt service program executed.
machine cycle
Interrupt signal
Interrupt service task
Interrupt latch
Instruction execution
Note
Instruction execution
Interrupt acceptance
Instruction \/\\
execution
RETI instruction execution
DQCDGHDC
Xb+lXb
)OQC
Note return address, entry address, address when RETI instruction stored Note2 maximum response time from when until interrupt acceptance processing starts 38/fc [s].
Figure 1-23. Timing Chart Interrupt Acceptance Interrupt Return Instruction
Example Correspondence between vector table address INTTBT entry address interrupt service program.
Vector table address
FFF2H FFF3H
Entry address
D203h D204h
maskable interrupt accepted until even maskable interrupt higher priority than that current interrupt being serviced.
When nested interrupt service necessary, interrupt service program. this case, acceptable interrupt sources selectively enabled individual interrupt enable flags.
3-31-29
TMP87CC31/H31
Saving Restoring General-purpose Register
During interrupt acceptance processing, program counter program status word automatically saved stack, accumulator other registers. These registers saved program necessary. Also, when nesting multiple interrupt services, necessary avoid using same data memory area saving registers. following method used save restore general-purpose registers:
General-purpose register save restore register bank changeover:
General-purpose registers saved high-speed switching register bank that use. Normally, bank used main task banks assigned interrupt service tasks. increase efficiency data memory utilization, same bank assigned interrupt sources which nested.
switched bank automatically restored executing interrupt return instruction [RETI] [RETN], Therefore, necessary program save RBS.
Example Register Bank Changeover
PINTxx RBS, Switches bank MHz) iintennupt processing RETI Restores bank Returns
main task
main task
bank acceptance interrupt interrupt service task
time
interrupt return
Switch bank RBS, INC(GRBS)] instruction
Restore bank automatically [RETI]/[RETN] instruction
acceptance interrupt interrupt service task
Bill
Bill
interrupt return
saving registers
restoring registers
Saving Restoring register bank changeover
Saving Restoring using push/pop data transfer instructions
Figure 1-24. Saving/Restoring General-purpose Registers
3-31-30
TMP87CC31/H31
General-purpose register save restore using push instructions:
save only specific register, when same interrupt source occurs more than once, general-purpose registers saved restored using push instructions. Example Register save using push instructions
PINTxx PUSH Save register pair PUSH Save register pair
interrupt processing
acceptance interrupt
Restore register pair Restore register pair RETI Return
Address (example) 0438h
0439
043A
043B
043C
execution push instruction
execution
instruction
execution
interrupt return instruction
General-purpose registers save restore using data transfer instructions:
Data transfer instructions used save only specific general-purpose register during processing single interrupt.
Example Saving/restoring register using data transfer instructions PINTxx (GSAVA), Save register
interrupt processing
(GSAVA)' Restore register RETI Return
interrupt return instructions [RETI] [RETN] perform following operations.
[RETI] Maskable interrupt return [RETN] Non-maskable interrupt return
contents program counter program status word restored from stack. stack pointer incremented times. interrupt master enable flag contents program counter program status word restored from stack. stack pointer incremented times. interrupt master enable flag only when non-maskable interrupt accepted interrupt enable status. However, interrupt master enable flag remains when clear interrupt service program.
Interrupt requests sampled during final cycle instruction being executed. Thus, next interrupt accepted immediately after interrupt return instruction executed.
Note When interrupt processing time longer than interrupt request generation time, interrupt service task performed main task.
3-31-31
TMP87CC31/H31
1.9.2 Software Interrupt (INTSW)
Executing [SWI] instruction generates software interrupt immediately starts interrupt processing (INTSW highest prioritized interrupt). However, processing non-maskable interrupt already underway, executing instruction will generate software interrupt will result same operation [NOP] instruction. Thus, [SWI] instruction behaves like [NOP] instruction.
Note development tool, processing non-maskable interrupt already underway, executing instruction will generate software interrupt software brake.
[SWI] instruction only detection address error debugging.
Address Error Detection
read some cause such noise attempts fetch instruction from nonexistent memory address. Code instruction, software interrupt generated address error detected. address error detection range further expanded writing unused areas program memory, address trap reset generated case that instruction fetched from areas.
Note fetch data from addresses BF80h BFFFH (test area) "FFh"-Q) Debugging
Debugging efficiency increased placing instruction software break point setting address.
3-31-32
TMP87CC31/H31
1.9.3 External Interrupts
87CC31/H31 three external interrupt inputs (INT3, INT4, INT5). these equipped with digital noise rejection circuits (pulse inputs less than certain time eliminated noise). Edge selection also possible with INT3 INT4.
Edge selection INT4 input performed external interrupt control register (EINTCR). Edge selection noise rejection control INT3 input performed Remote-control signal processor control registers, (refer selection Remote-control signal processor.)
Table 1-3. External Interrupts
Source Secondary function Enable conditions Edge Digital noise reject
INT3 INT3 P30/RXIN IMF- falling edge, rising edge falling/rising edqe Refer section Remote control signal preprocessor.
INT4 INT4 EF-,2 falling edge rising edge Pulses less than 7/fc eliminated noise. Pulses equal more than 24/fc[s] regarded assignais.
INT5 P20/STQP IMF- EF15 falling edge (hysteresis input)
Note pulse width (both level) input INT5 must over machine cycle. INT5 input
tiNTL, tiNTH tcyc {Note tcyc 4/fc[s])
Note
Note
tlNTL t||\|TH
noiseless signal input external interrupt pin, maximum time from edge input signal until follows INT4 25/fc
When high-impedance specified port output stop mode, port input forcibly fixed level
internally. Thus, interrupt latches external interrupt inputs except (INT5 STOP) which also used ports "1". specify high-impedance port output stop mode, first disable interrupt service (IMF activate stop mode. After releasing stop mode, clear interrupt latches using load instruction, then, enable interrupt service._
Example Activating stop mode (TMP87CC31/H31)
(SYSCR1), 01000000B
(SYSCR1).STOP
(IL), 1110011101010111B
(specifies high-impedance) (disables interrupt service) STOP<-1 (activates stop mode) IL12,11,7, 3<-0 (clears interrupt latches) (enables interrupt service)
3-31-33
TMP87CC31/H31
(TC4ES) INT4 (TC3ES)
eintcr
(0037h)
(Initial value 00*0 000*)
INT4 INT4 edge select Rising edge write
Falling edge only
Note Note
Note
Note Note
don't care
change EINTCR when IMF=1. After changing EINTCR, interrupt latches external interrupt inputs must cleared using load instruction.
order change external interrupt input rewriting contents INT4ES during NORMAL mode, clear interrupt latch external interrupt input (INT4) after machine cycles from time rewriting.
EINTCR write-only-register must used with read-modify-write instructions. Always write 6,2, EINTCR.
Figure 1-25. External Interrupt Control Register
1.10 Watchdog Timer (WDT)
watchdog timer rapidly detects malfunction such endless looping caused noise like, resumes normal state.
watchdog timer signal detecting malfunction selected either reset output nonmaskable interrupt request. However, selection possible only once after reset. first, reset output selected.
When watchdog timer being used malfunction detection, used timer generate interrupt fixed intervals.
3-31-34
TMP87CC31/H31
1.10.1 Watchdog Timer Configuration
reset release signal from T.G.
Watchdog Timer Control Registers
Figure 1-26. Watchdog Timer Configuration
1.10.2 Watchdog Timer Control
Figure 1-26 shows watchdog timer control registers (WDTCR1, WDTCR2). watchdog timer automatically enabled after reset.
Malfunction detection methods using watchdog timer malfunction detected follows:
Setting detection time, selecting output, clearing binary counter. Repeatedly clearing binary counter within setting detection time.
malfunction occurs cause, watchdog timer output will become active rise overflow from binary counters unless binary counters cleared. this time, when WDTOUT reset generated, which drives RESET reset internal hardware external circuits. When WDTOUT watchdog timer interrupt (INTWDT) generated. watchdog timer temporarily stops counting STOP mode (including warm-up) IDLE mode, automatically restarts (continues counting) when STOP/IDLE mode released.
Example Sets watchdog timer detection time 221/fc resets malfunction.
Clears binary counters
00001101B WDTOUT<-1 Clears binary counters
(always clear immediately after changing WDTT) Clears binary counters
Clears binary counters
Within detection time
Within detection time
(WDTCR2),
(WDTCR1),
(WDTCR2),
(WDTCR2),
(WDTCR2),
3-31-35
TMP87CC31/H31
Watchdog Timer Control Register
wdtcr1 (0034h)
WDTT (Initial value **** 1001)
WDTEN Watchdog timer Disable necessary write disable code WDTCR2)
enable/disable Enable
225/ (4.194 MHz)
WDTT Watchdog timer 223/fc (1.048 MHz) write
detection time 221/fc (262.1 msatfc 8MHz) 219/fc (65.5 msatfc 8MHz) only
WDTOUT Watchdog timer output select Interrupt request Reset output
Notel WDTOUT cannot program after clearing WDTOUT "0".
Note High-frequency clock [Hz] don't care
Note WDTCR1 write-onry-register must used with read-modi fy-w rite instructions
Note Disable watchdog timer clear counter just before switching STOP mode. When counter cleared just before switching STOP mode, clear counter again
subsequently releasing STOP mode.
Watchdog Timer Control Register
wdtcr2 (0035h)
(Initial value **** ****)
WDTCR2 Watchdog timer control code write register Watchdog timer binary counter clear (clear code) Watchdog timer disable (disable code) others Invalid write only
Note disable code invalid unless written when WDTEN
Note don't care
Figure 1-27. Watchdog Timer Control Registers
Watchdog Timer Enable
watchdog timer enabled setting WDTEN (bit WDTCR1) "1". WDTEN initialized during reset, watchdog timer operates immediately after reset released.
Example Enables watchdog timer
(WDTCR1), 00001000B
Watchdog Timer Disable
watchdog timer disabled writing disable code WDTCR2 after clearing WDTEN (bit WDTCR1) "0". watchdog timer disabled this procedure reversed disable code written WDTCR2 before WDTEN cleared "0". watchdog timer halted temporarily STOP mode (including warm-up) IDLE mode, restarts automaticallyafter STOP IDLE mode released.
During disabling watchdog timer, binary counters cleared "0".
Example Disables watchdog timer
(WDTCR1) 0B101H WDTEN<-0, code
3-31-36
TMP87CC31/H31
1.10.3 Watchdog Timer Interrupt (INTWDT)
This pseudo non-maskable interrupt which accepted regardless contents EIR. watchdog timer interrupt software interrupt already accepted, however, watchdog timer interrupt waits until previous non-maskable interrupt processing completed (the [RETN] instruction execution).
stack pointer (SP) should initialized before using watchdog timer output interrupt source with WDTOUT.
Example Watchdog timer interrupt setting
043FH Sets stack pointer
(WDTCR1) 00001000B WDTC)UT<-0
1.10.4 Watchdog Timer Reset
watchdog timer output becomes active, reset generated, which drives RESET (sink open drain output) reset internal hardware external circuits. reset output time 220/fc (131 msat MHz).
219/fc
217/fc
Clock _r~L fWDTT 11B)
Binary counter
Overflow
INTWDT interrupt
reset output (Hi-Z) |("L" output)
writes WDTCR2
Figure 1-28. Watchdog Timer Interrupt/Reset
1.11 Reset Circuit
TLCS-870 Series four types reset generation procedures: external reset input, address-trap-reset, watchdog timer reset system-clock-reset. Table shows on-chip hardware initialization reset action. internal source reset circuit (watchdog timer reset, address trap reset, system clock reset) initialized when power turned Thus, output from RESET (220/fc msat MHz) when power turned
Table 1-4. Initializing Internal Status Reset Action
On-chip Hardware Initial Value On-chip Hardware Initial Value
Program counter (PC) Register bank selector (RBS) Jump status flag (JF) Interrupt master enable flag (IMF) Interrupt individual enable flags (EF) Interrupt latches (IL) (FFFFH)-(FFFEH) Divider Timing generator
Watchdog timer Enable
Output latches ports Refer port circuitry
Control registers Refer each control register
3-31-37
TMP87CC31/H31
1.11.1 External Reset Input
When RESET held least machine cycles (12/fc [s]) with power supply voltage within operating voltage range oscillation stable, reset applied internal state initialized.
When RESET input goes high, reset operation released program execution starts vector address stored addresses FFFEh FFFFh._
RESET contains Schmitt trigger (hysteresis) with internal pull-up resistor. simple power-on-reset applied connecting external capacitor diode.
Figure 1-29. Simple Power-on-Reset Circuitry
1.11.2 Address-Trap-Reset
malfunction occurs attempt made fetch instruction from area (addresses OOOOh 013Fh), address-trap-reset will generated. Then, RESET output will low. resettime 220/fc (131msatfc MHz).
Instruction
execution
RESET output
Address-trap occurred "J_("L" output)
reset release Xinstruction address
J(Hi-Z)
220/fc
22/fc
24/fc
24/fc
Note 0^a^043FH
Note During reset release, reset vector read out, instruction address fetched decoded.
Figure 1-30. Address-Trap-Reset
1.11.3 Watchdog Timer Reset
Refer Section "1.10 Watchdog Timer".
1.11.4 System-Clock-Reset
Clearing both bits SYSCR2 stops high-frequency oscillation, causes deadlock. This prevented automatically generating reset signal whenever (bit7 SYSCR2) (bit6 SYSCR2) detected continue oscillation. Then, RESET output goes from high-impedance. resettime 220/fc (131 MHz).
3-31-38
TMP87CC31/H31
ON-CHIP PERIPHERALS FUNCTIONS
Special Function Registers (SFR) Data Buffer Registers (DBR)
TLCS-870 Series uses memory mapped system peripherals control data transfers performed through special function registers (SFR) data buffer registers (DBR). mapped addresses 0000H 003FH, addresses 0F80H 0FFFH. Figure shows list 87CC31/H31 SFRsand DBRs.
Address 0000H
Address 0F80h
0F94
0F9B
OFCF 0FD0
0FFF
Read Write Address Read Write
reserved 0020H reserved
reserved reserved
Port reserved
Port reserved
Port reserved
Port PWMSR (PWM status) PWMCR (PWM control)
Port PWMDBR (PWM data buffer)
Port PULSECR (Pulse output control)
reserved reserved
reserved reserved
reserved reserved
reserved reserved
P4CR control) reserved
P6CR control) reserved
(Comparator) reserved
CMPDR (Com parator input data register input control) reserved
TREG1Al reserved
TREG1Ah reserved
TREG1Bl .(Timer register TREG1Bh reserved
reserved
TC1CR (TC1 control) WDTCR1. ,wnTrnn+mh
TC2CR (TC2 control) WDTCR2
TREG2l TBTCR (TBT control)
(Timer register Ktvjz^i EINTCR (Exter, interrupt control)
TREG3A (Timer register SYSCR1
TREG3B (Timer register SYSCR2 pystem control;
TC3CR (TC3 control) EIRl
TREG4 (Timer register unierrupienaDie register;
TC4CR (TC4 control)
reserved .IL,,. (interrupt latch).
reserved reserved
reserved (Program status word) (Register bank selector)
Read
Special Function Registers Write
DCTR (OSD display-line counter)
ORDON
control registers
reserved
reserved
reserved RXCR1 (Remo-con control RXCR2 (Remo-con control) RXCTR (Remo-con receive RXDBR (Remo-con receive data uffer) RXSR (Remo-con status)
reserved
reserved
reserved
Note
Note Note
Note
Note
access reserved areas program.
Cannot accessed. When defining address 003FH with assembler symbols, GPSW GRBS. Write-only registers interrupt latches cannot read-modify-write instructions (bit manipulation instructions such SET, CLR, etc. logical operation instructions such AND, etc.)
Pulse Width Modulation Screen Display Remo-con Remote control
Data Buffer Registers
Figure 2-1.
3-31-39
TMP87CC31/H31
Ports
87CC31/H31 parallel input/output ports (34pins) follows:
Primary Function Secondary Functions
Port 1-bit port external interrupt input, STOP mode release signal input
Port 7-bit port external interrupt input, remote control signal input timer/counter input
Port 8-bit port pulse width modulation output
Port 8-bit port pulse width modulation output, pulse output, comparator input
Port 8-bit port Y/BL output from circuitry
Port 2-bit port horizontal synchronous pulse input vertical synchronous pulse input circuitry
Each output port contains latch, which holds output data. input ports have latches, external input data should either held externally until read reading should performed several times before processing. Figure shows input/output timing examples. External data read from port state read cycle during execution read instruction. This timing recognized from outside, that transient input such chattering must processed program.
Output data changes state write cycle during execution instruction which writes port.
fetch cycle fetch cycle read cycle H-H^-H^-H
Instruction execution cycle
Input strobe -Data input
Ey.:
j_i_i_i_l
fetch cycle fetch cycle write cycle H-H^-H^-H
Irictri irtinri
execution cycle-
Output latch_
pulse
Ey.: QQ.ft
j_i_i_i_l
Data output
Input Timing Output Timing
Note positions read write cycles vary, depending instruction.
Figure 2-2. Input/Output Timing (Example)
When reading port except programmable ports, whether input data output latch contents read depends instructions, shown below:
Instructions that read output latch contents (src) (pp).
CLR/SET/CPL (src).b ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), CLR/SET/CPL (pp).g (src) side ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) (src).b,
Instructions that read input data Instructions other than above
(HL) side ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)
3-31-40
TMP87CC31/H31
2.2.1 Port (P20)
Port 1-bit input output port. also used external interrupt input, STOP mode release signal input. When used input port, secondary function pin, output latch should setto "1". During reset,the output latch initialized "1".
recommended that should used external interrupt input, STOP mode release signal input, input port. used output port, interrupt latch falling edge output pulse.
When read instruction port executed, bits read undefined data.
SET/CLR/CPL/others Data input
CMP/MCMP/TEST/others
Data output INT5/STOP
output latcrH
STOP OUTEN
(0002h)
uvlr
(INT5/STOP)
INT5
STOP
Note don't care (Initial value *******1)
Figure 2-3. Port
2.2.2 Port (P36 P30)
Port 7-bit input output port, also used exrernal interrupt input timer counter input, Remote-control signal input. When used input port secondary function pin, output latch should setto "1". output latches initialized during reset. Example Outputs immediate data port
(P3), P3<-5AH
Example Inverts output lower 4bits(P33 P30) port (P3), 00001111B P30^-P33
Control input
CMP/ MCMP/ TEST /others
Data input
SET/CLR/CPL/others
Data output
others
dUMMO
Output latch
Control output
STOP Hi-Z control
Note 6toO
OUTEN
(0003h)
INT4
INT3 RXIN
(Initial value *111 1111)
Figure 2-4. PortP3
3-31-41
TMP87CC31/H31
2.2.3 Port (P47 P40)
Port 8-bit input output port which configured input output one-bit unit under software control. Input output mode specified corresponding port input output control register (P4CR). Port configured input corresponding P4CR cleared "0", output corresponding P4CR "1". During reset, P4CR initialized "0", which configures port P4asan input. output latches also initialized "1". Data written into output latch regardless P4CR contents. Therfore initial output data should written into output latch before setting P4CR. Port also used pulse width modulation (PWM) output. When used output pin, output pins should output mode beforehand output latch should setto "1".
Note Input mode port read state input pin. When input/output mode used mixed, contents output latch setting input mode changed executing manipulation instructions.
(0004h)
P4CR (OOOCh)
PWM4 PWM1 PWM0
STOP OUTEN
Data input
Data output'
pwmi
Note
(Initial value: 1111 1111)
(Initial value 0000 0000)
P4CR control port input mode write
output mode only
Figure 2-5. Ports P4CR
2.2.4 Port (P57 P50)
Port 8-bit input output port, also used comparator input, pulse output, pulse width modulation (PWM) output. When used input port secondary function pin, output latch should "1". output latches initialized during reset.
MCMP TEST others MCMP TEST others
P57to Note 7to4,j 3to0 P53to
(0005h) CIN3 CIN2 CIN1 CIN0 PULSE PWM9 PWM8 (Initial value 1111 1111)
Figure 2-6. Ports
3-31-42
TMP87CC31/H31
2.2.5 Port (P67 P60)
Port 8-bit input output port which configured input output one-bit unit under software control. Input output mode selected corresponding input/output control register (P6CR). example, port configured input corresponding P6CR cleared "0", output corresponding "1". During reset, P6CR initialized "0", which configures port input. output latches also initialized "1". Data written into output latch regardless P6CR contents. Therefore initial output data should written into output latch before setting P6CR. Pins available high current output, LEDs driven directly.
Port also used screen display (OSD) output Y/BL signal). When used output pin, output pins should output mode beforehand port data selection register (P67DS P64DS) should "1".
stop
outen
P6CRi
Data input
Data output
Y/BL
(0006h)
P6CR (OOODh)
Output latch
stop
outen
P6CRJ
Data input
|P6i Data output-
Output latch
Note
Note
(Initial value 1111 1111)
(Initial value 0000 0000)
P6CR control port Input mode Output mode write only
Port data selection register (P67DS P64DS)
(0F91h)
P67DS P66DS P65DS P64DS
(Initial value 0000 ****)
P6nDS
Selection output data port
Port output latch
:the output Y/BL)
write only
Notel
Note2 P6CR, P67DS P64DS write-only-register must used with read-modify-write instructions.
Figure 2-7. Ports P6CR, P67DS P64DS
Note Input mode port read state input pin. When input output mode used mixed, contents output latch setting input mode changed executing manipulation instructions.
Example lower port (P63 output port other input port.
(P6CR) P6CR <-0000 1111B
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TMP87CC31/H31
2.2.6 Port (P71 P70)
Port 2-bit input output port, also used vertical synchronous signal (VD) input horizontal synchronous signal (HD) input screen display (OSD) circuitry.
output latches initialized during reset. When used input port secondary function pin, output latch should setto "1".
When read instruction port executed, bits read undefined data.
CMP/MCMP/TEST/others
(Initial value **** **11)
Figure 2-8. Ports
Time Base Timer (TBT)
time base timer generates time base scanning, dynamic displaying, etc. also provides time base timer interrupt (INTTBT). time base timer controlled control register (TBTCR) shown Figure 2-10.
INTTBT generated first rising edge source clock (the divider output timing generator) after time base timer been enabled. divider cleared program; therefore, only first interrupt generated ahead interrupt period. interrupt frequency (TBTCK) must selected with time base timer disabled (When time base timer changed from enabling disabling, interrupt frequency can't changed.) (both frequency selection enabling performed simultaneously).
TBTCK zzxz
TBTEN machine cycle
Example: Sets time base (TBTCR) (EIRL)
timer frequency fc/216 [Hz] 00001010B
enables INTTBT interrupt.
3-31-44
TMP87CC31/H31
fc/223 fc/221 fc/216 fc/214 fc/213 fc/212 fc/211 fc/29
>->-
source clock
INTTBT
interrupt
request
TBTCK
Rising
edge
detector
TBTCR
TBTEN
Source dock
TBTEN
INTTBT
Time Base Timer Control Register Configuration
Enable
Interrupt period
Time Base Timer Interrupt
Figure 2-9. Time Base Timer
tbtcr
(0036h)
TBTEN ,TBTCK
(Initial value 0**0 0***)
TBTEN
TBTCK
Time base timer enable/disable
Time base timer interrupt frequency select
Disable Enable
fc/223 [Hz] 0.95 atfc MHz)
fc/221 3.81 atfc MHz)
fc/216 122.07 atfc MHz)
fc/214 488.28 atfc MHz)
fc/213 976.56 atfc MHz)
fc/212 1953.12 atfc MHz)
fc/211 3906.25 atfc MHz)
fc/29 15625 atfc MHz)
Notel High-frequency clock [Hz], don't care
Note2: TBTCR write-only register must used with read-modify-write instructions.
write only
Figure 2-10. Time Base Timer Control Register
3-31-45
TOSHIBA TMP87CC31/H31
16-bit Timer (TC1) 2.4.1 Configuration
Figure 2-11. Timer (TC1)
3-31-46
TMP87CC31/H31
2.4.2 Control
timer controlled timer control register (TC1CR) 16-bit timer registers (TREG1A TREG1B). Reset does affect TREG1A TREG1B.
treg1a
(0010,0011
treg1b
(0012, 0013H)
tc1cr
(0014H)
TREG1A (0011iH) TREG1AL (0010h)
Write only
TREGIB^ (0013(h) TREGIB^ (0012^)
Read only
SCAP1 TC,1S TC1CK TCJM (Initial value 0000 0000)
mode select timer mode
TC1M reserved reserved
internal clock fc/211 [Hz]
TC1CK source clock select internal clock fc/27 internal clock fc/23 reserved write only
start control stop counter clear
TC1S command start
reserved
SCAP1 software capture control software capture trigger
Note High-frequency clock [Hz], don't care
Note Writing low-byte timer register (TREG1AL), comparison inhibited until high-byte (TREG1Ah) written.
After writing high-byte, match during machine cycle (instruction cycle) ignored. Note source clock, when stops (TC1S 00). Note SCAP1 automatically cleared after capturing. Note Values loaded timer registers must satisfy following condition.
TREG1A>0 Note Always write TC1CR.
Note TC1CR write-only register, which cannot access read-modify-write instructions such
operate, etc. Note TREG1B written.
Figure 2-12. Timer Registers Control Register
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TMP87CC31/H31
2.4.3 Function
contents TREG1A compared with contents up-counter. match found, INTTC1 interrupt generated, counter cleared "0". Counting resumes after counter cleared. current contents up-counter transfered TREG1B setting SCAP1 (bit TC1CR)to (software capture function). SCAP1 automatically cleared after capturing.
Table 2-1. Timer Source Clock (Internal Clock)
Source clock Resolution (Atfc MHz) Maximum time setting MHz)
fc/211 [Hz] 16.77696
fc/27 1.04856
fc/23 65.535
Example Sets source clock fc/2? [Hz] generates interrupt [s]. Iater(atfc MHz). (TC1CR), 00000100B Sets source clock (TREG1A), 0F424H Sets timer register 27/fc F424H) (EIRL). Enables INTTC1 interrupt
(TC1CR), 00010100B StartsTC1
Note TC1CR write-only register started [SET (TC1CR). instruction.
Example Software capture
(TC1CR), 01010100B SCAP1<-1 (Captures) (TREG1B) Reads captured value
Source clock
Up-counter
TREG1A
INTTC1 interrupt
Source clock
Counter
TREG1B
Software Capture
Figure 2-13. Timer Mode Timing Chart
Command start
juHnrinjiAAnnnnnnnnnrL
Match Counter detect clear
Timer
ZXm-2 ?GED( m,Xm+iXm+2XII&X^llX )LmX
capture
capture
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TMP87CC31/H31
16-bit Timer (TC2) 2.5.1 Configuration
Timer control register 16-bit timer register TREG2H TREG2L _write strobe write strobe
Figure 2-14. Timer2(TC2)
2.5.2 Control
timer controlled timer control register (TC2CR) 16-bit timer register (TREG2). Reset does affect TREG2.
treg2
(0016,
tc2cr
(0015h)
T|REG2h|(0017h)
TREG2L|(0Q16H)
TC2S
JC2CK
TC2M
write only (Initial value **00 00*0)
TC2M Timer operating Timer mode
mode select Reserved
fc/223 [Hz]
TC2CK Timer source clock select fc/213 fc/28 fc/23 Reserved write only
TC2S Timer Stop counter clear
start control Start
Notel: High-frequency clock [Hz], don't care
Note When writing low-byte timer register (TREG2L), comparison inhibited until high-byte (TREG2H) written.
After writing high-byte, match during machine cycle (instruction execution cycle) ignored. Note source clock when timer stop (TC2S
Note Values loaded timer register must satisfy following condition. TREG2
Note Always write TC2CR.
Note TC2CR TREG2 write-only registers, which cannot access read-modify-write instructions such operate, etc.
Figure 2-15. Timer Register Control Register
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TMP87CC31/H31
2.5.3 Function
contents TREG2 compared with contents up-counter. match found, timer interrupt (INTTC2) generated, counter cleared. Counting resumed after counter cleared.
Table 2-2. Source Clock (Internal Clock) Timer
Source clock Resolution MHz) Maximum time setting MHz)
fc/223 [Hz] fc/213 fc/28 fc/23 1.048576 1.024 hour 18.4s 67.1 2.09712 65.535
Example
Sets source clock fc/23 [Hz] generates interrupt every (atfc MHz).
(TC2CR), 00001100B (TREG2), 61A8H (EIRH). EF14
(TC2CR), 00101100B
Sets source clock
Sets TREG2 23/fc 61A8H)
Enables INTTC2 interrupt
Starts
8-Bit Timer/Counter (TC3) 2.6.1 Configuration
Edge detector
rising
inhibit
falling
Capture control
TC3M
TC3ES
fc/2" fc/210 fc/2?
TC3CK
TC3S
TC3S
clear
source clock
8-bit up-counter
overflow
capture
TREG3B
TC3M
match
TREG3A
capture
SCAP
TC3CR
Timer/Counter3 Control Register
8-bit Timer Register
MTTr
INTTC3 interrupt
Figure 2-16. Timer/Counter
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TMP87CC31/H31
2.6.2 Control
timer counter controlled timer counter control register (TC3CR), external interrupt control register (EINTCR) 8-bit timer registers (TREG3A TREG3B). Reset does affect these timer registers.
TREG3A (0018h)
TREG3B (0019h)
TC3CR (001Ah)
EINTCR (0037h)
Read/Write
Read only
SCAP TC3S TG}CK TC3M (Initial value
TC3M Timer/counter operation mode select Timer/event counter mode Capture mode write only
TC3CK Timer/counter source clock select Internal clock fc/212 [Hz] Internal clock fc/210 Internal clock fc/27 External clock (TC3 input)
TC3S Timer/counter start control Stop counter clear Start
SCAP Software capture control Software capture
(TC4 (INT4
(Initial value OOOO OOO*)
TC3ES edge select Rising edge write
Falling edge only
Note High-frequency clock [Hz], don't care
Note mode, source clock edge selection (TC3ES) when stops (TC3S Note Values loaded timer register must satisfy following condition.
TREG3A timer/ event counter mode) Note TC3CR write-only-register, which cannot read-modify-write instructions such operate, etc.
Note Always write EINTCR.
Figure 2-17. Timer Register Control Registers
2.6.3 Function
timer/counter three operating modes timer, event counter, capture mode.
Timer Mode
this mode, internal clock shown Table used counting contents TREG3A compared with contents up-counter. match found, timer counter interrupt (INTTC3) generated, up-counter cleared. Counting resumes after up-counter cleared. current contents up-counter loaded into TREG3B setting SCAP (bit TC3CR) "1". SCAP automatically cleared after capturing.
Table 2-3. Source Clock (Internal Clock) forTimer/Counter
Source clock Resolution MHz) Maximum setting time MHz)
fc/212 130.56
fc/210 32.64
fc/27 /J.S 4.08
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TMP87CC31/H31
Event Counter Mode
this mode, input pulse used counting Either rising falling edge selected with TC3ES (bit EINTCR). contents TREG3A compared with contents up-counter. match found, INTTC3 interrupt generated counter cleared. maximum applied frequency fc/24 [Hz]. more machine cycles required both high levels pulse width.
current contents up-counter loaded intoTREG3B setting SCAP (bit TC3CR) "1". SCAP automatically cleared after capturing.
Example Generetesan interrupt every [s], inputting pulses pin.
(TC3CR), 00001100B (TREG3A), (EIRH).EF8
(TC3CR), 00011100B
SetsTC3 mode source clock Enables INTTC3 interrupt
Starts
Capture Mode
pulse width, period duty input measured this mode, which used decoding remote control signal, etc. counter running free internal clock. rising (falling) edge input, current contents counter loaded into TREG3A, then up-counter cleared INTTC3 interrupt generated. falling (rising) edge input, current contents counter loaded into TREG3B. this case, counting contineus. next rising (falling) edge input, current contents counter loaded into TREG3A, then counter cleared again interrupt generated. counter overflows before edge detected, into TREG3A overflow interrupt (INTTC3) generated. During interrupt processing, determined whether there overflow checking whether TREG3A value ffh- Also, after interrupt (capture TREG3A, overflow detection) generated, capture overflow detection halted until TREG3A been read out; however, counter continues. Therefore, TREG3B been read earlier than TREG3A.
JTJTJTJTJlvJTJTJTJlv^
Up-counter
input TREG3A
TREG3B
INTTC3 interrupt Reading TREG3A
(overflow)
capture capture overflow
Figure 2-18. Timing Chart Capture Mode (TC3ES
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TMP87CC31/H31
8-bit Timer/Counter (TC4) 2.7.1 Configuration
TC4ES
TC4S
fc/211 fc/27 fc/23
TC4CK TC4S
source clock
clear
8-bit up-counter
TC4M
TC4CR
TREG4
match
Note MPX; Multiplexer CMP; Comparator
Timer/Counter Control Register 8-bit Timer Register INTTC4
interrupt
Figure 2-19. Timer/Counter4
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TMP87CC31/H31
2.7.2 Control
timer counter controlled timer/counter control register (TC4CR), external interrupt control register (EINTCR) 8-bit timer register (TREG4). Reset does affect TREG4.
treg4
(001Bh)
tc4cr
(001CH)
TC4S TC4CK TC4M
Write only
(Initial value 00*0 0000)
TC4M operating mode select Timer/event counter mode Reserved Reserved write only
TC4CK source clock select Internal clock fc/211 [Hz] Internal clock fc/27 Internal clock fc/23 External clock (TC4 input)
TC4S start control Stop counter clear Start
(INT4 (TC3 (Initial value 0000 000*)
TC4ES edge select Rising edge Falling edge write only
Note High-frequency clock [Hz], don't care
Note operating mode, source clock selection edge selection (TC4ES) when
stops (TC4S Note Always write TC4CR.
Note Values loaded timer register must satisfy following condition. TREG4>0
Note TC4CR, EINTCR TREG4 write-only registers, which cannot access read-
modify-write instructions such operate, etc. Note Always write 7-6andbit2-1 EINTCR.
Figure 2-20. Timer Register Control Registers
2.7.3 Function
timer/counter4 operating modes timer event counter mode. Timer Mode
this mode, internal clock used counting contents TREG4 compared with contents up-counter. match found, timer counter interrupt (INTTC4) generated counter cleared. Counting resumes after counter cleared.
Table 2-4. Source Clock (Internal Clock) forTimer/Counter4
Source clock Resolution MHz) Maximum setting time MHz)
fc/211 [Hz] 65.28
fc/27 4.08
fc/23
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TMP87CC31/H31
Event Counter Mode
this mode, input (external clock) pulse used counting Either rising falling edge selected with TC4ES (bit EINTCR). contents TREG4 compared with contents up-counter. match found, INTTC4 interrupt generated counter cleared. maximum applied frequency fc/24 [Hz]. more machine cycles required both high levels pulse width.
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TMP87CC31/H31
8-bit Timer/Counter (TC4) 2.7.1 Configuration
TC4ES
TC4S
fc/211 fc/27 fc/23
TC4CK TC4S
source clock
clean
8-bit up-counter
TC4M
TC4CR
TREG4
match
Note MPX; Multiplexer CMP; Comparator
Timer/Counter Control Register 8-bit Timer Register INTTC4
interrupt
Figure 2-19. Timer/Counter4
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TMP87CC31/H31
2.7.2 Control
timer counter controlled timer/counter control register (TC4CR), external interrupt control register (EINTCR) 8-bit timer register (TREG4). Reset does affect TREG4.
treg4
(001Bh)
tc4cr
(001CH)
TC4S TC4CK TC4M
Write only
(Initial value 00*0 0000)
TC4M operating mode select Timer/event counter mode Reserved Reserved write only
TC4CK source clock select Internal clock fc/211 [Hz] Internal clock fc/27 Internal clock fc/23 External clock (TC4 input)
TC4S start control Stop counter clear Start
(INT4 (TC3 (Initial value 0000 000*)
TC4ES edge select Rising edge Falling edge write only
Note High-frequency clock [Hz], don't care
Note operating mode, source clock selection edge selection (TC4ES) when
stops (TC4S Note Always write TC4CR.
Note Values loaded timer register must satisfy following condition. TREG4>0
Note TC4CR, EINTCR TREG4 write-only registers, which cannot access read-
modify-write instructions such operate, etc. Note Always write 7-6andbit2-1 EINTCR.
Figure 2-20. Timer Register Control Registers
2.7.3 Function
timer/counter4 operating modes timer event counter mode. Timer Mode
this mode, internal clock used counting contents TREG4 compared with contents up-counter. match found, timer counter interrupt (INTTC4) generated counter cleared. Counting resumes after counter cleared.
Table 2-4. Source Clock (Internal Clock) forTimer/Counter4
Source clock Resolution MHz) Maximum setting time MHz)
fc/211 [Hz] 65.28
fc/27 4.08
fc/23
3-31-54
TMP87CC31/H31
Event Counter Mode
this mode, input (external clock) pulse used counting Either rising falling edge selected with TC4ES (bit EINTCR). contents TREG4 compared with contents up-counter. match found, INTTC4 interrupt generated counter cleared. maximum applied frequency fc/24 [Hz]. more machine cycles required both high levels pulse width.
3-31-55
TMP87CC31/H31
Remote Control Signal Preprocessor External Interrupt Input
remote control signal waveform determined inputting remote control signal waveform from which carrier wave eliminated receive circuit (INT3 RXIN) pin. When remote control signal preprocessor/external interrupt also used port, port output latch "1". When used remote control signal preprocessor external interrupt input pin, used normal port.
2.8.1 Configuration
fc/2">-
fc/2io>-
fc/28
fc/27
fc/26
fc/25
fc/22_^WM
Selector
INT3/RXIN
Polarity select
IRNC
Receive counter
RPOLS
Noise canceller
EINT
Receive counter value monitor (RBCTM)
Interrupt
RNCM select
Selector
Measurement width select
fc/26
"RCCK
fc/28 fc/210 <fc/2i2
INT.
8-bit up-counter
INT3
Interrupt request
Remote control receive counter register (RXCTR)
Match detect
CREGA
Shift register
RXCR1
RXCR2
Remote control receive data buffer register (RXDBR)
Remote control receive control register
Remote control receive control register
Figure 2-21. Remote Control Signal Preprocessor
2.8.2 Remote Control Signal Preprocessor Control
When remote control signal preprocessor used, operating states controlled monitored following registers. Interrupt requests also remote control signal preprocessor external interrupt input pin.
Remote control receive control register (RXCR1)
Remote control receive control register (RXCR2)
Remote control receive counter register (RXCTR)
Remote control receive data buffer register (RXDBR)
Remote control receive status register (RXSR)
When this used forthe external interrupt input, setEINTin RXCR1 otherthan"11'
3-31-56
TMP87CC31/H31
Remote control receive control register
RXCR1
(OFDOH) RCCK RPOLS EINT
(Initial value 0000 0000)
RCCK 8-bit up-counter source clock select fc/26 [Hz] fc/28 fc/210 fc/212 Read/ Write
RPOLS Remote control signal polarity select Positive Negative
EINT Interrupt source select Rising edge Falling edge (when RPOLS Rising/Falling edge 8-bit receive
Noise canceller noise eliminating time select Noise canceler disable 22/fc 1/fc 25/fc 1/fc 26/fc 1/fc 27/fc 1/fc 28/fc 1/fc 2io/fcx7-1/fc 211/fcx7 1/fc
Note High-frequency dock [Hz].
Note2 After reset, RPOLS does change value receiving remote control signal. setting interrupt edge measurement data, EINTand RMM.
Remote control receive control register
RXCR2 (0FD1H)
CREGA
(Initial value 0000 0*00)
Match detect time (Tth) CREGA/RCCK
CREGA Setting detect time match with CREGA
8-bit up-counter upper bits Example CREGA RCCK fc/26 [Hz],
[//s]
8-bit up-counter start control Stop counter clear Start Read/ Write
Measurement mode select (invalid when EINT "10") Reterto table
Note High-frequency clock [Hz]. don't care
Note2 When interrupt source rising/falling edge, high widths forcibly measured separately.
Note3 CREGA before EINT sets 8-bit receive end.
Figure 2-22. Remote Control Receive Control Register
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TMP87CC31/H31
Remote control receive counter register
RXCTR (0FD2H)
Remote control receive data buffer register
RXDBR (0FD3h)
t-1-1-1-1-r
Remote control receive status register
RXSR (0FD4h)
OVFF RNCM
Read Only
(Initial value 0000 0000)
Read Only
(Initial value 0000 0000)
(Initial value 0000 *000)
RBCReceive counter value monitor
OVFF 8-bit up-counter overflow flag overflow Overflow Read
Data buffer register input monitor Upper 4bits 8-bit up-counter CREGA Upper 4bits 8-bit up-counter CREGA Only
RNCM Remote control signal monitor after
passing through noise canceller
Note! Don't care.
Figure 2-23. Remote Control Receive Counter Register, Data Buffer Register, Status Register
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TMP87CC31/H31
Table 2-5. Combination Interrupt Source Measurement Mode
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TMP87CC31/H31
2.8.3 Noise elimination time setting
remote control receive circuit noise canceller. setting RXCR1, input signals shorter than fixed time eliminated noise.
Table 2-6. Noise Elimination Time Setting
Minimum signal pulse width atfc 8MHz Maximum noise width eliminated atfc 8MHz
4.63 [//s] 3.38 [//s]
32.63 27.88
64.63 55.88
(2i0 5)/fc 128.63 111.88
5)/fc 256.63 223.88
(213 1.025 [ms] 895.88
(214+5)/fc 2.049 X7-1)/fc 1.792 [ms]
2.8.4 Operation
interrupts rising, falling, rising/falling edge, measurement modes
First EINT RMM. Next, "1"; 8-bit up-counter counted internal clock. After measurement, 8-bit up-counter value saved RXCTR. Then, 8-bit up-counter cleared, INT3 request generated, 8-bit up-counter resumes counting. 8-bit up-counter overflows (FFh) before measurement completed, INT3 request generated overflow flag (OVFF) "1". Then, 8-bit up-counter cleared. overflow detected reading OVFF interrupt processing. restart 8-bit up-counter, "1". Setting zero-clears OVFF.
3-31-60
RNCM
rcck
iiiJiJijmjTJTJTimji^^
int3 request
8-bit up-counter value
rxctr
8-bit up-counter value
rxctr
width measurement
Rising edge cycle measurement
8-bit
High width measurement
Figure 2-24. Rising Edge Interrupt Timing Chart (RPOLS
RNCM
rcck
int3 request
8-bit up-counter value
mnnnjiJTrumrui^^
rxctr
High width measurement
8-bit up-counter value
rxctr
Falling edge cycle measurement
8-bit
width measurement
Figure 2-25. Falling Edge Interrupt Timing Chart (RPOLS
RNCM
rcck
miiJiJiJiJiJTJi/LrLjmjx^^
INT3 request
8-bit up-counter value
rxctr
High width measurement
Figure 2-26. Rising Falling Edge Interrupt Timing Chart
TMP87CC31/H31
8-bit receive interrupts measurement modes
determining one-cycle remote control signal one-pulse width one-bit data "1", INT3 request generated after 8-bit data received. When determined, this means upper four bits 8-bit up-counter have reached CREGA value. When determined, this means upper four bits 8-bit up-counter have reached exceeded CREGA value. 8-bit up-counter value saved RXCTR after determined. determined data saved, bit, RXDBR rising edge remote control signal (when RPOLS falling edge). number bits saved RXDBR counted receive counter saved RBCTM. RBCis "0001B" rising edgeofthe input (when RPOLS falling edge) afterthe INT3 request generated.
INT3 request
Note Valid only when bits received.
Receive counter value*
counter value*
8-bit counter value
RBCTM*
RNCM
RCCK
OVFF
Setto command.
Figure 2-27. Overflow Interrupt Timing Chart
3-31-64
Table 2-7. Count Clock Remote Control Preprosessor Circuit
Count clock (RCCK)
Resolution Maximum setting time
fc/26 [Hz] fc/28 fc/210 fc/212 2.048 8.192 32.768 131.072
TMP87CC31/H31
6-bit Conversion (Comparator) Inputs
comparator input analog input discriminate input (Auto Frequency Control) signal input, etc. analog input voltage level (pins CIN3 CINO) detected 64-stage setting reference voltage.
comparator input pins CIN3 CINO also used ports P54. When used comparator input, output latch should setto
2.9.1 Configuration
Figure 2-29. 6-bit Conversion (Comparator) Inputs
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TMP87CC31/H31
2.9.2 Control
conversion (comparator) inputs controlled comparator input control register (CMPCR) comparator input data register (CMPDR). CMPDR contains reference voltage setting register (write-only) comparison result register (read-only).
Comparator Input Control Register
cmpcr
(OOOEh)
ECMP SCIN
(Initial value 0****000)
ECMP Comparator input control Disable Comparator input Enable Comparator input write only
SCIN Number Comparator input channels select channel (CIN0) channels (CIN0to channels (CIN0to channels (CIN0to Reserved
Notel don't care
Note2 CMPCR write-only register must used with read-modify-write instructions such operate, etc.
Comparator Input Data Register
cmpdr
(OOOFh)
SV^EF
COUT3 COUT2 COUT1
(Initial value **00 0000)
SVREF Reference voltage (VREF) setting Vref Vddx (SVREF (SVREF write only
COUT3 Comparison result Result comparing CIN3 CIN0 analog input voltage with reference voltage. read only
Notel don't care
Note2 SVREF write-only bits must used with read-modify-write instructions such operate, etc.
Note3 Wich read instruction CMPDR, bits read undefined data.
Figure 2-30. Comparator Input Control Register Data Register
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TMP87CC31/H31
2.9.3 Function
Reference voltage (Vref) with SVREF (bits CMPDR).
Vref (SVREF (SVREF
number comparator input channels selected with SCIN (bits CMPCR). Sequential comparison selected number channels started setting ECMP(bit7 CMPCR) "1". comparison channel requires machine cycles; therefore, comparison result register (COUT3 COUTO) should read interval equal [number channels machine cycles] after setting reference voltage (Vref)- COUT3 COUTO input voltage (pins CIN3 CINO) higher than reference voltage (Vref) otherwise those cleared "0".
Note When entering STOP mode, ECMP automatically cleared SCIN/SVREF held. And, COUT3 COUTO always
Note pins specified comparator input with SCIN longer used normal digital input and, read outas"0".
Note COUT3 COUTO read when used comparator input. example, CMPDR always read when SCIN 010b-
Example
CIN3-CIN0 inputs with Vref
(P5), 11111111B (CMPDR), 00011111B (CMPCR), 10000011B
(CMPDR)
port output latches "1". VREF
SCIN channels Enables comparator input machine cycles machine cycles wait. Reads CMPDR (COUTO COUT3).
Table 2-8. Reference Voltage
SVREF Vref
0.078
0.156
0.234
1110 4.844
11110 4.922
111111 5.000
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TMP87CC31/H31
2.10 Pulse Width Modulation Circuit Output
87CC31/H31 14-bit resolution pulse width modulation (PWM) channel 7-bit resolution channels. converter output easily obtained connecting external low-pass filter. outputs multiplexed with general purpose ports (PWMO) (PWM7), (PWM8), (PWM9). When these ports used outputs,the corresponding bits output latches should "1".
2.10.1 Configuration
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TMP87CC31/H31
2.10.2 Output Wave Form
PWMO output
This 14-bit resolution output period 215/fc [s].
high-order bits data latch control pulse width pulse output with period Tm/64), which sub-period PWMO. When 8-bit data decimal 255), this pulse width becomes where 2/fc.
lower 6-bit data used control generation additional wide pulse each period. When 6-bit data decimal 63), additional pulse generated each periods periods contained period. relationship between bits data position period where additional pulse generated shown Table 2-9.
Table 2-9. Correspondence between Bits Data Additional Pulse Generated Period
position bits data Relative position where output pulse generated. (Number T$(i) isted)
BitO
30,.,
17,.,
Note When corresponding output.
PWM9 outputs
These 7-bit resolution outputs period 28/fc [s]. When 7-bit data decimal 127), pulse width becomes wave form illustrated Figure 2-32.
PWMO
64Ts
nxt0
TS(1)
Pulse width Pulse width
(63)
PWM1
PWM9
Pulse width kxto
Note shown additional pulse PWMO. Note 29/fc MHz), TN=28/fc MHz)
Figure 2-32. Output Wave Form
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TMP87CC31/H31
2.10.3 Control
output controlled Control Register (PWMCR) Data Buffer Register (PWMDBR). status transfer data from PWMDBR data latch read PWMEOT status register (PWMSR).
Control Register
PWMCR (0025H)
(Initial value **** 0000)
0000 Lower 6-bit PWM0
0001 High-order bits PWM0
0010 PWM1
0011
0100
Selection data latch 0101 PWM4 write
0110 only
request data transfer 0111
1000
1001 PWM8
1010 PWM9
1011 reserved
1100 Data Transfer Request
1101 reserved
111* reserved
Status Register
PWMSR (0025H)
PWMEOT
(Initial value 01111111)
PWMEOT data transfer flag Transfer Under Transfer read only
Note don't care
Data Buffer Register
PWMDBR (0026H)
write only
Figure 2-33. Control Register/PWM Status Register/PWM Data Buffer Register
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TMP87CC31/H31
Programing Data
output controlled writing output data data latches. sequence writing output data data latch shown follows;
Write channel number data latch PWMDLS.
Write output data PWMDBR.
Write "0CH" PWMCR.
When transferring output data completed, PWMEOT becomes "0", indicating that next data written. write data when PWMEOT because write errors occur this case.
Note: When writing output data PWMO data latch, write "0CH" PWMCR after writing 14-bit output data completed.
While output data being written data latch, previously written data being output. maximum time from point which "OCh" written data latch until output switched 215/fc (4.096 MHz) PWMO output 29/fc /us, MHz) PWM1 PWM9 output.
Example PWMO outputs wave form with low-level width additional pulse.
PWM1 outputs wave form with low-level width. PWM2 outputs wave form with low-level width.
Note
WAITO
WAIT1
WAIT2
(PWMCR), Select lower 6-bit PWMO
(PWMDBR), additional pulse
(PWMCR), Select high-order bits PWMO
(PWMDBR), 2/fc
(PWMCR), Request Data Transfer
TEST (PWMSR). PWMEOT
WAITO
(PWMCR), Select
(PWMDBR), 2/fc
(PWMCR), Request Data Transfer
TEST (PWMSR). PWMEOT
WAIT1
(PWMCR), Select PWM2
(PWMDBR), /us-T 2/fc
(PWMCR), Request Data Transfer
TEST (PWMSR). PWMEOT
WAIT2
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TMP87CC31/H31
2.11 Pulse Output Circuit (PULSE)
Pulse output circuit generates pulse clock duty dividing High-frequency clock.
pulse output used basic clock peripheral ICs. When port used
pulse output, output latch "1".
Pulse output control command register
PUL5ECR (0027h)
(Initial value
111*)
fc/27 [Hz] 62.5 kHz, MHz)
fc/26 (125 kHz,
fc/25 kHz, Read/ Write
Select pulse frequency fe/2* fc/23 fc/22 reserved kHz, MHz, MHz,
Disable pulse output
Note :fc; High-frequency clock don't care
Output data
Output latch
Selecter
fc/27
fc/26
fc/25
fc/24
fc/23
fc/22
PULSECR
Pulse Output Control Command Register
Figure 2-34. Pulse Output Circuit
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TMP87CC31/H31
2.12 On-Screen Display (OSD) Circuit
TMP87CC31/H31 features built-in on-screen display circuit used display characters symbols screen. characters character fonts displayed character rows.
circuit functions follows: Number character fonts (including blank character) Numberof display characters character rows).
Composition character Character sizes Display colors
dots
(selectable line line)
Character colors Fringe color Background color
(selectable character character), (selectable page page) (selectable page page)
Fringing function (for large, middle, small characters)
Smoothing function (for large middle characters)
Display position horizontal steps;
Full-raster blanking function
Blinking function
Reverse function
Reverse Blinking function
Window function
vertical
steps
2.12.1 Configuration
osci
OSC2
Oscillation circuit
(HD)
(VD)
Horizontal position counter
Horizontal position decoder
Vertical position counter
Vertical position decoder
control
Display memory 24x4x13 bits
Character code
Character bits
INTOSD Interrupt request
Character data
Y/BI,
Q.+J
P67(Y/BL) P66(B)
Figure 2-35. Circuit
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TMP87CC31/H31
2.12.2 Character Display Memory
Character
character contains character fonts. user fonts desired. character consists characters dots (character codes 5Fh). Each corresponds character ROM. When character "1", corresponding displayed; "0", displayed. start address character corresponding character code determined following expression:
Start address character CRAx40h 4000h Since character code used blank character, character font this character code cannot changed. Write data character code 00h-
unused bits (bit with lower 4-bit address) write data "FFh" unused address (the lower 4-bit address character ROM. Figure 2-36. showsan example character font configuration forthe character code together with addresses data.
Figure 2-36. shows character dump list these character fonts. Note CRA; Character code (00h 5FH)
Note data read from character software.
Note When ordering mask, load data character address 4000h 57FFh-
Address Data
(Hex) (Hex) 65432 65432
4000
4001
4002
4003
4004
4005
4006
4007
400ft
4010
4011
4012
4013
4014
4015
4016
4017
401R
Address Data
(Hex) (Hex)
4020
4021
4022
4023
4024
4025
4026
4027
4078
4030
4031
4032
4033
4034
4035
4036
4037
403R
(Character code 00h)
Address Data
(Hex) (Hex)
4060
4061
4062
4063
4064
4065
4066
4067
406R
4070
4071
4072
4073
4074
4075
4076
4077
407R
Character font configuration
(Character code
4000/ 4010/ 4020/ 4030/ 4040/ 4050/ 4060/ 4070/
dump list
Figure 2-36. Character font configuration dump list Display memory
Each character characters displayed characters rows consists bits display memory. Five data items written display memory: character code, color data, blinking specification, reverse specification, reverse blinking specification. display memory contents become unstable after reset operation released.
There modes writing display data display memory. mode writing display data (character code, color data, blinking specification, reverse specification, reverse blinking specification) simultaneously. other mode changing either character code character ornamentation data (color data, blinking specification, reverse specification, reverse blinking specification). display data written display memory described section 2.12.3(18).
3-31-75
TMP87CC31/H31
Display memory configuration
Character code specification register bits) Color data specification register bits) Blinking specification flag bit) Reverse specification flag bit) Reverse blinking specification flag bit)
CRA6 CRAO
RDT/GDT/BDT
CRA6 CRA5 CRA3 CRA2 CRA1 CRAO
Color data
specification register
Character code specification register
Blinking specification register Reverse specification register Reverse blinking specification register
Figure 2-37. Display Memory Configuration
Note: Numerals table indicate (hexadecimal) addresses display memory.
Figure 2-38. Display Memory Address Configuration
2.12.3 circuit control
circuit controlled using control registers assigned addresses 0F80h 0F9Ah data buffer register (DBR). write read from control registers, section 2.12.3 (19). control registers used display start position, display character ornamentations (that fringing, smoothing, color data, character size, etc.), display memory addresses, character codes, etc.
After settings complete, setting display on-off control bit, EDISP, (bit ORDON) enables display (starts display). Setting EDISP disables display (halts display).
Note contents control registers initialized STOP mode.
Display position
horizontal display start position steps. vertical display start positions specified each line using steps. horizontal display start position with control registers HS16to HS10 (bits ORHS1). vertical display start position line with VS17 VS10 ORVS1). vertical display start position 2nd-4th lines determined setting VS27 VS20 VS47 VS40 (ORVS2 ORVS4) same way.
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TMP87CC31/H31
Horizontal display start position Specification unit Display page Specification steps
Specification horizontal display start position Line HS16to HS10
When FORS (Normal mode)
(HS16 HS10) 2T0$C 11T0$C (Linei
When FORS (Double frequency mode)
(HS16to HS10) xTqsc+ 6.5Tqsc (Linei
Note Tqsc cycle oscillation
Vertical display start position Specification unit Line Specification steps Specification vertical display start position
Linei VS17 VS10
Line2 VS27 VS20
Line3 VS37to VS30
Line4 VS47to VS40
Line
(Setti ngs)
Lines Line Line
Display small character Display middle character Display large character
Line
Line
Line
Figure 2-39. Screen Image
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TMP87CC31/H31
When VDSMD (Normal mode)
Line (VSn7 VSnO) 2THd
When VDSMD is"1" (Double scan mode)
Line (VSn7 VSnO) 4THd
Note THd; cycle signal
Note display lines overlapped each other, previous display line enabled next line disabled. vertical display start position overlap display lines.
(display small character) (display canceled, middle character)
(display
Occasion overlapping
Note line which displayed managed small size character line.
recommendable that vertical display start position should screen. Note Transfer contents vertical display start position registers into circuit before position scanning line coincides with their vertical display start position.
Double scan mode
double scan mode used handle non-interlaced scanning When double scan mode enabled, vertical display counter increases every scan lines vertical size double. This function enabled setting VDSMD (bit ORETC) control register
Scan mode select register bit) VDSMD (bit ORETC) Normal mode Double scan mode
Double frequency mode
frequency doubler mode used display frequency doubled. When this function enabled, clock which doubled clock doubler inputted into circuit.
This function enabled setting FORS (bit ORDON) control registerto "1".
frequency select register bit) FORS (bit ORDON) Normal mode Double frequency mode
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TMP87CC31/H31
Character sizes display
Character size selected line line from sizes. display also line line. Small, middle large character size display with control registers CS11, CS10.CS41, CS40 (ORCS4) control registers.
Character sizes sizes (Small, middle large) Character size display specification unit Line Character size select/display register bits Linei: CS11andCS10 Line CS21andCS20 Line CS31andCS30 Line CS41 CS40
Table 2-10. Character Size Display On/Off Specifications
CSn1 CSnO Character size Display on/off
Small
Middle
Large
Note line which displayed managed small character size line overlap vertical display start position, display line counter function, etc.
Table 2-11. Character Sizes
VDSMD normal mode VDSMD double scan mode
size Character size size Character size
FORS (normal mode) Small Tosc Tqsc Tose TQSC
Middle T0sc Tose Tose Tose
Large Tqsc Tqsc Tqsc Tqsc
FORS (double frequency mode) Small Tqsc Tqsc 18Thd Tqsc Tqsc
Middle Tose Tose Tose Tose
Large Tqsc Tqsc Tqsc Tqsc
Tqsc cycle oscillation THD: cycle signal
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TMP87CC31/H31
Smoothing function
smoothing function used make characters look smooth. Enabling smoothing displays dots between dots connecting corner corner within character. Small size character enabled smoothing. Smoothing enabled setting ESMZ (bit ORETC) control register "1". Smoothing specification unit: Display page Smoothing specification register bit) ESMZ (bit ORETC) Disable smoothing Enable smoothing
Fringing function
fringing function used display character with fringe width different color from that character. small characters, fringe width dot. When character displayed with maximum vertical dots horizontal dots, fringe exceeds right left, top, bottom character display area. exceeded fringe displayed; however, display characters have higher priority fringe horizontally.
Fringing enabled each line setting EFR1 EFR4 (bit OREFR) control register "1".
color fringe specified common lines using control registers, RFDT, GFDT, BFDT, (bits ORBK).
Fringing specification unit: Line
Fringing enable register bitx4) EFRn (n:1 (bit OREFR) Disable fringing Enable fringing
Fringe color specification unit: Display page Fringe color register bits) RFDT, GFDT, BFDT
Note When display line enabled fringing function, vertical size increased dots when character size small) independent character font Therefore, when vertical display start position specified space between lines, display line overlapped with increasing canceled.
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TMP87CC31/H31
_(a) Smoothing_(b) Fringing_(c) Priority Smoothing Fringing_
Figure 2-40. Smoothing Fringing Priority Smoothing Fringing
Background color function
Background color function used color entire background character area (14x18 dots). Except character area whose character code 00h-
This function specified each display page setting EBKGD (bit ORBK) control register "1".
background color specified each display page setting RBDT, GBDT, BBDT (bit ORBK) control registers. color specification same them full-raster blanking.
Background specification unit: Display page Background enable register bit) EBKGD (bit ORBK) Disable background Enable background
Background color specification unit: Display page
Background color specification registers bits) RBDT, GBDT, BBDT (bit ORBK)
Note: When background color function used, blank character (Code 00h) used first character fringing line.
Full-raster blanking function
Full-raster blanking function used color entire background display area screen). When using full-raster blanking function, YBLCS (bit7 ORETC) "1", output signal
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