Very low-cost high-integration chip Supports 486SX, 487SX, 486DX,
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CS4031 CHIPSet
Very low-cost high-integration chip
Supports 486SX, 487SX, 486DX, 486DX2 CPUs
Operating speeds 33MHz
Two-chip chip set, external needed
Integrated industry-standard CHIPS core; external needed
Integrated on-chip oscillators 14.318MHz 32.768KHz clocks
Only devices required complete system with VL-Bus slot
3-2-2-2 4-3-3-3 reads, writes
64MB memory with banks DRAM 32MB with banks
Supports 256KB, 1MB, 4MB, 16MB DRAM with depth 256K,
Hidden refresh supported higher performance
Inflated Flash support
EXteni&l ISA-Bus drivers design flexibility optimum drive
^1^)100% PC/AT* compatible
Full VESA VL-Bus supports slots lfl&^n PQFP tifeF84031 100-pin PQFP superior system performance, e.g. graphics /"Ifcffihe F84035
Patented high-performance "Page-interleaV^*^
high-performance "Page DRAM controller
VL-BUS SLOT
ISA-BUS SLOT
System Diagram
Revision Advance Product Information CS4031
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Revision History
Revision History
Revision Date Comment
3/2/93 Internal draft.
3/26/93 Internal Product Overview Introduction sections.
4/30/93 Internal review.
5/10/93 Final release.
RevfcConLO
Advance Product Information CS4031
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Contents
Table Contents
Section
Paye
Section
Ease
Introduction.7
CS4031 Pinouts.9
84031 Pinouts.9
84035 Pinouts.10
CS4031 Descriptions.11
84031 Overview.11
84035 Overview.15
84031 Descriptions.17
84035 Descriptions.23
CS4031 Registers.27
84031 84035 Port Summary.27
84031 84035 Configuration Register
DRAM Controller.
DRAM Configuration.
DRAM Controller Page Interleaving.
DRAM Memory Map.
DRAM Timing Modes.62
DRAM Timing Mode Recommendations.
DRAM Address Multiplexing.65
LoctfBus Support.65
ISAJteJfc.68
Local Master Accesses
fiie ISA-bus.
Master Accesses
to^Jdd Slaves DRAM.
Descriptions^.
tPU/LBM Access to.thetSA-Bus.
^ratjofi.?:.
todlSA Master fvlemory Access
toilt^ BufTarget.
ISA^Mastetl/QAtcess
/^to Loca^^ul Target.
^KJRtB^^DiiMl LOGIC.
ADATABUS BUFFERS.
CONtROL LINK.
Conifol Link From 84035
84031.
Control Link From 84031
84035
Test Modes 84031 84035
84031 Configuration
84035 Port Addresses.T
84035 Configuration Registers.
CS4031 System Level Functions.
Reset
Refresh.^.^.Z.
Coprocessor Logic.48
Address Mapping.i^fcS.48
ISA-Bus.fe^X.48
Local
DRAM Controller.>
Data Buffets.^^Mif
84031 Functional Descriptions.5VV
Clocks.
Clock
Clock Inputs.
BUSCLK Generation.53
14.31818MHz Clock.53
SCLK.54
0^kZZZIZZZ"ZZ"
System Reset Logic.55
Reset From PWRGOOD.56
SYSRESET.56
Shutdown.56
GATEA20 Function.57
Address Mapping.58
Addressing.58
Memory Addressing.58
ROMCS#.58
84035 Functional Descriptions.77
Clocks.
14.31818MHz Clock.
SCLK.
32.768KHZ CLOCK.
Reset.78
GATEA20.
Arbitration.78
Performance Control.79
Refresh.80
ISA-Bus Refresh Cycles.
DRAM Refresh Cycles.
ISA-Bus.
Floating-Point Logic.
Port Speaker Logic.
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_Contents
Table Contents
Section Page
CS4031 Electrical Specifications.85
84031/84035 Absolute Maximum Conditions. 84031/84035 Recommended Operating
Conditions.85
84031/84035 Characteristics.85
84031 Characteristics.86
84035 Characteristics.90
CS4031 Mechanical Specifications.93
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List Figures
List Figures
Figure
Page
Figure
Page
CS4031 CHIPSet.1
System Diagram.1
CS4031 Pinouts.9
84031 Pinout.9
84035 Pinout.10
CS4031 Registers.27
84031 Port Addresses.28
Configuration Register Address Port.28
Configuration Register Data.28
Keyboard Data Port.28
PortB.29
Keyboard Command/Status Port.30
Real Time Clock Address Port
Mask.30
84031 Configuration Registers.
ISA-Bus Command Delays.*
ISA-Bus Wait States Address HoldL
ISA-Bus Clock Selection.
DRAM Timing.
DRAM Setup.A.%*.?.
DRAM DRAM DRAM Block Startjm^&essCv Video Area Shadow"
Local CoriftplS.35
DRAM Shadow RsadEnabl&t.*.3f'
DRAM Shadow Wpte Enabled.vfSW
ROMCS Enable.>0
Soft Reset GATEA20.A^V
Reserved Write).>
84035 Port Addresses.Al.J8\
ControUer (8-Bit DMApW-.<0*8
Interrupt ControUer
Configuration Register Address^ort .T^.
Configuration Register Data.38
Timer (8254).38
PortB.39
Real Time Clock Address Pott
Mask.40
Real Time Clock Data Port.40
Page Registers.40
Fast Reset GATEA20.41
Interrupt Controller (IRQ15:8).41
ControUer (16-Bit DMA).41
84035 Configuration Registers.42
Wait State Control.42
Performance Control.43
84035 MisceUaneous Control.44
Clock Selection.45
CS4031 System Level Functions.47
Schematic Symbols.49
8403H%^ional Descriptions.51
Connections With Heavier
^\lfcLKLoad.52
t%*tiormal Clock Connection.52
Clock Circuiti.53
/-Recommended Circuit
X^*Power-On Reset^imm^.Diaeram.55
Reset DRAl-_
ower-On Reset^imi^Di agram.
leset
^M^d^oip Bank
P*gfc
DHAM Bank
^Support**,.).61
Examples.61
B^AM Timing Diagram.63
Block Slot.66
VL-Bus Block Slots
With Multiple Masters.67
VL-Bus Block Slots
With Single Master.67
CPU/LBM Read Write
Timing Diagram.69
CPU/LBM Access ISA-Bus
Timing Diagram.70
IOCHRDY Effect Timing Diagram
(CPU/LBM Access ISA-Bus).71
Master Memory Local
Target Timing Diagram.
Master Access LBT.73
84035 Functional Descriptions.77
DRAM Refresh Timing Diagram.81
ISA-Bus Refresh Timing Diagram.81
Timing Diagram.82
CS4031 Electrical Specifications.85
Timing Waveforms.91
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List Tables
List Tables
Table
Table
Page
CS4031 Descriptions.11
84031 Overview.11
84035 Overview.15
84031 Descriptions.17
Clocks Reset.17
Aibitration.17
Local Control Signals.18
ISA-Bus.18
Address Bus.19
DRAM Controller.20
Data Bus.21
Interrupts.22
Control Link Keyboard.22
84035 Descriptions.23
Clocks.23
Resets.
Arbitration.
ISA-Bus.
Address Bus.^5
Data Bus.J&. 25^4,7
Interval Timer Control
CS4031 Registers.
84031 84035SumjmaOuT.
84031 84035 Agister Summary.
.JSfc-
84035 Functional Descriptions.77
84035 Clock Divider.77
Owner Indication.79
84035 Port Bits.83
CS4031 Electrical Specifications.85
84031/84035 Absolute Maximum
Conditions.85
84031^4035 Recommended Operating
/Conditions.85
\WQ31/84035 Characteristics.85
>%4031 Characteristics.86
S&%ignaJs.-4-*.15
JQranj, Signals.87
Formula Specifications.88
^GPU LocafBul^ignals.89
84031 Functional Descriptions.
Suggested BUSCLK Dividers Each,
Frequency.
Possible ISA-Bus Clock FrequendeS
Each
84035 Clock Divider.fe.
Special Cycle Encoding.56
DRAM Bank Starting Address.59
Suggested Ras-to-CAs Delay
Read Cycles.62
DRAM Timing Mode.62
Address Multiplexing.65
Port Bits.74
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CHIPS'
Introduction
Introduction
CS4031 very high-integration low-cost chip 486-based PC/AT compatible systems. consists chips, F84031 F84035. These optimally partitioned minimize external count.
Only devices required implement 100% PC/AT compatible complete system with 2-bank DRAM 32MB) VESA VL-Bus slot either master slave. Only additional needed system supporting VL-Bus slots with more than master.
84031 integrates DRAM controller, ISA-bus controller, VESA VL-Bus controller 160-pin PQFP package.
84035 super industry-standard CHIPS (Integrated Peripheral Controller, 82C206) which integrates 8237 controllers, 8259 interrupt controllers, 8254 timer/counter, MC1468J3 real time clock, 74LS612 memory mapper4n^ 100-pin PQFP package.
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Advance Prod Informstior CS4031
CS4031 Pinouts
CS4031 Pinouts
CS4031 CHIPSet comprised chips, 84031 84035. Following 84031 84035 pinout diagrams assignments listed signal names.
OJON CLK20UT SCKOUT LDEV# GATEA20 (8042CS#) ROMCS# LOUT DGNT# MEMW* MEMR# IOCS16# MEMCS16# SBHE* BALE IOR* IOW# IOCHRDY OWS* IOCHCK* SDIR1 SDERD SDEN#
BE0#
BE1#
BE2#
BRDY#
KEN#
RDY#
BE3*
EADS#
BLAST*
CAS7#
CAS6#
CASS#
CAS4#
RAS1*
RAS3#
RAS2#
MA11
DWE#
MA10
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CHIPS"
CS4031 Pinouts
.sEsaSlp^-
IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ1 IRQ10 IRQ12 IRQ15 SMEMR# SMEMW#
PWRGOOD SCLK
-a^iifc,
MEMR# MEMW# IOR# 3lOW# SBHE#
iIOCHRDY MASTER* 32EX2 32KX1 iVCC
"pwimra
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CS4031 Descriptions 84031 Overview
CS4031 Descriptions
84031 OVERVIEW
84031 Overview table below lists pins signal names. detailed functional descriptions 84031 follows overview tables.
84031 OVERVIEW
Si(ul Nunc
poi/ Output (mA)
<pF)
Notes
Pins)
1,20,40,81, 100,
Syatem
GND(lOPm)
21,41,42,79,80,81,101, 121,122,100,
Syslon gnuid
ows#
vsg^y
ISA-bus
CPU, lockl buffets
CPU, focal devices, buffers
Xla^ buiMfcvices, buffers
^CPU, local devices, buffers ytgPU, loc^busdevices, buffers
1_CT_
CPU,food devices, buffers devices, buffers
devices, buffers
Te*' CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffets
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffers
CPU, local devices, buffets
local devices
BALE ISA-bos
BB0# local devices
local devices
local devices
local devices
local devices
local devices
BUSCLK inverter
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CS4031 Descriptions 84031 Overview
84031 OVERVIEW (continued)
Signal Name put/ Output <mA) (bA) Load <pF> Pull-up Notes
CASO* DRAMs plus wiring
CASI* DRAMs plus wiring
CAS2# DRAMs pins wiring
CAS3# DRAMs 7pFplus wiring
CAS4* DRAMs TpFph* wiring
CAS5# DRAMs TpFpJus wiring
CAS6* DRAMs plus wiring
CASH DRAMs plus wiring
C3LK2 CLX20UT nrilUrnr circuit
CLK20UT 84031 CUC2
CLKIN -Va-* ^gcOlator
D/C# local devices
CPU, DRAMs, local devices
^JCPU, DRAMs, k*al devices
65-Vt DRAMs, devices
CPU, DRAMs^andJpaU devices
CPU, local devices
Vs*5 CPU, DRAMs; lo^d ^.devices
CPU.^BAMs, local devices
iocil devices
fife local devices
CPU, DRAXi^and local devices
-y^V ifrfc^i
local devices
DRAMs, local devices
DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
CPU, DRAMs, local devices
DWE# DRAMs 7pFpius wiring
local
QATEA20 4.7K Keyboard catto&cr
HLDA
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CS4031 Descriptions 84031 Overview
84031 OVERVIEW (continued)
Signal Name Input/ Output (mA) Load <pF> foil-up Note*
IOCHCX* 4.7K ISA-bus
IOCHRDY ISA-bus
IOCS16* ISA-bus
IOR# ISA-bus
IOW# ISA-bus
KBRST* 4.7K Keyboard controller
KEN#
from VL-Bus dots.
LOUT
M/IO# local developers
DRAMS fipFphjs wiring
DRAMS plus wiring
DRAMS plus wiring
DRAMS ttrdpP plus wiring
^200 DRAjMS^^pFplus wiring
20Ctv DftAMS-4 flpF plus wiring
2<l>ftAMS C^jpF.jJus wiring
18-%>' f^DRAM? 6)3?-plus wiring
VDRAM^ fipF plus wiring
DRAWS plus wiring
MA10 24-DK^MS plus wiring
MA11 24-pRAMS phis wiring
Wx-bus
ISA-bus
MEMR# ISA-bus
MEMW# 445-% ISA-bus
DRAMs
DRAMs
fc65 DRAMs
DRAMs
Reserved
Reserved
Requires pull-up
RASO* DRAMs plus wiring
RAS1# DRAMs plus wiring
RAS2# DRAMs 7pFptas wiring
DRAMs 7pFptns wiring
RDY# local devices
ROMCS* >042 chip aetect
SBHE# ISA-bus
SCLK OacOlator circuit
8GLKOUT (VBUFDIRf) 84031,14035, CPU, VRAM buffers
SDENf F245 inverter
8DIR0 F245
SDIR1 F245
SYSRESFT
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CS4031 Descriptions 84031 Overview
84031 OVERVIEW (continued)
Signal Nunc Output (mA) Load Pnli-up
W/R# local devices
F245
ROM, LS245, 84035
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CS4031 Descriptions 84031 Overview
84035 OVERVIEW
84035 Overview table below lists pins signal names. detailed functional descriptions 84035 follows this overview table.
84035 OVERVIEW
Input/ lofl Load Pull-up
Signs! Name_ftn Output Priver (mA) (bA) (pF)
Pins) 1,31,51, Battery backup circuit
Pint) 16,30,50, System ground
63,80,
connect
14MX1 1818MHz crystal input
14MX2 1431818MHz crystal output
32KX1 -jXJ- ^Crystal circuit
32KX2 ssStytfal circuit
/m^Sf >CPU 8403^
84()31^5
63.-' andf403j. Drivoi DMA; inputs generate
CPUagd 84Cpi. Dfiveiifor t)MA, inputs generate
CJgD frW3 tiriveri DMA; inputs generate
x^PJJ M031. ^iven DMA.
Ct?J and84Q?J. Driven DMA.
^CPUm5%*031. Driven DMA.
CKJi^84031. Driven DMA.
A20M#/TEST# 30,- ^lOK
ISA-bus
CPURESET CPU(s)
DACX0# ISA-bus
DACKl* V^-'Out ISA-bus
DACK2# 4^-C ISA-bus
DACK3* ISA-bus
DACX5* -1.05 ^2<0 ISA-bus
DACX6# ISA-bus
DACX7* ISA-bus
DONT* 84031; buffer direction
DREQ0 ISA-bus
DREQ1 ISA-bus
DREQ2 ISA-bus
DREQ3 ISA-bus
DRBQ5 ISA-bus
DREQ6 lfflk ISA-bus
DRBQ7 ISA-bus
FEKRt (KQ13) 7,83 coprocxwr logic
HLDA
HOLD CPU(s)
KJNNW/INTCLR coprocessor logic
IOCHRDY ISA-bus 84031
IOR* ISA-bus 84031. Driven cycles only.
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CS4031 Descriptions 84031 Overview
84035 OVERVIEW (continued)
Signal Name Input/ Output Driver (mA) (mA) Load <pF> Pull-up Notes
iow# ISA-bus 84031. Driven cycles cmly.
IRQ01 ISA-bus
IRQ03 ISA-bus
IRQ04 ISA-bus
IRQ05 ISA-bus
IRQ06 ISA-bus
IRQ07 ISA-bus
IRQ09 ISA-bus
IRQ10 ISA-bus
ISA-bus
ISA-bus
IRQ14 ISA-bus
ISA-bus
LONT# Local
84031
LOUT 84031
LREQ# Local tigs (puE-up uaed).
MASTER* ISXVfcras''
MEMR# IfcAJnis and(<4031 cycles oily.
MEMW# ^240 ISA-bus Driven cycles only.
PSRSTBt ^fcC citctiit
PWROOOD Power ii^ply circuit
REFRESH* Atoas
24<J. TSA-bus F245
^"^SA-bw F245
ISA-bus F245
-1%. ISA-bus F245
ISA-bus F245
ISA-bus F24S
ISA-bus F245
ISA-bus P245
SA17 ISA-bus (driven from A19:17)
SA18 ISA-bus (driven from A19:17)
SA19 -'ii^ 24-^ ISA-bus (driven Cram A19:17)
SBHE# ISA-bus 84031
SCLK Oscillator circuit
SLOW Turbo twitch
SMEMR* ISA-bus 84031
SMEMR* ISA-bus 84031
SPKR Speaker buffer
SYSRESET Capoceaaor, 4025, buffer ISA-bus.
ISA-bos
84031, LS244,8042,
LS244,8042,
>4031, LS244,8042,
84031, LS244,8042,
84031, LS244,8042,
>4031, LS244, >042,
LS244,8042,
LS244,8042,
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84031 DESCRIPTIONS
functional descriptions 84031 listed below. overview signal names, 84031 Overview table pinout diagram.
CLOCKS RESET
Input/
Signal Name Output Description
CLKIN Clock Input clock from oscillator). Used only create CLK20UT
SCLKOUT.
CLK20UT Clock Output CLK20UT buffered version CLK2, with very skew SCLKOUT. back taCLK2 8403land other logic requiring clock.
SCLKOUT clock output This <3LKIN divided used drive SCLK 84031,84035,
CLK2 clock input Ueedior SRAM state machine. also used source ISA-busdivid^pwfe.
SCLK clock iiw^^'
SYSRESET
BUSCLK
ARBITRATION
Signal Name 6^Hptk>n
HLDA ,^-CPU Hold Acknbv^ge. Wheriiow, indicates that control "\ylocal bus. Wjbien high, ciWi local master, controller, master ha&fte^us. p&44dsl generates parity DRAM write cycles when this ^high.
DGNT# DMA^eonSoller Crarft. When low, indicates that either controller an&>A*bus maittf'has control bus. 84031 becomes slave ^^floafe^he I&j^rfnfe commands when this signal low.
\*lSA-5ull4ast^r signal. Indicates that master bus. 84031 uses.t&is to^Betermine difference between master cycles. determining timing IOCHRDY generation.
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CS4031 Descriptions 84031 Descriptions
LOCAL CONTROL SIGNALS
Signal Name Input/ Output Description
ADS# Address Strobe. Input local master cycles. Output master cycles.
W/R# Write/Read status signal. Input local master cycles. Output master cycles.
D/C# Data/Code status signal. Input local master cycles. Output master cycles.
M/IO# Memory/IO status signal. Input local master cycles. Output master cycles.
RDY# Non-burst ready. Output Input from local slave external cache controller
BRDY# Burst Ready. Output wjie^ajteve. Input from local slave external cache controller.
KEN# Cache Enable to-Us CPU. Always driven. Optionally inactive shadow RAM.
BLAST# Burst Last. (1ot$ ISAinaSter cycles.
EADS# invalidate cache floated wtenMocal lakes cycle (the local drives i)Lon fhfc VL-bus).
ISA-BUS
Signal Name
BALE 150- OutN^ ^Buffered Latch Eri*ble. Direct drive ISA-bus.
MEMR# Memory Read Strobe, Direct drive ISA-bus. Output when HLDA I^ifrwhen these both high.
MEMW# Mertitsry SVrit^ ^robe. Direct drive ISA-bus. Output when HLDA lo%. ffiput when these both high.
IOR# Rpad^trotr. 'Direct drive ISA-bus. Output when HLDA LGNT# lo^'r^put when these high.
IOW# I/Q^/nte strobe. Direct drive ISA-bus. Output when HLDA LGNT# j^FJiw. Input when these both high.
IOCHRDY ISA^bus ready Channel Ready). Output slave (DMA master accesses local DRAM local slaves). Input local master accesses ISA-bus (open collector).
0WS# ISA-bus zero wait state signal. ISA-bus slave will drive this signal when memofy command falls face wait state cycle. also used force 8-bit memory signal into wait state cycles.
MEMCS16# 16-bit memory indicator. Output master accesses local DRAM local slaves. Ii^nitfOT local master accesses ISA-bus (open collcrtar).
IOCS16# Input local master arccsses ISA-bus.
Revision Arfver Product Information CS4031
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CS4031 Descriptions 84031 Descriptions
ADDRESS
Input/
Signal Name Output Description
BEO# BE1# BE2# BE3#
Byte enables (BE3:0#). Input local master accesses ISA-bus. Output master cycles. Generated from SBHE#.
SBHE# ISA-bus BHE#. Output local master accesses ISA-bus. Input
master cycles.
Output local master accesses ISA-bus. Input
master cycles.
~95~
Local address (A9:2). Always inputs.
(Al&iAQ). Output forUteA cycles. A16.10 from latd^in 84031.
address AhraJ|jnputs.
LocA
A31). Driven master cycles.
LogKdLOR chip select 8042 chip select 8042 chip select
ROMCS# (8042CS#)
ports chip select programmable.
LDEV#
Device. local slave cache Controller drives this Signal
indicate will handle cycle. This signal sampled either thefiretorsecondT2.
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CS4031 Descriptions 84031 Descriptions
DRAM CONTROLLER
Signal Name
RASO#
Input/
Output Description
RAS1# RAS2# RAS3#
CAS0# CAS1# CAS2# CAS3# CAS4# CAS5# CAS6# CAS7#
each DRAM banks (RAS3:0#). Direct Drive.
CAS7:0#. CAS3:0# banks CAS7:4# banks Direct drive.
DWE#
DRAM Write Enablg. Ifrrfet drive banks!"
MAIO
MA11
DRAM address Direct drive banks.
'tt>
V-"'
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ance Product Information CS4031
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CS4031 Descriptions 84031 Descriptions
DATA
Signal Name
Input/ Output
Description
Local data (D31:0).
-Hfc DRAM {^jitjL bits XMP3S). Connected DP0:3 486. generates parity 'fefeeRit has1|k%ijs. local masters, cycles, masters, Parity checked 84031 cycles.
data (XD70). Connected directly 84035, BIOS ROM, 8042, fcECumd, thwjtehwi LS245, ISA-bus.
SDIRO SDIR1 Direction control XD7:0 SD7:0 (SDIRO) D15:8 SD15:8 (SDIR1) buffer.
SDEN# Enable. Connects enable D15:8 SD15:8 buffer and, through inverter, enables SD15:8buffer that normally low. Goes high local master high word writes ISA-bus. Then master reads from high word local DRAM local slaves.
ance Product Information CS4031
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WHIP'S) CS4031 Descriptions 84031 Descriptions
INTERRUPTS
Signal Name Input/ Output Description
IOCHCK# Channel Check (parity error indicator from ISA-bus). Generates sets IOCHCK flag.
Nonmaskable Interrupt request CPU. Generated parity errors when IOCHCK* gone low. Each these enable bits plus final mask
CONTROL LINK KEYBOARD
Signal Name Input/ Output Description
UN/TEST Control Link Input from Transfers following information: Refresh Request, Refresh Complete^^M I3MA Address Strobe. Test Mode input ^S*.)
LOUT Control Link Outprftothe 840$5raTransfers thejjS&ojwng information: Interrupt Acknowledge cySt Refresh Request Acknowledge, GATEA20 n^m^.teybpa^cantroller
GATEA20 GATEA2Q 8^3T^etect^a9sitions this transmitt^emio over conboljfrik.
KBRST# Keyboard 8042. 84031 sends code ac^|hfe inform of^is^he 84035 will perform
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Advance Product Information CS4031
CS4031 Descriptions 84035 Descriptions
84035 DESCRIPTIONS
functional descriptions 84035 listed below. overview signal names, 84035 Overview table pinout diagram.
CLOCKS
Signal Nunc Input/ Output Description
14MX1 14.31818MHz crystal input
14MX2 14.31818MHz crystal output
SCLK clock input Used arbitration logic, reset generation, selectively divided down make E^iA clock.
RESETS
Signal Name Input/ Output De^riptio^V
PWRGOOD Power jjfc^^-fton} tjjj^fc^er supply gytowSr-oncdear circuit.
CPURESET ResetlpTbe CTUltely. Synchroniz^to $<XK
SYSRESET Systeiu Reseti'i-aReset re4t system^ same timing only being low.
ARBITRATION
Signal Name No.\ Input/ Output description^'
HOLD Out, HoldRequftst (HgLEO CPU. Synchronous SCLK.
HLDA from CPU. 84035 assumes syndigeftwus
LREQ# .JLo^aJJbus Request from local mastere. more than LREQ* present, logic (from PAL) creates additional LONT# signals.
LGNT# Local^us tiranl local masters. This signal goes give control lo^f.b&nuster.
DGNT* Out5 controller Giant hold acknowledge. Indicates that controller master control bus. Used buffer steering goes 84031.
MASTER* master pulls this signal after gaining control through channel's DREQ/DACK* signals. When this signal goes output taken low.
REFRESH* ISA-bus Refresh signal. 84035 drives this signal during refresh cycles. During refresh cycles while master control bus, master drives low.
Address Enable. High refresh cycles, other times, including when CPU, local masters, masters have control Ins. main function this signal disable decodes system.
Terminal Count This signal goes high during final cycle transfer. used mainly floppy disk controller, also used other devices.
Revision Advance Product Information CS4031
JHfM BjPHgj"
CS4031 Descriptions 84035 Descriptions
ARBITRATION (continued)
Signal Name Input/
Output Description
DREQO Requests. DREQ3.0 8-bit channels. DREQ7:5 16-bit channels.
DREQ1 these channels used masters, except DREQ7:5
DREQ2 preferred because there less arbitration overhead.
DREQ3
DREQ5
DREQ6
DREQ7
DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# DACK7#
Acknowledge.
SLOW#
FLUSH#
ISA-BUS
Signal Name MEMR#
MEMW#
SMEMR#
SMEMW#
Turbo switch fast order J&acecai
slow, high
t^Jfrogrammed emi2%ierthe speed 8MHz jioUs Some softwar^pfftdations require certain speeds
ormance CotiM must programmed
shgukRbe connected ttir&e FLuSH* pin. used wwfte performaiK^prarol cache optimally isjftfcinte HQLDf^he register better control
Gbnnected directly ISA-bus. Output during times generate SMEMR#.
Sfcobe. Connected directly ISA-bus. Output during other times generate SMEMR#.
Rtsd strobe bottom 1MB. Connected directly ISA-bus. .all times. This signal function A23:20 MEMR#, those signals low.
Write strobe bottom 1MB. Connected directly ISA-bus.
Output times. This signal function A23-20 MEMW#, when those signals low.
IOR# Read strobe. Connected directly ISA-bus. Output during cycles. Input other times, access internal I/O.
IOW# Write strobe. Connected directly ISA-bus. Output during cycles. Input other times, access internal I/O.
IOCHRDY ISA-bus ready. Injwt during cycles wait states command strobes. Output during accesses controller registers optionally wait state.
RjvidonLO
Advance Product Information CS4031
Stmilb QQQbS3Q
CS4031 Descriptions 84035 Descriptions
ADDRESS
Signal Name Input/ Output Description
SBHE# ISA-bus byte high enable. Driven only during cycles. 8-bit (channels driven with inverse 16-bit (channels 7:5) driven low.
ISA-bus address bits Direct drive ISA-bus. Outputs during cycles refresh cycles. Inputs other times.
SA17
Local address bits Connected local bus. Outputs dunng
cycles. alrdtlier times.
ISA-bus address bitg/M;17. Btirect drive ISA-bus. Outputs times except maSter these fld&ted, These driven from
Local busaatkes bjt$. li|ij_7. Connected the-CPU local bus. Outputs during DMA<
drive SA19:17)*tfll
bocal>us 23:20. cycl^bated
5SP57
local bus. Outputs during
A20M#/TEST#
A20M# pin. This logical emulated keyboard#ATEA20 fast GATEA20 (port
input after reset. pulled low, the~84035 will ^x^into test modei becomeSthe A20M output after configuration been thatfbl*the driving ignoring input. puMip b^connected this prevent test mode from being entged high power
DATA
huiat}^ Name PrifeWption
Outputs reads internal registers. Also outputs pass A16:10 84031 start cycles. Inputs writes internal registers.
Revision Advance Product Information CS4031
semant GDDt,s3i
CS4031 Descriptions 84035 Descriptions
INTERRUPTS
Signal Name Input/ Output Description
IRQ01 Interrupt inputs 8259s.
IRQ03
IRQ04
IRQ05
IRQ06
IRQ07
IRQ09
IRQ10
IRQ11
IRQ14 IRQ15
FERR# (IRQ13) Floating-point Enor/Intp&fepf Request Dual function pin. Normally FERR# from arid goes internal coprocessor error logic. optionally cofftocessor error logicis external.
IGNNE# (INTCLR)
INTR
Ignote
IGNNE*
'Active high for, roTorJt&gi^s external.
Clear. Dual pin. Normally SPtJ from error logic.
fwJ/O
ports
INTERVAL TIMER DATE-TliflECy^^
Signal Name
61hfor
SPKR
Driven
Real clock input
ViS,.,.-i
Rtal^JnoLclock gKjfe crystal Output. ReaLTtme Qo&fower Strobe. This
high when speaker use. port
32KX1
32KX2
PSRSTB#
signal, when low, indicates that real
power. battery backup power, 84035 pins should
100K pull-up resistor capacitor.
CONTROL LINK
Input/
Signal Name Output Description
Control Link Input from 84031. Transfers following information:
Interrupt Acknowledge cycle, Reset Request, Refresh Request Acknowledge cycle, GATEA20 from keyboard controller.
LOUT
Control Link Output 84031. Transfers following information: Refresh
Request, Refresh Complete, Address Strobe.
Revision Advance Product Information CS4031
EQRftllh QQObSBE
dllrO _CS4031 Registers
CS4031 Registers
84031 84035 PORT SUMMARY Port Address 84031 84035 Description
controller (8-bit DMA)_
Interrupt controller (IRQ7:0)_
Configuration register address data port_
Timer (8254)_
data port_
Port
cornmand/stat6srpfrrt_
Real time clock addfl^ssport mask, (84031 write only)
Real time clock data^Sri
page register
Fast relet QATEA20
A0-A1 Interrupt;oi^trollgii6;4 jlRQ 15:8)
CO-DF DMA^^Uer^g (16-bit DMA)^
84031 84035 CONnGURATIi^l&ISfEftuMMARY^^
Index Register 84031 84035 Deagription_^
yJPC controUer waitstatasjadpek.
^'^SA command ftglays/-
ISA-bus wajt^tates, a<ktfesrjhold_
ISA-bus glock^lecti^n\
8_Vf Performaftoe contf6I\
MiBcell^feous-fcontrol_
OB-OF qa^tji
^^RAM^nmg
DJFA&jsfetup
configuration, blocks
configuration, blocks
block starting address_
block starting address_
block starting address_
block starting address_
shadow local control_
DRAM shadow read enable_
shadow write enable_
enable_
Soft reset GATEA20
Reserved_
20-2F Reserved_
Revision Advance Product Information CS4031
SCHflllb DDDbS33
CS4031 Registers 80431 Port Address
84031 PORT ADDRESSES
Listed below 84031 port addresses that described this section. (Figures provided registers, where applicable.)
Configuration register address data port
Keyboard data port
Port
Keyboard command status port
Real time clock address port mask.
registers specific 84031 summarized 84031 84035 Port Summary 84031 84035 Configuration Register Summary tables.
CONFIGURATION REGISTER ADDRESS PORT
Port Address
Write only port which holds address Chips Technologies, Inc. index register that accessed through port This register must written before each access port even same index register being accessed twice row.
CONFIGURATION REGISTER DATA Port Address
Port addles accesses configuration register that points4> ptNt second access port without wrjti^ifi between port will ignored.
JSteSprved" bits unpredictable read y^j^ frOT^ read theFor compatibility with
O'^^niture revisions anomalies, rresgFvaj3 bits should bise&o write left their Alwdt state writ^n%fth value read) unless
KEYBoXiCDD AJ;^ORT
Fast Reset function.
Revision
201011b DGObSBM
Advance Product Information CS4031
di'SIPsT
CS4031 Registers 80431I/O Port Address
PORT
Port Address Default
Toner gate
-Speaker data
Parity enable IOCHCK
Refresh detect
Toner output
Channel check latch
Parity error
This AT-compatible port with miscellaneous/"91^
information. Bits read/write. Bits r^d^J
only. Only bits 2,3,6, available 840f
remainder available 84035.
half bits comes from each chip.
Parity check latch.
clear flip-flop. IOCHCK sent active preset input. output logic. output sent flip-flop index register, where preset input flip-flop (ALS74 AT-compatibles) precedence over clear input precedence over
Enable parity check.
function. enables local DRAM parity checking. disables local DRAM parity checking clears local parity error flif^flop. inverted sent active Josyjreset input flip-flop. output logic. parity Verfror clocks flip-flop index register used block local DRAM parity errors, plus prevents flip-flop from being clocked, ^w^preset input "ftbm flip-flop (F74
over lear input pgjcedence over
a**, functidh. available 84835 with output (artieri verted) produce actual fignal swtt^to speaker. When gate (see Jjit^pjhis gives direct software control ofjJ^jpeaker. this SPKR output Hgnajfis unconditionally driven high.
^(iijjmer gate.
Timer speaker with function. (Bit contained 84035.) When this timer enabled programmed will produce square wave programmed frequency. When this interna] timer output read port will forced SPKR output signal, following table summarizes effects bits when Timer been programmed square wave generation.
Channel check latch
Read only. been activate from ab6ve.
Timer output.
Read only.
Read only. indicates that fecil^ari_
occurred. Q*TS0rtfMt roajd^"1 above.
Jidica^feat IOCHCKif^. is^e output result
(Bit also 84035.) allows output timer Timer with inverted, produces signal. SPKR output sigSal will when this
Refresh detect.
Read only. (Bit 84035.) toggles each refresh. should toggle whenever timer produces pulse about every 15ps). software this time delay.
Enable IOCHCK.
enables local IOCHCK interrupt. disables IOCHCK clears IOCHCK flip-flop. inverted sent active
SPKR
TOG#
Revision
Advance Product Infonnation CS4031
PCHflllb 000bS35
CS4031 Registers 80431 Port Address
KEYBOARD COMMAND/STATUS PORT Port Address
Used keyboard GATEA20 Fast Reset function.
REAL TIME CLOCK ADDRESS PORT MASK
Port Address
-RTC address
mask
/T^MlMask
ible interrupt mask.
^^^Reaj^rwaock address. a3so a^jjable 84035.
Revision
Advance laformfation CS4031
DD0b53b
CS4031 Registers 84031 Configuration Registers
84031 CONFIGURATION REGISTERS
Listed below 84031 configuration registers that described this section. (Figures provide registers, where applicable.)
ISA-bus command delays
ISA-bus wait state address hold
ISA-bus clock selection
DRAM timing
DRAM setup
DRAM configuration, blocks
DRAM configuration, blocks
DRAM block starting address
DRAM block starting address
DRAM block starting address
DRAM block starting address
Video shadow local control
DRAM shadow read niable
DRAM shadow write enable
ROMCS enable
Soft reset GATEA20.
registers specific 84031 wmmarizecfifr 84031 84035 Port Sumnj^Bd the^fesf 84035 Configuration
ISA-BUS COMMAND DELAYS
Index Register Default
6^0.5 fiOSCLK delay (default cycles e*Sfcpt 16-bit memory).
l^ROBUSCLK delay. fE^T.5 BUSCLK delay. write
16-bit memory command delay. Default
^tyk- 16-bit memory command delay. Default ^^13:2 8-bit memory command delay. Default MfeV cycle comman^ delay. Default
Revision
Advance Product Information CS4031
2CHflllb 000LS37
CS4031 Registers 84031 Configuration Registers
ISA-BUS WAIT STATES ADDRESS HOLD Index Register Default
ISA-BUS CLOCK SELECTION Index Register Default
Reserved
8-bit stale
16-bit wait state
Reserved -Address hold
ISA-bos dock
wait states defined BUSCLK excess two. Thus, wait states BUSCLKs total including cycle.)
address hold time.
Ready delayed extra t^AT
Clock sele&4Qg
Reserved
command goes inactive additional hol<f;t: Additional hc^fimife
Reserved. 16-bit states.
BUSCLK wait states (default)- BUSCLK wait states.
10:. BUSCLK wait states.^\^ 11:0 BUSCLK wait 8-bit wait states.
BUSCLK wait states (default). BUSCLK wait states. BUSCLK wait states. BUSCLK wait states. Reserved.
sou^jpf theifocKls CLK2. Internally, 84Q3Wa ctocfehlt BUSCLK rate. Xh^CPU parenthesis indicates which
C|ettirigs yield 8.33MHz BUSCLlTtate. selects prescaler divider divide Bits determine second stage divider.
0010: 0011: 0100: 0101: 0110: 0111:
1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111:
CLKIN/20
CLKIN/16
CLKIN/12
Reserved
Reserved
Reserved
Reserved
Reserved
CLKIN/10 (40MHz CPU) CLKIN/8 (33MHz CPU) CLKIN/6 (25MHz CPU) CLKIN/5 (20MHz CPU) CLKIN/4 (16MHz CPU) CLKIN/3 Reserved Reserved
Revision Advance Product Information CS4031
t>35
CS4031 Registers 84031 Configuration Registers
DRAM TIMING
Index Register Default
DRAM SETUP
Index Register Default
Read wait
Reserved
RAS-to-CAS read
RAS-to-CAS write
Write wait state
precharge
Reserved
Bank interieave Bank interieave
Bank interieave
Bank interieave
Reserved
Local DRAM parity
Reserved, write
Precharge Time.
states precharge
states precharge tjgfe.
Write wait states. Specifies DRAM page hits. >CL,>
wait state writes. puUi3^the middle
wait state writes. pulled first
RAS-to-CAS timing memory write cyQl^s^V
generated state after RASpifar write mode (default).
generated states
write mode.
RAS-to-CAS timing memory read ig^e
generated state aftel (default).
generated states after RAS.
Reserved, write
Read Timing Mode.
Fast mode; 3-2-2-2 page hits (default).
Slow mode; 4-3-3-3 page hits.
/T^able Local mtA^'parity.
V8*- Dtaj^V^.
Enable>- 3xpr^yides additional parity over above /Ufa* ^om^bit from port mu6sbelnabled (set port NMLmaSk must also send
^J^fo (I/O port
ReKftfed, write
J^jjterleave bank
Interleave bank
Interleave bank
Interleave bank
bank interleaved, address range doubled; active only when interleave (All A12) does comparison. Banks compare interleave banks compare banks must interleaved same address proper operation. more information proper interleaving, DRAM Controller section. interleave bank. Interleave
Revision
ECHflllb GDDbSa^
Advance Product Information CS40"1
S4031 Registers 84031 Configuration Registers
DRAM Index Register Default
DRAM
Index Register Default
Block DRAM
Reacrved
Block DRAM
Reserved
L.-,
Block DRAM
Reserved
Block DRAM
Reserved
Block uses RAS0#. Block uses
Reserved, write yVj1*'
Block DRAM type:
definitions same block
Reserved, write Cl/^^V*
Block DRAM type:
uses RAS2#. ^31qp)T3 uses RAS3#.
Reserved, vcrrteEO.
000: Bank disabled. 001: 256K
2S6K 010: dee]
block
type:
tions same block
011: deep^DRAMs
Reserved
Revision
Advance Product Information CS4031
SG^flllb 000bS40
CS4031 Registers 84031 Configuration Registers
DRAM BLOCK STARTING ADDRESS
Index Registers through Default
VIDEO AREA SHADOW LOCAL CONTROL
Index Register Default
-A20 -A21
-A23
Reserved
Starting Addresses
Index block starting address. Index block starting address. Index block starting address. Index block starting Reserved, write
A26:20 starting addresseswaaib.
Shadow Shadow
Reserved
Local timeout
Local aample
dD^rite protectjJbdt
Write protect mode
Write protect^ Wjite protect J58AM cached
l^JKWte pr^eejDRAM cached 486, l^Af)S#is generated writes.
EADS |enferafion local master.
floated when local master
bus.
EADSW driven when local master bus; EADS asserted during second memory write cycles (LBM, master, DMA).
LDEV# sample point.
first cycle. second cycle. This delays start ISA-bus accesses.
Local timeout.
time (default). Time enabled. (84031 generates RDY# fails within approximately SCLKs after claiming cycle.)
Reserved, write BOOOO-BFFFF shadow enable. Access goes ISA-bus Access goes local DRAM A0000-AFFFF shadow enable.
Access goes ISA-bus Access goes local DRAM
Advance Product Information CS4031
CS4031 Registers 84031 Configuration Registers
DRAM SHADOW READ ENABLE
Index Register
DRAM SHADOW WRITE ENABLE
Index Register Default
COOOO-C3FFF -C4000-C7FFF
C8000-CBFFF
CCOOO-CFFFF
D0000-DFFFF
BOOOO-EFFFF
PD000-FFFFF
Reserved
00000-C3FFF C4000-C7FFF
address range reads that memory/^fe location coming from ISA-bus. reads that memory location coming local DRAM.
duress range bifcisss^to writes memory IS^bus. writes
Reserved FOOOO-FFFFF EOOOO-EFFFF D0000-DFFFF CCOOO-CFFFF C8000-CBFFF C4000-C7FFF C0000-C3FFF
aory locati Reserve^
mfc&FR^Sr
pOO-E^F^
^il^OOO-CBFFF C4000-C7FFF C0000-C3FFF
Hevisic^
SORflllb
Advance Product Information CS4031
CS4031 Registers 84031 Configuration Registers
ROMCS ENABLE Index Register Default
SOFT RESET GATEA20 Index Register Default
00000-C3FFF
C4000-C7FFF
C8000-CBFFF
CCOOO-CFFFF
DOOOO-DFFFF
BOOOO-EFFFF
FOOOO-FFFFF Write
Reaerved
Reaerved
Emulated keyboard reset
Emulated keyboard GATEA20
Reaerved
address range ISA-bus reads/"^ /^Disables IO$#etto 8042 emulated from that memory location activates ROMCS#. W^commands.
Diaable 8042 IOW#
memory ROMCS# activate!^ Note: ROMCS# activated access ftjfcc&d local DRAM.
Activate ROMCS writes also^defojilt
Does activate writes?
commands 8042
X}AftA20 RESET2 commands haveWfr* blocked speed 7%>peraii0n 8042 commands.
Activates ROMCS# writtfcllhhe
addresses selectedby'lhe femai^derW this register.
FOOOO-FFFFF, deffcj^
E0000-EFFFF,feiult-
DOOOO-DFFFF, default
CC000-CFFFF, default ^^^uf1
C8000-CBFFF, default
C4000-C7FFF, default
C0000-C3FFF, default
RSen^^Vite
tSthe
emulation.
<f^0: emulated 8042 GATEA20 logic ignores 8042 commands. 8042 commands enabled emulated 8042 GATEA20 logic.
8042 RESET2 emulation.
Disabled
emulated 8042 KBRST# function will cause soft reset CPU.
Reserved, write function.
Test function (default). Link input (normal operation). Reserved, write
RESERVED WRITE) Index 1D-1F
Advance Product Information CS4031
SCHflllb Q00bSW3
CHSn^sT CS4031 Registers 84035 Port Addresses
84035 PORT ADDRESSES
Listed below 84035 port addresses that, described this section. (Figures provide registers, where applicable.)
controller (8-bit DMA)
Interrupt controller (IRQ7:0)
Configuration register address port
Tinier (8254)
Port
Real time clock address port mask
Real time clock data port
page registers
Fast reset GATEA20
Interrupt controller (IRQ15:8)
controller (16-bit DMA)
registers specific 84035 summarized 84031 84035 Port Summary 84011V 84035 Configuration Register Summary table^W
CONTROLLER (8-BIT DMA)
Port Addresses OO-OF
Port addresses through contained megacell. controller will respond accesses original AT-compatible, 00-0F repeats 10-IF.)
INTERRUPT CONTROLLER (IRQ7:0) Port Addresses 20-21
These potts contained megacell. Interrupt controller does respond ports 22-3F.
CQNFIGURATION REGISTER PORT
^AcLkess
isJ^PjSffte only pc^^vfechholds address Technologies.fci3ex register. register accessed port must before paji even same ^^Jndex register ik^ihg twice row.
Port Address
REGISTER DATA
m2|)Oft"Z3 accesses configuration register pomtetf^lijy port second access port lthotyVritmg port between will ignored. On^ri^;'Reserved" bits should written
value read back unpredictable.
TIMER (8254)
Port Addresses 40-43
These ports contained megacell. timer does respond ports 44-4F.
Revision
EGTflllb QD0hSH4
Advance Product Information CS40.
CHSn^sT
CS4031 Registers 84035 Port Addresses
PORT
Port Address Default
Timer gale Speaker data
Parity enable lOCHCK
Re&esh detect
Timer output
Chamel check latch
Parity check latch
This AT-compatible port with miscellaneous/^ information. Bits read/write. Bits re^^/ only. Only bits available 84035 Qri^w there read-back purposes only^^Tfe remainder available 84031. tyQrufythe 84035 drives bits their proper value^Qh^ bits
Parity check latch. .MiuiiL
Read only. not^MJable 84035 will driveMJ^oO will result
Channel check k^gKV^ ""S*^
Read only. available 84035 will drive will result from flip-flop
Timer output.
Read only. allows sgjpt: output timer Tubus? together with produces speaker
ignal.
Refresh detect.
This read only toggles each refresh. should toggle whenever timer produces pulse (about every This should done even refresh disabled. Seme software uses this time delay.
Enable IOCHCK.
enables local IOCHCK interrupt. disables IOCHCK clears IOCHCK flip-flop. inverted sent active clear flip-flop. IOCHCK sent aegve preset input. output J&wNMI logic. output sent ^TbeTlip-flop (ALS74 AT-compatibles) input precedence over clear input "^J) precedence over
parity ched^>
enables local parity checks. disables DRAALjgaftfy checks clears local parity errotf&^flog^Bft inverted sent flip-flop. logic. T^.OTOT^wfe flip-flop index iiter local DRAM parity mors. flip-flop from being clocked. flip-flopff*74 AT-compatibles) preset injSSFprccedence over clear input over
Weaker data.
fcV^ ANDed with output timer produce actual signal sent speaker. When gate (see this gives direct software control speaker.
Timer gate.
Timer speaker with function. When this timer enabled, programmed will produce square wave programmed frequency. When this timer output will high.
Revision
EGTfllAfc,
Advance Product Information CS40.
jQBg BBPHuP*"*
_CS4Q31 Registers 84035 Port Addresses
REAL TIME CLOCK ADDRESS PORT MASK Port Address
RTCadikecs
REAL TIME CLOCK DATA PORT Port Address
Reading writing this port will read write register pointed last occurrence write port
PAGE REGISTERS Port Addresses 80-8F
These ports contained megacell. accesses through A23.16. (A23.17 16-bit DMAs).
Port Addltes used. This port written
BIOS indicate BIOS status. pair
LEDs often placed test boards
4isplay BIOS information.
mask
"<Lj|art Addiate Channdjj page register, interrupt mask. register.
available 84035. SffcV
available 84031 write only. Bttj^jl* inverted ANDed with soufS* (the from several sources). Tsgftlt function CPU-^
Time Clock addre*^-7
Write only. values written becomes address .far RTQCM&S kAM.
register.
iwea. Port page register.
page register.
page register.
SSfrt?
P^Xddresses used.
^Piprt Address page register. This register
during refresh cycles.
ffcrt Address SA19-17
aW^'
Revision
Advance Product Information CS4031
CHSn^sT
CS4031 Registers 84035 Port Addresses
FAST RESET GATEA20 Port Address
Fasi react
FMtQATEA2QE
Reserved
ORed with other GATEA20 signals (fcpn?^p42, example).
Force from Cf%/fewnif^&r
other GATEA20s ardour
Allow from
INTERRUPT CONTROLLER (IRQ15:8) Port Addresses A0-A1
These ports contained megacell. interrupt controller does respond ports A2-BF.
CONTROLLER (16-BIT DMA) Port Addresses CO-DP
These ports contained megacell. Only even numbered ports used. Reads writes numbered ports will access same register corresponding even numbered port.
Reserved, write Fast GATEA20.
Fast reset. transition
Revision
Advance Product Information CS40.
BGTflllb 000b547 L4fl
CS4031 Registers 84035 Configuration Registers
84035 CONFIGURATION REGISTERS
Listed below 84035 configuration registers that described this section. (Figures provide registers, where applicable.)
wait state control
Performance control
84035 miscellaneous control
clock selection.
registers specific 84035 summarized 84031 84035 Port Summary 84031 84035 Configuration Register Summary tables.
WAIT STATE CONTROL
Index Register Default
dock select
MEMR signal extension
Sfc.
8-bit wait Mates
16-bit wait Males
Reserved
n^ma] timir^i*^ Reserved 16-bilE^fWait
'conmiUThe number wait states duj^g lo-bit transfers. tsbeWT SfeeVait state (default), tf^wo wait states.
>^10: Three wait states. Til: Four wait states.
8-bit wait states.
Bits controls number wait states inserted during 8-bit transfers. values below:
wait state (default). wait states. Three wait states. Four wait states. MEMR# signal extension.
PC/AT, assertion MEMR# delayed clock cycle compared IOR#. This desirable some systems.
Enables delayed MEMR# function (default).
Starts MEMR# same time IOR#.
Advance Product Information CS4031
EDSflllb
CS4031 Registers 84035 Configuration Registers
clock select.
allows user program clock operate either BUSCLK BUSCLK/2. same clock drives both 8-bit 16-bit operations.
BUSCLK/2 (default).
BUSCLK.
PERFORMANCE CONTROL
Index Register Default
hold
flush^i^
cadie flash
Doe^^Jfesh^cli
width
during slow mode
each slow mode hold this prevents ^186 tinning internal cache durire tffe slow mode hold.
enabled separate register switching
turbo button. values below
number BUSCLKs which kept hold. This occurs about every 15pS.
000000: hold request (default). 000001: Minimum speed reduction
BUSCLK). 000010: BUSCLKs.
111111: Maximum speed reduction (127 BUSCLKs).
Revision
Advance Urortuct Information CS4031
Ztmilb DOObSM^
CS4031 Registers 84031 Configuration Registers
84035 MISCELLANEOUS CONTROL Index Register Default
Deiinbo
protocol
Refresh enable
Reaerved
OATEA2(yTesf
8042 emulation
Keyboard interrupt mode
Floating-point mode
A20M#/TEST# LOUT enable function. Note: Index register should before setting this
A20M#/TEST#, when low, forces input signal 84035 into test mode. LOUT signal also floated allow 84031 signal used test mode (default).
A20M#/TEST# output signal, drives A20M#. Test mode disabled LOUT driven.
Reserved, write
Floating-point error mode.
internal (486) mode, FERR# IGNNE# pins provided. generated internally (default).
external mode, wjC?NTCLRk\-' pins provided. reaiainifef Hw^T logic provided extemally^Xtfis ntf&eis used systems wher^ppih forJR(3i3 required (e.g. sysftosWith ia~Weitek
coprocessor)-
Keyboard interruptlnijde. Bfe^duld
IRQ1 re&iyeii dftwpfri directly. IRQ1 reofeived over control
GATEA20 emulation disable.
A20M# controlled only^^ftart default. ^lbWingf^etT port bit^aWve .i^iis^ This causes A20M# to^ls TEST# input external pull-up keeps A20M# signal high state needed proper startup. A20M# port GATEA20 emulated 8042 GATEA20 information received across control link.
request enable.
blocks Timer refresh request when disabled. prevents reset problems, which pbCur when refresji'tequest generated during iftset sequenq^Spf 8254, timing /""^i&bled restl^
BlocJygj^TOnet refresh requests.
Enjs^8 Jimcr j^^esh requests.
Preejitot}ve pna|ol
OTLGNT'
/nD:^Kon-fm^mptive protocol. arbitration wili^riof take LGNT# inactive until gone inactive (default).
jtejfereemptive protocol. arbitration Nlogic will take LGNT# when controller requests bus. will wait LREQ# inactive before granting controller. This VL-Bus compatible.
Deturbo (performance control enable).
enables performance control that programmed into register This ORed with inverting turbo switch. Normal mode (default). Performance control enabled.
Revision Advance Product Information CS4031
0D0bS50
jpji jCCtSt^
_CS4031 Registers 84035Configuration Registers
CLOCK SELECTION Index Register Default
dock
Reserved
diable
disable.
Enable normal operation inti RTC.
Disable internal RTC. ThisjdlcJWs external used. 32&Hf mpu_ becomes IRQ8#. Ports 7(&Limft71h*re^ disabled, except porf7e^ijit IMfo*
Clock select controllers.
Bits this register normally should same value index bits 3:0.
optionally further divide this clock before sending controllers should programmed index 00). source clock SCLK, which clock. resulting clock should about 8MHz. megacell will then divide 4MHz used controllers. Higher rates used risk incompatibilities with devices. prescaler divider divide JiOTjiivideby Bits determines second ^^st^ge dividers, which is/2,/4,/3,/2.5,/2, or/1.5.
SCLK/10, SCLK/8"^>
sQJfet
Reserved
0010:
84031 (NMI control Reserved, write
1010:
SCLK/5 (40MHz SCLK) SCLK/4 (33MHz SCLK) SCLK/3 (25MHz SCLK) SCLK/2.5 (20MHz SCLK) SCLK/2 (16MHz SCLK) SCLK/1.5 Reserved Reserved
1011: 1100: 1101: 1110: 1111:
Revision
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PAGE(S) INTENTIONALLY BLANK
^Rr-
jmmbS
Advance Product Information CS4031
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CS4031 System Level Functions
CS4031 System Level Functions
overview system level functions 84031 84051 listed below.
Clocks
Reset GATEA20
Arbitration
Refresh
Coprocessor Logic
Address Mapping
ISA-Bus
Local Support
DRAM Controller
Data Buffers.
CLOCKS
clock provided 84031, which then crates clock with very skew. jtiari^stem^w these used system crocks back into 84031, with dvO^Sloia^J^
i;oing 84035 CPU. oading necessary, such devices
RESET GATEA20
reset GATEA20 logic available 84035. addition, CS4031 CHIPSet ability emulate reset and/or GATEA20 signals normally generated 8042.
84035 receives reset from power supply power clear logic. also receives restart command from 8042 emulation 8042) acrossjffie^ontrol link from 84031 from port fchi^h internal 84035. 84035 SYSRESET CPURESET. SYSRESET jPacthje only power pushing RESET goes^tive soft restarts
A2<Ms gated thc^OTi onjy. 84035 provides >4>3pM#, which of4he. port GATEA20 8042 GATlWaOr
UTior
ARBI
vhtsSps arbitration logic. .afbitiltes between CPU, local masters, DMA,
buffering, su^fe ha|f
SLSjSS i^ss^ Tfc. will
.len^Rhe
bus<fV
masters supported accordance
several clock generator chips such Avaieta 9155 "it. CD2027. clock sent 840^>haeVT request sent 84031, 84035,
following clocks used ttegy&tefh:
CLK2 clock AeS>RA&$*
Vfeus master when unmasked
occurs.
controller.
SCLK clock CPU, etc. 14.31818MHz timers
ISA-bus. 32KHz Real time clock.
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REFRESH
ISA-bus refresh done 84035. drives REFRESH*, MEMR#, SA7:0. Refresh always hidden. ISA-bus must arbitrated prevent 84031 from doing ISA-bus cycle same time 84035 doing refresh cycle. This handled control link. sequence follows:
When timer produces refresh request, 84035 sends REFRESH REQUEST code 84031.
LOCAL SUPPORT
CS4031 CHIPSet fully supports VESA VL-Bus. Both local slaves masters supported does require external logic single VL-Bus slot. Below brief description VL-Bus support. Refer Local section more details:
84031:
Samples LDEV# start each cycle (either first second allows local slave capture cycle active.
84031 will arbitrate this request with pending ISA-bus request from local master. When ISA-bus free available refresh sends REFRESH ACKNOWLEDGE 84035. 84031 will delay ISA-bus requests this point.
84035 will refresh cycle ISA-bus, then issue REFRESH COMPLETE code 84031.
84031 free ISA-bus access jfOh*' receiving REFRESH COMPLETE
Local DRAM receives timer tick refre^r??^. "RAM master refresh indicator from thexdtttrbl linluV 8403Ivantegrates high-performance DRAM
ti:.<
Transiges master cycles local wben LDEV# active.
ABows local masters access most system resources were CPU.
LGNT# signals local ^Sismasters.
DRAM refresh cycles then placed DRAM activity.
COPROCESSOR LOGIC^
controlfer fiiat.j^pp^rts page mode 2-way page DRAM controller supports ji^to four DRAM with mixing 256K,
dlwcfe. This includes DRAMs with <Sthet41/ll%r 12/10 row/column addressing.
pins directly interfaced local data bus.
FERR# IGNNE#. gfeefated intematiy. CAS#, DWE#, lines driven write ports clears interrupt from 84031 banks, with
/t^niaximum loads. additional banks, F244 buffers must used lines.
reads, page cycles perform 3-2-2-2 burst speeds. writes, page hits either
coprocessor logic js'iui^
ADDRESS MAPPING
Each chip decodes ports
registers used internally, memory local DRAM.
ISA-BUS
local master accesses ISA-bus handled 84031. 84035 slave that time. 84035 contains controllers, becomes master cycles, provides arbitration masters. 84031 slave that time, converts cycles local cycles local DRAM local slaves.
accesses.
DATA BUFFERS
Data buffering performed 84031. XD7.-0 generated 84031. These buffered LS245 form SD7.-0. SD15.-8 generated external buffers from either D15:8 1)31:24, appropriate.
Revision Advance Prod Information CS4031
sonant ooobss4
QH^jpg*
CS4031 System Level Functions
OJON
C3JC2IN
SYSRESHT
HLDA
PONTI
KXSRDY aws#
IOCS16*
IB-C LDEVf ROMCSMSOCCSt
BBOi bfiw
84031
SMR1-
OATRA20
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84031 Functional Descriptions
84031 Functional Descriptions
CLOCKS
84031 receives clock, generates BUSCLK ISA-bus. also contains optionally used clock divider which takes clock from oscillator provides skew clock system.
system where there additional clock loadings, such containing VL-Bus slots, CLK20UT SCLKOUT buffered externally before being used. Half F244 should used, with gate being used CLK2 other three gates SCLK. Care should taken avoid adding skew clocks.
Clock Divider
clock divider consists following pins:
CLKIN clock from oscillator. CLK20UT clock output. SCLKOUT clock output.
TJiis; circuit^completely independent from heaw to^nnections. clocks (i.e. CLK2 SCLK) used mtemally.^1
minimum systems CLK20UT SCXKQJTTJ pins used directly. CLK20UT will into 84031. SCLKOUT will feed back 84031 also feed into 84035 .CEU.
Clock ta^ts
8^031 lias clock inputs which follows:
'feOH clock. clgck.
"^^The follS^ihg clock connections
frtf
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84031 Functional Descriptions
14J181BMH*
aXlN QX20UT
saxour 84031
CLK2IN BUSCXX* SYSOX
HMX1 14MX2
84035
32KX1
32EX2
<b\cm
ax3n
saxouT
84031 CLEW BUSaXf
sysqx
14MX2
84035
32KX1
32SX2
VL-Bm
BA-Btu
SYSCLK
BA-Bas
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84031 Functional Descriptions
BUSCLK Generation
BUSCLK generated from divider from CLK2. divider produces clock used ISA-bus state machine which twice BUSCLK rate. following table lists dividers frequencies which will used obtain standard ISA-bus frequency.
SUGGESTED BUSCLK DIVIDERS EACH FREQUENCY
Divider CLK2 Freq. (MHz) Freq. (MHz) SUte Machine Rate (MHz) BUSCLK Rate (MHz)
16.67 8.33
16.67 8.33
power-up default divide which adhen changed BIOS appropriate valjie.
following table lists resulting ^UStlKjiate^ most common dividers CKferaW
POSSIBLE ISA-BUS CLOCK FREQUENCIES EACH FREQUENCY
Operating Speed
Selection 16MHz 20MHz 25MHz 33MHz
CLK2/1.5 10.7 13.3 16.6 22.2
CLK2/2 12.5 16.3
CLK2/2.5 13.3
CLK2/3 8.33 11.1
CLK2/4 6.25
CLK2/5 6.67
CLK2/6 2.67 4.17 5.56
14J18^Hz Clock
ThfcJ^035 requires 14Mhz clock input. Crystal pins clocks that 14.31818MHz. Each
bufiferigfl with cjriYerjir inverter form oscillation bus. pKin sSfies resistor should placed the^viis^ Place resistor Tiose
14.31AJ.SI form th^"09]
timers.^/
divided internally MH^joSc which used
^PWSfc
84035
14.318Mffig
20pF
14MHz Clock Circuit
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^"^ggjjjtg* 84031 Functional Descriptions
SCLK
SCLK, clock, provided file 84035. system, clock with skew clock must provided (this also required VL-Bus slots).
SCLK used arbitration logic, control link timing, generation clock controllers refresh logic.
controller together with refresh clock should configured approximately 8MHz. divided core obtain 4MHz controllers normally operate. following dividers provided from SCLK form clock. divider actually implemented selectable divide prescaler followed programmable divider 2,2.5, table 84035 Clock Divider.
32.768KHz Clock
clock source 32KHz internal oscillator use^f^, y^Hf
rl/v>V lUA^S ntwnal ncMttslAr
84035 CLOCK DIVIDER
Divider Pre-scale Stage Sill Clock Freq. (MHz) 8237 Clock Rate (MHz)
8.33 4.17
8.33 4.17
8.33 4.17
real time clock 84035. external oscillator used desired. that case, 32KX1 ai&put leave 32KX2 unconnected.
84035 32KX2
20pF?
Recommended 32KHz Clock Circuit Diagram
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^"^ggjjjtg*
84031 Functional Descriptions
SYSTEM RESET LOGIC
There input sources used initiate system reset, these PWRGOOD KBRST#. FWRGOOD reset usually provided power supply will activate CPURESET
SYSRESET outputs. KBRST# supplied 8042 keyboard controller emulated KBRST# function within 84031.
PWRGOOD 14MHz
RUNNING
SYSRESET PULL-UP:
SYSRESET
CPURESET PULL-UP.
CFUR5T
SCLK
BUSCLK
RUNNING
8042 84031
^JR^JMockK^wn^^
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84031 Functional Descriptions
Reset From PWRGOOD
84035 contains reset logic system. receives PWRGOOD reset request signals generates SYSRESET CPURESET signals. also receives soft reset requests over control link generate CPURESET.
PWRGOOD disables outputs gates inputs 84035 except PSRSTB, 32KHz oscillator pins, PWRGOOD itself. When PWRGOOD goes high outputs enabled. SYSRESET CPURESET driven high, remain high million SCLKs (0.24 second 33.3MHz) assure proper startup 14.31818MHz oscillator, allow stabilize.
84035 arbitrates between CPURESET HOLD signal prevent both from occuring simultaneously. currently HOLD when reset request occurs, reset delayed until after HOLD removed. likewise hold request issued during reset sequence, delayed until after CPURESET removed.
CPURESET SCLKs long soft resets. falling edge always occurs during phase while SCLK high.
SYSRESET
84Q3treceives SYSRESET input from 8403V ifris input resets registers state maclflnei known state. Since 84035 receives jjs^blpik from SCLK, which uses generate resets, ^^dock-divider circuit operates while SYSRESET
clock provided, 84035 determines phase SCLK, indicates this rest system generating SYSRESET
CPURESET. does based internal SCLK,
will make high transition reset/% TBo^HpCPURESETgpnd=A20M (final GATEA20 pins during phase when SCLK high. j%wU) pins areja^ifttble 84035. 84031 84035 determined phase, will this^ phase resets which occur after power-m.
84035 used 80386 system (nan-84031)4 flip-flop should used delay CPURESBf until state SCLK (phased
ides infomulSBfflo both functions, informatiife^ienu$'thi 84035 over control TTie following functions:
D&e^s detects a-^Pu reset request from external
SYSRESET generated from PWRGOOB^cSttiit /^8042vy
alone. CPURESET generated, feoii Optterifclly emulates 8042 reset
PWRGOOD, also generated "soft jequat.
resets." following arefhe sources, feft resets: change GATEA20 signal from
Keyboard controller reset
shutdown cycle
Port transitioning from
Keyboard reset shutdown sent,tti$i$ through control link from 84031 .Whenfiiie receives request, immediately pa^setfthe fittest logic that arbitrates CPURESET HOLD. Control Link sectiofi'for imOhnation reset request sent from 84031.
Pott available 84035. When makes transition reset requested about BUSCLKs later. This delay allows execute HALT instruction.
X^the external 8042. Optionally emulates 8042 GATEA20 signal
speeding operation.
Shutdown
shutdown detected (see "Special Cycle Encoding" table below). table also shows encoding "special" cycles. Only SHUTDOWN causes restart. 84031 transmits shutdown code 84035 soon detected. Then 1-wait state returned response special cycles.
SPECIAL CYCLE ENCODING
Cycle M/IO* D/C# W/R# Addren BE3:0# BE3* BE2# BE1# BE0#
Shutdown 00000000
Flush 00000001
Halt 00000002
Write Back 00000003
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84031 Functional
GATEA20 Function
84035 generates A20M#. actually does gating. There sources A20M:
Keyboard controller GATEA20
Port
keyboard controller GATEA20 information sent from 84031 through control link. GATEA20 GATEA20 codes sent across. This sets resets flip-flop form keyboard GATEA20 84035. This flip-flop powers high state allow boot.
Port output port internal 84035.
internal sources A20M# ORed together driven A20M# pin.
A20M# output shared with TEST# input. power this floated remains that until index register written This bit.-disables test input begins driving A20M#.^ Until external pull-up resiltpEs-keeps high, prevents 80435 from goir^intO test mode, holds A20M# high before C5*U allowed boot.
8042 KBRST# GATEA20 Inpyti-The optionally receives KBRST# GATEAlOtnpots from 8042. generates c^dixm
control link when KBRST# g6el^tew, amfigerierates GATEA20 codes each transition. informatic^ils sent thfe84035 where, arbitration C^UftESETtoghal performed:
Emulated 8042 KBRSt# reset GATEA20 functions normally ^oht 8042. issues commands manipulate these signals. 846&^cafi.JtM! configured monitor these signals jf^^sjmulate'tHV RESET GATEA20 functions* OptionfiUy^fhe commands blocked 8042% orciaijfetpeed operation.
commands written 8042 through address commands that affect GATEA20 KBEST# are:
Self test. KBRST# GATEA20 high.
Write output port. Next byte written port data. KBRST#, GATEA20.
Pulse output ports.
pushes GATEA20 high.
even command codes cause KBRST#.
commands optionally blocked from 8042.^he 84031 does this issuing IOW#. cohunands blocked. commands complicated follow these rules:
B3^6&mmands aret&ocked.
^^oiowing Dl^oriimand, next write port ^/^tiO blocke0:- another (non-Dl) command occurs befofejport 6GWwritten, next port write ifet WockriT
Fol&wfog* port write,
a6himtmd (filing port occurs maUs write^o^the keyboard controller, blocked^lso. multiple commands issua^gnly first blocked.
\tdll block three writes typical sequence, whjdi It^e follows:
^|^Write command port
Write data port
Write command keyboard controller detect when finished updating GATEA20.
GATEA20 KBRST# pins 8042 remain connected 84031 GATEA20 input when GATEA20 KBRST# functions being emulated. They will ignored when function emulated.
Revision Advance Procuct Information CS4031
^"^ggjjjtg* 84031 Functional Descriptions
ADDRESS MAPPING Addressing
accesses ISA-bus except cycles claimed local slaves. accesses 84031 84035 ports ISA-bus cycles. only decodes 84031 configuration registers internal pais. 84031 decodes bits address. 84035 decodes A9.-0. A15:10are decoded 84031. following ports decoded:
Configuration registers
8042 registers
Port
mask
Port
0000-00FF
internal decodes disabled when DGNT#
decode. also forces decode show alternate DRAM pages, other pages will presumably another DRAM bank.
shadow registers selectively disable DRAM 640- address range present (there will always memory present this range normal systems). default bits disables memory specified range. following ranges individually controllable:
These address ranges have which controls reads writes together:
Video graphics area Video text area
AOOOQrAFFFF
Thesfeaddress ranges have separate bits control reads
y^OcfogtoFFF /Video BIOS
_CjdSSPCTFFF j/TE&eo BIOS extension
MASTER* high, which indicates that (usually used)
controller bus. XS8000-CBFFF
ISCOOO-CFFFI^* DOOOO-DFFESlV
/ftBOO-FEFiiD
ptoteajjon since memory eiuier enaoiea
almost always disabled).
DRAM thfe GQ000-FFFFF areas often contain ROMs, which
Memory Addressing
Memory accesses DRAMs, locat^ftis. ISA-bus (including BIOS ROM).^v priorities follows: Vl.-^
DRAM
Local Slaves
ISA-bus.
Qther adapter BIOS (disk) adapter BIOS Miscellaneous V^often page frame) System BIOS extension (rarely used) page frame System BIOS.
Local slaves must aot.3^erla|&>cil DRAM thfe GWflO-FFFFF areas often contain ROMs, which memory there collistfeh. Normally- this./ when shadowed generally write
i-ty local slave. JSRAM ^protected. requires separate read write controls.
rthe^JStTwhen memory address falls into above Uhe^T ranges, appropriate shadow compared.
avoided local slave. controller takes soon thev address programmed This geimtty^i the^L middle first cycle. samples DRAM decode
either first secoBif^f2 cyfle^CiTis programmable). either low, RDY# were returned, ISA-bus state machine will ignore cycle. both high ready returned, cycle begins.
DRAM decode consists DRAM bank decodes shadow registers. shadow registers selectively disable DRAM decode 640-1M address range. DRAM decodes ORed together, then ANDed with disable signal shadow registers.
DRAM bank decodes consist starting address length, which comes from DRAM size interleave bit. interleave doubles size
DRAM decode forced inactive. DRAM decode from bank decodes allowed pass through.
ROMCS#
addition shadow bits, each ranges above COOOO-FFFFF have ROMCS# that enables ROMCS# signal those ranges. Motherboard BIOS then becomes available those ranges. only accessed cycle reaches ISA-bus. local slave DRAM controller takes cycle, will ignored. ROMCS# optionally activated write cycles addition read cycles order support FLASH ROMs. ROMCS will always activated memory space (FFFFOOOO-FFFFFFFF) provide reset vector. ROMCSW 8042CS# share pin, which
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^"^ggjjjtg* 84031 Functional Descriptions
DRAM CONTROLLER DRAM Configuration
Four banks DRAM supported time. Each DRAM bank following programming:
Bank size (256K, deep) Programmable starting address (A26:20) Interleave bit.
Each DRAM bank have different DRAM size. banks must have same DRAM size interleaving (see interleaving section).
starting address must bank size boundary, which means that largest banks lowest address order achieve linear memory map. following table summarizes starting address restrictions.
performance gain with single active since many cycles, which would page miss cycles, inactive cycles.
Multi-RAS multiple banks DRAMs have pages open simultaneously thus allowing page open page. When combined with page interleaving allows faster cycles when bouncing between several areas (code, data, stack instance) when looping across page boundary. Multi-RAS active automatic where possible 84031. RASes active only banks DRAMs have separate lines. When page opened bank DRAMs, currenfiy active bank will only high TCAS lines with
DRAM BANK STARTING ADDRESS
Multi-RAS active automatic. Page always used local master initiated
actif^is used where possible. ^Pa&fcajnUrieaving ist>cdntroiled DRAM Mf^gifrationbits.
CS4031 interleaving.
Programmed BoundAi^V^Tf1
Address Sfee banks UTterle^vM they same size
Bits rfacwnfe'nt artW^numb^gdbank other
od?l Wfffoeredtea^ak Interleaving
nonmtgpe^yihg rtSyJc* mixed, multiple sets banks irftttleived. examples below:
DRAM Bank
Depth Interleave Size
256K
A26:20
A26:2i
^yga
interleave doublfes decode size JtpanK causes appear alternate DRAM pa&sltiiy. Bank.3 **** interleaved with
Banks will appear even fcage^^Y anything.
Example
Banks have 2S6K deep parts interleaved with each other.
Banks 6^and have 256K deep parts interleaved with each other.
have parts, interleaved with
rvrihin'
while banks will appear dd^^unlb^Ad Pages-
DRAM Controller Page InterleavTO<|
84031 employs Page Mode, Page Interleaving, Multi-RAS active techniques. These three different techniques used independently together.
Page always used this chip accesses, both bursts between bursts. Page mode simply means keeping while reading writing multiple words within DRAM page providing only column address toggling CAS.
Page interleaving DRAM banks DRAM page boundary. This gains most advantage when used with multi-RAS active, also
Banks have parts interleaved with each other.
Example
banks have DRAMs installed. interleaving could done either following ways:
Banks interleaved Banks interleaved.
Banks interleaved Banks interleaved.
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84031 Functional Descriptions
following bank combinations interleaved:
Oand Oand land
interleave scheme used CS4031 CHIPSet designed very versatile user. When block interleaved, block decode doubled size. interleave (either A12) included bank decode decoded either depending bank number. This makes bank show every other page 4K). Page Interleaving Example figure shows what address bits used DRAM address, column address, bank decode, interleave bit. also shows interleaving structure banks DRAM, total DRAM.
Memory Address
algorithm below used auto-configure interleaving:
block same size
Program blocks same address both interleave bite, endif
block sane size.
Program blocks same address both interleave bits, endif
blocks same size neither have been interleaved above Program blocks same address both interleave bits.
ifcbljBcks same Bize Tie^her have been interleaved above
PageO 000000-0007FF
Page 00O80O-000PFF
Page 001000-0017FF
Page 001800-001FFF
Page4 002000-0027FF
002800-002FFF
Page 07P00&-07F7FF
Page 07F800-07FFFF
Bank
Bank
Bank 0r<Row
Bvkl.RoW'l
Bank^l,
1023 Bank (V&owi023
^023. BanJcJ, 1023
blocks same ggjiress sft^both interleave bits.
ianks differient&locks interleaved th^ttMting .^dresses
same
settingthd^terifea^bit both blocks. deptli nTuSt size order avoid gaps A^^amory'TOto. It's required that blocks ewth nutmwred numbered that ofii-will decdtje e&en pages (interleave decoded tqtfftaid decode pages (interleave -decoded both blocks were programmed numtefed, banks will overlap each other evds nages pages will left empty. both blocks were programmed numbered pages, tfia^posite true.
DRAM Hookup Bank Support
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^"^ggjjjtg* 84031 Functional Descriptions
Single Bank SIMM SIMMS
84031
ras3#
Banks Interleaved.
Bukt Interleaved.
DRAM Hookup Exampies
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^"^ggjjjtg* 84031 Functional Descriptions
DRAM Memory
power-up, DRAMs disabled appear memory map. BIOS will program DRAM controller that will build memory map. DRAM memory consists DRAM bank decodes with selectable areas between 640K removed. Address Mapping section further details.
DRAM Timing Modes
local protocol used DRAM controller accesses, including master accesses. 84031, ISA-bus logic treats DRAM controller local slave, latching data read cycles what RDY# received, passing device master.
DRAM controller configuration bits following:
Read cycle timing mode
Write cycle timing mode
RAS-to-CAS delay reads
RAS-to-CAS delay writes
precharge time
Delayed start reads
Delayed start writes. cases there
have same timing.
modes read cycles mode
4-3-3-3 mode bursts iSf^page hits^,* 3-2-2-2 standard mode, which wWks through 33MHz. (^tmT' DRAM Timing Diagrams.) "Vr"
RAS-to-CAS timing reads eitl0t^ states. both cases, row-to-columriWlteh fSf,. between fall fall, JI^RAS H^AS delay should according the^'U DRAM speed. following table afttide.
modes write cycles wait state wait state writes. With wait state writes, CAS# pulled middle
wait state writes pulled first This allows adequate setup hold times speeds. When local master bus, wait state writes forced, since 84031 must generate parity. wait state writes allow half state 84031
RAS-to-CAS timing writes either states. wait state writes, where pulled state boundaries, there actually state detofr. delay should accordihg^the speed DRAM speed. example; 33MHz/60ns DRAM 25MHz/80ns DRAM," lwait state writes RAS-CAS delays m^tfte recommended settings.
Timing Mode Requnmendations
.TPjfeK^onMnended D^AM timing mode given speed ORAM acto&s.time shown ^^able below. Tti^etore bske^iOti conservative worst case systeifL more
DRAM
SUGGESTED RAS-TO-CAS DELAY READ CYCLES
DRAM Maximum Recommended
Ttining Mode Speed DRAM Access Time
3-^-2Read/lT 25MHz 60ns, 20MHz 80ns
,3*4-2 Read/2T 33MHz 60ns, 25MHz 80ns
>-3-3-3 Read/IT 25MHz 60ns, 20MHz 80ns
4-3-3-3 Read/2T 33MHz 80ns
Write/IT 16MHz 70ns
Write/2T 16MHz 70ns
Write/IT 25MHz 60ns, 20MHz 80ns
Write/2T 33MHz 70ns, 25MHz 80ns
Precharge 33MHz 60ns, 25MHz 80ns
Precharge 33MHz 80ns
IriT Denotes RAS-CAS delay.
3-2-2-2 4-3-3-3 3-2-2-2 4-3-3-3 3-2-2-2 4-3-3-3
lfiMHz
20MHz
25MHi
33MHz
*60ns DRAM recommended.
Revision
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84031 Functional Descriptions
ADS*
KDY# BRDYi
RAS#
\ows 1WS7
COLUMN
D31K) (DRAM)
RAS-HI READ 3-2-3-2 MODE
WRITE MODE
DRAM Timing Diagram
ision
BO^fillt DDOLSbT
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84031 Functional Descriptions
COLUMN COLUMN
cas* ows^7"xrws7
DWE* LATCHED/
D310 (CPU)
D31K) (DRAM)
Mffl^V -LATCHED/ LATCHED
pCHig^^SRi, INVERTED /"""^i t^fa
Mflfeiffwtrre
CASONLY WRITE WRITE
read
mode, nos-burst
roLUMfO^LmiN XCOLUMN X~COLUMN COL. COL-
CAS* DWE#
D31K) (MAM)
7Y_/V_^r\_A_r
F"~"'l
LATCHED LATCHED LATCHED LATCHED FORCE HIGH LATCHED
FOLLOWS W/R*, INVERTED
<zxzxzxz>-
ADDR
D31:0 (CPU)
<nxz =)cz
D3io
CAS-ONLY BURST READ 3-2-2-2 MODE
PAGE-MISS READ (BEGINNING) ADDED TCLK'S
DRAM Timing Diagrams (continued)
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84031 Functional Descriptions
DRAM Address Multiplexing
DRAM address line multiplexing shown table below. column address same configurations. address will change depending DRAM size interleaving.
ADDRESS MULTIPLEXING
Column (All Size)
Addra
20,21,
Interleave bit:
Page Size:
Addrew for:
256K
tatrh*
clocking scheme which provides clock with little skew local device used. VL-Bus requires this clock clock with little skew also available motherboard non-VL peripherals which require single slot clock directly from 84031 used. multiple slots, clocks from 84031 should buffered before being used. this case buffered clocks used places avoid clock skew.
Support LDEV# signal allows local busslave claim cycle. timing rwpns each VL-Bus slot provides totem ^l^butput LDEV#, which ORed qgether with (for slots) sent LDEV# pin. single slot gating necessary. 84031 will sample LDEV# ftrchd either thliifst second each tart cycle, f^e^nled configuration
"5T-^ ^.register. it^Sgcw sample point,
-cycle will thfe ISA-bus. Note that
LDEV#$jgfi*l wilf frist'take cycle away from fonthiller unless "delayed
ton- intrlve
special case which will have and-K^cblumn addresses. A23, which prdvi^ed tiSWmn address repeated jp&aflows 11/1 12/10 addressing chijf%t& be^sfed transparently; even mixed.
Local Support
84031 fully supports VL-Bus Bus) both slaves peripherals provide much higher^wiuglW^Nfof devices such video, mass storagS^hd L^N?^(See VL-Bus Block Diagrams.)
VL-Bus standard from Video Electronics Standards Association (VESA). specifies standard interface, including connector, local slaves masters. Adapter cards expected video, disk, interfaces, well other applications.
following local support provided:
single VL-Bus slot supported with additional external logic. Some additional logic required multiple slots LDEV# signals provide additional LREQ# LGNT# pairs.
from tfce SRAM &ntfr>ller unless "delayed stafir^lttts ar^tel. Delayed start reduces Dfcj^W will rarely required.
Gwieratjiig'iocal control signals
Oand ISLA^Master cycles. During master iycles, LDEV# signal well internal local decodes checked addressed device local bus. A^If'it ADS# generated read write J^/the local device. data passed through 84031 and/or through 245s from ISA-bus. IOCHRDY pulled 84031 until local slave completes cycle. reads from local bus, data latched chip when slave generates RDY# held there until controller master takes command signal high.
Support local masters. 84035 provides LREQ# LGNT# signals local masters. 84031 handles cycles. These cycles handled same 486-initiated cycles with following exceptions:
Parity generated DRAM writes (the supplies parity when bus).
Writes forced wait state mode delay generating parity.
DRAM controller returns RDY# accesses since local masters accept BRDY#.
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^"^ggjjjtg* 84031 Functional Descriptions
EBE=>
VL-Bus Block Slot
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^^ggjhjjjjjj*
84031 Functional Descriptions
LDEVf
VL-Bus Block Slots With Single Master
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84031 Functional Descriptions
ISA-BUS
Local Master Accesses ISA-bus
cycles which claimed local slave DRAM controller ISA-bus.
ISA-bus runs clock which derived from CLK2. should normally about 8MHz, faster peripherals handle faster cycles. Clock section programming ISA-bus clock rate.
Master Accesses Local Slaves DRAM
When DGNT# goes active (for master cycles) 84031 becomes ISA-bus slave floating commands, local master driving local control signals. When master cycle attempts access device local bus, 84031 performs control signal/""^ translation data steering cycle. Local DRAM handled identically. folio' basic sequence.
default states:
When DGNT# goes low, 84($1
ISA-bus commands drives
neither decode active. IOCS16# driven. 84031 also drives BE3:0# from SBHE#, XAO, asynchronously.
further action taken this decode until command goes active, because known whether address I/O, memory, whether valid all.
command going active:
memory command goes active, decodes from local slaves DRAM controller checked immediately determine cycle locpj not. both decodes inactive cycl^fy gnored, except provide proper data when necessary. either active, ^Clg&DY pulled local cycle ^initiated.
aaj/Q command g$ae active, M/IO# must allow lcwafbus slave switch from memory dj^&e decode. decodg^jlTgo inactive when M/IO goes
states samf
igld/ipfeow, 84031 waits d&o^eHf low, IOCHRDY lately with command,
signals. default values
W/R#- D/C# M/IO# BLAST#-0
D/C# BLAST#Vwill
main
their
values entire time. W/R# M/lOfetf^fce changed according ISA-bus but^^y
will return default values During cycles (DGNT# high) M/IO# wifl always DM/fyO device will never locaHjuS.
ForWl cytfes data buffers turned /fft^und a&slcgtiils command received. During ^CMA^teigemoiy commands used data stegingSy
ForJw^-bus cycle:
"^^initiate local cycle, W/R# goes itilt read command goes active, remains high
write command goes active. cycles, commands ignored. ADS# then generated state.
default direction data drivers "writing" direction, they turned around when read command received. SDEN driven according XA1.
address decoding:
address from controller master decoded asynchronously local slaves DRAM controller. Local slaves drive LDEV# with decode result while DRAM controller provides decode internally 84031. 84031 drives MEMCS16# asynchronously either decode active. Since MEMCS16# open collector signal, 84031 floats when
write cycles, data being driven through 84031 245s. When local slave DRAM controller returns RDY, IOCHRDY floated controller master will complete cycle.
Read cycles more complicated. local slave DRAMs will float data soon returns RDY#. device master will read data until much later. 84031 latches local data clock edge where RDY# received, thai redrives data onto local bytes drives appropriate data bus. IOCHRDY floated when RDY# received. 84031 holds data until command goes back high.
Revision Advance Product Information CS4031
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CHIPS'
84031 Functional Descriptions
CYCLE DESCRIPTIONS
CPU/LBM Read Write Local Target
Local Master access Local Target. figure below shows write followed read cycle. cycle claimed local target. 84031 will sample LDEV# signal points diagram. sampling point changed point index register programmed. diagram shows wait state write, asserts LRDY# during same state (point which LDEV# sampled 84031. number states occur before LRDY# signal asserted.
CPU/LBM Access ISA-Bus
Local Master access ISA-bus. next figure shows typical access cycle, with sampling points some signals. 84031 will sample LDEV# point must high valid ISA-bus cycle. Point variable synchronization time. 84031 must synchronize with BUSCLK beginning cycle. This time minimum CLK2 cycles.
ADS*
D310
CPU/LBM Read Write Timing Diagram
QDQbS75
Advance duct In'orma'ion CS4031
^"^ggjjjtg*
84031 Functional Descriptions
CLK2 SCLK ADS# RDY# LDBV# BUSCLK BALE "CMD"
XAO, SBHE#
SDEN# MEMCS16* IOCS16# OWS#
jinruiiL j\r\j~
riniuuir
D31:0 (READ)
D31:0 (WRITE)
VARIABLE, MINIMUM REA^W^TO
-"V*
'0-e-9-e-
FROM
LATCHED
FROM CFU/LBM
CPU/LBM Access ISA-Bus Timing Diagram
Rev^onl.r Advance Product Information CS4031
SGTflllb DD0bS7L H^il
_84031 Functional Descriptions
refers command signal, IOR#, IOW#, MEMR#, MEMW#, SMEMR#, SMEMW#. timing signal programmable using index 06h. command delay shown point programmable. pulse width shown point also programmable.
MEMCS16# sampled point BUSCLK rising edge.
IOCS16# latched full BUSCLK after falling edge. This shown diagram point this case falling edge BUSCLK falling; IOCS latch point also BUSCLK falling edge. falling edge BUSCLK rising edge, IOCS16# latch point would also BUSCLK rising edge.
0WS# sampled each falling edge BUSCLK. sampled low, command ends BUSCLKs later exception would IOCHRDY also pulled same time 0WS#; this case 0WS#
SDIRO SDIR1 defaults high state; this directs data from bus. SDIR transition synchronized CLK2, will only state when data must driven from bus.
ROMCS# follows local address timing from LBM. access flash memory, ROMCSW must gated with command (MEMR# MEMW#). same ROMCS# used enable accesses keyboard controller gating with command (IOR# IOW#).
Interrupt acknowledge cycle follows 8-bit read timing. Except that generated extemaUjCand target 84035 bus. sartie programmable options apply timing th^cj^cle
^foC^RDY Operation
^kjhe t^wnf" diagrams following ^figyfSv IOCHRDY Effect Master Meiiwry Access, stio^-Vhen CS4031 CHIPSet
ignored. diagram shows normal cycl^lWf* IOCHRDY si^^L terminates point
terminated point
diagram shows 8-bit cycle'VrSh fep^ conversion cycle. delay from the, theirs* cycle beginning next fixg^MpT.5 BUSCLK, this shown point&tM.
cycle terminates with J^Y#%ignll minimum delay from falling edge RDY#, aneSEEK cycle.
Access
Local Bii^iget^^
DMAimd Memory Local Target Timmg Diagram Slows timing typical access (LBT) Master evice. TOeXBT will assert LDEV# decode rf*tdresS M/IO# point MEMCS16# assttte3?in response LDEV# signal 84031 will drive local status indicate
resynchronizationtim^L variable, -^ftfory data write. 84031 detects command
mmrnurn SCLK sothe maximun^l^ JOCHRDY low. 84031 could longer than SCLK from command point using SCLK,
generates local cycle starting with
output ADS# point terminates local
BCLK (INTERNAL)
BUSCLK
"CMD"
IOCHRDY (FROM ISA-BUS)
IOCHRDY Effect Timing Diagram (CPU/LBM Access ISA-Bus)
Advance Product Information CS4031
^"^ggjjjtg* 84031 Functional Descriptions
cycle when returns LRDY# which sampled point 84031 will release lOCHRDY point Master device will release command after IOCHRDY gone high. cycle read cycle, 84031 will maintain valid latched data busses until point
Master access local DRAM same sequence followed point Between points local DRAM cycle will occur. cycle dependent DRAM controller.
LCLK
A31:2
M/IO#
MEMR#, MEMW#
MEMCS16*
lOCHRDY
JP'JP
LDEV#
ADS#V
jtry
LRDY# RDYRTN#
D31K) (WRITE)
D31K) (READ)
SD/XD (READ)
SDIRO,
NEEDED MEMORY READ
(DONTi
Master Memory Local Target Timing Diagram
Revision
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Advance Product Information CS4031
2D1flllb
84031 Functional Descriptions
Master Access Local h-js Target
diagram below shows Master access Local Target (LBT). sequence similar that access memory, with some exceptions. memory device assert LDEV# signal point cycle generates command point 84031 will pull M/IO# causing memory device raise LDEV#
84031 will deassert signal. 84031 will synchronize full LCLK cycles, points then pull IOCHRDY low. After LCLK cycle, point 84031 will generate ADS# start local cycle. cycle terminates when LRDY# sampled point 84031 will release IOCHRDY. Master will release command point
LCLK
A31:2
MAO*
LDEV*
IOCHRDY
ADS*
LRDY*.
D31K) (WRITE)
D31K> (READ)
SD/XD (READ)
_Ti_rLrLn_^rLr
,0\0V
\-i*^
s^!^
low* V^-A-f
'V*'
(^ISAMasterV^Aa^stoLB^^
-<z>-
NEEDED READ
(DOfW
Revision Advance Product Information CS4031
DDDb57^
84031 Functional Descriptions
PORT LOGIC
Port port address 0061. controls miscellaneous things such parity, speaker, etc. Bits read/write control these functions. Bits read only provide status information. These bits split between 84031 84035 shown table below:
PORT BITS
R/W, Chip Function
84035
Timer gate (speaker timer enable)
read command timing used take low.
default direction master cycles (DGNT# low) low, which drives data from turns around (goes high) following times:
reads from DRAM local slaves.
master reads from DRAM, local slaves, peripherals.
8-bit reads from byte 16-bit memory slaves.
master writes byte 8-bit
84035 Speaker data
84031
Enable parity check enabled)_
84031
Enable IOCHCK enabled)
84035 Refresh detect
(toggles each
84035 Timer _(monitor speaker
84031 Channel check (status IOCHCKJV Pari chw-Hik-' jf*.
IfrfrSDlRl signal:
i^re=default when local masters have
_(DGNT# high) high, which drives data from
tQ^J^It turns aroimdjgpes low) following
Read cycle* bus, reads (RQMj 804^^035, internal 84031 ert^^ I/O). interrupt
84031
Parity entSffiitus).,
SDIRiifiusf golygh^ith command allow buffets tuhn^&n cycle give
TTfe?- defaultdlrection master cycles
(DGNT#jbw) low, which drives data from 84035 latches bits turns around (goes high) following cycles drives bits drives (IniesT bits 1*031 latcfftfbits writes. read since theXD through chip, receives bus, usesfot*-f:0
from 84035, replaces with internal data before sending
DATA BUFFERS
data buffer external logic consists three F245s, SD7:0, SD15:8. These controlled SDIR0, SDIR1, SDEN# signals. These signals generated follows:
SDIR0 signal:
default when local masters have (DGNT high) high, which drives data from turns around (goes low) following times:
Read cycles from bus, reads (ROM, 8042,84035, internal 84031 I/O). does interrupt acknowledge cycles.
reads from DRAM local slaves. master reads from DRAM, local slaves, peripherals.
8-bit writes byte 16-bit memory slaves.
master reads from byte 8-bit slaves.
SDEN# signal:
SDEN# determines which enabled. enables D15:8 SD15:8 buffer while enables D31:24 toSD15:8 buffer. This mostly determined XA1. exception this following cases, where always low. This high speed byte swap.
8-bit write cycles.
master reads from (not local slave DRAM).
Revision Advance Product Information CS4031
acnaiib 000^500
JggahtF"'
_84031 Functional Descriptions
CONTROL LINK
control link mechanism pass information between 84031 84035 using minimum number pins. Both chips have LOUT pin. LOUT chip connected other.
"When PWRGOOD low, 84035 LOUT high impedence state 84031 test mode enable input. external pull-up resistor required 84031 prevent 84031 from entering test mode during reset.
Control Link From 84035 84031
following information must sent from 84035 84031:
Refresh Request Occurs only when DGNT#
high (CPU local master bus). Same above. Occurs only when DGNt#; MASTERW high (DMA cyclep^,. Occurs only when MASTER* (ISA :;Ss master has\hebus).^
Control Link From 84031 t^the 84035
Several pieces informationjnust from 84031 84035 thipgWo^dccj^simtiltaneously. These follows
Refresh address Strobe
Master refresh
Hidden Refresh Acknowledge GATEA20 GATEA20
Occurs drily when DGhfof
high.
Could happen tfme.< Could happen iime^
TEST MODES 84031 84035
There several test modes help testability systems using 84031. Both parts have connectivity test mode that initiated following steps:
Start with PWRGOOD initialize chip raising PWRGOOD keeping high.
test mode entered pulsing A20M#/TEST# 84035.
While TEST# test mode code presented XD7:0 pins. This data latched rising edge TEST Csi^uil. Test Mode Code
tjiis mode pins 84035 internally chained together by.A, series gates. (esfiTpin goofliolder connection, pull high stale. -Che output chain SPKRrijnr^This will high state. Pulse each prniow oriie^a time SPKR shouldalste state, there cotfiniiity. Thflre-are some pins that incradeSin chain cannot tested this
OWay They %i^as follows:
T4MX1
.4TA20M#/TEST#
yWRGOOD "32KX1
Interrupt Acknowledge Occurs only DGNT#
high.;.
Soft Reset Request Could happen atahy ^ime.
These events communicated 3-bit codes sent serially from 84031 84035. Each code preceded start bit. more stop bits occur between successive codes. sent during each SCLK cycle.
32KX2
test mode exited methods
Pulse PWRGOOD reset system.
Enter Terminate Test Mode Code XD7:0 pulse TEST pin.
Terminate Test Mode Code
Advance Product Information CS4031
flOb
^""I^ggjjjljgj^*
84031 Functional Descriptions
84031 several test modes. There solderability test similar that 84035 there high impedence mode where output pins high impedence state.
Start with FWRGOOD initialize chip raising PWRGOOD keeping high.
test mode altered pulsing 84031.
While test mode code must presented XD7:0 pins. This data latched rising edge signal.
Test Mode Code
this mode pins 84031 internally chained together series gates. test good solder connection, pull pins high state. output chain ROMCS pin. This will state. Pulse each time anda.^ ROMCS should also changed tcH&Jov* state, there continuity. There somfepins that included chain tested this way. They fcdlowst
SYSRESET
test mode ex^eaby tw*Jneinods.
Pulse PWRGOOJaj^ resetted
Enter TefininAte Code XD7:0 pin.
Terminate Test Mode Code OOjv^/Sfe
"SS?*
order have output pins m^nijgh impedence state same pro&9vre shJHrld followed, using test code XD7.0 rising edge pin.
Revision
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_84035 Functional Descriptions
84035 Functional Descriptions
84035 82C206 with additional logic added reduce signal chip count external logic. following features added '206 create 84035:
14MHz crystal circuit divider.
clock divider from SCLK.
System reset logic.
System arbitration logic, including support local masters.
ISA-bus hidden refresh logic.
Performance control logic emulate AT-compatible.
controller address generation logic.
A20M# generation.
floating-point error logic.
Speaker logic.
Control link logic comrnunica^wjth chip set.
84035 suitable (non-84031) well 80486 sy^t|m|J
CLOCKS There three clock fteqyi
s^^ms
84032^
14.31818MHz firflhe timer chip.
SCLK related function&anl generate DMACLK.
32KHz real time clock. 14.31818MHz Clock
Crystal pins provided 14MHz clock? 20pF capacitors should included from each crystal ground well resistor used across crystal pins. should buffered with driver inverter form oscillation bus. series resistor should placed between buffer bus. Place resistor close buffer possible.
14MHz clock divided internally form 1.19MHz clock used timers.
SCLK
SCLK, clock, provided 84035. system, clock with skew clock must provided (this also required VL-Bus slots).
SCLK used arbitration logic, control link timing, generating clock controller refresh logic.
ZfMA^con troll refresh clock should arourt^jSMHz. divided core Obtain 4MHz which controllers y^onriaUybperate. following dividers provided \lom form theTJE|A clock. divider
O^actttaily Implemented, selectable divide ntelcaler followed b^.a^Pbgrnnmable divider 2,2.5,
84035 CLOCK
JMiader mxfc Stage Freq. Used (MHz) Clock Freq. (MHz) 8237 Clock Rate (MHz)
8.33 4.17
8.33 4.17
4.17
32.768KHZ CLOCK
clock source 32KHz external internal oscillator that must made from battery when power from turned off. used real time clock 84035.
Revision
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Advance Product Information CS4Q31
CHIPS'
84035 Functional Descriptions
RESET
84035 contains reset logic system. receives PWRGOOD signals generates SYSRESET CPURESET signals. also receives soft reset requests over control link generate CPURESET.
PWRGOOD disables outputs gates inputs chip except PWRSTB#, 14MX2, 32KHz oscillator pins, from PWRGOOD itself. When PWRGOOD goes high outputs enabled. SYSRESET CPURESET driven high, remain high million SCLKs assure proper startup 14.31818MHz oscillator, allowthe stabilize. This accomplished 23-bit counter clocked SCLK.
SYSRESET generated based PWRGOOD circuit alone. CPURESET generated based PWRGOOD, also generated "soft resets". following sources soft resets:
Keyboard controller reset
aOtqa
internal sources A20M# ORed together driven A20M# pin.
A20M# output shared with TEST# input. power-up, this floated remains that until index register written This disables test input begins driving A20M#. Until external pull-up resistor keeps high, prevents 84035 from going into test mode, holds A20M# high before allowed boot.
shutdown cycle Port transitioning from;
Keyboard reset shutdown sent
through control link from 840j,L^WhrnMhe 84035 receives request, immediately pgssjOie request onto logic which arbitrates CPURjEsET with HOLD. DRAM COTtrdpeM^ontrol Link section information thetcset request sent from 84031.
ARBITRATION
ariutt^ion logic system contained 8403$. arbitrates between CPU, local maktfSTand internal controllers. also puts ^jfiySPUitj HOLD slow down when performance arbitrat&btttween HOLD TCPPR^SET, arbijrt&s between hidden i$|jiish-
following alfeWthe arbitration block: HOLD aSf^/ifopfre
local masters controller
asters anatne
Port contained $j%84035. When make^T transition reset requested alggut BUSCLKs later. This delay allows HALT instruction. ^-^V
CPURESET SCLKs long soft-^Rs/^pV falling edge always occurs during phas^srhile^yC ishigh.
GATEA20
84035 generates A20M# signal. actually does gating. keyboard controller GATEA20 port sources that generate A20M# signal.
keyboard controller GATEA20 information sent from 84031 through control link. There GATEA20 GATEA20 codes that sent across. This sets resets flip-flop form keyboard GATEA20 84035. This flip-flop powers high state, allow boot.
Port output port internal 84035.
arbitration between local
_DMA controller. gets
Otis when other master wants arbitration pertfbrlfred using SCLK, signals icrironous
Qiere fixed priority activity. priority follows:
controller
Hidden Refresh
Local Master
CPU.
Note that either local master have control when hidden refresh occurs. Hidden refresh listed above because occur when controller bus; lower priority. instance, controller requests hidden refresh request occurs before local master gives bus, hidden refresh will delayed until after controller gives bus.
Hidden refresh arbitrated with controller, since these must mutually exclusive. hidden refresh occur while local control refresh arbitrated
Revision
eOTfillb 000fci5A4
Advance Product Information CS4Q31
CHIPS* 84035 Functional Descriptions
with HOLD signal. will reset while hold.
LREQ# LGNT# signals support preemptive protocol VL-Bus masters. HOLD occurs while Vl^Bus master bus, LGNT# driven back high, requesting that local master give bus. local master will take LREQ# back high indicate that given bus.
performance control HOLD request ORed with other sources HOLD, does enter into arbitration. cycle master gain access during performance control HOLD without waiting finish.
84031 receives HLDA, DGNT#, MASTER# signals indication what device control bus. encoding follows:
OWNER INDICATION
Owner
HLDA DGNT# MASTER*
(Invalid)
(Invalid)
(Invalid)
ISA-Bus Master
Controller
(Invalid)
Local Master
major functions Controlled artyffa^i^ir signals follows:
84031 does generate pantylfer writes DRAM, does for. rbcafe^iastt^. masters (HLDA^sd sefec|).T
DRAM write cycles for&g!?o WSft^tate when local master (<3t)fc extra time required generate parity).
control link functions change (particularly 84035 84031 direction) with DGNT#.
When DGNT# high, 84031 local slave ISA-bus master. ISA-bus cycles generated response local activity.
When DGNT# low, 84031 local master ISA-bus slave. Local cycles generated response ISA-bus activity.
When DGNT# MASTER* high, 84031 drives A16:10 with contents latch.
PERFORMANCE CONTROL
Performance control refers slowing down. execute code rapidly some speed sensitive software. 84035 makes attempt reduce speed clock since cannot handle rapid frequency change. Instead puts hold programmable parentage time. This implemented follows:
every refresh request HOLD programmable period time. FLUSH# also pulled during this time make sure doesn't continue internal cache. length ^jOLD pulse selected provide !e$ired degradation performance. intent match speed 8MHz order ^s^/ allow some games copy protection programs taswfcrk properly.-^PFhe FLUSH# HOLD Wuhetions may,'be,gabled separately, SLtJ^neraHy these Wilfbe used together. After x,^t/HOLD ength'is set.'the slow mode enabled ^isabled^|yv either ways: IndexjegSfe- acc&s "slow" input. This
iunctW^iillowing either these ddw^ihe tSown (these both should forfufr speed).
e|The generated
controllers used time base performance control. This clock normally 8MHz. always given small slice time between performance control 7^-^HOLDs even count above time between refresh periods.
HOLD initiated each time refresh request occurs from timer Local master, DMA, master, refresh cycles occur while performance control HOLD taking place.
Advance Product Information CS4Q31
84035 Functional Descriptions
REFRESH
refresh function involves both 84031 84035. refresh arbitration must coordinated between chips with 84035 performing refresh cycle. drives SA7:0, REFRESH*, MEMR# directly. SA7:0 refresh address ISA-bus REFRESH* MEMR# signals indicate 84031 that this DRAM refresh cycle.
refresh mechanism starts with 84035. When timer produces refresh request, internal logic 84035 must arbitrate with controllers before refresh request code sent through control link 84031. When hidden refresh wins arbitration, LOUT pulled low, indicating refresh request 84031. (When DGNT* high, LOUT used only hidden refresh). 84031 will arbitrate this with local master accesses ISA-bus, send refresh grant back 84035.
MEMR# SMEMR#. 84035 also pulls LOUT duration REFRESH* active indicate 84031 that refresh occuring. 84031 will this refresh local DRAMs. 84031 knows this master refresh hidden refresh request looking DGNT# MASTER* pins.
84035 will drive both MEMR* SMEMR* refresh cycles, regardless address upper bits (for normal cycles SMEMR* only driven when A23:20 low).
ISA-Bus Refresh Cycles
refretfi cycle starts point when 84035 received ^Refresh Acknowledge code from 84031 vi^tlfcLBi/LOUT control link. falling edge opriurtiid point BUSCLK cycles from point Jfeytt point IOCHRDY signal sampled, will endatD BUSCLK cycle later.
This will encoded come pin. this/-^Tlf IOCHRDY thptaffltiand will extented.
point 84035 will perform refresh cycle. When!/ refresh cycle complete, 84035 will l^Rfe^, LOUT back high, indicating refretfv%> 84031. After LOUT goes high, HLDA tojheDMA controller active. There should b^jkt
clock between LOUT going high controller going active.
Ethe REF* sigplj^elminates refresh raises signtf[to indicate '"-e^imingon following
84031 contains DRAM controller, refresh requests, both Wddeiftefresh^d faster refresh, will perform J>efore refresh DRAMs. places thejrStesn cy<^Jbeftveen other DRAM activity. CPuW&ve^iHiia HOLD stati^ specifically refresh
master refresh arbitration need done current master requesting refresh. master pulls REFRESH* low, 84035 piyfarqte tjie refresh driving SA7:0 with drntet,.
DRAMRef,_T
These ^viai^hjoden refresh cycles; there DRAM refreshes RASstCfresh cycles. hidden refresh cycle immediately RDY* from cycle, anytime after RDY* before the'end next ADS#. RAS* CAS* signals high cycle. Once hidden /refresh cycle begins CAS* RAS* signals
fall staggered timings, cycles apart. fcfV last RAS* fall cycle time.
Revision Advance Product Information CS4031
Stmilb OOQbSflt.
ggybiF"*
Chira
RAS# DWE* ADS* SDY*
REF#
MEMR#, SMEMR*
KXHRDY
SCLK
LOUT
SA7K),
^-JssSr-^
MASTER*
LjC-iV
BusRefresh Timing Diajp-am
20R3TCLK
DRAM Refresh Timing Diagram
Revision Advance Product Inform ition
EO^flllb QQDbSfi?
CHIPS*
84035 Functional Descriptions
ISA-BUS
This section describes generation usage ISA-bus control signals 84035.
signal:
This signal high when DGNT* MASTER* high. always output. Internally disables d
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