WAR.P. WEIGHT ASSOCIATIVE RULE PROCESSOR ADVANCED DATA
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SGS-THOMSON
WAR.P.
WEIGHT ASSOCIATIVE RULE PROCESSOR
ADVANCED DATA
High Speed Rules Processing
Antecedent Membership Functions with Shape
Rules Antecedents, Consequent)
Input Configurable Variables
Membership Functions Input Variable
Output Variables
Membership Functions Consequents
MAX-DOT Inference Method
Defuzzification chip
Software Tools Emulators Availability
100-pin CPGA100 Ceramic Package
84-lead Plastic Leaded Chip Carrier package
GENERAL DESCRIPTION
W.A.R.P. VLSI Fuzzy Logic controller whose architecture arises from need realizing integrated structure with high inferencing performances flexibility. those results modular architecture based parallel memory blocks been implemented.
orderto obtain high performances W.A.R.P. uses different data representations during various phases computational cycle, that always operating optimal data representation. vectorial characterization been adopted Antecedent Membership Functions. W.A.R.P. exploits SGS-THOMSON patented strategy store AntecedentMembership
CPGA100
Figure Logic Diagram
PLCC84
MCLK
W.A.R.P. OCNTO-OCNT3
EPA0-EPA2
PRST
Table W.A.R.P. Configuration Settings
Number Inputs Configurable [1.8]
Standard Rule Format Antecedents, Consequent subsets]
Rules Number Rules Antecedent, Consequent format
Antecedent's Number Configurable input variable]
Consequent's Number outputs variables
Input Data Resolution,
Output Data Resolution
1QQR 7121237 007720A 35fl
1996_1/19
This advance information product development undergoing evaluation. Details subject change without notice.
W.A.R.P.
Figure CPGA100 Configuration
PRST OCNTI OCNTO
OMIS
MCLK OTST
VDD# S^JC
EPA0EPA2A7
VDDEPA1
910111213
Table Absolute Maximum Ratings
Symbol Parameter Value Unit
Supply Voltage -0.5
Input Voltage -0.5 Vdd+0.5
Ouput Voltage -0.5 Vdd+0.5
Output Sink PeakCurrent
Output Source PeakCurrent
Topt Operating Temperature
Tstg Storage Temperature (Ceramic) +150
Storage Temperature (Plastic) to+125
Notes: Stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device.
These stress ratings only operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also SGS-THOMSON SURE Program other relevant quality documents.
7TE1E37 Q0772CH
W.A.R.P.
Figure PLCC84Pin Configuration
CT*?QCOQ_CLQ.Ln(Or-~-CDO)QCO <<>>LiJUJLiJ<<<<<>> nnnnBnnnnnnnnnn
vssC
vddC
mclkC
SYNC
OTST
omtb
W.A.R.P.1.1
chmC OCNT3
finC OCNT2
oflC OCNT1
prstC OCNTO
mteC
vssC
vddL
uuuuuuuuuuuuuuu
OOOOcoOOOOO
Table Recomended Operation Conditions (Ta=0 unless otherwise specified)
Symbol Parameter Unit
Supply Voltage 4.75 5.25
Input Voltage
Input Voltage
Ouput Voltage
Ouput Voltage
FCLK Clock Frequency
Output Load Capacitance
3/19
W.A.R.P.
Table Description
Name Pins Type Function
Power Supply
Ground
A0-A9 Memory Address
I0-I7 Data Input
PRST Preset
First Input Signal
Off-Line/On-Line Switch
Charge Mode Switch
Testing must connected Vss)
Testing must connected Vss)
MCLK Clock MHz)
EPA0-EPA2* EPROM Address
00-09 Defuzzified Output
OCNTO-OCNT3 Output Counter
Strobe (Output Ready Signal)
Process
Process
OTST Testing must connected Vss)
OMTS Testing must connected Vss)
SYNC External Synchronization
Pins used W.A.R.P.
Functions dedicated memories orderto reduce computational time. Therefore great amount W.A.R.P. processing based look-up table approach rather than on-line calculation.
Those Membership Functions (MFs), each portrayed configurable resolution elements, stored four internal RAMs Kbyte each). consequent MFs, different modelling, loaded single storing each area barycentre. This adoption Center Gravity method.
downloading phase allows setting device, terms number, universes discourse shapes. During this phase W.A.R.P. prepares internal memories on-line elaboration phase loads microcode program memory. This microcode, which drives on-line phase, generated Compiler (see W.A.R.P.-SDT User Manual) according adopted configuration. possible configurations shown table
During on-line phase 40MHz working frequency), W.A.R.P. processes input data produces outputsaccording configuration loaded downloading phase.
W.A.R.P. conceived work together with tradi-
tional microcontrollers which shall perform normal control tasks while W.A.R.P. will indipendently responsible fuzzy related computing.
W.A.R.P. manufactured using high performance, reliable HCMOS4T (0.7|im) SGS-THOM-SON Microelectronics process.
DESCRIPTION
Vdd, Vss: Power supplied W.A.R.P. using these pins. power connection ground connection; multi-connections necessary.
A0-A9: When they accept input addresses internal memory bus. off-line mode they used address W.A.R.P. memories where microprogram data antecedentand consequent membership functions must loaded.
Each A0-A9 word composed assembling data contained memory support related .add files (see W.A.R.P.-SDT User Manual). particular, couples data respectively coming from .add files joined form single A0-A9 word following way:
7^237 D077211
W.A.R.P.
This resulting word allows identify appropriate memory [cs2-cs0] respective address [add6-add0] where relative I0-I7 stored.
When high, during off-line phase, W.A.R.P. generates addresses internal memories send those addresses single external memory support where data (.dat file) located. These addresses, which sent means EPA0-EPA2 A0-A9 (EPAO MSB, LSB) output pins, allow identify data EPROM) that have loaded W.A.R.P. internal memories. on-line mode A0-A9 used.
I0-I7: During off-line phase these data input pins accept microcode configuration data written into internal memories. antecedent memory word size bits, necessary give each word bits time. same written words consequent memory program memory.
on-line mode this carries input variables W.A.R.P. Input values have resolution bits accordance with configuration setting.
PRST: This restart W.A.R.P. possible restart work during computation (on-line phase) before writing internal memories (off-line phase). both cases must least clock period.
FIN: During on-line phase will start runtime acquisition cycle. This activated providing positive pulse time lower than entire clock period. When expected inputs have been processed, pulse must sent activate process. OFL: When this high, chip enabled load data internal RAMs (off-line phase). must when fuzzy controller waiting input values during processing phase (online phase).
CHM: This pin, which used only during off-line phase, determines charge mode. present W.A.R.P. release. When addresses internal memory locations where data have stored
7121237 DQ77212 flfll
must sent W.A.R.P. from outside means input pins A0-A9. When high W.A.R.P. automatically generates addresses internal memories manages EPROMs reading means addresses contained EPA0-EPA2 A0-A9 output pins bits).
testing purpose only. must connected Vss.
MTE: testing purpose only. must connected Vss.
MCLK: This input master clock whose frequency reach 40MHz (MAX). During off-line phase with high, DCLK signal with frequency MCLK/32 generated order drive downloading phase timing.
EPA0-EPA2: During off-line phase correspondence with high, these output pins joined MSB) A0-A9 obtaine complete address memory support where read data loaded W.A.R.P. internal memories. EPA0-EPA2 used when W.A.R.P. release.
00-09: These pins carry output values. When (strobe pin) high, output variable read external devices on-line mode). resolution output variables 1024 points bits). there more than output, output variables calculated they provided sequence stabilized during editing phase (see W.A.R.P.-SDT User Manual).
OCNTO-OCNT3: This output provides output variables with progressive number during on-line phase. consequence possible know which variable correspond data that output data (00-09). dimension OCNT connected with maximum number output variables (16).
STB: strobe enables user utilize output. When this high indicates that output variable been calculated ready output (00-09). This signal synchronizes external devices particular interfaces with controlled processes (on-line mode).
This signal indicates that processing rules been completed.
This output indicates that process start. automatically before last output been calculated, that possible start data acquisition before (with FIN) computation terminated.
W.A.R.P.
Figure Block Diagram
EPA0-EPA2
AO-.
KJ-I7
DOWNLOAD MANAGER
MCLK
DEMUX
ANTECEDENT MEMORY BBMCHS
BENCH BENCH! BENCH BENCH'
CLOCK MANAGER
INPUT ROUTER
RJZZFIER
BSKHS
INFERENCE
uiirr
PROQMM MEMORY
FUZZ]
OCNTO-OCNT3
00-09
OTST: testing purpose only. must connected Vss.
OMTS: testing purpose only. must connected Vss.
SYNC: W.A.R.P. uses this synchronize input data from external database off-line mode. database contains information about antecedent consequent membership functions about fuzzy rules. memorize this database possible host processor volatile memory.
FUNCTIONAL DESCRIPTION
W.A.R.P. works mode depending control signal level:
Off-line MODE (OFL High) On-line MODE (OFL Low) OFF-LINE MODE
W.A.R.P. memories loaded during offline phase. membership functions written inside their related memories process control rules loaded inside program memory. switch been then addresses words written memories provided external (A0-A9), while data must loaded time data bus. switch been high then addresses words written memories internally generated while addresses EPROM's locations read directly
Table Available Configurations Single Antecedent Memory.
Numbers Input Data Resolution Number Membership Functions Term
bit)
bit)
bit)
bit) 1x16
bit)
This configuration available W.A.R.P. 1.0.
6/19
7121237 0Q77213
W.A.R.P.
provided W.A.R.P. means A0-A9 EPA0-EPA2 output pins.
Data must loaded time data read from external volatile memory loaded host processor.
ON-UNE MODE
On-line mode W.A.R.P. enabled elaborate input values calculate outputs according fuzzy rules stored into microprogram. W.A.R.P. reads input values time input data when inputs given, signal pulled high indicate that computation starting. computational phase divided main parts. During first input values read corresponding ALPHA values (activation levels) extracted from internal memories. second part computation fuzzy rules defuzzification implemented.
block diagram shown figure describes structure W.A.R.P.
Antecedent Memory. formed benchs each containing four fuzzy sets bonded input variables.
Consequent Memory. formed bench where fuzzy sets bonded output variables stored.
Program Memory. formed single bench. Each line contains operating code execute computation rule. This code selects antecedentweights (ALPHA) involved rule, connects them programmed connective operators (AND,OR).
Figure Antecedent Memory Organization
Input Router. This internal block performs input data routing. Data read byte time from input data bus, stored different buffers and, thanks pipeline process, sent together indipendent modules processed parallel according chosen set-up configuration. Input data resolution decided user (MAX points) according available configurations, shown table
cycle starts when positive pulse applied time lower than entire clock period continues until (after low) PRST signal given.
Fuzzifier. This block generates addresses antecedentmemories where ALPHA values each sampled input value stored. reads first four input values calculates corresponding antecedent memories addresses. Afterwards reads other four inputs values simultaneously sends, thanks pipeline process, previous four ALPHA values into internal registers. These ALPHA values then sent Inference Unit. W.A.R.P. stores ALPHA values comprising term set, which formed connected IF-part rule, successive memory locations same memory word (see figure vectors characterizing term stored that ALPHAs different corresponding same universe discourse point (for same input) stored sequentially. W.A.R.P. retrieves alpha values term using crisp input value calculate memory word address used fuzzy memory device.The Fuzzifier Unit driven
W.A.R.P.
Figure Inference Unit Structure
OMEGA madmum rafarrad output
configuration accordance with antecedent part fuzzy rules. duration fuzzification process depends from chosen configuration input number.
Inference Unit. Thanks Theta Operator, Inference Unit generates THETA weights which used manipulate consequent MFs.
This calculation maximum and/or minimum performed ALPHA values according logical connectives fuzzy rules. possible utilize AND/OR connectives directly exploit ALPHA weights negated values. numberof THETA weights depends number rules.
rules have maximum four ALPHA weights (however they connected). more rules only joined with connective.
Inference Unit structure shown figure
Defuzzifier. generates output crisp values implementing consequent part rules according MAX-DOT method.
this method consequent multiplied weight value (OMEGA), which calculated basis antecedent logical operators.
terms needed evaluate sums numerator denominator center gravity equation (see formula) stored during off-line phase.
processing fuzzy rules produces, each output variable, resulting membership function. Each related processed output variable
firstly modified rule weight accordance MAX-DOT method.
Output value deduced from centroids (xi) modified (iii *Ai) using formula:
numberof defined Output Variable Area
Xi=absciss centroid
=membership degree output MFi.
represent membership function related with THEN-part rule WAR.P. uses single memory bench. each consequent each memory word contains both area multiplied with barycentre area itself. This area related first truth level (there truth levels bit), multiplication with calculated THETA must performed on-line.
parallel blocks calculate numerator denominator values implement centroids formula. Afinal division block calculates output values (see figure
8/19
7121237
W.A.R.P.
Figure Defuzzifier Structure
Program Memoiy
CONSEQUBUT MBMOnV xo-canboUMMclM
from opamor
,'20
MULTIPLIER
HEOISTBl
ADDER
MULTIPLIER
7~T~
HEttflTBR
ADDER
register
DIVIDER
ELECTRICAL SPECIFICATIONS
PARAMETRICS Across Temperature Range (T=Oto unless otherwise specified) INTERFACE
2.4V
0.8V 0.4V
Input Output
Table Characteristics
Symbol Parameter Unit
Level nput Voltage
High Level Input Voltage
Level Output Voltage
High Level Output Voltage
Level nput Current Vi=VSS
High Level Input Current Vi=Vdd
712T237 GG77Slb
9/19
W.A.R.P.
PARAMETRICS
PARAMETRICS Across Temperature Range (T=Oto unless otherwise specified INTERFACE
Table Characteristics
Symbol Parameters Test Conditions CK=20MHz CK=40MHz Unit
Clock Period
tCLH Clock High
tCLL Clock
Clock Rise 0.8V
Clock Fall
tsET Setup
tHLD Hold
10/19
7121237 GQ77217
W.A.R.P.
W.A.R.P. TIMING TABLES
Off-line Phase Timing (Internal RAMs Loading with Charge Mode "0")
nfig lion with uts,
Timing Table Description: OFF-LINE phase (CHM "0")
[INPUT] will enable 'manual downloading' specifying address data loaded into W.A.R.P.
MCLK [INPUT] must connected with external synchronization signal.
PRST [INPUT] must high enable device.
[INPUT] must high enable configuration loading phase into internal RAMs W.A.R.P.
input written into internal memories address specified A0-A9 must into 10-17 bus.
SYNC [OUTPUT] will provided synchronize input data (10-17,A0-A9) coming from external database. SYNC frequency MCLK/32 with phase delay tesp W.A.R.P. stores data present input buses rising edge MCLK, returns SYNC pulse after tcsp indicating that waiting data address that must given within next MCLK pulses. Afterwards W.A.R.P. stores data input buses restores SYNC pulse.
W.A.R.P. stores data situated I0-I7 addresses A0-A9 into internal registers. Figure Block Diagram W.A.R.P. downloading (CHM "0")
7151237 007721B
11/19
W.A.R.P.
Off-line Phase Timing (Internal RAMs Loading with Charge Mode "1")
EPA0-EPA2 A0-A9
W.A.R.P. stores DATAO W.A.R.P. slores DATAI R.P. stores DATAn
ADDRESSO ADDRESS1 ADDRESSn
^yjm
10-17
DATAO DATAI DATAn
Timing Table Description: OFF-LINE phase (CHM "1")
[INPUT] high will enable 'automatic downloading', specifying address non-volatile memory where data loaded into W.A.R.P. Internal memory addresses automatically generated.
MCLK [INPUT] must connected with external synchronization signal.
PRST [INPUT] must high enable device.
[INPUT] must high enable loading phase data into internal RAMs W.A.R.P.
SYNC [OUTPUT] will provided synchronize input data (I0-I7) coming from external database. SYNC frequency MCLK/32.
DCLK [INTERNAL] sets working frequency accordingto control signal. drives addressing data coming from external memory support I0-I7 input bus. external memory support must return data (addressed EPA0-EPA2+A0-A9 [OUTPUT]) into 10-17" period time longer than half period DCLK. DCLK frequency MCLK/32.
Figure Block Diagram W.A.R.P. downloading (CHM
12/19
7^537 DD772n
W.A.R.P.
On-line Phase Timing (Acquisition Elaboration) Working Frequency 40MHz
detection DATAOacquisition DATAI acquisition DATAn acquisition
MCLK
10-16
^ACQ configuration with inputs, outputs rules
Timing Table Description: ON-LINE phase, step: Acquisition
MCLK [INPUT] must connectedwith external synchronization signal.
[INPUT] must enable acquisition/elaboration phase W.A.R.P.
[INPUT] must high least clock period start acquisition phase. must already since least clock periods before providing pulse. duration must range clock,2clockperiods], pulse mustn't coincide with transitions.
[OUTPUT] will remain during acquisition phase.
input data must sent I0-I6 after been been high. Data situated I0-I6 stored into internal registers each next rising edge MCLK.
After current inputs have been acquired, [OUTPUT] high signal informs that elaboration phase start. This information provided thanks configuration stored program memory.
Figure Input/Output Connection Block Diagram
TRIGGER!
GENERATOR
JOHNSON COUNTER
Data Register
Data Register
Data liter
jwjI
OCNTO-OCNT3)
W.A.R.R RBQISTBl
B9JCH
oooa
ount
0UT2
OUTS
OUTrn^
7T2T237 0077220
13/19
W.A.R.P.1.1
On-line Phase Timing (Output Generation) Working Frequency 40MHz
OCNTO-3 last output number NUM1 NUM2 "")( nT)(
^comp= (first process, pipeline empty), (next configuration with 16inputs, outputs, rules _Elapsed time from first data acquisition fust output: first cycle other ones.
Timing Table Description: ON-LINE phase step:Elaboration
MCLK [INPUT] must connectedwith external synchronization signal.
[INPUT] must remain during this phase.
[OUTPUT) remains high during this phase.
[OUTPUT] high during this phase.
[OUTPUT] high clock period every time output value been calculated. informs that possible utilize outputwhich situated output (00-09). pulse starts rising edge MCLK stops next rising edge MCLK. falling edge
data situated 00-09 stored.
current output 00-09 [OUTPUT] provided exactly when signal rises does change until signal occurs.
output identifier OCNTO-OCNT3 [OUTPUT] provided exactly when signal rises does change until signal occurs.
[OUTPUT] when penultimate STROBE disabled allowing acquisition phase start while W.A.R.P. still elaborating last output.
When last output been provided, will automatically low.
14/19
7121237 0G77221 fill
W.A.R.P.
PROGRAMMING TOOL
W.A.R.P. Software Development Tool Figure W.A.R.P. Software Development Tools
SGS-THOMSON developed some software tools (see figure support A.R.P. allowing easy configurating loading memoriesand functional simulations. isfully compatible with A.R.P. board.
been designed order used with following hardware/software requirements:
80386 higher) processor
VGA/SVGA screen
Windows Version Higher constituting blocks are: W.A.R.P.-SDT Editor:
tool define fuzzy controller with User-Friendly Interface.
composed
Variable Editor define variable)
Membership Editor define membership function shape)
Rule Editor define base knowledge)
W.A.R.P-SDT Compiler:
generates code loaded W.A.R.P. memories according data defined through editor. also generates data base Debugger, Exporter Simulator.
W.A.R.P-SDT Debugger:
allows userto examine step-by-step fuzzy computation defined application. also allows
7121237 0077222
check results entire control process using list patterns stored into file. allows show:
Alpha values
Theta values
Defuzzification partial values
Output values
W.A.R.P.-SDT Exporter:
generates files imported different environments order develop W.A.R.P. based simulations exploiting user-developed models. addresses following environments:
Standard exporter generates function that recalled user program
Matlab: exporter generates '.M' file that used perform simulations Matlab environments
W.A.R.P.-SDT Simulator:
allows
define models controlled system terms differential equations
define external inputs points
resolve differential equations using Runge-Kutta algorithm
functionally simulate W.A.R.P.
show simulation results graphic charts.
MOmON_15/19
W.A.R.P.
W.A.R.P. Application Development Board board been designed connected RS232 port higher), also work stand alone. Inputs outputs provided compatible level. board allows user charge rules membership functions (seeW.A.R.P.-SDT User Manual) into W.A.R.P. memories.
manage inputs outputs. clock generatorfrequencyon board 24MHz.
automatic trigger used synchronize W.A.R.P. with external environment (working connectedwith PC).
When board used stand alone device fuzzy data (membership functions rules) stored EPROMs. board allows standalone/PC working selected setting switch (see W.A.R.P.-SDT User Manual). block diagram board described figure
Figure Board Block Diagram
sproni
16/19
7121237 0077223
16/15
W.A.R.P.
PACKAGE DIMENSIONS
Dim. inch
Min. Typ. Max. Min. Typ. Max.
4.20 5.08 0.16 0.19
0.56 0.02
2.54 0.10
0.38 0.01
1.14 0.003
30.10 30.35 1.18 1.19
29.20 29.41 1.14 1.15
27.69 28.70 1.11 1.13
30.10 30.35 1.18 1.19
29.20 29.41 1.14 1.15
27.69 28.70 1.11 1.13
1.27 0.05
30.10 30.35 1.18 1.19
29.20 29.41 1.14 1.15
27.69 28.70 1.11 1.13
0.50 0.020
1.78 0.070
Figure W.A.R.P. PLCC84 Plastic Package
7TS1B37 0Q77EE4
_17/19
W.A.R.P.
PACKAGE DIMENSIONS
Dim. inch
Min. Typ. Max. Min. Typ. Max.
33.58 1.332
17.78 0.700
2.24 0.088
2.54 0.100
4.70 0.185
1.40 0.055
1.68 0.065
30.78 1.212
2.54 0.100
0.50 0.020
1.78 0.070
Figure W.A.R.P. CPGA100 Ceramic Package
18/19
7121237 D07722S
W.A.R.P.1.1
Functions dedicated memories orderto reduce computational time. Therefore great amount WAR.P. processing based look-up table approach ratherthan on-line calculation.
Those Membership Functions (MFs), each portrayed configurable resolution elements, stored four internal RAMs Kbyte each). consequent MFs, different modelling, loaded single storing each area barycentre. This adoption Center Gravity defuzzifica-tion method.
downloading phase allows setting device, terms number, universes discourse shapes. During this phase W.A.R.P. prepares internal memories on-line elaboration phase loads microcode
program memory. This microcode, which drives on-line phase, generated Compiler (see W.A.R.P.-SDT User Manual) according adopted configuration. possible configurations shown table
During on-line phase 40MHz working frequency), W.A.R.P. processes input data produces outputs according configuration loaded downloading phase.
W.A.R.P. conceived work together with traditional microcontrollers which shall perform normal control tasks while W.A.R.P. will indipendently responsible fuzzy related computing. W.A.R.P. manufactured using high performance, reliable HCMOS4T (0.7|im) SGS-THOMSON Microelectronics process.
Table Ordering Information
Part Number Maximum Frequency Supply Voltage Temperature Range Package
STFLWARP11/PG CPGA100
STFLWARP11/PL PLCC84
Type Device Develop ment Tools
STFLSTUDI010/KIT STFLWARP11/PG STFLWARP11/Pi- W.A.R.P. W.A.R.P. programmer EPROM programmer RS-232 communication handler Internal Clock Variables Rules Editor W.A.R.P. Compiler/Debugger Exporter ANSI
Order Code Description Supported Target Functionalities System Requirement
STFLAFM10/SW WTA-FAM Building Rules BACK-FAMforBuiding STFLWARP11 STFLWARP11/PL STFLWARP20/PL ANSI Rules Minlmizer Step-by-Step Simulation Simulation from File Local Tuning MS-DOS higher Windows later 486, PENTIUM compatible
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specification mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics Printed Italy Rights Reserved
FUZZVSTUDI trademark SGS-THOMSON Microelectronics Microsoft regster trademarks Microsoft Corporation. registered trademark Mathworks Inc.
SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil Canada China France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands -Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
712^237 007722b
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