128Kx8 AS7C3102 CMOS SRAM 128KX8 CMOS SRAM (Common I/O)
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High Performance AS7C1025
128Kx8 AS7C3102
CMOS SRAM
128KX8 CMOS SRAM (Common I/O)
Organization: 131,072 words bits
High speed
10/12/15/20 address access time
3/3/4/5 output enable access time
power consumption
Active: cycle,
Standby: 27.5 max, CMOS (5V)
Very component active power data retention
Equal access cycle times
Easy memory expansion with inputs
TTL-compatible, three-state
2-pin JEDEC standard package 300/400
Center power ground pins noise protection 2000 volts
Latch-up current >200
3.3V version available (AS7C31025)
Industrial commercial temperature available
Logic block diagram
arrangement
-GND-
A6-h
Input buffer
512x256x8
Array (1,04-8,576)
Column decoder
AAAAAAAA 1011 131415
Control circuit
I/Ol I/02 I/O} I/Q4
1/08 I/06 1/05
Selection guide
7CJ025-10 7C1025-12 7C1025-15 7C1025-20
7C31025-12 7C31025-15 7C31025-20 Unit
Maximum address access time
Maximum output enable access time
Maximum operating current AS7C1025
AS7C31025
Maximum CMOS standby current
Shaded areas contain advance information.
l^0D34Mc] 00013b'i
ALLIANCE SEMICONDUCTOR
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AS7C1025
AS7C31025
Functional description
AS7C102S AS7C31025 high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized 131,072 words bits. They designed memory applications where fast data access, power, simple interfacing desired.
Equal address access cycle times (t^, tRC, twc) 10/12/15/20 with output enable access times (fc,E) 3/3/4/5 ideal high performance applications. chip enable input permits easy memory expansion with multiple-bank memory systems.
When HIGH device enters standby mode. standard AS7C1025 guaranteed exceed 27.5 power consumption standby mode, typically requires only Both devices also offer 2.0V data retention.
write cycle accomplished asserting write enable (WE) chip enable (CE). Data input pins I/00-I/07 written rising edge (write cycle (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with output enable (51) write enable (WE).
read cycle accomplished asserting output enable (OE) chip enable (CE), with write enable (WE) HIGH. chip drives pins with data word referenced input address. When either chip enable output enable inactive, write enable active, output drivers stay high-impedance mode.
chip inputs outputs TTL-compatible, operation from single supply (AS7C1025) 3.3V supply (7C3 1025). AS7C1025 ASC31025 packaged common industry standard packages.
Absolute maximum ratings
Faramettr Symbol Unit
Voltage relative -0.5
Power dissipation
Storage temperature (plastic) Tstj.
output current ^out
Stresses greater thill those listed under Mmtimum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Truth table
Data
Mode
High Standby (IsB> ISBi)
High Output disable
Dout Read
Write
Key: Don't Care, LOW, HIGH
Recommended operating conditions Parameter Symbol Nominal Unit
AS7C1025
Supply voltage AS7C31025
AS7C1025
Input voltage AS7C31025
-0.5
Ambient operating temperature
-3.0V pulse width less than tR(V2.
l-20013-A.
^00344^ 0a0137D
Copyright Alliance Semiconductor. rights reserved.
This Material Copyrighted Respective Manufacturer
AS7C1025
AS7C31025
operating characteristics
Parameter Symbol Test conditions Unit
Input leakage current iiui Max,
Output leakage current UloI Max, Vout toVcc
Operating power VIL, AS7C1025
supply current AS7C31025
Standby power supply current Cfr=V3H,f=fma,
!SBI VCC-0.2V, 0.2V VCC-0.2V,
Output voltage
I(->H 2,4:
Shaded areas contain advance information.
Capacitance2
Parameter
Symbol_Signals
Test conditions
Unit
Input capacitance
capacitance
11-20013-A.
^00344*1 0DD1371
Copyright Alliance Semiconductor. rights
This Material Copyrighted Respective Manufacturer
AS7C1025
AS7C31025
Read cycle
Parameter Symbol Mill Unit Notes
Read cycle time
Address access time
Chip enable (CE) access time 'ace
Output enable (OE) access time
Output hold from address change
output tciz
HIGH output high tCHZ
output tOLZ
HIGH output high 'ohz
Power time
Power down time
switching waveforms
WtfMX Rising input
Falling input
Undefined output/don't care
Read waveform J'6-7'9
Address
-lRC-
Data valid
Read waveform 3-6-8-9
11-20013-A.
^0034^ DDG137E
Copyright Alliance Semiconductor. rights reserved.
This Material Copyrighted Respective Manufacturer
AS7C1025
AS7C31025
Write cycle11
Parameter Symbol Unit Notes
Write cycle time
Chip enable (CE) write
Address setup write
Address setup time
Write pulse width
Address hold from write
Data valid write
Data hold time
Write enable output high
Output active from write
Write waveform i0>11
Address
Data valid
Write waveform 10,11
11-20013-A. TDDBHH^ 0001373 Copyright Semiconductor. rights reserved.
This Material Copyrighted Respective Manufacturer
AS7C1025
AS7C31025
Data retention characteristics
Parameter Symbol
data retention
Data retention current krcDR
Chip enable data retention time tCDR
Operation recovery time
Test conditions
Unit
Input leakage current
2.0V
Vin>Vc<r0.2Vor 0.2V
_|1A_
Data retention waveform
Data retention mode 2.0V
4.5V
test conditions
Output load: Figure except noted.
Input pulse level: 3.0V. Figure
Input rise fall times: Figure
Input output timing reference levels: l.SV.
+3.0V
GND.
Figure Input waveform
'GND Figure Output load
Thevenin equivalent:
+1.728V
"'out
scope capacitance
"GND
Figure Output load t^Lz, tcHZ* tOLZ> kiHZ'
Notes
During power-up, pull-up resistor Vccon required meet specification.
This parameter sampled 100% tested.
test conditions, test conditions. Figures
specified with Figure Transition measured from steady-state voltage.
This parameter guaranteed tested.
HIGH read cycle.
read cycle.
Address valid prior coincident with transition
read cycle timings referenced from last valid address first transitioning address.
must HIGH during address transitions.
write cycle timings referenced from last valid address first transitioning address.
This data applicable AS7C1025. 7C31025 functions similarly.
II-20013-A ^0344^ 0001374 Copyright Alliance Semiconductor. rights reserved.
This Material Copyrighted Respective Manufacturer
Typical characteristics12
AS7C1025
AS7C31025
Normalized supply current supply voltage
Supply voltage
Normalized supply current ambient temperature
Normalized supply current IcB1 ambient temperature
-.625
0.04
vcc=
Ambient temperature
Ambient temperature
Normalized access time supply voltage V(L-
1.25 3.75 Output voltage
5.0V
Normalized access time ambient temperature
5.0V
Supply voltage
Output source current output voltage
Output sink current output voltage
1.25 3.75 Output voltage
Normalized supply current cycle frequency /tRC, /twc
5.0V
Ambient temperature
5.0V
Cycle frequency (MHz)
Typical access time change output capacitive loading
vcc" 4.5V
Capacitance (pF)
1000
11-20013-A.
00D1375
Copyright Alliance Semiconductor. rights reserved.
This Material Copyrighted Respective Manufacturer
AS7C1025
AS7C31025
AS7C1025 ordering codes
Package Access time
10ns
15ns
Shaded areas contain advance information.
AS7C102S-10JC AS7C1025-12JC AS7C1025-15JC AS7C1025-20JC
Plastic SOJ, 3.3V AS7C31025-12JC AS7C31025-15JC AS7C31025-2
AS7C3102S-12J1 AS7C31025-15J1 AS7C31025-20JPlastic SOJ, AS7C1025-12TJC AS7C1025-15TJC
3.3V AS7C31025-12TJC AS7C31025-15TJC AS7C31025-20TJC
7C1025 part numbering system AS7C
1025
SRAM prefix
Blank
CMOS 3.3V CMOS
Device number Access time
Package:J
Temperature range Commercial, Industrial,
11-20013-A.
TDGiMUT GG0137b
Copyright Alliance Semiconductor. rights reserved,
This Material Copyrighted Respective Manufacturer
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