44-pin package cost volt operating range power consumpt

Datasheets.org.uk - 100 Million Datasheets from 7500 Manufacturers.

44-pin package cost volt operating range power consumpt

Datasheet Thumbnail

Top Searches for this datasheet

8-bit CMOS microcomputer
44-pin package
cost
volt operating range
power consumption (Typical)
Fast instruction pointer microsecond
standby modes STOP HALT
input/output lines (two with comparator inputs)
digital inputs CMOS levels, Schmitt triggered
ROMIess
bytes (236 general purpose)
GENERAL DESCRIPTION
Z86C90/C89 (Consumer Controller Processor) introduces level sophistication single-chip architecture. Z86C90/C89 ROMIess members single-chip microcontroller family with bytes general purpose RAM. only difference that exists between Z86C89 Z86C90 that on-chip oscillatorof Z86C89can accept external network other external clock source, while Z86C90's on-chip oscillator accepts crystal, ceramic resonator, external clocksource drive. controllers housed 40-pin DIP, 44-pin Leaded Chip Carrier, 44-pin Quad Flat Pack, CMOS compatible. offers external memory which enables this microcomputer used where code flexibility required. Zilog's CMOS microcomputer offers fast execution, efficient memory, sophisticated interrupts, input/output manipulation capabilities, easy hardware/software system expansion along with cost power consumption.
Z86C90/C89
ROMLESS CMOS
8-BlT MICROCONTROLLER
Expanded Register File control registers
programmable 8-bit Counter/Timers
6-bit programmable prescaler
vectored, priority interrupts from sixdifferent sources
Clock speeds
Brown-Out protection
Programmable Watch Dog/Power-On Reset Timer
Comparators with programmable interrupt polarity
On-chip oscillator that accepts crystal, ceramic resonator, external clock drive (Z86C90).
On-chip oscillator that accepts network external clock drive (Z86C89).
Z86C90/C89 architecture based Zilog's 8-bit microcontroller core with Expanded Register File allow access toregister mapped peripheral circuits. offers flexible scheme, efficient register address space structure, number ancillary features that useful many industrial, automotive, computer peripherals, advanced scientific applications.
applications demand powerful capabilities. Z86C90/C89 fulfills this with pins dedicated input output. These lines grouped into four ports. Each port consists eight lines, configurable under software control provide timing, status signals, parallel with without handshake, address/data interfacing external memory.
This Material Copyrighted Respective Manufacturer
GENERAL DESCRIPTION (Continued)
There four basic address spaces available support this wide range configurations: Program Memory, Register File, Data Memory, Expanded Register File. Register File composed bytes general purpose registers, four port registers, fifteen control status registers. Expanded Register File consists control registers.
unburden program from coping with real-time problems, such counting/timing data communication, Z86C90/C89 offers on-chip counter/timers.
Included large number user selectable modes, on-board comparators process analog signals with common reference voltage (Figure
Note: Signals with preceding front slash,"/", active Low, e.g.: B//W (WORD active Low); /B/W (BYTE active Low, only); /N//S (NORMAL SYSTEM both active Low).
Output Input
XTAL R//W /RESET
mimi
Port
Counter/ Timers
Interrupt Is*-
Control
Analog Comparators
Machine Tinning
Instruction Control
FLAGS
Register
Pointer
Register File
8-Bit
RESET WDT,
~7ST
Program Counter
(Bit Programmable)
Address (Nibble Programmable)
Address/Data (Byte Programmable)
Figure Functional Block Diagram
This Material Copyrighted Respective Manufacturer
DESCRIPTION
R//W
Z86C90/C89
XTAL2
XTAL1
/RESET
Figure 40-Pin Dual-ln-Line Assignments
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
Z86C90/C89 PLCC /RESET
R//W
T-0.
Figure 44-Pin Leaded Chip Carrier Assignments
This Material Copyrighted Respective Manufacturer
o_a.Q-Q.a_
Figure 44-Pin Quad Flat Pack Assignments
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
Table 40-Pin Dual-ln-Line Identification
Symbol Function Direction
R//W Read/Write Output
P25-27 Port 5,6,7 In/Output
P04-P06 PortO 4,5,6 In/Output
P14-P15 Port In/Output
Port In/Output
Power Supply Input
12-13 P16-P17 Port In/Output
Crystal, Oscillator Clock Output
XTAL1 Crystal, Oscillator Clock Input
16-18 P31-P33 Port 1,2,3 Input
Port Output
Address Strobe Output
/RESET Reset Input
Port Output
Port Output
Port Output
Port Input
26-27 P00-P01 Port In/Output
28-29 P10-P11 Port In/Output
Port In/Output
Ground Input
32-33 P12-P13 Port In/Output
Port In/Output
35-39 P20-P24 Port 0,1,2,3,4 In/Output
Data Strobe Output
This Material Copyrighted Respective Manufacturer
Table 44-Pin Leaded Chip Carrier Identification
Symbol Function Direction
6-10 P12-P13 P20-P24 Ground Port Port Port 0,1,2,3,4 Data Strobe Input In/Output In/Output In/Output Output
14-16 17-19 20-21 R//W P25-27 P04-P06 P14-P15 Connected Read/Write Port 5,6,7 PortO 4,5,6 Port Input Output In/Output In/Output In/Output
23-24 25-26 pfe-pi7 XTAL2 XTAL1 Port Power Supply Port Crystal, Oscillator Clock Crystal, Oscillator Clock In/Output Input In/Output Output Input
29-31 P31-P33 /RESET Port 1,2,3 Port Address Strobe Ground Reset Input Output Output Input Input
Port Port Port Port Output Output Output Input
40-41 42-43 P00-P01 P10-P11 PortO Port PortO In/Output In/Output In/Output
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
Table 44-Pin Quad Flat Pack Identification
Symbol Function Direction
P05-P06 Port In/Output
P14-P15 Port In/Output
Port In/Output
Power Supply Input
P16-P17 Port In/Output
XTAL2 Crystal, Oscillator Clock Output
XTAL1 Crystal, Oscillator Clock Input
12-14 P31-P33 Port 1,2,3 Input
Port Output
Address Strobe Output
Ground Input
/RESET Reset Input
Port Output
Port Output
Port Output
Port Input
23-24 P00-P01 Port In/Output
25-26 P10-P11 Port In/Output
Port In/Output
28-29 Ground Input
30-31 P12-P13 Port In/Output
Port In/Output
33-37 P20-P24 Port 0,1,2,3,4 In/Output
Data Strobe Output
Connected Input
R//W Read/Write Output
41-43 P25-27 Port 5,6,7 In/Output
Port In/Output
FUNCTIONS
/DS. (output, active Low). Data Strobe activated once each external memory transfer. READ operation, data must available prior trailing edge of/DS. WRITE operations, falling edge indicates that output data valid.
/AS. (output, active Low). Address Strobe pulsed once beginning each machine cycle. Address output PortO/Port external programs. Memory address transfers valid trailing edge /AS. Under program control, placed high-impedance state along with Ports Data Strobe, Read/ Write.
XTAL1. Crystal (time-based input). This connects parallel-resonant crystal, ceramic resonator, network external single-phase clock on-chip oscillator input.
XTAL2. Crystal 2(time-based output). This connects parallel-resonant, crystal, ceramic resonant, network on-chip oscillator output.
R//W. (output, write Low). Read/Write, R//W signal when writing external program data memory.
This Material Copyrighted Respective Manufacturer
Port (P00-P07). Port 8-bit, bidirectional, CMOS compatible port. These eight lines configured under software control nibble port, address port interfacing external memory. input buffers Schmitt triggered output drivers
push-pull. PortO placed under handshake control. this configuration, Port lines used handshake control /DAVO RDYO. Handshake signal direction dictated direction Port upper nibble P04-P07. lower nibble must have same direction upper nibble.
external memory references, PortO provide address bits A11-A8 (lower nibble) A15-A8 (lower upper nibble) depending required address space.
address range requires bits less, upper nibble Port programmed independently while lower nibble used addressing. both nibbles needed operation, they must configured writing Port mode register. After hardware reset. Port configured address lines A15-A8, extended timing accommodate slow memory access. initialization routine include reconfiguration eliminate this extended timing mode.
Port high-impedance mode selected address output state along with Port control signals /AS, R//W (Figure
Z86C90/C89
Port (I/O
Handshake Controls /DAVO RDYO (P32 P35)
Figure Port Configuration
This Material Copyrighted Respective Manufacturer
FUNCTIONS (Continued)
Port (P10-P17). Port multiplexed Address (A7-AO) Data (D7-D0), CMOS compatible port. Port dedicated Zilog ZBUS'-compatible memory interface. operations Port supported Address Strobe (/AS) Data Strobe (/DS) lines, Read/ Write (R//W) Data Memory (/DM) control lines. Data memory read/write operations done through this port (Figure more than external locations required, Port outputs additional lines.
Port placed high-impedance state along with Port /AS, R//W, allowing Z86C90/C89 share common resources multiprocessor applications.
wakes with bits Port configured address outputs external memory.
Port (I/O ADO)
Z86C90/C89
Handshake Controls /DAV1 RDY1 (P34 P33)
Figure Port Configuration
This Material Copyrighted Respective Manufacturer
Port (P20-P27). Port 8-bit, bidirectional, CMOS compatible port. These eight lines configured under software control input output, independently. Port always available operation. input bulfers Schmitt triggered. Bits programmed outputs globally programmed either push-pull
open-drain. Port placed under handshake control. this configuration, Port3lines, andP36areused handshake controls lines /DAV2 RDY2. handshake signal assignment Port lines dictated direction (input output) assigned bit-7 Port (Figure
Handshake Controls /DAV2 RDY2 (P31 P36)
Figure Port Configuration
Port (P30-P37). Port 8-bit, CMOS compatible four-fixed input four-fixed output. Port consists four-fixed input (P30-P33) four-fixed output (P34-P37), configured under software control Input/Output,
Counter/Timers, interrupt, Port handshake Data Memory functions. Port Pin-0 input Schmitt triggered, pins P31, P32, standard CMOS inputs; outputs push-pull.
This Material Copyrighted Respective Manufacturer
FUNCTIONS (Continued)
on-board comparators process analog signals with reference voltage P33. analog function enabled programming Port Mode Register (bit-1). Port pins falling edge interrupt inputs. programmable rising, falling, both edge triggered interrupts (IRQ register bits comparator reference voltage input. Access Counter/Timer made through (TIN) (T^). Handshake lines Ports available through P36.
Port also provides following control functions: handshake Ports (/DAV RDY); four external interrupt request signals (IRQ0-IRQ3); timer input output signals Data Memory Select [(/DM) (Figure 8)].
Auto-Latch. Auto-Latch puts valid CMOS levels CMOS inputs (except P31-P33) that externally driven. Whether this level zero one, cannot determined. valid CMOS level, rather than floating node, reduces excessive supply current flow input buffer.
Z86C90/C89
Port (I/O Handshake)
Figure Port Configuration
This Material Copyrighted Respective Manufacturer
Table Assignments
CTC1 Int.
IRQ3
IRQ2
IRQO
IRQ1
^our
Noies:
Handshake Signals
Comparator Inputs. Port Pins each have comparator front end. comparator reference voltage (Pin P33) common both comparators. analog mode, positive inputs comparators reference voltage supplied both comparators. digital mode, used register input IRQ1 source.
/RESET, (input, active-Low). Initializes MCU. Reset accomplished either through Power-On, Watch Timer reset, STOP Mode Recovery, external reset. During Power-On Reset Watch Reset, internally generated reset drives reset time. devices driving reset line should open-drain order avoid damage from possible conflict during reset conditions. Pull-up provided internally.
After time, /RESET Schmitt triggered input. avoid asynchronous noisy reset problems, Z86C90/ equipped with reset filter four external clocks (4TpC). external reset signal less than 4TpC duration, reset occurs. fifth clock after reset detected, internal signal latched held internal register count external clocks, duration external reset, whichever longer.
During reset cycle, held active while cycles rate TpC/2. Program execution begins location OOOC (HEX), 5-10 cycles after released. Power-On Reset, typical reset output time Z86C90/C89 does reset WDTMR, SMR, P2M, registers STOP Mode Recovery operation.
FUNCTIONAL DESCRIPTION
incorporates special functions enhance Z8's functionality industrial, scientific research advanced technologies applications.
Reset. device reset following condi-
tions:
Power-On Reset
Watch-Dog Timer
STOP Mode Recovery Source
Brown-out Recovery
External Reset
Program Memory. Z86C90/C89 addresses external program memory (Figure first bytes program memory reserved interrupt vectors. These locations contain 16-bit vectors that correspond available interrupts. Program execution begins location OOOC (HEX) after reset.
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
65535
Location First Byte Instruction Executed After RESET
Interrupt Vector (Lower Byte)
Interrupt Vector (Upper Byte)
External
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQO
IRQO
External
Data Memory
000C
Addressable
Figure Data Memory
Figure Program Memory
Data Memory. (/DM). Z86C90/C89 ROMIess version addresses bytes external data memory beginning location OOOCH (Figure 10). External data memory included with, separated from, external program memory space. /DM, optional function that programmed appear P34, used distinguish between data program memory space. state signal controlled type instruction being executed. opcode references PROGRAM (/DM inactive) memory, instruction references data (/DM active Low) memory.
Expanded Register File. register file been expanded allow additional system control registers, mapping additional peripheral devices along
with ports into register address area. register address space through been implemented groups registers group (Figure 11). These register groups known (Expanded Register File). Bits register select working register group. Bits register select expanded register group (Figure 12). system configuration registers reside Expanded Register File Bank rest Expanded Register physically implemented open future expansion.
This Material Copyrighted Respective Manufacturer
STANDARD CONTROL REGISTERS
RESET CONDITION
REGISTER POINTER
EXPANDED REG. GROUP REGISTER
RESET CONDITION
REGISTER
FLAGS
P01M
PREO
PRE1
Reserved
EXPANDED REG. GROUP
REGISTER RESET
WDTMR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
%(0)00
Unknown
Will reset with STOP Mode Recovery
Figure Expanded Register File Architecture
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
Expanded Register Group Working Register Group
Default setting after RESET OOOOOOOO
Figure Register Pointer Register
Register File. register file consists four port registers, general purpose registers control status registers (R0-R3, R4-239 R240-R255, respectively), plus system configuration registers expanded register group. instructions access registers directly indirectly 8-bit address field. This allows short, 4-bit register address using Register Pointer (Figure 13). 4-bit mode, register file divided into working register groups, each occupying continuous locations. Register Pointer addresses starting location active working register group.
Note: Register Bank EO-EF only accessed through working registers indirect addressing modes.
Stack. Z86C90/C89 external data memory internal register file used stack. 16-bit Stack Pointer (R254-R255) used external stack residing anywhere data memory ROMIess mode. 8-bit Stack Pointer (R255) used internal stack that resides within general purpose registers (R4-R239). used general purpose register only when using internal stacks.
Counter/Timers. There 8-bit programmable counter/ timers (T0-T1), each driven 6-bit programmable prescaier. prescaler driven internal external clock sources; however, prescaler driven internal clock only (Figure 14).
6-bit prescaler divides input frequency clock source integer number from Each prescaler drives counter, which decrements value 256) that been loaded into counter. When counter reaches count, timer interrupt request, IRQ4 (TO) IRQ5 (T1), generated.
counters programmed start, stop, restart continue, restart from initial value. counters also programmed stop upon reaching zero (single pass mode) automatically reload initial value continue counting (modulo-n continuous mode).
counters, prescalers, read time without disturbing their value count mode. clock source user-definable either internal microprocessor clock divided four, external signal input Port Timer Mode register configures external timer input (P31) external clock, trigger input that retriggerable non-retriggerable. gate input internal clock. counter/timers cascaded connecting output input
R255 R2S3 R240
upper nibble register file address provided register pointer specifies active woiKing-register group
Specified Working Register Group
Ports
lower nibble register File address provided instruction points specified register
Figure Register Pointer
This Material Copyrighted Respective Manufacturer
Internal Data
(SMR)
Internal Clock Gated Clock Triggered Clock
Write
Write
Internal Data
Figure Counter/Timer Block Diagram
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. Z86C90/C89 different interrupts counter/timers (Table Interrupt Mask from different sources. interrupts maskable Register globally individually enables disables prioritized (Figure 15). sources divided interrupt requests, follows; four sources claimed Port lines P30-P33,
IRQO IRQ2
Figure Interrupt Block Diagram
This Material Copyrighted Respective Manufacturer
Table Interrupt Types, Sources, Vectors
Name Source Vector Location
/DAV
/DAV
IRQ3
10,11
Comments
External (P32), Rising Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising Falling Edge Triggered
External (P30), Falling Edge Triggered
Internal
Internal
When more than interrupt pending, priorities resolved programmable priority encoder that controlled Interrupt Priority register. interrupt machine cycle activated when interrupt request granted. Thus, this disables subsequent interrupts, saves Program Counter Status Flags, then branches prog memory vector location reserved that interrupt. Z86C90/C89 interrupts vectored through locations program memory. This memory location next byte contain 16-bit address interrupt service routine that particular interrupt request. accommodate polled interrupt systems, interrupt inputs masked Interrupt Request register polled determine which interrupt requests need service.
interrupt resulting from mapped into IRQ2, interrupt from mapped into IRQO. Interrupts IRQ2and IRQOmay rising, falling both edge triggered, programmable user. software poll identify state pin.
Programming bits Interrupt Edge Select located Register (R250), bits configuration shown Table
Table Register
Interrupt Edge
Notes:
F=Falling Edge R=Rising Edge
Clock. Z86C90 on-chip oscillator high-gain, parallel-resonant amplifier connection crystal, ceramic resonator, suitable external clock source
(XTAL1 Input, XTAL2= Output). crystal should cut, max., with series resistance (RS) less than equal Ohms. Z86C89 on-chip oscil lator driven with cost network other suitable external clock source. (Note: option available part).
crystal should connected across XTAL1 XTAL2 using recommended capacitors (capacitance more than equal from each ground. oscillator configuration external resistor connected from XTAL1 XTAL2, with frequency-setting capacitor from XTAL1 ground (Figure 16). Figures 52-54 typical characteristics.
Power-On-Reset (POR). timer circuit clocked dedicated on-board oscillator used Power-On Reset (POR) timer function. time allows oscillator circuit stabilize before instruction execution begins.
timer circuit one-shot timer triggered three conditions:
Power fail Power status.
STOP mode recovery SMR=1).
timeout.
time nominal Bit-5 Stop Mode Register determines whether timer bypassed after STOP mode recovery (typical external clock, oscillators).
HALT. HALT turns internal clock, XTAL oscillation. counter/timers external interrupts IRQO, IRQ1, IRQ2, IRQ3, remain active. devices recovered interrupts, either externally internally generated.
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
Ceramic Resonator Crystal
C1,C2-47pFTYP*
C1,C2-22pF
(TYP)
External Clock
Pieliminaiy value including parasitics
Figure Oscillator Configuration
STOP. This instruction turns internal clock external crystal oscillation reduces standby current microamperes less. STOP Mode terminated reset only, either timeout, POR, recovery external reset. This causes processor restart application program address 000C (HEX). order enter STOP HALT) mode, necessary first flush instruction pipeline avoid suspending execution mid-instruction. this, user must execute (opcode=FFH) immediately before appropriate sleep instruction, i.e.:
clear pipeline STOP enter STOP mode
clear pipeline HALT enter HALT mode
Stop Mode Recovery Register (SMR). This register selects clock divide value determines mode STOP Mode Recovery (Figure 17). bits write only, except which read only. flag that hardware condition STOP recovery reset power-on cycle. controls whether level high level required from recovery source. controls reset delay after recovery. Bits register, specify source STOP Mode Recovery
signal. Bits determine timeout period WDT. located Bank Expanded Register Group address OBH.
<F)0B
SCLK/TCLK Divide
OFF*
Reserved
Stop Mode Recovery Source
Only*
Only
Stop Delay
Stop Recovery Level
Level*
High Uvei
Stop Flag
POR*
Stop Recovery
Default setting after RESET
Figure STOP Mode Recovery Register
This Material Copyrighted Respective Manufacturer
SCLK/tCLK divide-by-16 Select (DO). control divide-by-16 prescaler SCLK/TCLK. purpose this control selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers interrupt logic).
STOP Mode Recovery Source (D2, D4). These three bits specify wake source STOP recovery (Figure Table
V-y- .001 .100 .101 .110
S-CS-H^ "-{>i CM>i
Stop Mode Recovery Edge Select (SMR)
From Pads
RESET
Data Latch IRQ1
Digital/Analog Mode Select (P3M)
Figure STOP Mode Recovery Source
Table STOP Mode Recovery Source
SMR:432 Operation
Description Action
and/or external reset recovery
transition
transition
transition
transition
transition
Logical through
Logical through
STOP Mode Recovery Delay Select (D5). This bit, high, disables /RESET delay after STOP Mode Recovery. default configuration this one. "fast" wake selected, STOP Mode Recovery source needs kept active least TpC.
STOP Mode Recovery Edge Select (D6). this position indicates that high level recovery sources wakes Z86C90/C89 from STOP Mode. indicates level recovery. default (Figure 18).
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
Cold Warm Start (D7). This device upon entering STOP Mode. this (cold) indicates that device will reset POR/WDT RESET. this (warm) indicates that device awakens source.
Watch-Dog-Timer Mode Register (WDTMR).
retriggerable one-shot timer that resets reaches
terminal count. initially enabled executing instruction refreshed subsequent executions instruction. circuit driven on-board oscillator external oscillator from XTAL1 pin. clock source selected with register (Figures 20).
WDTMR
External Clock
1024
4096
During HALT
During STOP
XTAL1/INT Select
On-Board
Default setting after RESET
Figure Watch-Dog Timer Mode Register
Time Select (DO,D1). Selects time period. configured shown Table
Table Time Select
Timeout Timeout
internal XTAL clock
256TpC
512TpC
1024TpC
4096TpC
Notes:
XTAL clock cycle default reset Figures details.
WDTMR During HALT (D2). This determines whether active during HALT Mode. indicates active during HALT. default
WDTMR During STOP (D3). This determines whether active during STOP Mode. Since XTAL clock stopped during STOP Mode, on-board selected clock source counter. indicates active during STOP. default
Clock source (D4). This determines which oscillator source used clock internal counter chain. internal oscillator bypassed clock source driven from external pin, XTAL1. default configuration this which selects oscillator.
This Material Copyrighted Respective Manufacturer
/RESET.
Clock
Filler
Select (WDTMR)
Source Select (WDTMR)
XTAL
REF.
From Stop Mode
Clear
Clock RESET Generator
RESET
OSC.
Internal RESET
SELECTl
15mS 25mS 100mS
WDT/POR Counter Chain
Operating Voltage Det.
Recovery
Source 12ns Glitch Filter
Stop Delay Select (SMR)
Figure Resets
Brown-Out Protection. on-board Voltage Comparator checks that required level ensure correct operation device. Reset globally driven below (Brown-Out Voltage). minimum operating voltage varies with temperature operating frequency, while varies with temperature only.
brown-out trip voltage (VBO) less than volts above volts under following conditions.
Maximum (VBO) Conditions:
Case Internal Clock Frequency equal less than
Case Internal Clock Frequency equal less than
Note: internal clock frequency one-half external clock frequency.
This Material Copyrighted Respective Manufacturer
FUNCTIONAL DESCRIPTION (Continued)
device functions normally above under conditions. Below device functions normally until Brown-Out Protection trip point reached, below which reset globally driven. device guaranteed function normally supply voltages above brown
trip point temperatures operating frequencies cases actual brown trip point function temperature process parameters (Figure 21).
(Volts)
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
ypical)
Temperature
Power-on Reset threshold overlap Figure Typical Z86C90/C89 Brown-Out Voltage Temperature
This Material Copyrighted Respective Manufacturer
STANDARD TEST CONDITIONS
characteristics listed below apply standard test conditions noted. voltages referenced GND. Positive current flows into referenced (Figure 22).
From Output Under Test
"ft"
Figure Test Load Diagram
ABSOLUTE MAXIMUM RATINGS
Symbol Description Units
Supply Voltage -0.3 +7.0
TsrG Storage Temp
Oper Ambient Temp
Power Dissipation
Notes:
Voltage pins with respect GND. Ordering Information.
CAPACITANCE
MHz, unmeasured pins
Parameter
Input capacitance
Output capacitance
capacitance
Stress greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; operation device condition above those indicated operational sections these specifications implied. Exposure absolute maximum rating conditions extended period affect device reliability.
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
Parameter Typ@ Units Conditions Notes
Note
Input Voltage 3.3V 250|jA
5.0V
Clock Input 3.3V Vcc+0.3 Vcc+0.3 Driven External
High Voltage Clock Generator
5.0V Vcc+0.3 Vcc+0.3 Driven External
Clock Generator
Clock Input 3.3V -0.3 GND-0.3 Driven External
Voltage Clock Generator
5.0V GND-0.3 GND-0.3 Driven External
Clock Generator
Input High Voltage 3.3V Vcc+0.3 Vcc+0.3
5.0V Vcc+0.3 Vcc+0-3
Input Voltage 3.3V GND-0.3 GND-0.3
5.0V GND-0.3 GND-0.3
Output High Voltge 3.3V V0.4 Vcc-0-4 -2.0
5.0V V0.4 Vcc-0.4 -2.0
Output Voltage 3.3V +4.0
5.0V +4.0
Output Voltage 3.3V
5.0V l0L=+12mA,
Reset Input 3.3V
High Voltage 5.0V
Reset Input 3.3V GND-0.3 GND-0.3
Voltage 5.0V GND-0.3 GND-0.3
OFFSET Comparator Input 3.3V
Offset Voltage 5.0V
Input Leakage 3.3V vN=ov,vcc
5.0V v*=ov,vcc
Output Leakage 3.3V 0V,Vcc
5.0V
Reset Input Current 3.3V
5.0V
Supply Current 3.3V @8MHz [4,5]
5.0V @8MHz [4,5]
3.3V [4,5]
5.0V [4,5]
This Material Copyrighted Respective Manufacturer
Parameter Units Conditions Notes
Note
'coi Standby Current 3.3V HALT Mode V0V,Vcc [4,5]
5.0V HALT Mode [4,5]
3.3V HALT Mode [4.5]
vw=ov,vcc
5.0V HALT Mode [4,5]
V.-OV.V*
3.3V Clock Divide [4,5]
5.0V Ciock Divide [4,5]
3.3V Clock Divide [4,5]
5.0V Clock Divide [4,5]
'cc2 Standby Current 3.3V STOP Mode
Running
5.0V STOP Mode
Running
3.3V STOP Mode
Running
5.0V 1000 STOP Mode Running
Auto Latch 3.3V 0V<VH<Vcc
Current 5.0V 0V<VH<Vcc
'alh Auto Latch 3.3V ov<vN<vcc
High Current 5.0V ov<vK<vcc
Power Reset 3.3V
5.0V
Brown- 2.65 2.95
Voltage Ext. Freq.
Notes:
icc,
Crystal/Resonator
External Clock Drive
GND=0V
5.0V
outputs unloaded, pins floating, inputs rail.
CL1=CL2=100pF
Same note except inputs
increases temperature decreases.
Unit
Frequency
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
External Memory Read Write Timing Diagram
Figure External Memory Read/Write Timing
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
External Memory Read Write Timing Table
Symbol Parameter Units Notes
Note[3]
TdA(AS) Address Valid
Rising Delay
TdAS(A) Rising Address
Float Delay
TdAS(DR) Rising Read [1,21
Data Required Valid
TwAS Width
Address Float
Falling [1,2]
TwDSR (Read) Width
TwDSW (Write) Width [1,2]
TdDSR(DR) Falling Read [1,2]
Data Required Valid
ThDR(DS) Read Data
Rising Hold Time
TdDS(A) Rising Address
Active Delay
TdDS(AS) Rising
Falling Delay
TdR/W(AS) R//W Valid
Rising Delay
TdDS(R/W) Rising
R//W Valid
TdDW(DSW) Write Data Valid
Falling (Write) Delay
TdOS(DW) Rising Write
Data Valid Delay [1,2]
TdA(DR) Address Valid Read
Data Required Valid
TdAS(DS) Rising
Falling Delay [1,2]
TdDI(DS) Data Input Setup
Rising
TdDM(AS) Valid to/AS
Falling Delay
Notes:
When using extended memory timing TpC.
Timing numbers given minimum TpC.
5.0V 3.3V Standard Test Load
timing references logic logic
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
Additional Timing Diagram
d>-l
Clock Setup
Stop Mode Recovery Source
Figure Additional Timing
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
Additional Timing Table
Symbol Parameter Units Notes
Note[6]
Input Clock Period 3.3V 100000 100000 100000 100000
5.0V 100000 100000 100000 100000
TrC.TfC Clock Input Rise 3.3V
Fall Times 5.0V
Input Clock Width 3.3V
5.0V
TwTinL Timer Input 3.3V
Width 5.0V
TwTinH Timer Input 3.3V 3TpC 3TpC 3TpC 3TpC
High Width 5.0V 3TpC 3TpC 3TpC 3TpC
TpTin Timer Input Period 3.3V 8TpC 8TpC 8TpC 8TpC
5.0V 8TpC 8TpC 8TpC 8TpC
TrTin.TfTin Timer Input Rise 3.3V
Fall Timers 5.0V
TwIL Interrupt Request 3.3V [1,2]
Time 5.0V [1,2]
TwIL Int. Request 3.3V 3TpC 3TpC 3TpC 3TpC 11,3]
Time 5.0V 3TpC 3TpC 3TpC 3TpC [1,3]
TwIH Interrupt Request 3TpC 3TpC 3TpC 3TpC [1,2]
Input High Time 5.0V 3TpC 3TpC 3TpC 3TpC [1,2]
Twsm STOP Mode
Recovery Width Spec 5.0V
3.3V 5TpC
5.0V 5TpC
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
Additional Timing Table (Continued)
Symbol Parameter Units Notes
Note[6]
Tost Oscillator 3.3V 5TpC 5TpC 5TpC 5TpC
Startup Time 5.0V 5TpC 5TpC 5TpC 5TpC
Twdt Watchdog Timer 3.3V 0(5]
Delay Time 5.0V
3.3V
5.0V
3.3V
5.0V
3.3V
5.0V
Notes:
Timing Reference uses logic V,,,. logic
Interrupt request Port (P31-P33).
Interrupt request Port (P30).
SMR-D5
Reg. WDTMR
5.0V 3.3V
Reg. D5=0
Reg. SMR-D5=1
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
Handshake Timing Diagrams
Data
/DAV (Input)
(Output)
Data Valid
Next Data Valid
Delayed
Delayed
Figure Input Handshake Timing
/DAV (Output)
(Input)
Data Valid
Next Data Valid
Delayed
Delayed
Figure Output Handshake Timing
This Material Copyrighted Respective Manufacturer
CHARACTERISTICS
Handshake Timing Table
Symbol Parameter
Note[1] Data
Direction
TsDI(DAV) Data Setup Time 3.3V
5.0V
ThDI(DAV) Data Hold Time 3.3V
5.0V
TwDAV Data Available Width 3.3V
5.0V
TdDAVI(RDY) Falling 3.3V
Falling Delay 5.0V
TdDAVId(RDY) Rising 3.3V
Falling Delay 5.0V
TdDO(DAV) Rising 3.3V
Falling Delay 5.0V
TcLDAVO(RDY) Data 3.3V
Falling Delay 5.0V
TcLDAVO(RDY) Falling 3.3V
Falling Delay 5.0V
TdRDY0(DAV) Falling 3.3V
Rising Delay 5.0V
TwRDY Width 3.3V
5.0V
TdRDYOd(DAV) Rising 3.3V
Falling Delay 5.0V
Note:
3.3V
This Material Copyrighted Respective Manufacturer
EXPANDED REGISTER FILE CONTROL REGISTERS
WDTMR
SGLK/TCLK Divide
RESERVED
Stop Mode Recovery Source
Only
Stop Delay
Stop Recovery Level
High
Stop Flag
POR'
Stop Recovery
External Clock
1024
4096
During HALT
During STOP
XTAL1 /INT Select
On-Board
Reserved
Default setting after RESET
Figure Watchdog Timer Mode Register
Default setting after RESET
Figure Stop Mode Recovery Register
This Material Copyrighted Respective Manufacturer
CONTROL REGISTER DIAGRAMS
Figure Reserved
Function
Load
Disable Count
Enable Count
Function
Load
Disable Count
Enable Count
Modes
External Clock Input
Gate Input
Trigger Input (Non-retriggerable)
Trigger input (Retriggerable)
TOUT Modes
Used
Internal Clock
Count Mode
Single Pass
Modulo
Clock Source Internal External Timing Input (TIN) Mode
Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure Prescaler Register (F3H:Write Only)
Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) Current Value (When Read)
Figure Counter/Timer Register (F4H:Read/Write)
Figure Timer Mode Register (F1H:Read/Write)
Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) Current Value (When Read)
Count Mode
Single Pass
Modulo
Prescaler Modulo (Range: 1-64 Decimal HEX)
Figure Prescaler Register (F5H:Write Only)
Figure Counter/Timer Register
Definition
Defines Output
Defines Input
Figure Port Mode Register (F6h: Write Only)
This Material Copyrighted Respective Manufacturer
Port Pull-Ups Open Drain
Port Pull-Ups Active
P31, Digital Mode
P31. Analog Mode
P32- Input Output
/DAVO/RDYO RDYOWDAVO
Input Output
Input (TIN) Output (TOUT)
-/DAV2/RDY2 RDY2//DAV2
Input Output
"Till
Interrupt Group Priority
Reserved
Reserved
IRQ1, IRQ4 Priority (Group
IRQ1 IRQ4
IRQ4 IRQ1
IRQ0, IRQ2 Priority (Group
!RQ2>IROO
IRQ0 IRQ2
IRQ3, IRQ5 Priority (Group
IRQ5 IRQ3
1RQ3 IRQ5
Figure Port Mode Register (F7H:Write Only)
Figure Interrupt Priority Register (F9H:Write Only)
Mode
Output
Input
A11-A8
Stack Selection
External
Internal
Mode Must AD7-AD0
External Memory Timing
Normal
Extended
Mode
Output
Input
A15-A12
IRQ0 Input IRQ1 Input IRQ2 Input IRQ3 Input IRQ4 IROS
Inter Edge P321 P321
Figure Interrupt Request Register (FAH:Read/Write)
Figure Ports Mode Registers (F8H:Write Only)
This Material Copyrighted Respective Manufacturer
CONTROL REGISTER DIAGRAMS (Continued)
Enables IRQO-IRQS IRQO)
Reserved
Envies Interrupts
Figure Interrupt Mask Register (FBH:Read/Write)
Expanded Register File Working Register Pointer
Figure Register Pointer (FDH:Read/Write)
R252 FLAGS
User Flag User Hall Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure Flag Register
Stack Pointer Upper Byte SP8)
Figure Stack Pointer High (FEH:Read/Write)
Stack Pointer Lower Byte (SP7 SPO)
Figure Stack Pointer (FFH:Read/Write)
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS
1000 2000 4000 8000 12000 16000
Frequency (KHz)
Legend:
5.0V 3.5V
Figure Typical Frequency
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS (Continued)
Legend:
k)c1 5.0V
loci 5.0V (SCLK Divided
Icc1 3.5V
Icc1 3.5V (SCLK Divided
Figure Typical Frequency
This Material Copyrighted Respective Manufacturer
Temperature
Legend:
3.0V 4.5V
3.5V 5.0V
4.0V -Vcc 5.5V
Figure Typical Frequency
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS (Continued)
Legend:
Figure Typical Over Temperature
This Material Copyrighted Respective Manufacturer
(mA)
(mA)
Legend:
V_=3.3V
Figure Typical Over Temperature
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS (Continued)
Temperature
Legend:
3.0V 4.5V
3.5V 5.0V
4.0V
Figure Typical Power-On Reset Time Temperature
This Material Copyrighted Respective Manufacturer
Temperature Typical Auto Latch Current Temperature
Temperature Typical Auto Latch High Current Temperature
Legend:
3.0V -Vcc
3.3V -Vcc 5.0V
3.6V -Vcc 5.5V
Figure Typical Auto-Latch Current Temperature
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS (Continued)
Frequency* 10000 (KHz)
5000
1000
Resistance Ohms)
Legend:
5.0V 33pF 3.3V 33pF
Note: internal clock frequency external clock frequency.
This chart reference only. Each process will have different characteristic curve.
Figure Typical Internal Frequency Resistance
This Material Copyrighted Respective Manufacturer
Resistance (kohms)
Legend:
Note: internal dock frequency half external dock frequency.
This chart reference only. Each process will have different characteristc curve.
Figure Typical Internal Frequency Resistance
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS (Continued)
Internal 10000 Frequency* (KHz)
5000
Capacitance (pF)
Legend:
Note: internal clock frequency half external clock frequency.
This chart reference only. Each process will have different characteristc curve. kohm
Figure Typical Internal Frequency Capacitance
This Material Copyrighted Respective Manufacturer
Temperature
Legend:
3.0V 4.5V
3.5V 5.0V
4.0V 5.5V
Figure Typical Setting Temperature
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS (Continued)
Legend:
3.0V 4.5V
3.5V 5.0V
4.0V 5.5V
Figure Typical Setting Temperature
This Material Copyrighted Respective Manufacturer
Legend:
3.0V 4.5V
3.5V 5.0V
4.0V 5.5V
Figure Typical Setting Temperature
This Material Copyrighted Respective Manufacturer
DEVICE CHARACTERISTICS (Continued)
Temperature
Legend:
3.0V 4.5V
3.5V 5.0V
4.0V 5.5V
Figure Typical Setting Temperature
This Material Copyrighted Respective Manufacturer
INSTRUCTION NOTATION
Addressing Modes. following notation used describe addressing modes instruction operations shown instruction summary.
Symbol Meaning
Indirect register pair indirect working-
register pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register working-register address
Working-register address only
Indirect-register indirect
working-register address
Indirect working-register address only
Register pair working register pair
address
Flags. Control register (R252) contains following flags:
Symbol Meaning
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flages indicated
Clear zero
clear according operation Unaffected Undefined
Symbols. following symbols used describing instruction set.
Symbol Meaning
Destination location contents
Source location contents
Condition code
Indirect address prefix
Stack Pointer
Program Counter
FLAGS Flag register (Control Register 252)
Register Pointer (R253)
Interrupt mask register (R251)
This Material Copyrighted Respective Manufacturer
CONDITION CODES
Value Mnemonic Meaning Flags
1000 Always True
0111 Carry
1111 Carry
0110 Zero
1110 Zero
1101 Plus
0101 Minus
0100 Overflow
1100 Overflow
0110 Equal
1110 Equal
1001 Greater Than Equal
0001 Less than
1010 Greater Than
0010 Less Than Equal
1111 Unsigned Greater Than Equal
0111 Unsigned Less Than
1011 Unsigned Greater Than
0011 Unsigned Less Than Equal
0000 Never True
This Material Copyrighted Respective Manufacturer
INSTRUCTION FORMATS
CCF, IRET, NOP, RCF, RET,
One-Byte Instructions
MODE
dst/src
dst/CC
CLR, CPL, DEC,
DECW, INC. INCW,
dst/src PUSH RRC, SRA, SWAP
CALL (Indrect)
1110
MODE
MODE
dst/src src/dst
ADC, ADD, AND, SBC, SUB, TCM,
LDE, LDEI, LDC, LDCI
DJNZ,
MODE
MODE
MODE
MODE
dst/src
ADDRESS
ADC, ADD, AND,
1110 SBC, SUB, TCM,
1110
ADC, ADD, AND.
1110 SBC, SUB, TCM,
1110
1110
Two-Byte Instructions
Three-Byte Instructions
INSTRUCTION SUMMARY
Note: Assignment value indicated symbol example:
indicates that source data added destination data result stored destination location.
notation "addr (n)" used refer given operand location. example:
refers destination operand.
This Material Copyrighted Respective Manufacturer
INSTRUCTION SUMMARY (Continued)
Instruction Operation Address Mode Opcode Byte (Hex) Flags Affected
dst,
dst,
dst, dst<-dst
CALL SP<-SP-2
dst,
dst<-DA
DECW
DJNZr, Range: +127, -128
HALT
Instruction Address Opcode Flags
Operation Mode Byte (Hex) Affected
INCW
IRET ******
IMR(7)<-1
JPcc,
true,
istrue,
Range: +127, -128
dst,
dst,
LDCl dst,
dst,
LDEI dst,
This Material Copyrighted Respective Manufacturer
INSTRUCTION SUMMARY (Continued)
Instruction Operation Address Mode Opcode Byte (Hex) Flags Affected
dst,
dst<-@SP; SP<-SP
PUSH SP<-SP-1;
C<-0
SP<-SP
EH-4'
LFK-I'
UjFi
dst,
C<-1
Instruction Operation Address Mode Opcode Byte (Hex) Flags Affected
STOP
dst, dst<-dst<-src
SWAP
dst, (NOT dst)
dst,
dst,
These instructions have identical addressing modes, which encoded brevity. first opcode nibble found instruction table above. second nibble expressed symbolically this table, value found following table left applicable addressing mode pair.
example, opcode instruction using addressing modes (destination) (source)
Address Mode Lower Opcode Nibble
This Material Copyrighted Respective Manufacturer
OPCODE
Lower Nibble (Hex)
10.5 10.5 10.5 10.5
10.5 10.5 10.5 10.5
10.5 10.5 10.5 10.5 IR1,
IRR1 10.5 10.5 10.5
10.5 10.5 10.5 10.5 IR1.
10.5 10.5 10.5 10.5 10.5 10.5
10.5 10.5 10.5 10.5 IR1,
10/12.1 PUSH 12/14.1 PUSH 10.5 R2.R1 10.5 10.5 IR1,
10.5 DECW 10.5 DECW 12.0 Irr2 18.0 LDEI Ir1, Irr2
12.0 18.0 LDEI Ir2,
INCW 10.5 INCW 10.5 10.5 IR2, 10.5 10.5 IR1,
10.5 10.5 IR2, 10.5 10.5 IR1,
12.0 Irr2 18.0 LDCI Irl, Irr2 10.5 r1,x,R2
12.0 Irr2 18.0 LDCI Irl, Irr2 CALL* IRR1 20.0 CALL 10.5 r2,x,R1
10.5 10.5 10.5 10.5 IR1,
SWAP SWAP Ir1, 10.5
12/10.5 DJNZ
12/10.0
12.10.0
STOP
HALT
14.0
16.0 1RET
Bytes Instruction
Execution Cycles
Lower Opcode Nibble
Upper
Nibble
Firsf Operand
R,,R2
Pipeline Cycles
Mnemonic
Second Operand
Legend:
8-bit address 4-bit address address address
Sequence
Opcode, First Operand, Second Operand
Note: Blank areas defined.
2-byte instruction appears 3-byte instruction
This Material Copyrighted Respective Manufacturer
PACKAGE INFORMATION
40-Pin Dual-ln-Line (DIP) Plastic Package
V'EV BOTTOM VIEW
DIM. FROM CENTER CENTER RADII
SEATING PLANE
.045
NOTES:
DIMENSIONS INCH,
LEADS COPLANAR WITHIN .004 RANGE.
44-Pin Plastic Chip Carrier (PLCC)
This Material Copyrighted Respective Manufacturer
PACKAGE INFORMATION (Continued)
Note:
package dimensions millimeters.
44-Pin Quad Flat Pack (QFP)
This Material Copyrighted Respective Manufacturer
ORDERING INFORMATION
Z86C90
40-Pin 40-Pin PLCC 44-Pin
Z86C9008PSC Z86C9008VSC Z86C9008FSC/
Z86C9008PEC Z86C9008VEC Z86C9008FEC
40-Pin
Z86C9012PSC Z86C9012PEC
40-Pin PLCC
Z86C9012VSC Z86C9012VEC
44-Pin
Z86C9012FSC Z86C9012FEC
Z86C89
40-Pin 40-Pin PLCC 44-Pin
Z86C8908PSC^ Z86C8908VSC Z86C8908FSC
Z86C8908PEC Z86C8908VEC Z86C8908FEC
fast results, contact your local Zilog sales olfice assistance ordering part desired.
Codes
Package
Plastic Plastic Chip Carrier Ceramic Ceramic
Longer Lead Time
Plastic Quad Flat Pack
Speed
Temperature
Example:
86C90 86C90 MHz, DIP, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
This Material Copyrighted Respective Manufacturer
ZILOG DOMESTIC SALES OFFICES INTERNATIONAL SALES OFFICES
TECHNICAL CENTERS
CALIFORNIA CANADA
Agoura 818-707-2160 Toronto.416-b73-0b34
Campbell.408-370-8120
T,,oiin .714-838-7800 GERMANY
TUSt'n.Munich.49-89-672-045
JAPAN
Tokyo
HONG KONG
Kowloon.
COLORADO
Boulder.303-494-2905
FLORIDA
Larg0.813-585-2533
GEORGIA
Norcross.404-448-9370
ILLINOIS
Schaumburg.708-517-8080
HAMPSHIRE
Nashua.603-888-8590
TAIWAN
JERSEY Taipei Clark.201-382-5700
KOREA
Seoul.
.81-3-587-0528 .852-7238979 .82-2-552-5401
SINGAPORE
Singapore.65-2357155
.886-2-741-3125
NORTH CAROLINA
Raleigh.919-790-7706
OHIO
Independence.216-447-1480
PENNSYLVANIA
Ambler.215-653-0230
TEXAS
Dallas.214-987-9987
WASHINGTON
Seattle.206-523-3591
UNITED KINGDOM
Maidenhead.44-628-392-00
byZilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold byZilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale
only. Zilog, Inc. makes warranty, express, statutory, implied
description, regarding information forth herein regarding freedom described devices from intellectual property infringement. Zilog, Inc. makes warranty mer-
chantability fitness purpose. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex -980 ZILOG CPTO 370-8056/8027
DC-2506-01
This Material Copyrighted Respective Manufacturer

44-pin package cost volt operating range power consumpt

Top Searches for this datasheet

Other recent searches