Semiconductor DM54190/DM74190, DM54191/DM74191 Synchronous Up/Dow
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National
Semiconductor
DM54190/DM74190, DM54191/DM74191 Synchronous Up/Down Counters with Mode Control
These circuits synchronous, reversible, up/down counters. 4-bit binary counter counter. Synchronous operation provided having flip-flops clocked simultaneously that outputs change simultaneously when instructed steering logic. This mode operation eliminates output counting spikes normally associated with asynchronous (ripple clock) counters.
outputs four master-slave flip-flops triggered low-to-high level transition clock input, enable input low. high enable input inhibits counting. Level changes either enable input down/up input should made only when clock input high. direction count determined level down/up input. When low, counter counts when high, counts down.
These counters fully programmable; that outputs preset either level placing load input entering desired data data inputs. output will change independent level clock input. This feature allows counters used modulo-N dividers simply modifying count length with preset inputs.
clock, down/up, load inputs buffered lower drive requirement; which significantly reduces number clock drivers, etc., required long parallel words.
outputs have been made available perform cascading function: ripple clock maximum /minimum count. latter output produces high-level output pulse with duration approximately equal complete cycle clock when counter overflows underflows. ripple
clock output produces low-level output pulse equal width low-level portion clock input when overflow underflow condition exists. counters easily cascaded feeding ripple clock output enable input succeeding counter parallel clocking used, orto clock input parallel enabling used. maximum /minimum count output used accomplish look-ahead high-speed operation.
Features
Counts 8-4-2-1 binary
Single down/up count control line
Count enable control input
Ripple clock output cascading
Asynchronously presettable with load control
Parallel outputs
Cascadable n-bit applications
Average propagation delay
Typical clock frequency
Typical power dissipation
Absolute Maximum Ratings (Note
Supply Voltage
Input Voltage 5.5V
Storage Temperature Range
"Absolute Maximum Ratings" those values beyond which safety device guaranteed. device should operated these limits. parametric values defined "Electrical Characteristics" table guaranteed absolute maximum ratings. "Recommended Operating Conditions" table will define conditions actual device operation.
Connection Diagram
Dual-ln-Line Package
INPUTS OUTPUTS INPUTS
DATA RIPPLE
DATA
DATA
ENABLE DOWN/
INPUTS
OUTPUTS
TL/R6562-T
Asynchronous inputs: input load sets
54190 74190 _54191 (J)_74191 (N)_
6-259
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Recommended Operating Conditions
Parameter DM54190,191 DM74190,191
Norn
Supply Voltage 4.75 5.25
High Level Input Voltage
Level Input Voltage
High Level Output Current -0.8 -0.8
Level Output Current
'clk Clock Frequency
Pulse Width Clock
Load
Data Setup Time
Hold Time
'fiel Load Release Time
Free Operating Temperature
'190 '191 Electrical Characteristics over recommended operating free temperature (unless otherwise noted)
Parameter Conditions (Note Units
Input Clamp Voltage Vcc= Min,
High Level Output Voltage Vcc= V|L= Max, V|H=
Level Output Voltage Vcg= Min, Iol= Min, V|L=
Input Current@Max Input Voltage Max, 5.5V
High Level Input Current 2.4V Enable
Others
Level Input Current 0.4V Enable -4.8
Others
Short Circuit Output Current (Note DM54
DM74
Supply Current (Note DM54
DM74
Note Note Noie typicals more than output shoulcf shorted time. measured with inputs grounded outputs open.
6-260
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'190 '191 Switching Characteristics (See Section Test Waveforms Output Load)
Parameter From (Input) (Output) 400S2 Units
Mill
'max Maximum Clock Frequency
tpi_H Propagation Delay Time High Levet Output Load
tpHL Propagation Delay Time High Level Output Load
tp[_n Propagation Delay Time High Level Output Data
tpHL Propagation Delay Time High Level Output Data
tpLH Propagation Delay Time High Level Output Clock Ripple Carry
tpHL Propagation Delay Time High Level Output Clock Ripple Carry
tpLH Propagation Delay Time High Level Output Clock
tpHL Propagation Delay Time High Level Output Clock
tpLH Propagation Delay Time High Level Output Clock Max/Min
tpHL Propagation Delay Time High Level Output Clock Max/Min
tpLH Propagation Delay Time High Level Output Down/Up Rippte Carry
tpHL Propagation Delay Time High Level Output Down/Up Ripple Carry
tpLH Propagation Delay Time High Level Output Down/Up Max/Min
tpHL Propagation Delay Time High Level Output Down/Up Max/Min
tPLH Propagation Delay Time High Level Output Enable Ripple Carry
tphl Propagation Delay Time High Level Output Enable Ripple Carry
6-261
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Logic Diagrams
Decade Counter
(16) Vcc. TL/F/6562-6-26This Material Copyrighted Respective Manufacturer
Logic Diagrams (Continued)
down/
data <1s> imputa
data input
data (10) input
data mput
Binary Counter
_(12)
(13) R|pple "clock (12> hax/min
"output
preset
clock
clear
output
preset
clock
.(2)
output
preset
(6),
output
J7).
output
(16) Vcc,
tuf/6562-3
6-263
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Timing Diagrams
Decade Counter Typical Load, Count, Inhibit Sequences
LOAD
Sequence:
Load (preset) seven
Count eight, nine, zero, one.
Inhibit
Count down one, zero, nine, eight, seven
DOWN
TLfF/6562-4
Decade Counter Typical Load, Count, Inhibit Sequences
CLOCK DOWN/UP ENABLE
LJTjnjnjijnjTjnjnjijn_n_rL
COUNT LOAD
Sequence:
Load (preset) binary thirteen
Count fourteen, fifteen, zero, one,
Inhibit
Count down one, zero, fifteen, fourteen, thirteen
TiTL
-iir
COUNT DOWN
TLiF/6562-5
6-264
This Material Copyrighted Respective Manufacturer
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