UP/DOWN DECADE COUNTER (With Preset Ripple Clock) '190 rever
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54/74190 ^54LS/74LS190
UP/DOWN DECADE COUNTER
(With Preset Ripple Clock)
'190 reversible (8421) decade counter featuring synchronous counting asynchronous presetting. preset feature allows '190 used programmable dividers. Count Enable input, Terminal Count output Ripple Clock output make possible variety methods implementing multi-stage counters. counting modes, state changes initiated rising edge clock.
HIGH SPEED TYPICAL COUNT FREQUENCY
SYNCHRONOUS COUNTING
ASYNCHRONOUS PARALLEL LOAD
CASCADABLE
ORDERING CODE: Section
COMMERCIAL GRADE MILITARY GRADE
PKGS +5.0 +5.0 TYPE
Plastic 74190PC, 74LS190PC
Ceramic 74190DC, 74LS190DC 54190DM, 54LS190DM
Flatpak 74190FC, 74LS190FC 54190FM, 54LS190FM
CONNECTION DIAGRAM PINOUT
Pi|T
QiQ[
CE[T
jUTC
GND[8 T]P3
LOGIC SYMBOL
INPUT LOADING/FAN-OUT: Section U.L. definitions
NAMES DESCRIPTION 54/74 (U.L.) HIGH/LOW 54/74LS (U.L.) HIGH/LOW
Count Enable Input (Active LOW) 3.0/3.0 1.5/0.75
Clock Pulse Input (Active Rising Edge) 1.0/1.0 0.5/0.25
P0-P3 Parallel Data Inputs 1.0/1.0 0.5/0.25
Asynchronous Parallel Load Input 1.0/1.0 0.5/0.25
(Active LOW)
Up/Down Count Control Input 1.0/1.0 0.5/0.25
Flip-flop Outputs 20/10 10/5.0
(2.5)
Ripple Clock Output (Active LOW) 20/10 10/5.0
(2.5)
Terminal Count Output (Active HIGH) 20/10 10/5.0
(2.5)
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LOGIC DIAGRAM
MODE SELECT TABLE
INPUTS MODE
Count
Count Down
Preset <AsynJ
Change (Hold)
HIGH VoMage Level Voilage Level Immaterial
TRUTH TABLE
INPUTS OUTPUT
generated internally
STATE DIAGRAM
COUNT
COUNT
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IDOMbT? D2T3GST
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FUNCTIONAL DESCRIPTION '190 synchronous up/down decade counter '191 synchronous up/down 4-bit binary counter. operating modes the'190 decade counter the'191 binary counter identical, with only difference being count sequences noted state diagrams. Each circuit contains four master/slave -flip-flops, with internal gating steering logic provide individual preset, count-up count-down operations.
Each circuit asynchronous parallel load capability permitting counter preset desired number. When Parallel Load input LOW, information present Parallel Data inputs loaded into counter appears outputs. This operation overrides counting functions, indicated Mode Select Table.
HIGH signal input inhibits counting. When LOW, internal state changes initiated synchronously LOW-to-HIGH transition clock input. direction counting determined input signal, indicated Mode Select Table. When counting enabled, signal made when clock either state. However, when counting inhibited, LOW-to-HIGH transition must occur only while clock HIGH. Similarly, signal should only changed when either clock HIGH. These restrictions apply 'LS190 'LS191; changed with clock either state, provided only that recommended setup hold times observed.
types outputs provided overflow/underflow indicators. Terminal Count (TC) output normally goes HIGH when circuit reaches zero count-down mode reaches maximum the'190,15 '191) count-up mode. output will then remain HIGH until state change occurs, whether counting presetting until changed. output should used clock signal because subject decoding spikes.
signal also used internally enable Ripple Clock (RC) output. output normally HIGH. When andTC HIGH, theRC output will when clock next goesLOW will stay until clock goes HIGH again. This feature simplifies design multi-stage counters, indicated Figures Figure each output used clock input next higher stage. This configuration particularly advantageous when clock source limited drive capability, since drives only first stage. prevent counting stages only necessary inhibit first stage, since HIGH signal inhibits output pulse, indicated Truth Table. disadvantage this configuration, some applications, timing skew between state changes first last stages. This represents cumulative delay clock ripples through preceding stages.
method causing state changes occur simultaneously stages shown Figure clock inputs driven parallel outputs propagate carry/borrow signals ripple fashion. this configuration state duration clock must long enough allow negative-going edge carry/borrow signal ripple through last stage before clock goes HIGH. There such restriction HIGH state duration clock, since theRC output package goes HIGH shortly after input goes HIGH.
configuration shown Figure avoids ripple delays their associated restrictions. input fora given stage formed combining signals from preceding stages. Note that order inhibit counting enable signal must included each carry gate. simple inhibit scheme Figures doesn't apply, because output given stage affected
Fig. N-Stage Counter Using Ripple Clock
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Fig. Synchronous Counter Using Carry/Borrow
DIRECTION
Fig. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow
tpHL-
IPLM
(1.3
Fig.
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CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS
Power Supply Current Inputs
CHARACTERISTICS: +5.0 (See Section waveforms load configurations)
SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS
fmax Maximum Count Frequency Figs. 3-1,
tPLH tPHL Propagation Delay
tPLH tPHL Propagation Delay
tPLH tPHL Propagation Delay Figs. 3-1,
tPLH tPHL Propagation Delay
tPLH tPHL Propagation Delay
tPLH tPHL Propagation Delay Figs. 3-1, 3-16
tPLH tPHL Propagation Delay Fig. 3-1, Fig.
tPLH tPHL Propagation Delay
OPERATING REQUIREMENTS: +5.0
SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS
Setup Time HIGH Fig. 3-13
Hold Time HIGH
Setup Time Fig.
Hold Time CEto
Pulse Width Fig.
Pulse Width Fig. 3-16
tree Recovery Time Fig. 3-16
4-284
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