16/32-BIT RISC MICROPROCESSOR USER'S MANUAL Important Notice
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S3F4A1HJ
16/32-BIT RISC MICROPROCESSOR USER'S MANUAL
Important Notice
information this publication been carefully checked believed entirely accurate time publication. Samsung assumes responsibility, however, possible errors omissions, consequences resulting from information contained herein. Samsung reserves right make changes products product specifications with intent improve function design time without notice required update this documentation reflect such changes. This publication does convey purchaser semiconductor devices described herein license under patent rights Samsung others. Samsung makes warranty, representation, guarantee regarding suitability products particular purpose, does Samsung assume liability arising application product circuit specifically disclaims liability, including without limitation consequential incidental damages. S3F4A1HJ 16/32-Bit RISC Microprocessor User's Manual, Revision Publication Number: 21-S3-F4A1HJ-022007 2007 Samsung Electronics rights reserved. part this publication reproduced, stored retrieval system, transmitted form means, electric mechanical, photocopying, recording, otherwise, without prior written consent Samsung Electronics. Samsung Electronics' microcontroller business been awarded full ISO-14001 certification (BSI Certificate FM24653). semiconductor products designed manufactured accordance with highest quality standards objectives. Samsung Electronics Co., Ltd. Nongseo-Dong, Giheung-Gu Yongin-City, Gyunggi-Do, Korea C.P.O. #37, Suwon 446-711 TEL: (82) (31) 209-4956 FAX: (82) (31) 209-3262 Home-Page URL: Http://www.samsungsemi.com Printed Republic Korea "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Samsung products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Samsung product could create situation where personal injury death occur. Should Buyer purchase Samsung product such unintended unauthorized application, Buyer shall indemnify hold Samsung officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising either directly indirectly, claim personal injury death that associated with such unintended unauthorized use, even such claim alleges that Samsung negligent regarding design manufacture said product.
Table Contents
Chapter Product Overview
Overview .1-1 Functional Description .1-1 Features.1-2 Block Diagram .1-4 Architectural Overview.1-5
Chapter
Configuration
Configuration.2-1 Assignments.2-2 Description .2-5
Chapter Chapter
Memory Module Generic Functions
Registers access .4-1 Enable Disable Status Registers .4-1 Access Registers.4-2 Registers Undefined Bits .4-2 Ghost Registers .4-3 Power Management Block .4-4
Chapter
Analog Digital Converter
Overview .5-1 Functional Description .5-1 Block Diagram .5-2 External Description .5-3 Functional Operation .5-4 Detailed Functionalities.5-4 Software Sequence Conversion.5-9 Registers Description .5-10
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Table Contents (Continued)
Chapter Capture Module (CAPT)
Overview. Functional Description External Description. Functional Operation Mode Operation Capture's limits. Programming Examples. Registers Description.
Chapter
Clock Manager
Overview. Functional Description Block Diagram. Functional Operation Clock Management Clock Power Supply Monitoring 7-57 Reset Management. 7-57 Registers Description. 7-59
Chapter
Controller Area Network (CANB)
Overview. Functional Description Block Diagram. Interface Description. External Description. Functional Operation Protocol Operating Modes. 8-27 Application 8-34 Registers Description. 8-54
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Table Contents (Continued)
Chapter Data Flash Controller (DFC)
Overview .9-1 Functional Description .9-1 Block Diagram .9-2 Functional Operation .9-3 Internal Data Flash Controller.9-3 Read Access.9-4 Erase Cycle .9-5 Write Cycle .9-9 Standby Mode.9-10 Interrupts Generation.9-10 Data Abort Generation.9-10 Registers Description .9-11
Chapter
General Purpose (PIO)
Overview .10-1 Functional Description .10-1 Block Diagram .10-1 Functional Operation .10-2 Controller Block .10-2 Registers Description .10-4
Chapter
General Purpose Timer (GPT)
Overview .11-1 Functional Description .11-1 Block Diagram .11-2 External Description .11-3 Functional Operation .11-4 General Description .11-4 Timer Capture Mode .11-10 Timer Waveform Mode .11-14 Timer Block Programming .11-20 Programming Examples .11-22 Programming Examples .11-22 Registers Description .11-23
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Table Contents (Continued)
Chapter Generic Interrupt Controller (GIC)
Overview. 12-1 Functional Description 12-1 Blcok Diagram. 12-3 External Description. 12-3 Functional Operation 12-4 Interrupt Handling 12-4 Standard Interrupt Sequence. 12-6 Fast Interrupt Sequence 12-7 Spurious Interrupt Sequence 12-8 Registers Description. 12-9
Chapter
Configuration (IOCONF)
Overview. 13-1 Functional Description 13-1 Block Diagram. 13-1 Functional Operation 13-2 Configuration 13-2 Pinout Configuration 13-2 Registers Description. 13-9
Chapter
Overview. 14-1 Functional Description 14-1 Block Diagram. 14-1 External Description 14-2 Functional Operation 14-3 Concept 14-3 Registers Description. 14-17 Timings 14-41
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Table Contents (Continued)
Chapter Interleave Program Flash Memory
Overview .15-1 Functional Description .15-1 Block Diagram .15-2 Functional Operation .15-3 Interleaved Flash .15-3 Read Access.15-6 Erase Cycle .15-7 Write Cycle .15-10 Interrupts Generation.15-11 Data Abort Generation.15-11 Registers Description .15-12
Chapter
Internal Controller (IRC)
Overview .16-1 Functional Description .16-1 Registers Description .16-2
Chapter
Controller (LCDC)
Overview .17-1 Functional Description .17-1 External Description .17-1 Functional Operation .17-2 Controller .17-2 Timings.17-5 Static Mode.17-5 Duty, Bias Mode .17-6 Duty, Bias Mode .17-8 Duty, Bias Mode .17-10 Duty, Bias Mode .17-12 Registers Description .17-19
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Table Contents (Continued)
Chapter Lite Direct Memory Access (LDMA)
Overview. 18-1 Functional Description 18-1 Block Diagram. 18-1 Functional Operation 18-2 Lite Direct Memory Access 18-2 LDMA with Hardware Trigger. 18-3 LDMA with Software Trigger 18-5 Priority Management. 18-6 LDMA User Interface 18-7 Power Management. 18-9 Debug Mode. 18-9 Registers Description. 18-10
Chapter
Pulse Width Modulation (PWM)
Overview. 19-1 Functional Description 19-1 Block Diagram. 19-1 External Description 19-2 Functional Operation 19-2 Parameters. 19-2 Programming Examples. 19-2 Registers Description. 19-4
Chapter
Serial Peripheral Interface 16-Bit (SPI16)
Overview. 20-1 Functional Description 20-1 External Description 20-1 Description 20-2 Functional Operation 20-2 Master mode 20-2 Slave Mode 20-6 Timings 20-7 Timings Module. 20-7 Timings Values. 20-9 Registers Description. 20-10
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Table Contents (Continued)
Chapter Serial Peripheral Interface 8-Bit (SPI8)
Overview .21-1 Functional Description .21-1 Block Diagram .21-2 External Description .21-2 Functional Operation .21-3 Master Mode.21-3 Slave Mode.21-7 Timings.21-8 Timings Module .21-8 Registers Description .21-11
Chapter
Simple Timer (ST)
Overview .22-1 Functional Description .22-1 Functional Operation .22-2 General Description .22-2 Example.22-4 Registers Description .22-5
Chapter
Special Function Module (SFM)
Overview .23-1 Functional Description .23-1 Registers Description.23-2
Chapter
Stamp Timer (STT)
Overview .24-1 Functional Description .24-1 Block Diagram .24-1 Functional Operation .24-2 Timer Functionality .24-2 Programming Examples .24-3 Registers Description .24-4
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Table Contents (Continued)
Chapter Stepper Motor Controller (SMC)
Overview. 25-1 Functional Description 25-1 Block Diagram. 25-2 External Description 25-3 Functional Operation 25-3 Operation Overview 25-3 Mode 25-3 Stepper Motor Mode 25-5 Programming Examples. 25-13 Registers Description. 25-14
Chapter
Universal Sync/Async Receiver/Transmitter (USART)
Overview. 26-1 Functional Description 26-1 Block Diagram. 26-2 External Description 26-2 Functional Operation 26-3 Baud Rate Generator. 26-3 Receiver 26-6 Transmitter 26-9 Break. 26-10 Interrupts 26-10 Test Modes 26-10 Protocol (Compliant with LIN1.2 LIN2.0 Releases). 26-11 Smart-Card Protocol 26-13 Programming Examples. 26-14 Registers Description. 25-16
Chapter
Watchdog (WD)
Overview. 27-1 Functional Description 27-1 Functional Operation 27-2 Watchdog Functionality. 27-2 Example 27-4 Registers Description. 27-5
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Table Contents (Continued)
Chapter
Electrical Data
Absolute Maximum Ratings .28-1 Recommended Operating Conditions .28-2 D.C. Electrical Characteristics.28-3
Chapter
Package Specifications
S3F4A1HJ MICROCONTROLLER
List Figures
Figure Number 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 Title Page Number
S3F4A1HJ Block Diagram .1-3 Configuration.2-1 S3F4A1HJ Default Memory after Reset.3-1 Block Diagram .5-2 Capture Resynchronization .6-2 Clock Manager Block Diagram .7-2 Clock Manager State Machine.7-4 Transition Diagram: Hardware Reset NORMAL Mode .7-10 Transition Diagram: Reset CKFAIL mode.7-11 Normal Mode High Speed Mode.7-12 Normal Mode IDLE-Normal Speed Mode .7-13 IDLE-Normal Mode Normal Speed Mode .7-14 Transition Diagram: NORMAL Mode SLOW mode .7-15 Normal Mode Power Mode (LF_SEL 0).7-16 Transition Diagram: NORMAL Mode LOWPOWER Mode (LFSEL=1).7-17 Transition Diagram: NORMAL Mode HALT Mode (LFSEL=0) .7-18 Transition Diagram: NORMAL Mode HALT Mode (LFSEL=1) .7-19 Transition Diagram: NORMAL Mode STOP Mode .7-20 Transition Diagram: LOWPOWER Mode IDLE-LOWPOWER Mode (LFSEL=0).7-21 Transition Diagram: LOWPOWER Mode IDLE-LOWPOWER Mode (LFSEL=1).7-22 Transition Diagram: IDLE-LOWPOWER Mode LOWPOWER Mode (LFSEL=0).7-23 Transition Diagram: IDLE-LOWPOWER Mode LOWPOWER Mode (LFSEL=1).7-24 Transition Diagram: LOWPOWER Mode NORMAL Mode (LFSEL=0).7-25 Transition Diagram: LOWPOWER Mode NORMAL Mode (LFSEL=1).7-26 Transition Diagram: LOWPOWER Mode HIGHSPEED Mode (LFSEL=0).7-27 Transition Diagram: LOWPOWER Mode HIGHSPEED Mode (LFSEL=1).7-28 Transition Diagram: LOWPOWER Mode SLOW Mode .7-29 Transition Diagram: LOWPOWER Mode HALT Mode (LFSEL==0).7-30 Transition Diagram: LOWPOWER Mode HALT Mode (LFSEL==1).7-31 Transition Diagram: SLOW Mode IDLE-SLOW Mode .7-32 Transition Diagram: IDLE-SLOW Mode SLOW Mode .7-33 Transition Diagram: SLOW Mode NORMAL Mode .7-34 Transition Diagram: SLOW Mode HIGHSPEED Mode.7-35 Transition Diagram: SLOW Mode LOWPOWER Mode .7-36 Transition Diagram: SLOW Mode HALT Mode.7-37 Transition Diagram: HIGHSPEED Mode IDLE-HIGHSPEED Mode.7-38 Transition Diagram: HIGHSPEED Mode IDLE-HIGHSPEED Mode.7-39 Transition Diagram: HIGHSPEED Mode NORMAL Mode.7-40 Transition Diagram: HIGHSPEED Mode SLOW Mode.7-41 Transition Diagram: HIGHSPEED Mode LOWPOWER Mode (LFSEL=0).7-42
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List Figures (Continued)
Figure Number 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 Title Page Number
Transition Diagram: HIGHSPEED Mode LOWPOWER Mode (LFSEL=1) 7-43 Transition Diagram: HIGHSPEED Mode HALT Mode (LFSEL=0). 7-44 Transition Diagram: HIGHSPEED Mode HALT Mode (LFSEL=1). 7-45 Transition Diagram: HALT Mode NORMAL Mode (LFSEL=0). 7-46 Transition Diagram: HALT Mode NORMAL Mode (LFSEL=1). 7-47 Transition Diagram: HALT Mode HIGHSPEED Mode (LFSEL=0). 7-48 Transition Diagram: HALT Mode HIGHSPEED Mode (LFSEL=1). 7-49 Transition Diagram: HALT Mode SLOW Mode 7-50 Transition Diagram: HALT Mode LOWPOWER Mode (LFSEL=0) 7-51 Transition Diagram: HALT Mode LOWPOWER Mode (LFSEL=1) 7-52 Transition Diagram: STOP Mode NORMAL Mode (LFSEL=0) 7-53 Transition Diagram: STOP Mode NORMAL Mode (LFSEL=1) 7-54 Frequency Transition: DIVOUT RINGCLK 7-55 Frequency Transition: RINGCLK DIVOUT 7-56 Reset Manager Diagram 7-58 Instruction Follows Peripheral Write Access Instruction 7-68 Peripheral access follows peripheral write access instruction 7-69 Block Diagram. Layers Description Data Frame. 8-10 Standard Format. 8-11 Extended Format 8-11 Control Field. 8-12 Field 8-13 Field 8-14 Remote Frame. 8-15 Error Frame 8-16 Overload Frame. 8-17 Interframe Space Receiver 8-18 Interframe Space Transmitter 8-18 Partition Time 8-23 Example Nominal Time 8-25 Core Silent Mode 8-30 Core Loop Back Mode 8-31 Core Loop Back Combined with Silent Mode 8-32 Data Transfer Between Registers Message 8-35 Handling FIFO Buffer. 8-41 Timing. 8-43 Propagation Time Segment. 8-44 Synchronization Late Early Edges 8-46 Filtering Short Dominant Spikes. 8-48 Structure Controller Core. 8-50 Time Built from Time Quantum 8-62 Open Drain Mode 8-95
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List Figures (Continued)
Figure Number 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 12-1 13-1 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 Title Page Number
Data Flash Memory Controller Block Diagram .9-2 Data Flash Segmentation .9-3 Read Access Timing Diagram .9-4 Chip Erase Flow Chart .9-6 Sector Erase Flow Chart.9-7 Page Erase Flow Chart .9-8 Write Flow Chart .9-9 Block Diagram.10-1 General Purpose Timer channels) Block Diagram .11-2 Clock Selection Block Diagram.11-5 Burst Clock Timing Diagram .11-6 Counter Reset Diagram .11-7 TIOA Pulse.11-11 TIOA Edges.11-12 TIOA Pulse Period .11-13 Counter TCLK .11-13 Dual Pulse Width Modulation.11-15 Square Signals.11-16 Pulse Generation .11-17 Single Waveform with Trigger TIOB .11-18 Event Counter .11-19 General Purpose Timer Block Programming Diagram .11-20 Application with General Purpose Timer Block Programming .11-21 Generic Interrupt Controller Block Diagram .12-3 Configuration Module Block Diagram.13-1 Block Diagram .14-1 Data Validity .14-5 Start Stop Conditions .14-6 Data Transfer .14-7 Acknowledge.14-8 master-Transmitter Addresses Slave .14-10 master-Transmitter Addresses Slave-Receiver with 10-bits Address .14-16 Hold Setup Delays .14-40
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List Figures (Continued)
Figure Number 15-1 15-2 15-3 15-4 15-5 15-6 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 18-1 18-2 18-3 18-4 19-1 19-2 20-1 20-2 20-3 20-4 20-5 20-6 20-7 Title Page Number
Interleaved Program Flash Memory Controller Block Diagram. 15-2 Interleaved Memory. 15-4 Flash Data Timing 15-5 Chip Erase Flow Chart 15-8 Sector Erase Flow Chart 15-9 Write Flow Chart. 15-10 Controller Block Diagram 17-2 Bias Driver. 17-4 COM/SEG Signals Under Static Mode. 17-5 COM/SEG Signals Under Duty Bias Mode 17-7 COM/SEG Signals Under Duty Bias Mode 17-9 COM/SEG Signals Under Duty Bias Mode 17-11 COM/SEG Signals Under Duty Bias Mode 17-13 Connection Example Static Mode 17-14 Connection Example Duty, Bias 17-15 Connection Example Duty, Bias 17-16 Connection Example Duty, Bias 17-17 Connection Example Duty, Bias 17-18 LDMA Block Diagram 18-1 LDMA with Peripherals. 18-2 Example Transfers From Memory Peripheral 18-4 Example Transfers From Peripheral Memory 18-5 Block Diagram 19-1 Example. 19-4 SPI16 Block Diagram Master Mode 20-4 SPI16 Flow Diagram Master Mode. 20-5 SIP16 Slave Mode. 20-6 SPI16 Block Diagram Master Mode, phase=0 20-7 SPI16 Master Mode, phase=1. 20-7 DLYBCS, DLYBS DLYBCT 20-8 SPI16 Timings 20-8
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List Figures (Continued)
Figure Number 21-1 21-2 21-3 21-4 21-5 21-6 21-7 22-1 24-1 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 27-1 29-1 Title Page Number
SPI8 Block Diagram .21-2 SPI8 Flow Chart Master Mode .21-5 SPI8 Master Mode.21-6 SPI8 Slave Mode.21-7 SPI8 Master Mode, Phase=0 .21-8 SPI8 Master Mode, Phase=1 .21-8 SPI8 Timings.21-9 Simple Timer Block Diagram .22-3 Simple Timer Block Diagram .24-1 Block Diagram.25-2 Stepper Motor Connection .25-5 Phase Full Stepping .25-6 Phase Full Stepping .25-7 Half Stepping.25-8 Cosinus/Sinus Microstepping.25-9 High Torque Microstepping.25-10 Example .25-13 USART Block Diagram.26-2 USART Baud Rate Generator Block Diagram .26-4 Asynchronous Mode, Start Detection .26-6 Asynchronous Mode, Character Reception .26-6 Synchronous Mode, Character Reception .26-7 IDLE Flag .26-8 Synchronous Asynchronous Modes, Character Transmission.26-9 Message Characteristics.26-12 Smart-Card Transmission Error .26-13 Error Signaling Reception .26-14 Watchdog Block Diagram .27-3 Package Dimensions .29-1
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List Tables
Table Number 7-10 7-11 7-12 7-13 7-14 8-10 8-11 8-12 8-13 Title Page Number
Assignments-Pin Number Order .2-2 Description .2-7 Base Address Peripheral Special Registers.3-1 Description .5-3 NBRCH[3:0] Values Number Conversions .5-4 Values Selected Input .5-5 Status Bits Reflecting Power Management.5-8 Memory Map.5-10 NBRCH[3:0] Values Number Conversions .5-16 Ready Conversion .5-18 CAPT Description .6-1 Capture Special Function Registers .6-4 Clock Sources .7-3 Derived Clock Sources.7-3 Oscillators Activity .7-5 Clock Transition .7-6 Reset Sources.7-57 Clock Manager Memory Map.7-59 Multiplier Parameter .7-63 Post Scalar Parameter .7-64 Divider Parameter.7-64 PLLPRE/PMUL/PLLPOST Allowed Values .7-65 Peripheral Divider.7-67 Clock Manager Modes .7-70 Core-Clock Divider .7-72 Frequency Oscillator Clock Divider .7-73 Description .8-3 Identifier Length Within Standard Extended Frame.8-9 Bit.8-12 .8-12 Data Length Code .8-13 Interface Register Sets.8-28 Message Object Content .8-29 Initialization Transmit Object.8-37 Initialization Receive Object.8-38 Parameters Time.8-43 Special Function Register .8-54 rate Minimal Core Frequency .8-62 Control CAN_TX .8-95
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List Tables (Continued)
Table Number 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 12-1 12-2 12-3 12-4 12-5 13-1 13-2 Title Page Number
Special Function Registers 9-11 Special Function Registers 10-4 Descriptions Corresponding Operation Modes 11-3 Available Interrupts. 11-9 Special Function Resisters 11-23 Multi Channels Control Registers Memory Map. 11-23 Clock Select. 11-28 Burst 11-29 External Trigger Edge 11-30 Load 11-30 Clock Select. 11-31 Burst 11-32 External Event Edge. 11-33 External Event 11-33 Effect TIOA Event. 11-34 Effect TIOB Event. 11-35 Interrupt Sources 12-1 Generic Interrupt Controller Description 12-3 Priority Levels 12-4 Special Function Registers 12-9 Interrupt Source Type Field. 12-10 Configuration 13-2 IOCONF Special Function Registers. 13-9
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List Tables (Continued)
Table Number 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 15-1 15-2 16-1 Title Page Number
Description .14-2 Examples Baud Rate Configuration.14-4 Definition Bytes First Byte .14-11 Special Function Registers.14-17 Values FSCL Depending PRV, FAST PCLK .14-24 Master/Transmitter Mode Status Codes .14-26 Master/Receiver Mode Status Codes .14-27 Slave/Receiver Mode Status Codes .14-29 Slave/Transmitter Mode Status Codes .14-32 Miscellaneous Status Codes.14-34 Timing Requirements .14-41 Special Function Registers .15-12 Sector Number .15-14 Special Function Registers .16-2
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List Tables (Continued)
Table Number 17-1 17-2 18-1 18-2 19-1 19-2 20-1 20-2 20-3 20-4 20-5 21-1 21-2 21-3 21-4 21-5 21-6 21-7 22-1 23-1 23-2 23-3 23-4 23-5 24-1 Title Page Number
Description 17-1 LCDC Special Function Registers. 17-19 LDMA Special Function Registers. 18-10 LDMA Transfers Size 18-21 Description 19-2 Special Function Registers. 19-5 SPI16 Description 20-1 SPI16 Timing Values. 20-9 SPI16 Special Function Registers. 20-10 Bits Transfer. 20-26 Baudrate 20-27 SPI8 Description 21-2 SPI8 Timing Values 21-10 SPI8 Special Function Registers. 21-11 Bits Transfer. 21-26 Baudrate 21-26 Delay Before SPCK. 21-27 Delay between Consecutive Transfers 21-27 Simple Timer Special Function Registers 22-5 Special Function Registers 23-2 Type Chip 23-3 Chip Architecture 23-4 Memory type. 23-5 Memory type. 23-5 Stamp Timer Special Function Registers. 24-4
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List Tables (Continued)
Table Number 25-1 25-2 25-3 25-4 25-5 25-6 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 26-11 26-12 26-13 26-14 27-1 27-2 28-1 28-2 28-3 28-4 28-5 28-6 28-7 28-8 28-9 28-10 28-11 28-12 28-13 28-14 Title Page Number
Description .25-3 Limits Frequency .25-4 Special Function Registers .25-14 Relation Between NCM[2:0] Number Cycle microstep .25-21 Relation Between NMSQ[1:0] Number microstep Sinusoid Quarter .25-21 Relation Between DM[2:0] Driving Method.25-22 USART Description.26-2 Asynchronous Mode (SYNC 0).26-4 Synchronous Mode (SYNC 1).26-5 USART Special Function Registers .26-16 SENDTIME Configuration Field .26-22 CLKS Clock Selection Field .26-23 Character Length Field.26-23 Parity Type Field .26-23 NBSTOP Configuration Field .26-24 Channel Mode Field .26-24 Clock Divisor Field .26-38 Time-Out Configuration Field.26-39 Time-Guard Configuration Field.26-40 Number Data Field LIN1.2 Release.26-41 Watchdog Special Function Registers .27-5 Watchdog Clock Divider.27-10 Absolute Maximum Ratings .28-1 Recommended Operating Conditions.28-2 D.C. Electrical Characteristics I/O).28-3 D.C. Electrical Characteristics (3.3V I/O).28-5 Current Consumption .28-7 Oscillation Characteristics.28-7 Oscillation Stabilization Time .28-8 Internal Oscillation Characteristics .28-8 Characteristics .28-8 Input/Output Capacitance .28-9 A.C. Electrical Characteristics.28-9 A.C. Electrical Characteristics Internal Flash .28-10 Electrical Characteristics .28-10 D.C. Electrical Characteristics Controller .28-11
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List Important Notice
Notice Number 7-10 7-11 7-12 7-13 7-14 12-1 15-1 17-1 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 Title Page Number
Regarding SPGM_nBOOT connection flash writing mode Regarding STOP command continuous mode Regarding writing access CM_PSTR register. 7-62 Regarding writing access CM_PDPR register 7-63 Regarding PLLPRE, PMUL PLLPOST values 7-65 Regarding frequency APB(PCLK) 7-65 Regarding CM_DIVBR register case external clock. 7-67 Regarding clock frequency between PCLK SCLK 7-68 Regarding clock management case Slow, power, Halt mode 7-70 Regarding mode transition STABLE interrupt 7-70 Regarding divided master clock frquency 7-72 Regarding changing MDIV value CM_MDIVR register 7-72 Regarding changing LDIV value CM_MDIVR register 7-73 Regarding configuration changing frequency 7-74 Regarding LFUSED CM_STR register. 7-74 Regarding STOP mode STOPMODE 7-75 Regarding message object number 8-28 Regarding message object number 8-81 Regarding control standby mode STANDEN 9-17 Regarding clear pending interrupts 12-16 Regarding SPEEDMODE switching Mode 15-16 Regarding configuration. 17-1 Regarding transfer huge number data 18-5 Regarding channel priority during transfer 18-6 Regarding transfer size LDMA 18-7 Regarding LDMA register modification with debug state 18-9 Regarding writing access LDMA_MR register 18-21 Regarding CHEN LDMA status register 18-23 Regarding writing access LDMA_ASRCR register 18-27 Regarding writing access LDMA_ADSTR register. 18-28 Regarding writing access LDMA_CNTRX register. 18-29
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List Important Notice (Continued)
Notice Number 22-1 22-2 22-3 22-4 22-5 22-6 22-7 24-1 24-2 24-3 24-4 24-5 25-1 25-2 25-3 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 Title Page Number
Regarding condition between LFCLK PCLK ST0.22-9 Regarding simple timer en/disable with software reset .22-9 Regarding restart simple timer.22-11 Regarding condition writing access ST_PR0 register .22-15 Regarding value ST_CT0 register auto-reload mode .22-16 Regarding condition writing access ST_PR1 register .22-17 Regarding value ST_CT1 register auto-reload mode .22-18 Regarding internal oscillator clock .24-3 Regarding condition LFCLK clock .24-8 Regarding writing access CNTRST STT_MR register .24-9 Regarding writing access STT_CNT register invalid data .24-16 Regarding writing access STT_ALR register invalid data.24-17 Regarding condition write value into SMC_DLY0/1 register.25-28 Regarding condition write value into SMC_PUL0/1 register.25-29 Regarding condition write value into SMC_TPR register .25-30 Regarding non-effected US_PMSR register software reset .26-19 Regarding setting LIN2_0 during message transfer .26-22 Regarding RXRDY clear reading US_RHR register .26-36 Regarding setting US_BRGR value under synchronous mode.26-38 Regarding timeout operation receiver disable re-enable .26-39 Regarding writing access US_LIR register during message transfer .26-41 Regarding writing access US_DFWR0 during message transfer.26-42 Regarding writing access US_DFWR1 during message transfer.26-43 Regarding writing access US_SBLR during message transfer .26-46
S3F4A1HJ MICROCONTROLLER
S3F4A1HJ
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
FUNCTIONAL DESCRIPTION SAMSUNG S3F4A1HJ 16/32-bit RISC micro-controller cost-effective high-performance solution general micro-controller application. outstanding feature S3F4A1HJ core, 16/32-bit RISC processor (ARM7TDMI-S) designed advanced RISC machines, Ltd. ARM7TDMI-S core low-power, general-purpose, microprocessor macrocell which developed application-specific customer-specific integrated circuits. simple, elegant, fully static design particularly suitable cost-sensitive power-sensitive applications. Other feature integration 512Kbytes 32Kbytes type flash, 16Kbytes SRAM, CAN, LIN, LCD, Stepper Motor Controller. providing complete common system peripherals, S3F4A1HJ minimize overall system costs eliminate need configure additional components, externally. S3F4A1HJ developed using ARM7TDMI-S core, CMOS standard cell, data path compiler. Most on-chip function blocks will designed using synthesizer. S3F4A1HJ will fully verified SAMSUNG ASIC test environment including internal qualification assurance process.
PRODUCT OVERVIEW
S3F4A1HJ
FEATURES Architecture ARM7TDMI-S Core 16/32-bit RISC architecture JTAG-based debugging solution Program Flash Memory 512Kbytes internal Flash Support high normal speed mode Data Flash Memory 32Kbytes internal Flash Memory 16Kbytes internal SRAM Support changeable base address
Controller channels with 32buffers CAN0, CAN1 Support 2.0A 2.0B Full Speed Stampable message CAPTURE 16bit capture module CAPT0 LDMA channel Pulse Width Modulations (PWM) channels 16bit PWM0, PWM1 channels 8bit PWM2~PWM5 Stepper Motor Controllers (SMC) channels SM[00:03] SM[30:33] Mode Micro-stepping cosinus/sinus high torque Stamp Timer (STT) channels 32-bit Timer Alarm interrupt Converters (ADC) channel analog inputs AIN[15:0] 10bit resolution, 500KSps conversion rate LDMA channel UART- channels UART0, UART1, USART0 Support hardware Support 5,6,7,8, 9bit data length Support J1587 protocol channel, USART0, support synchronous transfer LDMA channels Interface (I2C) channels, Multi-master IIC-Bus Serial, 8-bit oriented bi-directional data transfers made 100Kbit/s stand mode 400Kbit/s fast mode
Clock Generator with Configurable Programmable clock synthesizer (Max. 40MHz) Lite Direct Memory Access (LDMA) channels Transfer from peripheral memory Transfer from memory memory Interrupt Controller (GIC) interrupt lines internal external interrupt lines 16-Level priority vectored interrupt General Purpose multiplexed GPI/O 16bit General Purpose Timer (GPT) channels GPT0, GPT1, GPT2 configurable modes: Counter, PWM, Capture Support capture/compares 16bit Simple Timer (ST) channels simple timer channels simple timer Core Clock Frequency Clock
S3F4A1HJ
PRODUCT OVERVIEW
FEATURES (Continued) Controller (LCDC) 4com segment Static, bias mode Interface 8-bit programmable data length, SPI0 16-bit programmable data length, SPI1 Support Master Slave mode LDMA channels Watchdog (WD) Programmable watchdog timer Clock Manager (CM) Internal Ring oscillator (Typ.1MHz) Peripherals deactivated individually Clock monitor Voltage Detector (LVD) Internal reset generation: Typ. 2.4V Interrupt generation: Typ. 4.2V Power Reset (POR) Operating Frequency Range 6MHz External Crystal 40MHz Operating Voltage Range 5.5V except ADC, ADC, Stepper Motor: 5.5V Operating Temperature Range 85°C
Available TQFP Package
PRODUCT OVERVIEW
S3F4A1HJ
BLOCK DIAGRAM
MD[1:0] NRESET
JTAG Interface Generic Interrupt Controller 16KB
IRQ[19:0]
Embedded ARM7TDMI-S Core
AMBA Bridge
Program Flash (512KB) Data Flash (32KB) XOUT
NSS0 SPCK0 MOSI0 MISO0 NPCS[3:0] SPCK1 MOSI1 MISO1 UARTTXD0 UARTRXD0
SPI0 (8-bit)
Ring 1MHz
SPI1 (16-bit)
ST1(CORECLK)
LCDC
SEG[29:0] COM[3:0]
UART-LIN0 TCLK[2:0] TIOA[2:0] TIOB[2:0]
UARTTXD1 UARTRXD1
UART-LIN1
ST0(LFCLK)
USARTTXD0 USARTRXD0 USARTCLK0 SCL0 SDA0 SCL1 SDA1 CANTX0 CANRX0 CANTX1 CANRX1 CAPTURE0
USART-LIN0 I2C0 I2C1 CAN0 buffers) CAN1 buffers) CAPTURE0 SM/PWM 10-bit ADC0 16-channels SM[00:03]/PWM2 SM[10:13]/PWM3 SM[20:23]/PWM4 SM[30:33]/PWM5 AIN[15:0] AVREF ADTRG PWM[1:0]
Figure 1-1. S3F4A1HJ Block Diagram
S3F4A1HJ
PRODUCT OVERVIEW
ARCHITECTURAL OVERVIEW S3F4A1HJ architecture consists main buses, Advanced System (ASB) Advanced Peripheral (APB). designed maximum performance. interfaces processor on-chip 32-bit memories. designed accesses on-chip peripherals optimized power consumption. AMBA bridge provides interface between APB. S3F4A1HJ peripherals designed programmed with minimum number instructions. Each peripheral space bytes address allocated upper bytes bytes address space. Except interrupt controller, peripheral base address lowest address memory space. peripheral register composed control, mode, data, status interrupt registers. S3F4A1HJ microcontroller operates little-endian mode. processor's internal architecture THUMB instruction sets described ARM7TDMI-S data sheet. memory on-chip peripherals described sub-sequent sections this data sheet. Standard In-Circuit-Emulation debug interface supported port S3F4A1HJ microcontroller (this standard IEEE 1149.1 JTAG Boundary Scan interface).
S3F4A1HJ
CONFIGURATION
CONFIGURATION
CONFIGURATION
P2.15/TIOB2/AIN15 P2.14/TIOA2/AIN14 P2.13/CAPT0/AIN13 P2.12/IRQ11/AIN12 P2.11/IRQ10/ANI11 P2.10/AIN10 P2.9/AIN9 P2.8/AIN8 P2.7/AIN7 P2.6/AIN6
VSSIO0 VDDIO0 VDDCORE0 VSSCORE0 VDDCOREOUT XOUT nRESET/nTRST AVSS AVREF AVDD
VDDIO1 VSSIO1 VDDCORE1 VSSCORE1 VLCD P0.22/COM0 P0.23/COM1 P0.24/COM2 P0.25/COM3 P1.0/SEG0 P1.1/SEG1 P1.2/SEG2 P1.3/SEG3 P1.4/SEG4 P1.5/SEG5 P1.6/SEG6 P1.7/SEG7 P1.8/SEG8 P1.9/SEG9 P1.10/SEG10 P1.11/SEG11 P1.12/SEG12
VDDPLLOUT P0.0/NSS0/SM00 P0.1/MISO0/SM01 P0.2/MOSI0/SM02 P0.3/SPCK0/SM03 P0.4/IRQ0/SM10 P0.5/TCLK0/SM11 P0.6/TCLK1/SM12 P0.7/TCLK2/SM13 P0.8/UARTRXD1/SM20 P0.9/UARTTXD1/SM21 P0.10/TIOA1/SM22 P0.11/TIOB1/SM23 P0.12/IRQ1/SM30 P0.13/USARTCLK0/SM31 P0.14/USARTRXD0/SM32 P0.15/USARTTXD0/SM33 VDDIO2 VSSIO2 P0.16/CANRXD0/IRQ2 P0.17/CANTXD0/IRQ3 P0.18/UARTRXD0/IRQ4 P0.19/UARTTXD0/IRQ5 P0.20/TIOA0/SDA1 P0.21/TIOB0/SCL1
S3F4A1HJ (100-TQFP)
P2.5/AIN5 P2.4/AIN4 P2.3/AIN3 P2.2/AIN2 P2.1/AIN1 P2.0/AIN0 P1.31/ADTRG/SCL0 P1.30/IRQ9/SDA0 P1.29/CANTXD1/SEG29 P1.28/CANRXD1/SEG28 P1.27/PWM1/SEG27 P1.26/PWM0/SEG26 P1.25/SPCK1/SEG25 P1.24/MOSI1/SEG24 P1.23/MISO1/SEG23 P1.22/NPCS0/SEG22 P1.21/NPCS1/SEG21 P1.20/NPCS2/SEG20 P1.19/NPCS3/SEG19 P1.18/IRQ8/SEG18 P1.17/IRQ7/SEG17 P1.16/IRQ6/SEG16 P1.15/SEG15 P1.14/SEG14 P1.13/SEG13
Figure 2-1. Configuration
CONFIGURATION
S3F4A1HJ
ASSIGNMENTS
Table 2-1. Assignments-Pin Number Order Name VDDPLLOUT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 VDDIO2 VSSIO2 P0.16 P0.17 P0.18 P0.19 P0.20 P0.21 VDDIO1 VSSIO1 VDDCORE1 VSSCORE1 VLCD Name NSS0 MISO0 MOSI0 SPCK0 IRQ0 TCLK0 TCLK1 TCLK2 UARTRXD1 UARTTXD1 TIOA1 TIOB1 IRQ1 USARTCLK0 USARTRXD0 USARTTXD0 CANRXD0 CANTXD0 UARTRXD0 UARTTXD0 TIOA0 TIOB0 Name SM00 SM01 SM02 SM03 SM10 SM11 SM12 SM13 SM20 SM21 SM22 SM23 SM30 SM31 SM32 SM33 IRQ2 IRQ3 IRQ4 IRQ5 SDA1 SCL1 Flash
S3F4A1HJ
CONFIGURATION
Table 2-1. Assignments-Pin Number Order (Continued) Name P0.22 P0.23 P0.24 P0.25 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 P1.16 P1.17 P1.18 P1.19 P1.20 P1.21 P1.22 P1.23 P1.24 P1.25 P1.26 P1.27 P1.28 P1.29 Name IRQ6 IRQ7 IRQ8 NPCS3 NPCS2 NPCS1 NPCS0 MISO1 MOSI1 SPCK1 PWM0 PWM1 CANRXD1 CANTXD1 Name COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 Flash FS_CLK(I) FS_DIO(I/O) SPGM_nBOOT
CONFIGURATION
S3F4A1HJ
Table 2-1. Assignments-Pin Number Order (Continued) Name P1.30 P1.31 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 AVDD AVREF AVSS nRESET XOUT VDDCOREOUT VSSCORE0 VDDCORE0 VDDIO0 VSSIO0 Name IRQ9 ADTRG IRQ10 IRQ11 CAPT0 TIOA2 TIOB2 nTRST 2-1. IMPORTANT NOTICE SPGM_nBOOT must connected flash writing SPGM mode. Name SDA0 SCL0 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 Flash
S3F4A1HJ
CONFIGURATION
DESCRIPTION
Table 2-2. Description Module RESET Name IRQ[11:0] NRST COM[3:0] SEG[29:0] VLCD CLOCK XOUT P0.X P1.X P2.X PWM[1:0] SM[3:0][3:0] TCLK[2:0] TIOA[2:0] TIOB[2:0] AIN[15:0] ADTRG SDA[1:0] SCL[1:0] Function External interrupt request Hardware reset common signal segment Bias Crystal oscillator input Oscillator output General purpose multiplexed Pulse width modulation output Stepper motor output Timer external clock Multipurpose timer Multipurpose timer Input channels [15:0] external trigger Serial data Serial clock Type Power Active Level Comments Multiplexed with Schmitt trigger, internal filter Multiplexed with peripheral module Multiplexed with peripheral module Multiplexed with peripheral module Multiplexed with SM[3:0][1:0] used Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with
Analog
CONFIGURATION
S3F4A1HJ
Table 2-2. Description (Continued) Module U(S)ART Name UARTRXD0/1, USARTRXD0 UARTTXD0/1, USARTTXD0 USARTCLK0 CAPT SPI0 CAPT0 SPCK0 MISO0 MOSI0 NSS0 SPI1 SPCK1 MISO1 MOSI1 NPCS[3:0] CANTX0 CANRX0 CANTX1 CANRX1 JTAG MODE
NOTES: input floating. must connected through resistor reduce current consumption power down mode.
Function Received signal Transmit signal Clock signal Capture input clock Master slave Master slave Peripheral chip select clock Master slave Master slave Peripheral chip select Transmit line Receive line Transmit line Receive line Test mode select Test data Test data Test clock Test reserved
Type
Active Level
(note
Comments Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with Multiplexed with internal pull-up internal pull-up Internal pull-down (note
MD[1:0]
Name MD[1:0] Value Mode Setting Normal/ debug mode Flash writing mode (Tool mode) External JTAG (Boundary SCAN) SCAN mode (Only test)
S3F4A1HJ
CONFIGURATION
Table 2-2. Description (Continued) Module Power Name VDDCORE[1:0] VSSCORE[1:0] VDDIO[2:0] VSSIO[2:0] VDDCOREOUT AVREF AVDD AVSS VLCD VDDPLLOUT Function Core supply voltage Core ground voltage block supply voltage block ground voltage From internal regulator reference voltage supply voltage ground voltage supply voltage Internal flash power test From internal regulator Type Active Level recommended operating condition connect Connected through capacitor Connected through capacitor recommended operating condition recommended operating condition recommended operating condition Comments recommended operating condition
NOTE: VLCD must greater than VDDCORE VDDIO.
S3F4A1HJ
MEMORY
MEMORY
When S3F4A1HJ micro-controller reset, core boot mode access internal flash address 0x00000000. internal located address 0x00300000 internal data flash located address 0x80000000. But, internal data flash disabled reset.
Memory Space 0XFFFFFFFF 0XFFE00000 0XFFDFFFFF 0X80008000 0X80007FFF 0X80000000 0X7FFFFFFF 0X00304000 0X00303FFF 0X00300000 0X002FFFFF 0X00080000 0X0007FFFF 0X00000000
Application
Abort
Peripheral devices memory
Reserved
32Kbytes disabled data FLASH
Reserved
16kbytes internal
Reserved
512kbytes internal program FLASH
Figure 3-1. S3F4A1HJ Default Memory after Reset
MEMORY
S3F4A1HJ
Table 3-1. Base Address Peripheral Special Registers Peripheral channels) 10-bit channels) SPI0 (8-bit) Watchdog CAN0 buffers) Channels) channels) channels) UART0 IOCONF UART1 USART0 CAN1 buffers) CAPT0 I2C0 I2C1 LCDC SPI1 (16-bit) PIO0 PIO1 PIO2 SMC0 SMC1 SMC2 SMC3 LDMAC Base Address 0xFFE00000 0xFFE04000 0xFFE08000 0xFFE0C000 0xFFE10000 0xFFE14000 0xFFE18000 0xFFE1C000 0xFFE20000 0xFFE24000 0xFFE28000 0xFFE2C000 0xFFE30000 0xFFE34000 0xFFE38000 0xFFE3C000 0xFFE48000 0xFFE50000 0xFFE54000 0xFFE58000 0xFFE60000 0xFFE64000 0xFFE68000 0xFFE6C000 0xFFE74000 0xFFE78000 0xFFE7C000 0xFFE80000 0xFFFE4000 0xFFFE8000 0xFFFF0000 0xFFFF8000 0xFFFFF000
S3F4A1HJ
MODULE GENERIC FUNCTIONS
MODULE GENERIC FUNCTIONS
REGISTERS ACCESS
ENABLE DISABLE STATUS REGISTERS order reduce code size subsequently increase speed when accessing internal peripherals, most registers have been split into address locations: first address location (Enable register) used logical second address location (Disable Clear register) used logical third address location (Status register Mask register) gives current state bit.
logical Status Mask register, write command Enable register must performed with corresponding logical logical Status Mask register, write command Disable Clear register must performed with corresponding logical Example: When supposing that value GPT_PSR register 0x00000000, enable TIOB TCLK pins PIOs block, 0x00050000 must written GPT_PER register. value read GPT_PSR register will 0x00050000. software wants disable TIOB (i.e. enable use), write access GPT_PSR register with value 0x00010000 must performed. value read GPT_PSR register will 0x00010000. following chapters, registers sharing same behavior will shown single page with table Enable Disable Clear registers table Status Mask register. description will documented after Status Mask register.
MODULE GENERIC FUNCTIONS
S3F4A1HJ
ACCESS REGISTERS Some bits registers only value only right written same time. Example: RSTALW WD_PWR register logical only KEY[7:0] bits equal 0x91. enable restart mode Watchdog, 0x91000001 must written WD_PWR register. disable restart mode Watchdog, 0x91000000 must written WD_PWR register. REGISTERS UNDEFINED BITS Undefined bits Each undefined read zero, writing undefined bits consequence. They marked grayed. Reserved bits Writing reserved with different value than reset value unpredictable effect. Writing effect except express specification. Read back value reset sate depending bit. There marked `reserved'.
S3F4A1HJ
MODULE GENERIC FUNCTIONS
GHOST REGISTERS S3F4A1HJ micro-controller integrates (In-Circuit Emulation) interface that associated with JTAG connection software debugger that provides powerful debug possibility. Effectively, running program stopped, Internal registers internal external memories monitored, Instructions added when core stopped, also, program resumed.
However, some S3F4A1HJ registers `read-active', which means that reading such registers affect state other registers. This usual wanted register's behavior. example, module, (End Conversion) automatically cleared when (numerical value input converted) read. amount code needed application. Meanwhile, when debugging software, users interested monitoring value such registers, without modify state another register. this purpose, each module, ghost register field been implemented design. Users reading this ghost field will affect value other registers. Ghost registers `read-active', mirrors original registers. They located memory inversing 14th module base address. example, base address module 0xFFE0C000, ghost registers base address 0xFFE0E000. reading this ghost field, users disturb behavior module. Ghost registers exist modules. Find below "read-active" registers list: Module "Read-Active" Registers GIC_IVR GIC_FVR ADC_DR SPI_RDR Effect Clears interrupt present Clears interrupt present Clears ADC_SR register Clears RDRF SPI_SR register
MODULE GENERIC FUNCTIONS
S3F4A1HJ
POWER MANAGEMENT BLOCK
order reduce power consumption, S3F4A1HJ micro-controller provides power management block some peripherals used switch on/off peripheral clocks (peripheral block). This function independent Power Reset Controller (peripheral) used switch on/off ARM7TDMI core. registers provided: PERIPHERAL_ECR peripheral offset 0x0050) enables clock PERIPHERAL_DCR peripheral offset 0x0054) disables clock PERIPHERAL_PMSR peripheral offset 0x0058) gives status clock
bits provided these registers: controls block peripheral controls peripheral function
When peripheral clock disabled, clock immediately stopped. When clock re-enabled, peripheral controller resumes action where left off. table below lists modules which have power management blocks Module LCDC LDMAC U(S)ART core Power Management Block Present
S3F4A1HJ
ANALOG DIGITAL CONVERTER
ANALOG DIGITAL CONVERTER
OVERVIEW
FUNCTIONAL DESCRIPTION 10-bit Analog Digital Converter (ADC) module provides following features: analog inputs: AIN[15:0] LDMA transfer programmable conversions sequence: Sequence analog inputs converted. This allows user make conversions some inputs order. length sequence (number conversion) defined setting NBRCH field ADC_MR. composition sequence defined ADC_CMR register. conversion modes: `one shot' single) mode `continuous mode'. `one shot' mode, inputs specified conversions sequence successively converted after start command, conversion results successively stored data register then stops. `continuous mode', inputs specified conversions sequence converted after other continuously until stop requested. Each time conversions sequence completed, re-starts conversion selected inputs order sequence. this mode, microprocessor starts which then completely independent. Conversions started CPU. Conversions also started external device using dedicated input pin. (ADTRG) Analog clock frequency tuned (less than maximum 2.5MHz) whichever system clock frequency. This feature allows configure sampling frequency analog inputs. Note that analog clock cycles required perform single conversion. Interrupt line connected GIC. Power management features allowing reduce power consumption.
ANALOG DIGITAL CONVERTER
S3F4A1HJ
BLOCK DIAGRAM
ADC_MR[20] CONTCV
ADC_MR[5] ADC_CR[3] START
TRIG
ADC_MR[19:16] NBRCH[3:0]
ADC_CMR0/1 CVx[3:0]
ADC_CR[4] STOP ADC_MR[6] STOPEN ADC_SR[3] TEND
Inputs management
ADC_MR[4:0] PRLVAL[4:0]
START
AIN0 AIN1
ADC_PMSR[1] PCLK
Prescalar
ADCCLK
ADCIN
AIN15
ADC10 VREF ADC_CR[2] ADCDIS ADC_CR[1] ADCEN PCLK
START
STARTUPTIME
AVREF
ENABLE ADCOUT
ADC_DR ADC_SR[0] ADC_SR[1] READY ADC_SR[2]
ADC_INT
ADC_IMR
Figure 5-1. Block Diagram
S3F4A1HJ
ANALOG DIGITAL CONVERTER
EXTERNAL DESCRIPTION
Table 5-1. Description Name AIN[15:0] AVREF ADTRG Analog input Analog reference voltage External start Function Type Analog Input Analog Input Digital Input Active Level High Comments
ANALOG DIGITAL CONVERTER
S3F4A1HJ
FUNCTIONAL OPERATION
DETAILED FUNCTIONALITIES 3.1.1 Conversion Sequence Definition conversions sequence sequence analog inputs converted. User configure block make conversions some inputs order. length sequence other terms number conversions) defined setting NBRCH field ADC_MR. following table gives relation between NBRCH field number conversion performed sequence: Table 5-2. NBRCH[3:0] Values Number Conversions NBRCH[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Number Conversions
S3F4A1HJ
ANALOG DIGITAL CONVERTER
This means that, even configured `one shot' mode, will specified number conversion after start request. data register will updated with conversion results each conversion which composes sequence. composition sequence programmed ADC_CMRx register. field defines first input converted sequence. field defines second input converted Find table below relation between values input selected: Table 5-3. Values Selected Input Values 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Selected Analog Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Selected
example, assuming that: NBRCH 0x2, 0x5,
After start conversion request, converts input (AIN5), followed input (AIN2) finishes converting input (AIN0).
ANALOG DIGITAL CONVERTER
S3F4A1HJ
3.1.2 shot Continuous Conversion Mode programmed modes: shot continuous conversion mode. shot conversion mode enabled setting CONTCV mode register '0'. this mode, upon conversion start request, performs only complete conversions sequence then stops waits another start request. stopped until finishes conversions sequence. Continuous conversion mode enabled setting CONTCV mode register '1'. this mode, upon conversion start request, repetitively performs conversions sequences until forced stopped. stop continuous conversion, must write STOP control register. When stop requested, finishes current conversion updates data register with this last conversion result. other conversions performed even conversions sequence finished.
5-1. IMPORTANT NOTICE However, user should vigilant, because after stop command continuous mode, finishes on-going conversion this look like extra conversion.
S3F4A1HJ
ANALOG DIGITAL CONVERTER
3.1.3 Start Sources Conversions started (writing START ADC_CR). Conversions also started external device using dedicated input (ADTRG). Internal start enabled mode register `0'. conversion request initiated writing START control register. External start enabled mode register `1'. conversion request initiated each time rising edge detected "ADTRG" pin. following constraints apply "ADTRG" input: There setup hold constraint "start" versus system clock anti- metastability structure provided ADC. "ADTRG" signal must stable more than system clock period.
3.1.4 Analog Cell Clock Frequency specified electrical characteristics (see Table "ADC characteristics"), analog cell clock frequency limited 2.5MHz, whereas system clock usually higher. module provides clock frequency divider based 6-bit counter. following expression gives relation between system clock frequency, analog cell clock frequency PRLVAL field mode register: PRLVAL '1', then FANA FCLK_B else other values PRLVAL, FANA FCLK_B (2*PRLVAL) PRLVAL data must chosen order ensure that analog frequency lower than 2.5MHz. Note that analog clock cycles required perform single conversion. clock rate must exceeded MHz.
3.1.5 Power Management peripheral includes power management features that used minimize power consumption. Power saved sides: analog digital. Analog power saving: reduce analog power consumption, shall disable module (write ADCDIS ADC_CR) which effect analog cell 'standby' mode. Digital power saving: reduce digital power consumption, shall disable clock (write ADC_DCR) which effect disable incoming clocks. Then, digital consumption reduced close Note that when clock disabled, write access registers ineffective except 'Enable Clock Register'. Read access registers still enabled.
ANALOG DIGITAL CONVERTER
S3F4A1HJ
Then, order have peripheral lowest consumption mode, necessary disable (write ADCDIS ADC_CR) first then switch clock (write ADC_DCR). other round, order completely leave lowest power consumption mode, necessary enable clock (write ADC_ECR) first then enable (write ADCEN ADC_CR). following table summarizes status bits reflecting power management: Table 5-4. Status Bits Reflecting Power Management Status Register ADC_PMSR ADCENS ADC_SR When Clock enabled Analog cell active When Clock disabled. Digital power saving Analog cell standby mode. Analog power saving
3.1.6 Interrupts peripheral generates interrupt least EOC, READY, TEND active (set `1') status register while enabled (corresponding ADC_IMR read `1'). Each interrupt enabled disabled using respectively interrupt enable register interrupt disable register.
3.1.7 Conversion Details 3.1.7.1 Flag (End Conversion) status register flags presence valid data data register. `0', means that conversion been done since last reset this that last conversion result been read data register. `1', means that conversion been completed conversion result been read data register.
flag reset each time read access performed data register (ADC_DR). 3.1.7.2 READY Flag READY status register means that ready accept conversion start request. This read while currently running conversion. 3.1.7.3 Flag (Overrun) This flag indicates that data overwrites previous converted data which been read. previous data been lost. flag clear (writing clear status register).
S3F4A1HJ
ANALOG DIGITAL CONVERTER
SOFTWARE SEQUENCE CONVERSION following lines list basic sequence operations after reset using peripheral: Enable clock ADC_ECR. Configure mode ADC_MR. PRLVAL field shall programmed order have analog frequency clock less than 2.5MHz. Indicate conversion continuous. Define conversions sequence: number conversion (NBRCH field ADC_MR) which inputs converted (CVx fields ADC_CMRx). Enable (ADC_EN ADC_CR). Wait READY ADC_SR. When flag set, ready start conversion. interrupt generated when READY flag rises corresponding enabled ADC_IMR. Initiate conversion writing START ADC_CR. selects analog input associated with conversion number conversion sequence. analog input voltage sampled conversion completes after clock cycles from start command. digital 10-bit conversion result stored into ADC_DR ADC_SR rises flag already set, then also set. then read digital value ADC_DR, which automatically clears EOC. decides that more data should converted continuous mode, then respectively writes STOP bit. this case, stops operating waits next start request. Note that `one shot' mode, stopped until conversions specified conversion sequence. NBRCH non-null, selects analog input associated next conversion number operation flow restarts from step CONTCV read `1', restarts another conversion sequence from step
ANALOG DIGITAL CONVERTER
S3F4A1HJ
REGISTERS DESCRIPTION
Base Address 0xFFE0C000
Table 5-5. Special Function Registers Offset Address 0x000 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 Name Reserved Description Reset State
ADC_ECR ADC_DCR ADC_PMSR ADC_CR ADC_MR ADC_CSR ADC_SR ADC_IER ADC_IDR ADC_IMR ADC_CMR0 ADC_CMR1 ADC_DR
Enable clock register Disable clock register Power management status register Reserved Control register Mode register Reserved Clear status register Status register Interrupt enable register Interrupt disable register Interrupt mask register Conversion mode register Conversion mode register Convert data register
(note)
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
NOTE: reset value register depends identifier code.
5-10
S3F4A1HJ
ANALOG DIGITAL CONVERTER
Enable Clock Register DBGEN
ADC_ECR (0x050)
Access: Write only
clock enable
effect Enable clock DBGEN Debug mode enable
effect Enable debug mode
5-11
ANALOG DIGITAL CONVERTER
S3F4A1HJ
Disable Clock Register DBGEN
ADC_DCR (0x054)
Access: Write only
clock disable
effect Disable clock DBGEN Debug mode disable
effect Disable debug mode
5-12
S3F4A1HJ
ANALOG DIGITAL CONVERTER
Power Management Status Register DBGEN Write Read
ADC_PMSR (0x058)
Access: Read only
IPICODE[25:20]
IPICODE[19:12]
IPICODE[11:4]
IPICODE[3:0]
After reset
After reset
Undefined after reset
clock status
clock disabled. clock enabled. IPICODE[25:0] identifier code This field contains version number module, coded 26bits. DBGEN Debug mode
halted during core debug mode. halted during core debug mode.
5-13
ANALOG DIGITAL CONVERTER
S3F4A1HJ
Control Register Write Read
ADC_CR (0x060) START ADCDIS
Access: Write only SWRST
STOP
ADCEN
After reset
After reset
Undefined after reset
SWRST software reset
effect. Reset peripheral. When software reset performed, registers peripheral reset except ADC_PMSR (Power Management Status) register. ADCEN enable
effect. enabled conversion. ADCDIS disable
effect. disabled (Standby Mode). case both ADCEN ADCDIS equal when control register written, will disabled. START Start conversion
analog digital conversion started. Begin analog digital conversion, clears bit.
NOTE: Before starting conversions, users should ensure that ready conversion (READY logical ADC_SR).
STOP Stop conversion continuous conversion
effect. Stop continuous conversion.
5-14
S3F4A1HJ
ANALOG DIGITAL CONVERTER
Mode Register R/W-0 R/W-0 R/W-0 R/W-0 Write R/W-0 R/W-0 R/W-0 R/W-0 Read R/W-0 R/W-0 R/W-0 R/W-0
ADC_MR (0x064) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRLVAL[4:0] R/W-0 R/W-0
Access: Read/Write R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0 CONTCV R/W-0 R/W-0
NBRCH[3:0]
After reset
After reset
Undefined after reset
PRLVAL[4:0] Preload Value division Master clock (Coreclk) determines ADC_clk. preload value chosen user adapt Master clock peripheral well possible. start value down counter. fixed because this value even parity guaranty duty cycle user only initialize MSB. (PRLVAL PRLVAL FADC PCLK Else FADC PCLK (2*PRLVAL)
NOTE: clock rate must exceeded MHz.
Internal/External Start
Internal start. External start.
5-15
ANALOG DIGITAL CONVERTER
S3F4A1HJ
NBRCH[3:0] Number Conversions
NOTE: Even shot mode, will multiple conversions NBRCH[3:0] greater than 0000b.
Table 5-6. NBRCH[3:0] Values Number Conversions NBRCH[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Number Conversions
CONTCV Continuous Conversion
shot mode. converts much inputs specified NBRCH[3:0] order specified ADC_CMR, stops. Continuous mode. converts much inputs specified NBRCH[3:0] order specified ADC_CMR, repeats. This initialized
NOTE: continuous mode, after stop command, finishes on-going conversion this look like extra conversion.
5-16
S3F4A1HJ
ANALOG DIGITAL CONVERTER
Clear Status Register Write Read
ADC_CSR (0x06C)
Access: Write only
After reset
After reset
Undefined after reset
Clear overrun interrupt
effect. Clear interrupt.
5-17
ANALOG DIGITAL CONVERTER
S3F4A1HJ
Status Register Write Read
ADC_SR (0x70)
Access: Read only ADCENS
CTCVS READY
After reset
After reset
Undefined after reset
conversion
Conversion complete inactive. Conversion complete, data ADC_DR valid. This cleared when ADC_DR read. READY ready conversion
ignores start stop command: ready conversion converting data. ready start conversion. explain more completely ready flag, let's call "working" event high when converting data "analog_ready" event when analog part disabled initializing phase. Table 5-7. Ready Conversion analog_ready working ready_flag
Overrun
Zero data been converted since last ADC_DR read. least data been converted since last ADC_DR read.
5-18
S3F4A1HJ
ANALOG DIGITAL CONVERTER
ADCENS enable status
disabled. enabled. CTCVS Continuous mode status
shot mode with help microprocessor. Continuous mode, peripheral stand-alone. This initialized changes when there change mode. This never generates interruption.
5-19
ANALOG DIGITAL CONVERTER
S3F4A1HJ
Interrupt Enable Register Write Read
ADC_IER (0x074)
Access: Write only
READY
After reset
After reset
Undefined after reset
conversion interrupt enable
effect Enable interrupt READY ready conversion interrupt enable
effect Enable READY interrupt Overrun interrupt enable
effect Enable interrupt
5-20
S3F4A1HJ
ANALOG DIGITAL CONVERTER
Interrupt Disable Register Write Read
ADC_IDR (0x078)
Access: Write only READY
After reset
After reset
Undefined after reset
conversion interrupt disable
effect Disable interrupt READY ready conversion interrupt disable
effect Disable READY interrupt Overrun interrupt disable
effect Disable interrupt
5-21
ANALOG DIGITAL CONVERTER
S3F4A1HJ
Interrupt Mask Register Write Read
ADC_IMR (0x07C)
Access: Read only
READY
After reset
After reset
Undefined after reset
conversion interrupt mask
interrupt disabled. interrupt enabled. READY ready conversion interrupt mask
READY interrupt disabled. READY interrupt enabled. Overrun interrupt mask
interrupt disabled. interrupt enabled.
5-22
S3F4A1HJ
ANALOG DIGITAL CONVERTER
Conversion Mode Register Write CV8[3:0] CV6[3:0] CV4[3:0] CV2[3:0] Read
ADC_CMR0 (0x080) CV7[3:0] CV5[3:0] CV3[3:0] CV1[3:0]
Access: Read/Write
After reset
After reset
Undefined after reset
CVx[3:0] Analog Input Selection conversion number. Values 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Selected Analog Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Selected Analog
5-23
ANALOG DIGITAL CONVERTER
S3F4A1HJ
Conversion Mode Register Write CV16[3:0] CV14[3:0] CV12[3:0] CV10[3:0] Read
ADC_CMR1 (0x084) CV15[3:0] CV13[3:0] CV11[3:0] CV9[3:0]
Access: Read/Write
After reset
After reset
Undefined after reset
CVx[3:0] Analog Input Selection conversion number. Values 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Selected Analog Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Selected Analog
5-24
S3F4A1HJ
ANALOG DIGITAL CONVERTER
Convert Data Register Write Read
ADC_DR (0x088) DATA[7:0]
Access: Read only DATA[9:8]
After reset
After reset
Undefined after reset
DATA[9:0] Converted data result data from analog digital conversion latched into this register conversion remains valid until conversion completed. When this register read, ADC_SR register cleared.
NOTE: When debugging, avoid clearing bit, users should ghost registers.
5-25
S3F4A1HJ
CAPTURE MODULE
CAPTURE MODULE (CAPT)
OVERVIEW
FUNCTIONAL DESCRIPTION capture module frame analyzer. stores period duration high level duration 15bit capture counter (CAP_DR). Those durations described number counter cycle (CAPTCLK). capture clock CAPTCLK equal PCLK divided configurable pre-scalar value. capture allows data transfer with LDMA. EXTERNAL DESCRIPTION Table 6-1. CAPT Description Name CAPT0 Function Capture input Type Active Level Comments
CAPTURE MODULE
S3F4A1HJ
FUNCTIONAL OPERATION
MODE OPERATION 2.1.1 General Description capture clock frequency equal CAPTCLK PCLK 2PRESCALAR[3:0] where PCLK peripheral clock frequency PRESCALAR[3:0] bits data written CAPT_MR
possible choose among modes measurement: measure duration between each edges (positive negative). measure duration between positives edges (period). measure duration between negatives edges (period).
overrun occurs, possible choose overwrite data stored Data Register (CAPT_DR) stop data acquisition through mode register (CAPT_MR). DATACAPT CAPT_SR register) automatically cleared (i.e. logical after reading data register. recommended disable capture module after every modification CAPT_MR register. Otherwise first measure could false. When capture disabled, capture counter reset. CAPTURE'S LIMITS avoid capture miss frame edges, capture counter clock frequency CAPTCLK must chosen that: CAPTCLK 2/tb2edgeMIN, where tb2edgeMIN minimum "time between edges" observed frame. Moreover capture detects each frame edge with delay equal CAPTCLK period.
CAPTCLK Frame Frame observed capture Delay
Figure 6-1. Capture Resynchronization
S3F4A1HJ
CAPTURE MODULE
PROGRAMMING EXAMPLES Example usage capture: Capture period signal using LDMA associated interrupt. PCLK frequency equal 20MHz; capture clock CAPTCLK maximum frequency 10MHz (CAPT_MR PRESCALAR[3:0] these conditions, observed signal maximum frequency 5MHz. Configuration: Capture clock enable writing CAPT_ECR Software reset capture peripheral known state writing SWRST CAPT_CR. Capture mode register (CAPT_MR) configuration: PRESCALAR[3:0] field that CAPTCLK 10MHz. ONESHOT OVERMODE ignored because capture will stop after first acquisition. MEASMODE=2 measure duration between positive edges. Enable CAPT writing CAPEN CAPT_CR Configuration CAPT_IER: interrupt generated capture. When LDMA will finish capture, interrupt will generated. must configured status CAPENS CAPT_SR start capture writing STARTCAPT CAPT_CR, otherwise users should wait CAPENS flag, consequence CAPEN CAPT_CR.
Interruption Handling: entry call function. Read CAPT_SR verify source interrupt. Clear corresponding interrupt peripheral level writing CAPT_CSR. Interrupt treatment: Read duration between positive edges received memory space programmed LDMA. duration expressed number capture clock (duration/10 MHz). exit
CAPTURE MODULE
S3F4A1HJ
REGISTERS DESCRIPTION
Base Addresses CAPT0 0xFFE48000
Table 6-2. CAPTURE Special Function Registers Offset Address 0x0000 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 Name Reserved Description Reset State
CAPT_ECR CAPT_DCR CAPT_ PMSR CAPT_CR CAPT_MR CAPT_CSR CAPT_SR CAPT_IER CAPT_IDR CAPT_IMR CAPT_DR
Enable clock register Disable clock register Power management status register Reserved Control register Mode register Reserved Clear status register Status register Interrupt enable register Interrupt disable register Interrupt mask register Data register
(note)
0x00000000 0x00000000 0x00000000 0x00000000
NOTE: reset value register depends identifier code.
S3F4A1HJ
CAPTURE MODULE
CAPTURE Enable Clock Register DBGEN Write Read After reset
CAP_ECR(0x0050) After reset
Access: Write only
Undefined after reset
Capture clock enable
effect Enable Capture clock DBGEN Debug mode enable
effect Enable debug mode.
CAPTURE MODULE
S3F4A1HJ
CAPTURE Disable Clock Register DBGEN Write Read After reset
CAP_DCR (0x0054) After reset
Access: Write only
Undefined after reset
Capture clock disable
effect Disable Capture clock DBGEN Debug mode disable
effect Disable debug mode.
S3F4A1HJ
CAPTURE MODULE
CAPTURE Power Management Status Register CAP_PMSR (0x0058) DBGEN Write Read
Access: Read only
IPICODE[25:20]
IPICODE[19:12]
IPICODE[11:4]
IPICODE[3:0]
After reset
After reset
Undefined after reset
Capture clock status
Capture clock disabled. Capture clock enabled. IPIDCODE[25:0] This field contains version number module, coded bits. DBGEN Debug mode
Capture module halted during core debug mode. Capture module halted during core debug mode.
CAPTURE MODULE
S3F4A1HJ
CAPTURE Control Register Write Read After reset
CAP_CR(0x0060) STARTCAPT After reset CAPDIS CAPEN
Access: Write only SWRST
Undefined after reset
SWRST CAPTURE software reset
effect Reset CAPTURE software triggered hardware reset CAPTURE performed. reset registers. CAPEN: CAPTURE enable
effect. Enables CAPTURE. CAPDIS CAPTURE disable
effect. Disables CAPTURE. case both CAPEN CAPDIS equal when control register written CAPTURE will disabled. STARTCAPT START CAPTURE
effect. CAPTURE starts capture. start effective only capture previously enabled. (CAPEN set.)
S3F4A1HJ
CAPTURE MODULE
CAPTURE Mode Register
R/W-0 R/W-0 R/W-0 ONESHOT R/W-0 R/W-0 R/W-0 R/W-0 OVERMODE R/W-0 R/W-0 R/W-0 R/W-0 MEASMODE R/W-0
CAP_MR (0x0064)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRESCALAR R/W-0 R/W-0
Access: Read/Write
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
Write
Read
After reset
After reset
Undefined after reset
PRESCALAR[3:0] pre-scalar factor CAPTCLK CAPTCLK PLCK 2PRESCALAR+1
MEASMODE[1:0] Measurement Mode MEASMODE[1:0] Measure realized Measure between each edges (positive negative) Measure between positives edges. Measure between negatives edges.
OVERMODE Overrun mode
When overrun happened, capture stops writing Data Register. DATACAPT CAPT_SR enabled CAPTURE module receives data, data register will refreshed. When overrun happened, capture does stop writing Data Register. ONESHOT Shot
capture still captures frame variation. module captures frame variation stop. other capture, STARTCAPT CAP_CR.
CAPTURE MODULE
S3F4A1HJ
CAPTURE Clear Status Register Write Read After reset
CAP_CSR (0x006C) After reset OVERFLOW
Access Write only OVERRUN
Undefined after reset
OVERRUN: Clear Overrun Interrupt
effect. Clear OVERRUN interrupt. OVERFLOW: Clear Overflow Interrupt
effect. Clear OVERFLOW interrupt.
6-10
S3F4A1HJ
CAPTURE MODULE
CAPTURE Status Register
CAP_SR (0x0070)
DATACAPT OVERFLOW
Access: Read only
OVERRUN CAPENS
Write
Read
After reset
After reset
Undefined after reset
OVERRUN: Over
effect overrun occurred. Overrun indicates valid data read when overwriting occurred. OVERFLOW: Over flow
effect overflow occurred. Overflow indicates that counter duration saturated. DATACAPT Data Captured Data CAP_DR read. This cleared reading CAP_DR register. CAPENS Capture enable status
effect
Capture disabled. Capture enabled.
6-11
CAPTURE MODULE
S3F4A1HJ
CAPTURE Interrupt Enable Register
CAP_IER (0x0074)
DATACAPT OVERFLOW
Access: Write only
OVERRUN
Write
Read
After reset
After reset
Undefined after reset
OVERRUN Over interrupt enable
effect Enables OVERRUN interrupt. OVERFLOW Over flow interrupt enable
effect Enables OVERFLOW interrupt. DATACAPT Data captured interrupt enable
effect. Enables DATACAPT interrupt.
6-12
S3F4A1HJ
CAPTURE MODULE
CAPTURE Interrupt Disable Register
CAP_IDR (0x0078)
DATACAPT OVERFLOW
Access: Write only
OVERRUN
Write
Read
After reset
After reset
Undefined after reset
OVERRUN Over interrupt disable
effect Disables OVERRUN interrupt. OVERFLOW Over flow interrupt disable
effect Disables OVERFLOW interrupt. DATACAPT Data captured interrupt disable
effect. Disables DATACAPT interrupt.
6-13
CAPTURE MODULE
S3F4A1HJ
CAPTURE Interrupt Mask Register
CAP_IMR (0x007C)
DATACAPT OVERFLOW
Access: Read only
OVERRUN
Write
Read
After reset
After reset
Undefined after reset
OVERRUN Over interrupt mask
OVERRUN Interrupt disabled. OVERRUN interrupt enabled. OVERFLOW Over flow interrupt mask
OVERFLOW Interrupt disabled. OVERFLOW interrupt enabled. DATACAPT Data captured interrupt mask
DATACAPT interrupt disabled. DATACAPT interrupt enabled.
6-14
S3F4A1HJ
CAPTURE MODULE
CAPTURE DATA Register LEVEL Write Read After reset
CAP_DR (0x0080) DURATION DURATION After reset
Access: Read only
Undefined after reset
NOTES: When reading this register, DATACAPT clear CAPT_SR. When debugging, avoid clearing DATACAPT bit, users should ghost registers.
DURATION Capture duration Numbers CAPTCLK during which output level indicates LEVEL bit, during frame period, depending MEASMODE CAP_MR.
LEVEL Level measured (NOTE)
duration concerns level duration concerns high level
NOTE: That MEASMODE[1:0] Mode register) equal LEVEL used Duration
6-15
S3F4A1HJ
CLOCK MANAGER
CLOCK MANAGER
OVERVIEW
FUNCTIONAL DESCRIPTION This module delivers clock, clock enables reset signals used on-chip blocks composing emulated ARM-based device. Clock Manager provides: internal frequency oscillator (Internal Ring Oscillator) master oscillator Programmable operational frequency Programmable master clock divider Programmable ring clock divider Master oscillator failure detection feature (referred "clock monitor" this manual). Internal Power-On-Reset Power supply monitoring
Clock Manager manages clock sources selection transitions: manage master oscillator stabilization time manage frequency oscillator stabilization time manage stabilization time manage peripheral clock manage system clock manage clock manage Core clock
clock manager manages circuit reset sources: Power-On-Reset External asynchronous hardware reset Power supply monitor reset Clock monitor reset Watchdog reset
CLOCK MANAGER
S3F4A1HJ
BLOCK DIAGRAM
CM_SELR CMCLK_SEL[1:0] MCLK XOUT
CM_SELR CMCLK_SEL[1:0]
Master Clock Oscillator 6MHz)
Programmable PLLOUT
CDIV
(note1)
ARMCLK clock SCLK (ASB clock) :FLASH, SRAM, LDMA PCLK(APB clock) Other blocks GICCLK :GIC, edge detecting circuit
MDIV
CORECLK
CM_RSR
DIVOUT
(note4)
(note2)
PCLK1DIV
RINGCLK
Frequency Oscillator (1MHz)
clock monitor
LDIV CM_LFOSCR LFSEL
LFDIV
LFCLK :ST0, WDT,
CM_LFOSCR LFOSCEN
NOTES: chip halt mode (CM_CR.HALTMODE==1) idle mode (CM_CR.IDLEMODE==1), clock disabled. chip halt mode (CM_CR.HALTMODE==1) CM_WFIR.PCLK1 clock disabled. stop mode (CM_CR.STOPMODE==1), clock disabled. reset functionality must turned (MR16.0 before entering stop mode. frequency (PCLK) must less than 20MHz.
Figure 7-1. Clock Manager Block Diagram clock manager allows user select between different operating modes: Normal Mode (CMCLK_SEL 00), High-speed Mode (CMCLK_SEL 01), Slow Mode (CMCLK_SEL 10), Lower Power Mode (CMCLK_SEL 11), HALT Mode, IDLE mode, STOP mode. Moreover, upon master oscillator failure detection, clock manager will force circuit reset restart CKFAIL mode.
S3F4A1HJ
CLOCK MANAGER
shown previous synoptic, clock-manager responsible generation global clocks: Table 7-1. Clock Sources Name SCLK Definition ARM7 sub-system clock Comments This clock running actually clock used internal modules connected embedded system (except ARM7 core). This clock almost same SCLK (same frequency) except that always HALT mode IDLE mode whereas SCLK left active. This clock used peripherals. From this clock source, possible defined locally each peripheral actually using clock programming module level power management register (PMSR). This clock almost same PCLK (same frequency) except that always running HALT mode whereas PCLK cut.
ARMCLK
Clock used ARM7TDMI core
PCLK
Peripheral clock source
GICCLK
Clock dedicated (Generic Interrupt Controller)
This clock always running generated from divided main clock divided frequency oscillator. This clock programmed through CM_MDIVR register.(refer this register's description details) Each those global clocks will derived from following clock sources: Table 7-2. Derived Clock Sources Name MCLK RINGCLK PLLOUT Definition This clock output master oscillator This clock output ringoscillator This clock output internal programmable This clock derived from MCLK through frequency divider This clock derived from RINGCLK through frequency divider Comments master oscillator internal oscillator using external crystal connected XIN/XOUT pins. ring oscillator fully embedded (typical) oscillator. output frequency programmed MHz. This done through CM_PDPR register.(refer this register's description details) DIVOUT frequency programmed through CM_MDIVR register (refer this register's description details). LFDIV frequency programmed through CM_MDIVR register (refer this register's description details).
LFCLK
frequency clock
DIVOUT
LFDIV
CLOCK MANAGER
S3F4A1HJ
following drawing displays operating mode state diagram with associated possible transitions. Each those transitions will detailed further this document.
RESET (any kind)
CM_RSR.2
IDLE POWER
CKFAIL
POWER STOP NORMAL
HALT
HIGH SPEED
IDLE HIGH SPEED
IDLE NORMAL
SLOW
IDLE SLOW
Transition requested software Transition automatically handled hardware upon reset. Transition automatically handled hardware upon interrupt. Transition automatically handled hardware upon external wake-up interrupt.
Figure 7-2. Clock Manager State Machine
S3F4A1HJ
CLOCK MANAGER
introduced previously, clock-manager manages master oscillator, programmable internal frequency oscillator. Each them shall enabled disabled according software programming current operating mode. effect each previous operating modes given following tables Table 7-3. Oscillators Activity Mode NORMAL, IDLE NORMAL LFOSCEN (note1) SLOW, IDLE SLOW STOP CKFAIL LFSEL(note1) HALT, LOWPOWER, IDLE LOWPOWRER HIGHSPEED, IDLE HIGHSPEED Enabled Enabled Disabled Forbidden Enabled Enabled Enabled Disabled Enabled Disabled Enabled Enabled Ring Oscillator Disabled Master Oscillator Enabled Forbidden
(note2)
Disabled Disabled Disabled
Enabled Enabled Forbidden (note2) Forbidden (note2) Enabled Enabled Forbidden (note2) Enabled Disabled Enabled Forbidden (note2) Enabled Enabled Disabled
(note2)
Disabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled Disabled
Disabled
NOTES: LFOSCEN LFSEL bits part CM_LFOSCR register written only normal mode. software must avoid this situation, otherwise unpredictable effect will occur inside device.
CLOCK MANAGER
S3F4A1HJ
Also, clock manager manages clock sources introduced above according following table: information given this table true outside transition period (i.e: when selected clock manager state fully established). will following paragraphs that some clocks generated differently during state transitions. Table 7-4. Clock Transition Mode NORMA LFOSCE (note1) LFSEL
(note1)
ARMCLK MCLK/ (CDIV+1) MCLK/ (CDIV+1) MCLK/ (CDIV+1)
SCLK MCLK/ (CDIV+1) MCLK/ (CDIV+1) MCLK/ (CDIV+1) MCLK/ (CDIV+1) MCLK/ (CDIV+1) MCLK/ (CDIV+1) PLLOUT/ (CDIV+1) PLLOUT/ (CDIV+1) PLLOUT/ (CDIV+1) PLLOUT/ (CDIV+1) PLLOUT/ (CDIV+1) PLLOUT/ (CDIV+1)
PCLK (note2) MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV Forbidden (note3)
GICCLK MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV MCLK/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV PLLOUT/ C_PCLK_DIV
LFCLK DIVOUT/ (LDIV+1) DIVOUT/ (LDIV+1) RINGCLK/ (LDIV+1) DIVOUT/ (LDIV+1) DIVOUT/ (LDIV+1) RINGCLK/ (LDIV+1) DIVOUT/ (LDIV+1) DIVOUT/ (LDIV+1) RINGCLK/ (LDIV+1) DIVOUT/ (LDIV+1) DIVOUT/ (LDIV+1) RINGCLK/ (LDIV+1)
Forbidden (note3)
IDLE NORMA
Forbidden (note3) PLLOUT/ (CDIV+1) PLLOUT/ (CDIV+1) PLLOUT/ (CDIV+1)
HIGH SPEED
Forbidden (note3)
IDLE HIGH SPEED
Forbidden (note3)
SLOW
DIVOUT DIVOUT
Forbidden (note3) DIVOUT/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) RINGCLK/ (LDIV+1)
S3F4A1HJ
CLOCK MANAGER
Table 7-4. Clock Transition (Continued) Mode LFOSCEN LFSEL
(note1) (note1)
ARMCLK
SCLK
PCLK (note2) Forbidden (note3)
GICCLK
LFCLK
IDLE SLOW POWER IDLE POWER HALT STOP CKFAIL RINGCLK/ (CDIV+1) DIVOUT DIVOUT RINGCLK DIVOUT DIVOUT DIVOUT DIVOUT DIVOUT
Forbidden (note3) DIVOUT/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) Forbidden (note3) DIVOUT/ (PCLK1DIV+1) RINGCLK/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) Forbidden (note3) DIVOUT/ (PCLK1DIV+1) RINGCLK/ (PCLK1DIV+1) Software control
(note4)
DIVOUT/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) RINGCLK/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) RINGCLK/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) DIVOUT/ (PCLK1DIV+1) RINGCLK/ (PCLK1DIV+1) RINGCLK/ C_PCLK_DIV
RINGCLK/ (LDIV+1) DIVOUT/ (LDIV+1) DIVOUT/ (LDIV+1) RINGCLK/ (LDIV+1) DIVOUT/ (LDIV+1) DIVOUT/ (LDIV+1) RINGCLK/ (LDIV+1) DIVOUT/ (LDIV+1) DIVOUT/ (LDIV+1) RINGCLK/ (LDIV+1) RINGCLK/ (LDIV+1)
RINGCLK DIVOUT
RINGCLK DIVOUT
Forbidden (note3) Software control
(note4)
RINGCLK RINGCLK/ (CDIV+1)
Software control
(note4)
Forbidden (note3) RINGCLK/ C_PCLK_DIV
CLOCK MANAGER
S3F4A1HJ
NOTES LFOSCEN LFSEL bits part CM_LFOSCR register written only normal mode. PCLK GICCLK derived from master clock through programmable frequency divider controlled PCLK1DIV field accessable CM_DIVBR register. software must avoid this clock mode condition, otherwise unpredictable effect will occur inside device. HALT mode, PCLK "on" "off" depending value PCLK1 CM_WIFR register C_PCLK_DIV (CDIV+1) (PCLK1DIV+1) mode, divided master clock frequency (CORECLK) must always greater than frequency oscillator (RINGCLK). recommended check stable when changing mode. when user switch from HIGH SPEED mode NORMAL mode, user must sure switch finished when SPEED mode (refer module) disabled (SPEEDMODE bit=0 IFC_MR register).So when changing mode, should check `STABLE' CM_SR. Program following steps: Clear stable interrupt Enable High speed mode FLASH controller HIGH SPEED mode "Wait stable rise" Clear stable status NORMAL mode "Wait stable rise" Disable high speed mode FLASH controller Clear stable status When waking-up from IDLE/HALT, user must insert NOPx4. IDLE/HALT Mode Flash/SRAM clock disabled. When asserted wake-up signal, Memory released from IDLE/HALT mode. faster than FLASH/SRAM memory. read FLASH/SRAM being under wait-state. protect this, user must have some-wait using NOP.
S3F4A1HJ
CLOCK MANAGER
FUNCTIONAL OPERATION
CLOCK MANAGEMENT 2.1.1 General Description power-up, master internal frequently oscillator enabled default. After reset, clock manager operates NORMAL mode disabled. Only NORMAL mode, user change configuration frequency oscillator with CM_LFOSCR register. CMCLKSEL field CM_SELR register HALTMODE, IDLEMODE, STOPMODE fields CM_CR register allows software select amongst user programmable modes: NORMAL, HIGH SPEED, SLOW, POWER, HALT, IDLE STOP. Before switching different mode, software ensure that clock manager already switching from mode another current mode already stable). IDLEMODE CM_CR register allows software disable ARM7 clock, other clock circuit stay unchanged (ARM7 will start again interrupt). Thus additional mode defined IDLE NORMAL, IDLE SLOW, IDLE POWER IDLE HIGH SPEED. NORMAL mode, main clocks directly generated from master oscillator. disabled. HIGH SPEED mode, automatically enabled. Before selecting this mode, user configure stabilization time CM_PSTR register, divider parameters (PLL_PRE, PMUL PLL_POST fields CM_PDPR register). PLL_ST CM_STR register used flag indicate that enabled stabilized. SLOW mode, main clock generated from divided master clock. MDIV division factor configured CM_MDIVR register. real division factor corresponds MDIV+1 value. This mode allowed only frequency oscillator enabled used. POWER mode (and HALT mode), main clocks generated from frequency oscillator from master oscillator divided MDIV+1. When frequency oscillator enabled, master oscillator automatically shut off. user must forget configure master oscillator stabilization time into CM_OSTR register before clock manager will switch SLOW, NORMAL HIGH SPEED mode from POWER mode. HALT mode, clocks disabled except clock, SCLK PCLK. But, user stop PCLK with CM_WIFR HALT mode. Interrupt will switch operating mode from HALT mode previous mode CM_SELR register. STOP mode, clocks disabled. Only external interrupt will allow switch normal mode from STOP mode. STOP mode must entered only from Normal mode, otherwise unexpected effect occur device.
enabled CM_MR register, embedded clock monitor will continuously check master oscillator operation. Upon master oscillator failure, clock manager will force circuit reset re-start CKFAIL mode. software informed oscillator failure reading CM_RSR register.
CLOCK MANAGER
S3F4A1HJ
2.1.2 Modes Transition Description Hardware Reset NORMAL mode Initial State Hardware reset sources nRESET, Watchdog timer Transition trigger Transition initialized whenever reset condition disappears Transition notes case power-up reset master oscillator off, circuit shall wait oscillator stabilization time, counting 65535 periods master oscillator clock. Final State After reset transition, circuit starts NORMAL mode using master oscillator clock source internal clocks, divider factor PCLK1DIV CDIV parameters their reset values. LFCLK DIVOUT/(LDIV+1) clock.
Wait oscillator stabilization time RESET Condition Active Inactive
Ring Oscillator
Enabled
Master Oscillator
Enabled Disabled
SCLK
Disabled
MCLK
ARMCLK
Disabled
MCLK
PCLK
Disabled
MCLK
GICCLK
Disabled
MCLK
LFCLK
Disabled
MCLK
Figure 7-3. Transition Diagram: Hardware Reset NORMAL Mode
7-10
S3F4A1HJ
CLOCK MANAGER
Clock monitor reset CKFAIL mode Initial State circuit state before this transition. Clock monitor feature must activated. (CM_EN must CM_MR register) internal frequency oscillator must enabled.(LFOSCEN must CM_LFOSCR register) Transition trigger transition occurs whenever clock monitor detects malfunction master clock. Final State After clock monitor reset, circuit enters CKFAIL mode, which functionally equivalent NORMAL mode except that clocks derived from internal frequency oscillator. Important note User should change other modes writing CMCLK_SEL field CKFAIL mode. Otherwise, unpredictable effects occur inside device.
Clock monitor detects failure master oscillator Clock Monitor RESET Ring Oscillator Inactive Active Inactive
Enabled
Master Oscillator
Enabled
Unavailable (failure)
Working (note)
Disabled
SCLK
Working (note)
RINGCLK (CDIV+1)
ARMCLK
Working (note)
RINGCLK (CDIV+1)
PCLK
Working (note)
RINGCLK C_PCLK_DIV
GICCLK
Working (note)
RINGCLK C_PCLK_DIV
LFCLK
Working (note)
RINGCLK (LDIV+1)
Figure 7-4. Transition Diagram: Reset CKFAIL mode
NOTE: Clock status before clock monitor reset depends state device.
7-11
CLOCK MANAGER
S3F4A1HJ
NORMAL mode HIGHSPEED mode Initial State assumed that circuit NORMAL mode before transition. software must have previously written appropriate values CM_PDPR register (PLL divider parameters) CM_PSTR register (PLL stabilization time). This very important because those registers provide valid initial parameters after reset. Transition trigger transition triggered upon software control when HIGHSPEED code written CM_SELR register. Final State After automatic transition, circuit resumes HIGHSPEED mode, where system clock derived from output. status LFCLK depends LFSEL field described below. STABLE interrupt occurs programmed)
Software writes CMCLK_SEL field Automatically waits stabilization time
CMCLK_SEL
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
Enabled
SCLK
MCLK (CDIV+1)
PLLCLK (CDIV+1)
ARMCLK
MCLK (CDIV+1) MCLK C_PCLK_DIV MCLK C_PCLK_DIV
PLLCLK (CDIV+1)
PCLK
PLLCLK C_PCLK_DIV PLLCLK C_PCLK_DIV
(note)
GICCLK
LFCLK
Depends LF_SEL field value
STABLE interrupt
Figure 7-5. Normal Mode High Speed Mode
NOTE: (LS_SEL then LFCLK MCLK (MDIV+1)x(LDIV+1)) Else LFCLK RINGCLK/(LDIV+1)
7-12
S3F4A1HJ
CLOCK MANAGER
NORMAL mode IDLE-NORMAL mode Initial State assumed that circuit NORMAL mode before transition. Transition trigger transition triggered upon software control when IDLEMODE CM_CR register. Final State After automatic transition, circuit resumes IDLE-NORMAL mode, which same NORMAL mode except that ARM7 clock disabled.
Software writes IDLEMODE
IDLEMODE
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
SCLK
MCLK (CDIV+1)
ARMCLK
MCLK (CDIV+1)
Disabled
PCLK
MCLK C_PCLK_DIV
GICCLK
MCLK C_PCLK_DIV
LFCLK
Depends LFSEL field value (note)
Figure 7-6. Normal Mode IDLE-Normal Speed Mode
NOTE: (LS_SEL then LFCLK MCLK (MDIV+1)x(LDIV+1)) Else LFCLK RINGCLK/(LDIV+1)
7-13
CLOCK MANAGER
S3F4A1HJ
IDLE-NORMAL mode NORMAL mode Initial State assumed that circuit IDLE-NORMAL mode before transition. Transition trigger transition triggered upon valid interrupt from (interrupt controller) Final State After automatic transition, circuit resumes NORMAL mode same state before entering IDLE-NORMAL mode.
Interrupt occurs
interrupt
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
SCLK
MCLK (CDIV+1)
ARMCLK
Disabled
MCLK (CDIV+1)
PCLK
MCLK C_PCLK_DIV
GICCLK
MCLK C_PCLK_DIV
LFCLK
Depends LFSEL field value (note)
Figure 7-7. IDLE-Normal Mode Normal Speed Mode
NOTE: (LS_SEL then LFCLK MCLK (MDIV+1)x(LDIV+1)) Else LFCLK RINGCLK/(LDIV+1)
7-14
S3F4A1HJ
CLOCK MANAGER
NORMAL mode SLOW mode Initial State assumed that circuit NORMAL mode before transition. software must have selected low-frequency from ring-oscillator (LFOSCEN LFSEL other values forbidden SLOW mode selection. Transition trigger transition triggered upon software control when SLOW mode code written CM_SELR register. Final State After automatic transition, circuit resumes SLOW mode, where system clock derived from master oscillator through frequency divider. LFCLK clock RINGCLK (LDIV+1). STABLE interrupt occurs.(if programmed)
Software writes CMCLK_SEL field
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
SCLK
MCLK (CDIV+1)
DIVOUT
ARMCLK
MCLK (CDIV+1) MCLK C_PCLK_DIV MCLK C_PCLK_DIV
DIVOUT
PCLK
DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1) RINGCLK (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-8. Transition Diagram: NORMAL Mode SLOW mode
7-15
CLOCK MANAGER
S3F4A1HJ
NORMAL mode LOWPOWER mode Initial State assumed that circuit NORMAL mode before transition. software must have previously written appropriate value CM_OSTR register (master oscillator stabilization time) software must have previously selected Low-Frequency clock strategy CM_LFOSCR register. Note that this register must written only NORMAL mode. Transition trigger transition triggered upon software control when LOWPOWER mode code written CM_SELR register. Final State After automatic transition, circuit resumes LOWPOWER mode, where system clock derived from LFCLK clock. LFCLK clock status depends LFSEL field value STABLE interrupt occurs.(if programmed)
Software writes CMCLK_SEL field
CMCLK_SEL
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
SCLK
MCLK (CDIV+1)
DIVOUT
ARMCLK
MCLK (CDIV+1) MCLK C_PCLK_DIV MCLK C_PCLK_DIV
DIVOUT
PCLK
DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1) DIVOUT (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-9. Normal Mode Power Mode (LF_SEL
7-16
S3F4A1HJ
CLOCK MANAGER
Software writes CMCLK_SEL field
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
Disabled
SCLK
MCLK (CDIV+1)
RINGCLK
ARMCLK
MCLK (CDIV+1) MCLK C_PCLK_DIV MCLK C_PCLK_DIV
RINGCLK
PCLK
RINGCLK (PCLK1DIV+1) RINGCLK (PCLK1DIV+1) RINGCLK (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-10. Transition Diagram: NORMAL Mode LOWPOWER Mode (LFSEL=1)
7-17
CLOCK MANAGER
S3F4A1HJ
NORMAL mode HALT mode Initial State assumed that circuit NORMAL mode before transition. software must have previously selected Low-Frequency clock strategy CM_LFOSCR register. Note that this register must written only NORMAL mode. software must have previously written appropriate value CM_OSTR register (master oscillator stabilization time) Transition trigger transition triggered upon software control when HALTMODE CM_CR register. Final State After automatic transition, circuit resumes HALT mode, where clock disabled, SCLK clock derived from LFCLK, clock derived from LFCLK others system clocks activity depends CM_WFIR value. LFCLK clock status depends LFSEL field value. STABLE interrupt occurs.(if programmed)
Software writes HALTMODE field
HALTMODE
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
SCLK
MCLK (CDIV+1)
DIVOUT
ARMCLK
MCLK (CDIV+1) MCLK C_PCLK_DIV MCLK C_PCLK_DIV
Disabled
PCLK
Software Controlled
(note)
GICCLK
DIVOUT (PCLK1DIV+1) DIVOUT (LDIV+1)
LFCLK
STABLE interrupt
Figure 7-11. Transition Diagram: NORMAL Mode HALT Mode (LFSEL=0)
NOTE: PCLK activity depends CM_WIFR register value either (DIVOUT (PCLK1DIV+1)) disabled
7-18
S3F4A1HJ
CLOCK MANAGER
Software writes HALTMODE field
HALTMODE
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
SCLK
MCLK (CDIV+1)
RINGCLK
ARMCLK
MCLK (CDIV+1) MCLK C_PCLK_DIV MCLK C_PCLK_DIV
Disabled
PCLK
Software Controlled (note)
GICCLK
RINGCLK (PCLK1DIV+1) RINGCLK (LDIV+1)
LFCLK
STABLE interrupt
Figure 7-12. Transition Diagram: NORMAL Mode HALT Mode (LFSEL=1)
NOTE: PCLK activity depends CM_WIFR register value either (RINGCLK (PCLK1DIV+1)) disabled
7-19
CLOCK MANAGER
S3F4A1HJ
NORMAL mode STOP mode Initial State assumed that circuit NORMAL mode before transition. software must have previously written appropriate value CM_OSTR register (master oscillator stabilization time) software must have previously selected Low-Frequency clock strategy CM_LFOSCR register. Note that this register must written only NORMAL mode. Transition trigger transition triggered upon software control when STOMODE CM_CR register. Final State After automatic transition, chip switched STOP mode, where oscillators disabled. circuit shall only wake-up external wake-up interrupts. (Refer P14-46)
Software writes STOPMODE field
STOPMODE
Depends LFOSC_EN
Ring Oscillator
Disabled
Master Oscillator
Enabled
Disabled
Disabled
SCLK
MCLK (CDIV+1)
Disabled
ARMCLK
MCLK (CDIV+1) MCLK C_PCLK_DIV MCLK C_PCLK_DIV Depends LFSEL Value
Disabled
PCLK
Disabled
GICCLK
Disabled
LFCLK
Disabled
Figure 7-13. Transition Diagram: NORMAL Mode STOP Mode
7-20
S3F4A1HJ
CLOCK MANAGER
LOWPOWER mode IDLE-LOWPOWER mode Initial State assumed that circuit LOWPOWER mode before transition. Transition trigger transition triggered upon software control when IDLEMODE CM_CR register Final State After automatic transition, circuit resumes IDLE-LOWPOWER mode which same LOWPOWER mode except that ARM7 clock disabled.
Software writes IDLEMODE field
IDLEMODE
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
SCLK
DIVOUT
ARMCLK
DIVOUT
Disabled
PCLK
DIVOUT (PCLK1DIV+1)
GICCLK
DIVOUT (PCLK1DIV+1)
LFCLK
DIVOUT (LDIV+1)
Figure 7-14. Transition Diagram: LOWPOWER Mode IDLE-LOWPOWER Mode (LFSEL=0)
7-21
CLOCK MANAGER
S3F4A1HJ
Software writes IDLEMODE field
IDLEMODE
Ring Oscillator
Enabled
Master Oscillator
Disabled
Disabled
SCLK
RINGCLK
ARMCLK
RINGCLK
Disabled
PCLK
RINGCLK (PCLK1DIV+1)
GICCLK
RINGCLK (PCLK1DIV+1)
LFCLK
RINGCLK (LDIV+1)
Figure 7-15. Transition Diagram: LOWPOWER Mode IDLE-LOWPOWER Mode (LFSEL=1)
7-22
S3F4A1HJ
CLOCK MANAGER
IDLE-LOWPOWER LOWPOWER mode Initial State assumed that circuit IDLE-LOWPOWER mode before transition. Transition trigger transition triggered upon valid interrupt from (interrupt controller) Final State After automatic transition, circuit resumes LOWPOWER mode same state before entering IDLE-LOWPOWER mode.
Interrupt occurs
Interrupt
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
SCLK
DIVOUT
ARMCLK
Disabled
DIVOUT
PCLK
DIVOUT (PCLK1DIV+1)
GICCLK
DIVOUT (PCLK1DIV+1)
LFCLK
DIVOUT (LDIV+1)
Figure 7-16. Transition Diagram: IDLE-LOWPOWER Mode LOWPOWER Mode (LFSEL=0)
7-23
CLOCK MANAGER
S3F4A1HJ
Interrupt occurs
Interrupt
Ring Oscillator
Enabled
Master Oscillator
Disabled
Disabled
SCLK
RINGCLK
ARMCLK
Disabled
RINGCLK
PCLK
RINGCLK (PCLK1DIV+1)
GICCLK
RINGCLK (PCLK1DIV+1)
LFCLK
RINGCLK (LDIV+1)
Figure 7-17. Transition Diagram: IDLE-LOWPOWER Mode LOWPOWER Mode (LFSEL=1)
7-24
S3F4A1HJ
CLOCK MANAGER
LOWPOWER mode NORMAL mode Initial State assumed that circuit LOWPOWER mode before transition. Transition trigger transition triggered upon software control when NORMAL mode code written CM_SELR register Final State After automatic transition, circuit resumes NORMAL mode where system clocks derived from master oscillator LFCLK clock status depends LFSEL value. STABLE interrupt occurs.(if programmed)
Software writes CMCLK_SEL field
CMCLK_SEL
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
SCLK
DIVOUT
MCLK (CDIV+1)
ARMCLK
DIVOUT DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1)
MCLK (CDIV+1)
PCLK
MCLK C_PCLK_DIV MCLK C_PCLK_DIV DIVOUT (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-18. Transition Diagram: LOWPOWER Mode NORMAL Mode (LFSEL=0)
7-25
CLOCK MANAGER
S3F4A1HJ
Software writes CMCLK_SEL field
Automatically waits oscillator stabilization time
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Disabled
Enabled
Disabled
SCLK
RINGCLK
MCLK (CDIV+1)
ARMCLK
RINGCLK RINGCLK (PCLK1DIV+1) RINGCLK (PCLK1DIV+1)
MCLK (CDIV+1)
PCLK
MCLK C_PCLK_DIV MCLK C_PCLK_DIV RINGCLK (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-19. Transition Diagram: LOWPOWER Mode NORMAL Mode (LFSEL=1)
7-26
S3F4A1HJ
CLOCK MANAGER
LOWPOWER mode HIGHSPEED mode Initial State assumed that circuit LOWPOWER mode before transition. software must have previously written appropriate values CM_PDPR register (PLL dividers parameters), CM_PSTR register (PLL stabilization time) CM_OSTR (master oscillator stabilization time). This very important because those registers provide valid initial parameters after reset. Transition trigger transition triggered upon software control when HIGHSPEED code written CM_SELR register. Final State After automatic transition, circuit resumes HIGHSPEED mode, where system clock derived from output. status LFCLK depends LFSEL field described bellow. STABLE interrupt occurs.(if programmed) Important note During transition, previous clock maintained until master oscillator LFSEL=1) stabilized. Then high-speed clock provided circuit STABLE interrupt occurs.
Software writes CMCLK_SEL field Automatically waits stabilization time
CMCLK_SEL
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
Enabled
SCLK
DIVOUT
PLLOUT (CDIV+1)
ARMCLK
DIVOUT DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1)
PLLOUT (CDIV+1)
PCLK
PLLOUT C_PCLK_DIV PLLOUT C_PCLK_DIV DIVOUT (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-20. Transition Diagram: LOWPOWER Mode HIGHSPEED Mode (LFSEL=0)
7-27
CLOCK MANAGER
S3F4A1HJ
Software writes CMCLK_SEL field
Automatically waits oscillator stabilization time
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Disabled
Enabled
Disabled
Enabled
SCLK
RINGCLK
PLLOUT (CDIV+1)
ARMCLK
RINGCLK RINGCLK (PCLK1DIV+1) RINGCLK (PCLK1DIV+1)
PLLOUT (CDIV+1)
PCLK
PLLOUT C_PCLK_DIV PLLOUT C_PCLK_DIV RINGCLK (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-21. Transition Diagram: LOWPOWER Mode HIGHSPEED Mode (LFSEL=1)
7-28
S3F4A1HJ
CLOCK MANAGER
LOWPOWER mode SLOW mode Initial State assumed that circuit LOWPOWER mode before transition. software must have selected low-frequency from ring-oscillator (LFOSCEN LFSEL other values forbidden SLOW mode selection. software must have previously written appropriate value CM_OSTR register (master oscillator stabilization time) Transition trigger transition triggered upon software control when SLOW mode code written CM_SELR register. Final State After automatic transition, circuit resumes SLOW mode, where system clock derived from master oscillator through frequency divider. LFCLK clock RINGCLK (LDIV+1). STABLE interrupt occurs.(if programmed) Important note During transition, system clock remains derived from RINGCLK. Then, when main oscillator stable, STABLE interrupt issued that software informed effective clock source change.
Software writes CMCLK_SEL field Automatically waits oscillator stabilization time
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Disabled
Enabled
Disabled
SCLK
RINGCLK
DIVOUT
ARMCLK
RINGCLK RINGCLK (PCLK1DIV+1) RINGCLK (PCLK1DIV+1) RINGCLK (LDIV+1)
DIVOUT
PCLK
DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-22. Transition Diagram: LOWPOWER Mode SLOW Mode
7-29
CLOCK MANAGER
S3F4A1HJ
LOWPOWER mode HALT mode Initial State assumed that circuit LOWPOWER mode before transition. Transition trigger transition triggered upon software control when HALTMODE CM_CR register. Final State After automatic transition, circuit resumes HALT mode, where clock disabled, SCLK clock derived from LFCLK, clock derived from LFCLK others system clocks activity depends CM_WFIR value. LFCLK clock status depends LFSEL field value. STABLE interrupt occurs.(if programmed)
Software writes HALTMODE field
HALTMODE
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Disabled
SCLK
DIVOUT
ARMCLK
DIVOUT DIVOUT (PCLK1DIV+1)
Disabled
PCLK
Software Control (note)
GICCLK
DIVOUT (PCLK1DIV+1)
LFCLK
DIVOUT (LDIV+1)
STABLE interrupt
Figure 7-23. Transition Diagram: LOWPOWER Mode HALT Mode (LFSEL==0)
NOTE: PCLK activity depends CM_WIFR register value either (DIVOUT (PCLK1DIV+1)) disabled
7-30
S3F4A1HJ
CLOCK MANAGER
Software writes HALTMODE field
HALTMODE
Ring Oscillator
Enabled
Master Oscillator
Disabled
Disabled
SCLK
RINGCLK
ARMCLK
RINGCLK
Disabled
PCLK
RINGCLK (PCLK1DIV+1)
Software Control (note)
GICCLK
RINGCLK (PCLK1DIV+1)
LFCLK
RINGCLK (LDIV+1)
STABLE interrupt
Figure 7-24. Transition Diagram: LOWPOWER Mode HALT Mode (LFSEL==1)
NOTE: PCLK activity depends CM_WIFR register value either (RINGCLK (PCLK1DIV+1)) disabled
7-31
CLOCK MANAGER
S3F4A1HJ
SLOW mode IDLE-SLOW mode Initial State assumed that circuit SLOW mode before transition. Transition trigger transition triggered upon software control when IDLEMODE CM_CR register Final State After automatic transition, circuit resumes IDLE-SLOW mode which same SLOW mode except that ARM7 clock disabled.
Software writes IDLEMODE field
IDLEMODE
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
SCLK
DIVOUT
ARMCLK
DIVOUT
Disabled
PCLK
DIVOUT (PCLK1DIV+1)
GICCLK
DIVOUT (PCLK1DIV+1)
LFCLK
RINGCLK (LDIV+1)
Figure 7-25. Transition Diagram: SLOW Mode IDLE-SLOW Mode
7-32
S3F4A1HJ
CLOCK MANAGER
IDLE-SLOW SLOW mode Initial State assumed that circuit IDLE-SLOW mode before transition. Transition trigger transition triggered upon valid interrupt from (interrupt controller) Final State After automatic transition, circuit resumes SLOW mode same state before entering IDLE-SLOW mode.
Interrupt occurs
Interrupt
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
SCLK
DIVOUT
ARMCLK
Disabled
DIVOUT
PCLK
DIVOUT (PCLK1DIV+1)
GICCLK
DIVOUT (PCLK1DIV+1)
LFCLK
DIVOUT (LDIV+1)
Figure 7-26. Transition Diagram: IDLE-SLOW Mode SLOW Mode
7-33
CLOCK MANAGER
S3F4A1HJ
SLOW mode NORMAL Initial State assumed that circuit SLOW mode before transition Transition trigger transition triggered upon software control when NORMAL mode code written CM_SELR register. Final State After automatic transition, circuit resumes NORMAL mode, where system clock derived from master oscillator. LFCLK clock same ring oscillator output. STABLE interrupt occurs.(if programmed)
Software writes CMCLK_SEL field
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
SCLK
DIVOUT
MCLK (CDIV+1)
ARMCLK
DIVOUT DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1)
MCLK (CDIV+1)
PCLK
MCLK C_PCLK_DIV MCLK C_PCLK_DIV RINGCLK (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-27. Transition Diagram: SLOW Mode NORMAL Mode
7-34
S3F4A1HJ
CLOCK MANAGER
SLOW mode HIGHSPEED mode Initial State assumed that circuit SLOW mode before transition. software must have previously written appropriate values CM_PDPR register (PLL divider parameters) CM_PSTR register (PLL stabilization time). This very important because those registers provide valid initial parameters after reset. Transition trigger transition triggered upon software control when HIGHSPEED mode code written CM_SELR register. During stabilization time, slow mode clock maintained into circuit. Final State After automatic transition, circuit resumes HIGHSPEED mode, where system clock derived from output. LFCLK clock RINGCLK (LDIV+1). STABLE interrupt occurs.(if programmed)
Software writes CMCLK_SEL field Automatically waits stabilization time
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
Enabled
SCLK
DIVOUT
PLLOUT (CDIV+1)
ARMCLK
DIVOUT DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1)
PLLOUT (CDIV+1)
PCLK
PLLOUT C_PCLK_DIV PLLOUT C_PCLK_DIV RINGCLK (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-28. Transition Diagram: SLOW Mode HIGHSPEED Mode
7-35
CLOCK MANAGER
S3F4A1HJ
SLOW mode LOWPOWER mode Initial State assumed that circuit SLOW mode before transition. Transition trigger transition triggered upon software control when LOWPOWER mode code written CM_SELR register. Final State After automatic transition, circuit resumes LOWPOWER mode, where clocks derived from LFCLK clock. LFCLK clock RINGCLK (LDIV+1). STABLE interrupt occurs.(if programmed)
Software writes CMCLK_SEL field
CMCLK_SEL
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
Disabled
SCLK
DIVOUT
RINGCLK
ARMCLK
DIVOUT DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1)
RINGCLK
PCLK
RINGCLK (PCLK1DIV+1) RINGCLK (PCLK1DIV+1) RINGCLK (LDIV+1)
GICCLK
LFCLK
STABLE interrupt
Figure 7-29. Transition Diagram: SLOW Mode LOWPOWER Mode
7-36
S3F4A1HJ
CLOCK MANAGER
SLOW mode HALT mode Initial State assumed that circuit SLOW mode before transition. Transition trigger transition triggered upon software control when HALTMODE CM_CR register. Final State After automatic transition, circuit resumes HALTMODE mode, where system clock derived from ring oscillator. LFCLK clock RINGCLK (LDIV+1). STABLE interrupt occurs.(if programmed)
Software writes HALTMODE field
HALTMODE
Ring Oscillator
Enabled
Master Oscillator
Enabled
Disabled
Disabled
SCLK
DIVOUT
RINGCLK
ARMCLK
DIVOUT
Disabled
PCLK
DIVOUT (PCLK1DIV+1) DIVOUT (PCLK1DIV+1)
Software Controlled (note)
GICCLK
RINGCLK (PCLK1DIV+1)
LFCLK
RINGCLK (LDIV+1)
STABLE interrupt
Figure 7-30. Transition Diagram: SLOW Mode HALT Mode
NOTE: PCLK activity depends CM_WIFR register value either (RINGCLK (PCLK1DIV+1)) disabled.
7-37
CLOCK MANAGER
S3F4A1HJ
HIGHSPEED mode IDLE-HIGHSPEED mode Initial State assumed that circuit HIGHSPEED mode before transition. Transition trigger transition triggered upon software control when IDLEMODE CM_CR register Final State After automatic transition, circuit resumes IDLE-HIGHSPEED mode which same HIGHSPEED mode except that ARM7 clock disabled.
Software writes IDLEMODE field
IDLEMODE
Ring Oscillator
Enabled (LFOSCEN
Master Oscillator
Enabled
Enabled
SCLK
PLLOUT (CDIV+1)
ARMCLK
PLLOUT (CDIV+1)
Disabled
PCLK
PLLOUT C_PCLK_DIV
GICCLK
PLLOUT C_PCLK_DIV
LFCLK
Depends LFSEL field value (note)
Figure 7-31. Transition Diagram: HIGHSPEED Mode IDLE-HIGHSPEED Mode
NOTE: (LS_SEL then LFCLK MCLK (MDIV+1)x(LDIV+1)) Else LFCLK RINGCLK/(LDIV+1)
7-38
S3F4A1HJ
CLOCK MANAGER
IDLE-HIGHSPEED mode HIGHSPEED mode Initial State assumed that circuit IDLE-HIGHSPEED mode before transition. Transition trigger transition triggered upon valid interrupt from (interrupt controller) Final State After automatic transition, circuit resumes HIGHSPEED mode same state before entering IDLE-HIGHSPEED mode.
Software writes IDLEMODE field
IDLEMODE
Ring Oscillator
Enabled (LFOSCEN
Master Oscillator
Enabled
Enabled
SCLK
PLLOUT (CDIV+1)
ARMCLK
Disabled
PLLOUT (CDIV+1)
PCLK
PLLOUT C_PCLK_DIV
GICCLK
PLLOUT C_PCLK_DIV
LFCLK
Depends LFSEL field value (note)
Figure 7-32. Transition Diagram: HIGHSPEED Mode IDLE-HIGHSPEED Mode
NOTE: (LS_SEL then LFCLK MCLK (MDIV+1)x(LDIV+1)) Else LFCLK RINGCLK/(LDIV+1)
7-39
CLOCK MANAGER
S3F4A1HJ
HIGHSPEED mode NORMAL mode Initial State assumed that circuit HIGHSPEED mode before transition. Transition trigger transition triggered upon software control when NORMAL mode code written CM_SELR register. Final State After automatic transition, circuit resumes NORMAL mode, where system clocks derived from master oscillator clock. LFCLK clock status depends LFSEL field value. STABLE interrupt occurs.(if programmed)
Software writes CMCLK_SEL field
CMCLK_SEL
Ring Oscillator
Enabled (LFOSC_EN==1)
Master Oscillator
Enabled
Enabled
Disabled
SCLK
PLLOUT (CDIV+1)
MCLK (CDIV+1)
ARMCLK
PLLOUT (CDIV+1) PLLOUT C_PCLK_DIV PLLOUT C_PCLK_DIV
MCLK (CDIV+1)
PCLK
MCLK C_PCLK_DIV MCLK C_PCLK_DIV Depends LF_SEL field value
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