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BeagleBoard System Reference Manual
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THIS DOCUMENT This work licensed under Creative Commons Attribution-Share Alike Unported License. view copy this license, visit send letter Creative Commons, Second Street, Suite 300, Francisco, California, 94105, USA. derivative works attributed Gerald Coley BeagleBoard.org. more information, questions, concerns, issues submit them gerald@BeagleBoard.org BEAGLEBOARD DESIGN These design materials referred this document *NOT SUPPORTED* constitute reference design. Only "community" support allowed resources BeagleBoard.org/discuss. THERE WARRANTY DESIGN MATERIALS, EXTENT PERMITTED APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED WRITING COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE DESIGN MATERIALS WITHOUT WARRANTY KIND, EITHER EXPRESSED IMPLIED, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. ENTIRE RISK QUALITY PERFORMANCE DESIGN MATERIALS WITH YOU. SHOULD DESIGN MATERIALS PROVE DEFECTIVE, ASSUME COST NECESSARY SERVICING, REPAIR CORRECTION. mean these design materials totally unsuitable purposes.
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BeagleBoard.org provides enclosed product(s) under following conditions:
This evaluation board/kit intended ENGINEERING DEVELOPMENT, DEMONSTRATION, EVALUATION PURPOSES ONLY considered BeagleBoard.org finished end-product general consumer use. Persons handling product(s) must have electronics training observe good engineering practice standards. such, goods being provided intended complete terms required design-, marketing-, and/or manufacturing-related protective considerations, including product safety environmental measures typically found products that incorporate such semiconductor components circuit boards. This evaluation board/kit does fall within scope European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, therefore meet technical requirements these directives other related directives. Should this evaluation board/kit meet specifications indicated User's Guide, board/kit returned within days from date delivery full refund. FOREGOING WARRANTY EXCLUSIVE WARRANTY MADE SELLER BUYER LIEU OTHER WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, INCLUDING WARRANTY MERCHANTABILITY FITNESS PARTICULAR PURPOSE. user assumes responsibility liability proper safe handling goods. Further, user indemnifies BeagleBoard.org from claims arising from handling goods. open construction product, user's responsibility take appropriate precautions with regard electrostatic discharge. EXCEPT EXTENT INDEMNITY FORTH ABOVE, NEITHER PARTY SHALL LIABLE OTHER INDIRECT, SPECIAL, INCIDENTAL, CONSEQUENTIAL DAMAGES. BeagleBoard.org currently deals with variety customers products, therefore arrangement with user exclusive. BeagleBoard.org assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. Please read User's Guide and, specifically, Warnings Restrictions notice User's Guide prior handling product. This notice contains important safety information about temperatures voltages. additional information BeagleBoard.org environmental and/or safety programs, please contact visit BeagleBoard.org. license granted under patent right other intellectual property right BeagleBoard.org covering relating machine, process, combination which such BeagleBoard.org products services might used. Mailing Address: BeagleBoard.org North Glenville #195 Richardson, 75081
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WARRANTY: BeagleBoard warranted against defects materials workmanship period days from purchase. This warranty does cover problems occurring result improper use, modifications, exposure water, excessive voltages, abuse, accidents. boards will returned standard mail issue found. issue found express return needed, customer will shipping costs.
Before returning board, please visit BeagleBoard.org/support
Please refer sections this document board checkout procedures troubleshooting guides.
return defective board, please request
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Table Contents
FIGURES TABLES 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 INTRODUCTION.13 CHANGE HISTORY.14 CHANGE HISTORY REVISION DEFINITIONS REFERENCES.15 DEFINITIONS BEAGLEBOARD OVERVIEW BEAGLEBOARD USAGE SCENARIOS BEAGLEBOARD SPECIFICATION BEAGLEBOARD FEATURES.17 OMAP PROCESSOR.18 MEMORY.18 POWER MANAGEMENT.18 PORT HOST PORT STEREO AUDIO OUTPUT CONNECTOR STEREO AUDIO CONNECTOR S-VIDEO CONNECTOR DVI-D CONNECTOR.20 HEADER SD/MMC CONNECTOR RESET BUTTON USER/BOOT BUTTON INDICATORS POWER CONNECTOR JTAG CONNECTOR RS232 HEADER EXPANSION HEADER BEAGLEBOARD MECHANICAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS PRODUCT CONTENTS.26 BEAGLEBOARD SOFTWARE BEAGLEBOARD REPAIR BEAGLEBOARD HOOKUP.28 CONNECTING OTG.28 CONNECTING HOST CONNECTING OPTIONAL POWER CONNECTING JTAG.31 CONNECTING SERIAL CABLE CONNECTING S-VIDEO.33 CONNECTING DVI-D CABLE.34
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CONNECTING STEREO CABLE.35 CONNECTING STEREO CABLE INDICATOR LOCATIONS.37 BUTTON LOCATIONS SD/MMC CONNECTION CONNECTION BEAGLEBOARD SYSTEM ARCHITECTURE DESIGN
SYSTEM BLOCK DIAGRAM INPUT POWER.44 8.2.1 Source 8.2.2 Wall Supply Source 8.2.3 Source Control.45 8.2.4 3.3V Supply.46 8.2.5 Meter Current Measurement 8.2.6 Processor Current Measurement.46 POWER CONDITIONING TPS65950 RESET POWER MANAGEMENT 8.4.1 Main Core Voltages.49 8.4.2 Main Input.49 8.4.3 OMAP3530 Control.49 8.4.4 VIO_1V8.49 8.4.5 Main Core Voltages Smart Reflex 8.4.6 VOCORE_1V3.51 8.4.7 VDD2.51 PERIPHERAL VOLTAGES 8.5.1 VDD_PLL2.52 8.5.2 VDD_PLL1.52 8.5.3 VDAC_1V8 8.5.4 VDD_SIM 8.5.5 VMMC1 8.5.6 VAUX2.54 8.5.7 Boot Configuration.54 8.5.8 Backup Battery.55 8.5.9 Power Sequencing 8.5.10 Reset Signals.57 8.5.11 mSecure Signal OMAP3530 PROCESSOR 8.6.1 Overview.59 8.6.2 SDRAM Bus.60 8.6.3 GPMC Bus.60 8.6.4 8.6.5 McBSP2.61 8.6.6 McBSP1.61 8.6.7 McBSP3.62 8.6.8 Muxing 8.6.9 GPIO Mapping 8.6.10 Interrupt Mapping MEMORY DEVICE SYSTEM CLOCKS 8.8.1 32KHz Clock 8.8.2 26MHz Clock.66 8.8.3 McBSP_CLKS PORT.67 8.9.1 Overview
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8.9.2 Design 8.9.3 ULPI Interface.68 8.9.4 Charge Pump.69 8.9.5 Connector.70 8.9.6 Protection.70 8.10 HOST PORT 8.10.1 Host OMAP3 Interface.71 8.10.2 Host PHY.71 8.10.3 Host Connector 8.10.4 Host Power Control.73 8.11 SD/MMC.73 8.11.1 Power 8.11.2 OMAP3530 Interface.76 8.11.3 Card Detect 8.11.4 Write Protect.78 8.11.5 Mode 8.11.6 Booting From SD/MMC Cards.78 8.12 AUDIO INTERFACE 8.12.1 OMAP3530 Audio Interface 8.12.2 TPS65950 Audio Interface.80 8.12.3 Audio Output Jack 8.12.4 Audio Input Jack.80 8.13 DVI-D INTERFACE 8.13.1 OMAP3530 Interface 8.13.2 OMAP3530 Power 8.13.3 TFP410 Framer.83 8.13.4 TFP410 Power.84 8.13.5 TFP410 Control Pins.84 8.13.6 DVI-D Connector 8.14 EXPANSION HEADERS 8.15 S-VIDEO.89 8.16 RS232 PORT 8.16.1 OMAP3530 Interface.90 8.16.2 OMAP3530 Level Translator 8.16.3 RS232 Transceiver.90 8.16.4 Connector 8.17 INDICATORS 8.17.1 Power Indicator.92 8.17.2 Status Indicator.92 8.17.3 User Indicators 8.18 JTAG.93 8.18.1 OMAP3530 Interface.93 8.18.2 Connector 8.19 EXPANSION HEADER 8.19.1 OMAP3530 Interface.95 8.19.2 Expansion Signals.96 8.19.3 Power.98 8.19.4 Reset 8.19.5 Power Control 8.20 ADDITIONAL EXPANSION HEADER CONNECTOR PINOUTS CABLES .100 POWER CONNECTOR .100 OTG.101 S-VIDEO.102
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DVI-D .103 LCD.105 9.5.1 Connector Pinout .105 9.5.2 Connector Suppliers .106 9.5.3 Dimensions .107 9.5.4 Mounting Scenarios.108 AUDIO CONNECTIONS .110 AUDIO .111 JTAG.112 RS232.114 9.10 EXPANSION .115 9.11 BATTERY INSTALLATION .116 9.11.1 Battery .116 9.11.2 Battery Installation .116 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 11.0 BEAGLEBOARD ACCESSORIES .118 POWER SUPPLY .119 SERIAL RIBBON CABLE .120 HUBS .121 CABLES .121 DVI-D MONITORS .122 SD/MMC CARDS .122 ETHERNET .123 WIFI .123 BLUETOOTH .124 EXPANSION CARD DESIGN .125 MECHANICAL INFORMATION.126
11.1 BEAGLEBOARD DIMENSIONS .126 11.2 BEAGLEBOARD EXPANSION CARD DESIGN INFORMATION .127 11.2.1 Mounting Method .127 11.2.2 Expansion EEPROM .127 12.0 BOARD VERIFICATION .129 12.1 EQUIPMENT .129 12.2 BOX.130 12.3 CARD CONFIGURATION .131 12.4 SETUP .132 12.5 FACTORY BOOT VERIFICATION .132 12.6 BOARD BOOT .133 12.7 FACTORY BOOT REINSTALL .134 12.8 BOOTING KERNEL .136 12.9 UBOOT TESTS .142 12.9.1 EDID Test .142 12.9.2 Test .142 12.9.3 DVI-D Test.143 12.10 KERNEL BASED TESTS .143 12.10.1 DVI-D Test.143 12.10.2 S-Video Test.143 12.10.3 Audio Test.144 13.0 TROUBLESHOOTING .148 13.1 ACCESS POINTS .148 13.1.1 Voltage Points.148 13.1.2 Signal Access Points.150
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13.2 TROUBLESHOOTING GUIDE .151 13.3 SERIAL PORT ISSUES .152 13.3.1 First Step .153 13.3.2 Second Step.154 13.3.3 Third Step .155 13.3.4 Fourth Step .155 14.0 15.0 16.0 17.0 18.0 KNOWN ISSUES.157 COMPONENT LOCATIONS .158 SCHEMATICS.160 BILLS MATERIAL .171 INFORMATION.172
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure BeagleBoard Usage Scenarios Y-Cable Box. Contents. Connection Host Connection. Power Connection BeagleBoard JTAG Connection BeagleBoard Serial Cable Connection. BeagleBoard S-Video Connection. BeagleBoard DVI-D Connection. BeagleBoard Audio Cable Connection. BeagleBoard Audio Cable Connection. BeagleBoard Indicator Locations BeagleBoard Button Location. BeagleBoard SD/MMC Location BeagleBoard Header Location. BeagleBoard High Level Block Diagram BeagleBoard Side Components. BeagleBoard Backside Components. Input Power Section. Processor Current Measurement Power Conditioning Main Power Rails. Peripheral Voltages. Power Sequencing. Reset Circuitry OMAP3530 Block Diagram McBSP2 Interface. McBSP1 Interface.
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McBSP3 Interface. Memory System Clocks. Design Host Design. Example SDIO Card RS-MMC Card SD/MMC Interface Audio Circuitry DVI-D Interface S-Video Interface RS232 Interface Design RS232 Cable Indicator Design. JTAG Interface. Expansion Header Power Connector. Connector. Host Shorting Pads S-Video Connector. DVI-D Connector. DVI-D Cable. Mount Adapter. Mount Adapter. Bottom Mount Adapter Audio Plug. Audio Plug. Audio Plug Audio Plug. JTAG Connector Pinout. JTAG Adapter JTAG Connector Pinout. RS232 Header RS232 Flat Cable Expansion Sockets Optional Battery. Optional Battery Location. Power Supply RS232 Cable RS232 Cable Wiring HDMI DVI-D Cable Ethernet Adapters. WiFi Bluetooth. BeagleBoard Dimension Drawing BeagleBoard Bottom Stacked Daughter Card Page
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BeagleBoard Expansion Board EEPROM Schematic BeagleBoard Voltage Access Points. BeagleBoard Signal Access Points BeagleBoard Serial Cable Orientation. Male Connector Null Modem Cable Serial Cable Loopback. BeagleBoard Side Components. BeagleBoard Bottom Side Components
Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Change History BeagleBoard Features BeagleBoard Electrical Specification OMAP3530 Muxing Settings OMAP3530 GPIO Pins. OMAP3530 Interrupt Pins OMAP3530 ULPI Interface. OMAP3530 ULPI Interface. Charge Pump Pins. Host Port OMAP Signals SD/MMC OMAP Signals OMAP3530 Audio Signals OMAP3530 Audio Signals OMAP3530 Signals TFP410 Interface Signals. Signals Signals S-Video Interface Signals JTAG Signals Expansion Connector Signals Expansion Connector Signal Groups GPIO Signals. GPIO Signals. DVI-D HDMI Cable Signals Signals Connector Sources Connector Dimensions. JTAG Signals Power Supply Specifications. Power Supplies Cable Pinout. Hubs Tested. DVI-D Monitors Tested.
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SD/MMC Cards Tested. Ethernet Adapters. WiFi Adapters Bluetooth Adapters Voltages Troubleshooting Known Issues
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Introduction
This document System Reference Manual BeagleBoard, cost OMAP3530 based board supported through BeagleBoard.org. This document provides detailed information overall design usage BeagleBoard from system level perspective. intended provide detailed documentation OMAP3530 processor other component used board. expected that user will refer appropriate documents these devices access detailed information. sections this document are: Section 2.0- Change History Provides tracking changes made System Reference Manual. Section 3.0- Definitions References This section provides definitions commonly used terms acronyms. Section 4.0- Overview This high level overview BeagleBoard. Section 5.0- Specification Provided here features electrical specifications BeagleBoard. Section 6.0-Product Contents Describes what BeagleBoard package looks like what included box. Section 7.0- Hookup Covered here connect various cables BeagleBoard. Section 8.0- System Architecture Design This section provides information overall architecture design BeagleBoard. This very detailed section that goes into design each circuit board. Section 9.0- Connector Pinouts Cables section describes each connector cable used system. This will allow user create cables, purchase cables, perform debugging needed. Section 10.0- BeagleBoard Accessories Covered this section accessories that used with BeagleBoard. This exhaustive list, does provide idea types cables accessories that supported find them. also provides definition what they need does guarantee that these devices will work implementations. Section 11.0 Mechanical Information provided here dimensions BeagleBoard. Section 12.0 Board Verification description provided setup board using verification process verify that board functional.
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Section 13.0 Troubleshooting Here where find tips troubleshooting setup BeagleBoard. Section 14.0- Known Issues This section describes known issues with current revision BeagleBoard workarounds that possible. Section 15.0- BeagleBoard Components This section provides information bottom side silkscreen BeagleBoard showing location components. Section 16.0- BeagleBoard Schematics These schematics BeagleBoard information where OrCAD files. Section 17.0- Bill Material This section describes where latest Bill Material BeagleBoard. Section 18.0- BeagleBoard Information This section describes where file information BeagleBoard.
Change History
Change History
Table tracks changes made each revision this document.
Table
Initial release.
Change History
Changes
Date
12/15/2009
Revision
There three changes board versus version. OMAP3530DCBB72 device which 720MHZ version OMAP3530. updated version UBoot software. following changes will affect user experience: Beagle splash screen been replaced with orange only screen boot Turning VAUX2 EHCI more advanced EHCI noise issue board. This involves change power circuitry 1.8V rail supplied EHCI
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interface. power derived from VAUX2 TPS65950 through filter circuit.
Definitions References
Definitions Secure Digital SDIO- Secure Digital Input Output MMC- Multimedia Card MDDR- Mobile Dual Data Rate SDRAM- Synchronous Dual Access Memory OMAP3530- CortexA8 based System Chip from Texas Instruments.
BeagleBoard Overview
BeagleBoard OMAP3530 platform designed specifically address Open Source Community. been equipped with minimum features allow user experience power OMAP3530 intended full development platform many features interfaces supplied OMAP3530 accessible from BeagleBoard. utilizing standard interfaces, BeagleBoard highly extensible many features interfaces. intended products. design information freely available used basis product. BeagleBoards will sold product this hampers ability boards many community members possible grow community. BeagleBoard Usage Scenarios
Figure provides example various usage scenarios BeagleBoard.
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WiFi
beagle>
Batter
Figure
BeagleBoard Usage Scenarios
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BeagleBoard Specification
This section covers specifications BeagleBoard provides high level description major components interfaces that make BeagleBoard. BeagleBoard Features
Table provides list BeagleBoard's features.
Table BeagleBoard Features
Processor Memory PMIC TPS65950 Debug Support Indicators Port Host Port Audio Connectors SD/MMC Connector User Interface Video Power Connector Expansion Connector (Not Populated) Connectors
Feature OMAP3530DCBB72 720MHz Micron NAND (256MB) MDDR SDRAM (256MB) Power Regulators Audio CODEC Reset 14-pin JTAG GPIO Pins UART LEDs layers 3.1" 3.0" (78.74 76.2mm) Power 2-User Controllable Mini connector TPS65950 MiniAB Single Port 500ma Power 3.5mm 3.5mm Stereo SD/MMC/SDIO support, Dual voltage 1-User defined button Reset Button DVI-D S-Video Power Power Power 1.8V) UART McBSP McSPI GPIO Access 3.3V, 1.8V control signals plus
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following sections provide more detail each feature sections BeagleBoard. OMAP Processor
BeagleBoard uses OMAP3530DCBB72 720MHZ version comes .4mm pitch package. (Package Package) technique where memory, NAND SDRAM, mounted OMAP3530. this reason, when looking BeagleBoard, will find actual part labeled OMAP3530. Memory
Micron memory used BeagleBoard mounted processor mentioned. function memory provide: NAND (256MB) MDDR SDRAM (256MB 166MHz) other memory devices BeagleBoard. possible however, that additional memory added BeagleBoard Installing SD/MMC slot port powered drive Thumb drive hard drive. Install thumbdrive into EHCI port Support this dependent upon driver support Power Management
TPS65950 used provide power BeagleBoard with exception 3.3V regulator which used provide power DVI-D encoder RS232 driver. addition power TPS65950 also provides: Stereo Audio Stereo Audio Power reset Status
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port used primary power source communication link BeagleBoard derives power from over cable. client port limited most cases 500mA single port sufficient power BeagleBoard. additional devices connected expansion rail used power them high powered device connected EHCI port, then power required could exceed that supplied port Hub. possible take this using cable additional power needed either host port expansion card. Figure shows example Y-Cable USB.
Figure
Y-Cable
BeagleBoard requires single minAB cable mentioned Y-Cable used needed. There option provide external power BeagleBoard using supply discussed later this section. Host Port
board single only Host port provided Type connector. provides power on/off control 500mA current Port only. order support FS/LS device, must used.
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Stereo Audio Output Connector
3.5mm standard stereo output audio jack provided access stereo output onboard audio CODEC. Audio CODEC provided TPS65950. Stereo Audio Connector
3.5mm standard stereo audio input jack provided access stereo output onboard audio CODEC. S-Video Connector
connector provided access S-Video output BeagleBoard. This separate output from OMAP processor contain different video output data from what found DVI-D output software configured will support NTSC format output standard default NTSC, changed Software. 5.10 DVI-D Connector
BeagleBoard drive panel equipped with DVI-D digital input. This standard panel interface OMAP3530 will support color output. DDC2B (Display Data Channel) EDID (Enhanced Display support over provided order allow identification monitor type required settings. BeagleBoard equipped with DVI-D interface that uses HDMI connector that selected small size. does support full HDMI interface used provide DVI-D interface portion only. user must HDMI DVI-D cable adapter connect monitor. This cable adapter provided with BeagleBoard. standard HDMI cable used when connecting monitor with HDMI connector. PLUG DVI-D CONNECTOR DISPLAY WITH BEAGLEBAORD POWERED PLUG CABLE DISPLAY THEN POWER BEAGLEBOARD. 5.11 Header
pair 1.27mm pitch 2x10 headers provided gain access signals. This allows creation boards that will allow adapters made provide level translation support different panels.
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SD/MMC connector provided means expansion support such devices WiFi Cards Camera Bluetooth Cards Modules Memory Cards Memory Cards SDIO Cards MMCMobile cards RS-MMC Cards miniSD Cards
supports MMC4.0 (MMC+) standard boot from cards. will support both cards. will also support most SDHC cards well. 5.13 Reset Button
When pressed released, causes power reset BeagleBoard. 5.14 User/Boot Button
button provided BeagleBoard provide functions: Force change boot sequence OMAP3530. Used application button that used needed.
When used conjunction with RESET button, will force change order which boot sources checked viable boot sources. button pressed while RESET button released, sequence becomes: UART MMC1 NAND
Even though NAND have program card placed slot, will boot from first. there, will boot from NAND. There also option have serial download application that will program NAND connected serial ports. this scenario internal will
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stop either serial port start download process from there. does require application host order perform this function. user button pressed reset, sequence which internal looks viable boot sources follows: NAND UART3 MMC1
this case, NAND overrides every option will always boot from NAND there data NAND. NAND empty, then other sources available used based boot order. force boot from SD/MMC card, reset button must pushed reset button pushed reelased. 5.15 Indicators
There three green LEDs BeagleBoard that controlled user. TPS65950 that programmed interface OMAP3530 Processor controlled GPIO pins There fourth BeagleBoard that provides indication that power supplied board controlled software. 5.16 Power Connector
Power will supplied connector need arises additional power, such when board added expansion connectors, larger wall supply plugged into optional power jack. When wall supply plugged will remove power path from connector will power source whole board. power supply provided with BeagleBoard. When using port host mode, supply must connected port will used provide limited power maximum 100mA, must powered. 100mA impacted having higher amperage supply plugged into power jack. 100mA function port itself. PLUG ANYTHING CONNECTOR BOARD WILL DAMAGED!
WARNING:
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Make sure supply regulated clean supply. 5.17 JTAG Connector
JTAG header provided BeagleBoard facilitate development debugging board using various JTAG emulators. interface 1.8V signals. Only 1.8V Levels supported. expose JTAG header 3.3V. 5.18 RS232 Header
Support RS232 UART3 provided header BeagleBoard access onboard RS232 transceiver. does require flat cable, which provided, access serial port. 5.19 Expansion Header
option single header provided board allow connection various expansion cards that could developed users other sources. multiplexing, different signals provided each pin. This header populated BeagleBoard that based usage scenario populated needed. 5.20 BeagleBoard Mechanical Specifications Size: 3.0" 3.1" height: Layers: thickness: .062" RoHS Compliant: Weight:
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Table electrical specification external interfaces BeagleBoard.
Table BeagleBoard Electrical Specification
Specification Power Input Voltage Current Input Voltage Current Expansion Voltage (5V) Current (Depends source current available) Expansion Voltage (1.8V) Current Host (Same supplied power plug Current (Depends what source supply over what board requires) High Speed Mode Full Speed Mode Speed Mode Host High Speed Mode RS232 Transmit High Level Output Voltage Level output voltage Output impedance Maximum data rate Receive High level Input Voltage Level Input Voltage Input resistance JTAG Realview Tool XDS560 XDS510 Lauterbach(tm) SD/MMC Voltage Mode 1.8V Voltage Mode 3.0V Current Clock DVI-D Pixel Clock Frequency High level output voltage Swing output voltage Maximum resolution 1.75 Varies 1.85 Unit
12.5
Mb/S Mb/S Mb/S Mb/S
+/-35 -2.7 -3.2
-5.5 +/-60
Kbit/S
Kohms mVp-p
1.71
1.89
1024
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Full scale output voltage (75ohm load) Offset voltage Output Impedance Audio Peak-to-peak single-ended input voltage dBFs) Total harmonic distortion (sine wave 1.02 dBFs) Total harmonic distortion (sine wave 1.02 kHz) kHz, A-weighted audio, Gain Audio Load Impedance @100 Maximum Output Power 0.53 Vrms differential output voltage load impedance Ohms) Peak-to-Peak output voltage Total Harmonic Distortion dBFs Idle channel noise (20Hz 20KHz)
82.5
Ohms ohms
17.56
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Product Contents
Under this section description what comes when BeagleBoard purchased. BeagleBoard
final packaged product will contain following: BeagleBoard CABLES PROVIDED WITH BEAGLEBOARD.
Figure
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Figure
Contents
Software BeagleBoard
board ships with U-Boot X-Loader flashed onto BeagleBoard. Repair
feel board need repair, follow Request process found
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BeagleBoard Hookup
This section provides overview connectors BeagleBoard they should used. Connecting
port connects host uses miniAB cable through which power provided BeagleBoard. desired, BeagleBoard also connected self powered hub. Figure shows where cable connected BeagleBoard. Port used Host, must grounded. This means that must have cable connected port BeagleBoard must powered HUB. There also option ground board discussed later.
Figure Connection
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Beagle equipped with Host only connector used support based devices. order connect multiple devices required. powered un-powered total current devices connected exceed available power from power supply that used. board powered from connector, then power available from this port extremely limited will able provide sufficient power most devices. possible keyboard mouse, that about will have power supply. Host port only does support devices without hub. Figure below shows location Host connector.
Figure
Host Connection
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optional supply used power BeagleBoard plugging into power jack BeagleBoard. power supply provided with BeagleBoard, obtained from various sources. need make sure supply regulated supply. Figure shows where insert power supply into power jack.
Figure Power Connection
power supply must have 2.1mm 5.5mm O.D. 9.5mm either straight right angle. Connecting anything other than will result damage board. using port host mode, must have external supply powering BeagleBoard. highly recommended that version board that external power supply double cable used Host used. Most supplies will able supply required current over single port. Page
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JTAG emulator used advanced debugging connecting JTAG header BeagleBoard. Only 14pin version JTAG supported 20pin version needed, will contact your emulator supplier appropriate adapter. Figure shows connection JTAG cable BeagleBoard.
Figure
BeagleBoard JTAG Connection
expose JTAG header 3.3V. supports 1.8V only.
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order access serial port BeagleBoard flat cable required connect adapter will plug directly into will require external Female Female twisted cable (Null Modem) order connect ribbon cable supplied with BeagleBoard obtained from numerous sources. Figure shows where ribbon cable installed.
Figure
BeagleBoard Serial Cable Connection
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S-Video cable connected BeagleBoard from there connected monitor that supports S-Video input. This cable supplied with BeagleBoard. Figure shows connector S-Video cable.
Figure BeagleBoard S-Video Connection
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order connect DVI-D output monitor, HDMI DVI-D cable required. This cable supplied with BeagleBoard obtained through numerous sources. Figure shows proper connection point cable.
Figure BeagleBoard DVI-D Connection
PLUG DVI-D CONNECTOR DISPLAY WITH BEAGLEBAORD POWERED PLUG CABLE DISPLAY THEN POWER BEAGLEBOARD.
Only digital portion HDMI supported BeagleBoard.
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Connecting Stereo Cable
external Audio output device, such external stereo powered speakers, connected BeagleBoard 3.5mm jack. audio cables provided with BeagleBoard, obtained from just about anywhere. Figure shows cable connected stereo jack.
Figure BeagleBoard Audio Cable Connection
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External Audio input devices, such powered microphone audio output player, connected 3.5mm jack. audio cables provided with BeagleBoard, obtained from just about source. Figure shows cable connected stereo input jack.
Figure BeagleBoard Audio Cable Connection
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There four green indicators BeagleBoard. them, POWER, indicates that main supply active. other three controlled software. Figure shows location each indicator.
Figure BeagleBoard Indicator Locations
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There buttons BeagleBoard; RESET button when pressed will force board reset USER button which used user interaction. user holds USER button down while pressing releasing RESET button, BeagleBoard will enter boot loader mode allowing boot from other sources than onboard NAND. Figure shows location buttons.
Figure BeagleBoard Button Location
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SD/MMC connector used Memory SDIO type cards. This full size connector will support various cards. Whether particular card supported not, dependent available software drivers. Figure shows location SD/MMC connector.
Figure BeagleBoard SD/MMC Location
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There headers provided allow access signals BeagleBoard. These headers 2x10 headers with spacing (1.27mm) pitch. these connectors used determined design adapter board. Figure shows location headers Beagle.
Figure BeagleBoard Header Location
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BeagleBoard System Architecture Design
This section provides high level description design BeagleBoard overall architecture. System Block Diagram
Figure high level block diagram BeagleBoard. will notice, block diagram configured match component placement BeagleBoard.
DVI-D SVideo EXPANSION JTAG
RESET USER
Stereo
Stereo
TFP410
OMAP 3530 w/POP
TPS65950
mSecure
RS232
HOST SD/MMC
Figure BeagleBoard High Level Block Diagram
Figure shows location components shown block diagram.
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Figure BeagleBoard Side Components
There components back BeagleBoard, Figure been provided completeness.
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Figure BeagleBoard Backside Components
This remainder this section describes detail architecture design BeagleBoard. will notice certain things this section. schematic been created each section showing only pertinent components their connections. names differ from actual schematic. ease reading, names have been truncated only show specific functions that used design.
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There possible sources required BeagleBoard. come from port connected powered HUB, supply. supply sufficient power BeagleBoard. However, depending load needed expansion port BeagleBoard, additional power required. This where supply comes play. PLUG ANYTHING CONNECTOR BOARD WILL DAMAGED!
WARNING:
should also noted that configuration used, example tying BeagleBoards together cable, both BeagleBoards must powered supply. port used Host port, then supply must also used. Figure design power input section.
VBUS_5V0
VBAT LDO_IN LDO_PLDN LDO_OUT MAIN_DC
C129 0.1uF
PGB0010603MR
USB_CLIENT
USB_5V
TESTPT1 10K,0603,DNI PJ-002A USB_PWR_EN
LDO_EN
LDO_PG
SW_IN SW_IN
SW_OUT SW_OUT SW_PLDN
DC_5V JUMPER,DNI 0.1uF
SW_EN
SW_PG
TPS2141
0.1,0805 C128 10UF
Figure Input Power Section
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8.2.1 Source
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specification requires that current consumed prior enumeration limited 100mA (500mW). from routed through TPS2141 switch insure that this requirement uncharged capacitors BeagleBoard exhibit large current drain during start that could exceed this requirement. TPS2141 Specification-compatible containing dual-current limiting power switch adjustable dropout regulator (LDO). Both switch limit inrush current controlling turn slew rate. dual-current-limiting feature switch allows peripherals utilize high-value capacitance output switch, while keeping inrush current low. During turn switch limits current delivered capacitive load less than When output voltage from switch reaches about input voltage, switch current limit increases 800mA (minimum), which point higher current loads turned higher current limit provides short circuit protection while allowing peripheral draw maximum current from bus. When powered mode supply connected, TPS2141 enabled, allowing power supplied board from port through integrated switch inside TPS2141.
8.2.2 Wall Supply Source
wall supply used provide power board. regulated supply least 500mA required. needs have 2.1mm plug with center configuration. PLUG ANYTHING CONNECTOR BOARD WILL DAMAGED!
WARNING:
event that higher load required addition Daughtercard higher current supply used. maximum current should exceed
8.2.3 Source Control
Unlike when powering from port, case voltage, current limiting required. long supply connected, switch enabled. When supply plugged switch disabled because ground removed from TPS2141. This insures that from connected disabling internal FET. case where there plugged there available routed removal pullup affect.
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When mode operation, used Host Client modes. TPS65950 will responsible handling supply VBUS_5V0 rail Host modes. this limited 100mA, powered must used support peripherals port.
8.2.4 3.3V Supply
TPS2141 integrated 3.3V which being used supply 3.3V required BeagleBoard DVI-D interface UART. input supplied main DC_5V. This insures that power supplied either wall supply that current measurement includes 3.3V supply.
8.2.5 Meter Current Measurement
Jumper header that allows voltage drop across resistor measured using meter, providing measure current consumption BeagleBoard from main voltage rails, either resistor, resistor across which voltage measured. reading .1mV current.
8.2.6 Processor Current Measurement
resistor across also used measure current board reading voltage drop across from software. There pairs resistors provided TPS65950 that measure voltage either side This done control TPS65950 from OMAP3530 processor. These values along with resistance used calculate current consumption board. Figure schematic measurement circuitry. maximum value that input inputs based setting VINTANA2.OUT voltage rail which defaults 2.5V. order prevent voltage levels from exceeding this value pair resistors used scale voltage down.
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Figure Processor Current Measurement
This results value that actual value. maximum value 5.25V, voltage read would 2.415V which keeps below 2.5V pint. voltage drop across will small value resistor ohms. every current voltage .01V will detected. order determine actual power, input voltage voltage drop must measured. Power Conditioning
This circuitry regulates input nominal 4.2VDC level. This required order meet maximum voltage level specified TPS65950 Power Management device which 4.7V. Using 4.2V gives some margin meets nominal 4.2V rating TPS65950. Figure power conditioning section BeagleBoard.
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VBAT
VBAT_FB 22.6K,0603
56.2K,0603 C109 10UF
TPS73701
0.1uF
4.2V
POWER
D5_RES
0.1uF
330,0603 0.125W
Figure Power Conditioning
TPS65950 provides main power rails board maximum limit 4.7V VBAT input nominal 4.2V. TPS73701, used convert DC_5V, which come from wall supply USB, 4.2V meet this requirement. TPS737701 linear low-dropout (LDO) voltage regulator thermal shutdown current limit protected. ability deliver current, although this above requirements board. adjusting values actual voltage adjusted needed. indication that 4.2V present. TPS65950 Reset Power Management
TPS65950 supplies several functions BeagleBoard. This section covers portion those functions centered power reset functions. Included this section Main Core Voltages Peripheral Voltages Power Sequencing Reset Current measurement
other functions covered other sections this document grouped their overall board functions. explanation various regulators found TPS65950 based upon they used board design intended reflect overall capability TPS65950 device. Please refer TPS65950 documents full explanation device operation.
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8.4.1 Main Core Voltages
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TPS65950 supplies three main voltage rails OMAP3530 processor board:
VOCORE_1V3 (1.2V, adjustable) VDD2 (1.3V) VIO_1V8 (1.8V)
VOCORE_1V3 defaults 1.2V power adjusted software 1.3V level. Figure interfacing TPS65950 system provides three main rails.
8.4.2 Main Input
main supply TPS65950 main rails VBAT rail which nominal 4.2V. Each rail filter 10uF connected each three inputs. .1uF also provided high frequency noise filtering.
8.4.3 OMAP3530 Control
various components TPS65950 controlled from OMAP3530 interface. I2C_0 used control TPS65950 device.
8.4.4 VIO_1V8
VIO_1V8 rail generated TPS65950 regulator. output stepdown converter with choice output voltage settings: 1.85 voltage configuring VSEL (VIO_VSEL[0]). When VSEL output voltage when output voltage 1.85 When TPS65950 resets, default value this 1.80 OMAP3530 must write VSEL field change output 1.85 default BeagleBoard 1.8V. This regulator output used supply power system memories ports. first power supplies switched power-up sequence. does support SmartReflex voltage control schemes. into sleep mode configuring SLEEP_STATE OFF_STATE fields VIO_REMAP register.
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Power control
REGEN
REGEN
VBAT
I2C4_SCL I2C4_SDA nSLEEP VBAT CP.CAPP C108
VMODE1(VDD1) VMODE2(VDD2)/I2C.SR.SCL N.C. N.C./I2C.SR.SDA nSLEEP1 nSLEEP2
IO_1P8
CP.IN CP.CAPP CP.CAPM CP.GND
4.7uf ,CER,0402
2.2uF,0603
CP.CAPM
VBAT VOCORE_1V3
TESTPT1 1uH,2A 0.1uF 10uF,CER,JMK,0805 T2_VDD1.L
VDD1.IN VDD1.IN VDD1.IN VDD1.OUT VDD1.L VDD1.L VDD1.L VDD1.GND VDD1.GND VDD1.GND
VDD1
10uF,CER,JMK,0805
VBAT VDD2 TP12 VDD2 TESTPT1 0.1uF T2_VDD2.L VDD2.IN VDD2.IN VDD2.FB VDD2.L VDD2.L VDD2.GND VDD2.GND
10uF,CER,JMK,0805
10uF,CER,JMK,0805
TP14 VIO_1V8 TESTPT1
VBAT T2_VIO.L VIO.IN VIO.IN VIO.OUT VIO.L VIO.L VIO.GND VIO.GND
1uH,2A
0.1uF
10uF,CER,JMK,0805
10uF,CER,JMK,0805
Figure Main Power Rails
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8.4.5
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Main Core Voltages Smart Reflex
VDD1 VDD2 regulators TPS65950 provide SmartReflex-compliant voltage management. SmartReflex controller OMAP3530 interfaces with TPS65950 counterpart through dedicated bus. OMAP3530 computes required voltage informs TPS65950 using SmartReflex interface. SmartReflex control VDD1 VDD2 regulators enabled setting SMARTREFLEX_ENABLE (DCDC_GLOBAL_CFG[3]) perform VDD1 voltage control through SmartReflex interface, TPS65950 provides VDD1_SR_CONTROL register. MODE field VDD1_SR_CONTROL register VDD1 ACTIVE state; setting field moves VDD1 SLEEP state. VDD1 output voltage programmed setting VSEL field VDD1_SR_ CONTROL register. VDD1 output voltage given VSEL*12.5
8.4.6 VOCORE_1V3
VOCORE_1V3 rail supplied VDD1 regulator TPS65950. VDD1 regulator 1.1A stepdown power converter with configurable output voltage between 1.45 steps 12.5 This regulator used power OMAP3530 core. OMAP3530 request TPS65950 scale VDD1 output voltage reduce power consumption. default output voltage power-up depends boot mode settings, which case BeagleBoard 1.2V. output voltage VDD1 regulator scaled software hardware setting ENABLE_VMODE (VDD1_VMODE_CFG[0]). each these modes, output voltage ramp single-step multiple-step, depending value STEP_REG field VDD1_STEP[4:0] register. VOCORE_1V3 rail should 1.3V after boot Apart from these modes, VDD1 output voltage also controlled OMAP3530 through SmartReflex interface between OMAP3530 TPS65950. default voltage scaling method selected reset software-controlled mode. Regardless mode used, VDD1 configured same output voltage sleep mode active mode programming DCDC_SLP VDD1_VMODE_CFG[2] register When DCDC_SLP sleep mode output voltage VDD1 equals floor voltage that corresponds VFLOOR field (VDD1_VFLOOR[6:0]).
8.4.7 VDD2
VDD2 voltage rail generated TPS65950 using VDD2 regulator. VDD2 regulator stepdown converter with configurable output voltage between
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1.45 used power OMAP3530 core. VDD2 differs from VDD1 current load capabilities with output current rating active mode. VDD2 provides different voltage regulation schemes. When VDD2 controlled VMODE2 signal with SmartReflex interface, range output voltage 1.45 VMODE2 signal VDD2_VMODE_CFG, VDD2_STEP, VDD2_FLOOR, VDD2_ROOF registers similar corresponding signals registers VDD1. VDD2 shares same SmartReflex provide voltage regulation. VDD2_SR_CONTROL register provided controlling VDD2 output voltage SmartReflex mode. When VDD2 used software-control mode, VSEL (VDD2_ DEDICATED[4:0]) field programmed provide output voltages between 1.45 output voltage given value VSEL field given VSEL*12.5 VSEL field programmed that output voltage computes more than 1.45 TPS65950 sets VDD2 output voltage Peripheral Voltages
There additional voltages used system that generated TPS65950. These are: VDD_PLL2 VDD_PLL1 VDAC_1V8 VDD_SIM VMMC1 VAUX2
Figure shows peripheral voltages supplied TPS65950.
8.5.1 VDD_PLL2
This programmable used power OMAP3530 circuitry. VPLL2 configured through interface provide output voltage levels based value VSEL field (VPLLI_DEDICATED[3:0]). board this rail used power output pins DSS_DATA(0:5), DSS_DATA(10:15) DSS_DATA(22:23). VPLL2 must 1.8V proper operation DVI-D interface.
8.5.2 VDD_PLL1
VPLL1 programmable regulator low-noise, linear regulator used OMAP3530 supply. VDD_PLL1 rail initialized 1.8V.
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FBGA209_15-74_280x280 ICTLAC1 ICTLAC2 ICTLUSB1 ICTLUSB2 VPRECH PCHGAC PCHGUSB VCCS VBATS VBAT BCIAUTO Backup battery BKBAT IO.1P8 VBAT.RIGHT VBAT.RIGHT VBAT.LEFT VBAT.LEFT
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T2_VPRECH VBAT 1uF,CER
Revision
VIO_1V8 VIO_1P8 0.1uF
Level
IO_1P8
1uF,CER
1uF,CER VBAT
VMMC2.IN VMMC1.IN VAUX4.IN VBAT.USB VDAC.IN VAUX12S VPLLA3R VINT
TP10 TP11
1uF,CER 1uF,CER 1uF,CER 1uF,CER
TESTPT1 TESTPT1 TESTPT1 TESTPT1 VPLL2 VPLL1 VDAC.OUT VSIM VMMC2.OUT VMMC1.OUT VAUX4.OUT VAUX3.OUT VAUX2.OUT VAUX1.OUT VDD_PLL2 VDD_PLL1 VDAC_1V8 VDD_SIM VMMC1 TP13 1uF,CER 1uF,CER 1uF,CER TESTPT1 2.2uF,CER 1uF,CER
VDD_EHCI VINTUSB1P8 VINTUSB1P5 VUSB.3P1 VINTDIG VRTC VINTANA2.OUT VINTANA2.OUT VINTANA1.OUT VINTUSB1P8 VINTUSB1P5 VUSB.3P1 VINTDIG VRTC VINTANA2.OUT VINTANA1.OUT 1uF,CER 1uF,CER
1uF,CER 1uF,CER
1uF,CER 1uF,CER
C100
1uF,CER
Figure Peripheral Voltages
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8.5.3 VDAC_1V8
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VDAC programmable regulator high-PSRR, low-noise, linear regulator that powers OMAP3530 dual-video DAC. controllable with registers powered down needed. VDAC configured provide 1.2V, power mode, based value VSEL field (VDAC_DEDICATED[3:0]). VDAC_1V8 rail should 1.8V BeagleBoard.
8.5.4 VDD_SIM
This voltage regulator programmable, dropout, linear voltage regulator supplying bottom bits SD/MMC card slot. VSEL field (VSIM_DEDICATED[3:0]) programmed provide output voltage deliver 50mA. default output voltage this directed TPS65950 boot pins 1.8V.
8.5.5 VMMC1
VMMC1 regulator programmable linear voltage converter that powers MMC1 slot includes discharge resistor overcurrent protection (short-circuit). This regulator also turned automatically when card extraction detected. VMMC1 powered from main VBAT rail. VMMC1 rail defaults 3.0V directed TPS65950 boot pins will deliver 220mA. 3.0V event cards being used.
8.5.6 VAUX2
VAUX2 regulator programmable linear voltage converter that powers 1.8V rail includes discharge resistor overcurrent protection (short-circuit). VAUX2 powered from main VBAT rail. VMMC1 rail defaults 3.0V directed TPS65950 boot pins will deliver 220mA. voltage rail labeled VDD_EHCI schematic.
8.5.7 Boot Configuration
boot configuration pins TPS65950 determine power sequence device. OMAP3530 support, boot configuration fixed BOOT0 tied VBAT BOOT1 tied Ground.
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8.5.8 Backup Battery
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optional battery backup Real Time Clock that TPS65950. board does come equipped with battery. battery purchased from DigiKey other component suppliers. When battery installed, must installed. must make sure that prior installing battery that removed. Refer section 9.11 information battery selection installation.
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8.5.9 Power Sequencing
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Based boot configuration pins, TPS65950 knows type OMAP processor that needs support, this case OMAP3530. voltages ramped sequence that compatible with OMAP3530 processor. Figure sequence which power rails, clocks, reset signal come
Figure Power Sequencing
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8.5.10 Reset Signals
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BeagleBoard uses three distinct reset circuits: Warm Reset Cold Reset User Reset Figure shows connections Reset interfaces.
OMAP3530_ES3.0 4.7K VBAT
IO_1P8 VBAT
VIO_1V8
AH25 AF24
SYS_nRESPWRON SYS_nRESWARM/GPIO_30
nRESPWRON nRESWARM PWRON
nRESPWRON nRESWARM PWRON 4.7K VIO_1V8
VIO_1V8
OMAP3
nRESET
0.1uF
B3F-1000 SN74LVC2G07DCKR
Figure Reset Circuitry 8.5.10.1 Warm Reset
warm reset generated OMAP3530 processor power nRESWARM signal bidirectional reset. When internal reset occurs, nRESWARM goes resets peripherals TPS65950. TPS65950 configured perform warm reset device bring into known defined state detecting request warm reset NRESWARM pin. minimum duration pulse nRESWARM should 32-kHz clock cycles. nRESWARM output open-drain; consequently, external pullup resistor required. There user generate warm reset BeagleBoard.
8.5.10.2 Cold Reset
power shown Figure TPS65950 generates nRESPWRON, power reset. signal from TPS65950 output only open drain signal. running signal through buffer, SN74LVC2G07, signal becomes open drain, which requires pullup signal. This will allow nRESPWRON signal
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pulled low, pressing reset switch force reset OMAP3530 processor device expansion card that require reset. also allows reset signal pulled held extended time circuitry expansion card needed.
8.5.10.3 User Reset
USER RESET button used request Warm Reset from processor. After initialization, this becomes input processor. pushing Reset button, interrupt generated into OMAP3530 processor. software that result this then whatever housekeeping required then send processor into reset mode.
8.5.10.4 PWRON
will notice another signal TPS65950 called PWRON. This signal referenced TPS65950 documentation. BeagleBoard design used pulled high insure desired operation maintained.
8.5.11 mSecure Signal
This signal provides protection registers TPS65950 disabling that function control signal form OMAP3530 processor. more information operation signal, please refer OMAP3530 Technical Reference Manual.
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OMAP3530 Processor
heart BeagleBoard OMAP3530 processor. Figure high level block diagram OMAP3530.
Figure OMAP3530 Block Diagram
8.6.1
Overview
OMAP3530 high-performance, multimedia application device based enhanced OMAP3 architecture integrated TI's advanced 65-nm process technology. OMAP3530 architecture configured with different sets features different tier devices. Some features available lower-tier devices. more information, refer OMAP3530 Technical Reference Manual (TRM).The architecture designed provide best-in-class video, image, graphics processing sufficient various applications. OMAP3530 supports high-level operating systems (OSs), such Windows
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This OMAP3530 device includes state-of-the-art power-management techniques required high-performance power products. OMAP3530 supports following functions interfaces BeagleBoard: Microprocessor unit (MPU) subsystem based Cortex-A8microprocessor Memory interface MDDR (256Mbytes) NAND Flash (256Mbytes) Display interface (DSS) SD/MMC interface interface NTSC/PAL/S-Video output Power management Serial interface interface Audio interface (McBSP2) Expansion McBSP1 JTAG debugging interface
8.6.2 SDRAM
SDRAM accessible BeagleBoard. connectivity limited memory access OMAP3530 therefore only accessible SDRAM memory. base address SDRAM device 0x8000 0000.
8.6.3 GPMC
GPMC accessible BeagleBoard. connectivity limited memory access OMAP3530 therefore only accessible NAND memory. memory GPMC NAND therefore will support classical NAND interface. address memory space programmable.
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8.6.4
display subsystem provides logic display video frame from memory frame buffer SDRAM onto liquid-crystal display (LCD) display DVI-D interface standalone panel interface connectors. logic levels expansion connectors 1.8V will require buffering signals drive most panels. configured maximum bits, used lower modes needed.
8.6.5 McBSP2
multi-channel buffered serial port (McBSP) McBSP2 provides full-duplex direct serial interface between OMAP3530 audio CODEC TPS65950 using format. Only four signals supported McBSP2 port. Figure depiction McBSP2.
Figure McBSP2 Interface 8.6.6 McBSP1
McBSP1 provides full-duplex direct serial interface between OMAP3530 expansion interface. There signals supported McBSP1, unlike signals other ports. Figure diagram McBSP1.
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Figure McBSP1 Interface
8.6.7
McBSP3
McBSP3 provides full-duplex direct serial interface between OMAP3530 expansion interface. Figure diagram McBSP3.
Figure McBSP3 Interface
8.6.8
Muxing
OMAP3530, majority pins have multiple configurations that essence, become different signals depending they software. order BeagleBoard operate, pins used must correct signal. some cases, default signal correct signal. Each have maximum options pin. This called mode indicated three
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value (0:3). case signals going expansion connector, settings required those pins depends they used. explanation options, please refer Expansion Header section. Each different mode independent other pins connector. Table list signals used OMAP3530 BeagleBoard required mode setting each pin. Where default setting needed, will indicated. USER notation under mode indicates that this expansion signal discretion user. FIXED indicates that there only function that signal that cannot changed,
Table
OMAP3530 Muxing Settings
Signal
MMC1 MMC2 UART3 GPMC UART1 I2C1 I2C2 I2C3 I2C4 JTAG TV_OUT SYS_nRESPWRON SYS_nRESWARM SYS_nIRQ SYS_OFF SYS_CLKOUT SYS_CLKOUT2 SYS_CLKREQ SYS_XTALIN GPIO_149 GPIO_150 McBSP1 McBSP2 McBSP3 GPIO_171 GPIO_172
Mode
Default Default User Default Default Default Default Default Default Default FIXED Default Default Default Default Default Default Default Default FIXED Default User Default
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8.6.9 GPIO Mapping
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There number GPIO pins from OMAP3530 that used BeagleBoard design. Table shows which these GPIO pins used design whether they inputs outputs. While GPIO pins used interrupts, table only covers GPIO mode. interrupt, then covered interrupt section.
Table
OMAP AE21 INT/GPIO GPIO_149 GPIO_150 GPIO_23 GPIO_170 GPIO_7 Signal LED_GPIO149 LED_GPIO149 MMC1_WP DVI_PUP SYSBOOT_5
OMAP3530 GPIO Pins
USAGE Controls User LED0 Controls User LED1 SD/MMC card slot Write protect Controls DVI-D interface. DVI-D enabled. Used device boot mode user button input
Other signals, such those that connect expansion connector, also GPIO pin. information those, refer Expansion Connector section.
8.6.10 Interrupt Mapping
There small number pins OMAP3530 that interrupt. Some these interrupts connected TPS65950 their status reflected through main TPS65950 interrupt. Table lists interrupts.
Table
TPS65950 OMAP AF26 INT/GPIO SYS_nIRQ GPIO_29 GPIO0
OMAP3530 Interrupt Pins
USAGE Interrupt from TPS65950 Write protect lead. polled interrupt. MMC1 card detect input. Goes OMAP3530 over SYS_nIRQ pin.
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OMAP3530 uses what called (Package-on-Package) memory. memory (Multi Chip Package) that contains both Mobile SDRAM NAND Flash. Figure shows Memory concept.
Figure Memory
Memory device mounts OMAP3530 device. configuration used board NAND Flash plus MDDR SDRAM device from Micron. System Clocks
There three clocks needed operation BeagleBoard, 32KHz, 26MHz McBSP_CLKS. Figure shows components that make System Clocks.
Figure System Clocks 8.8.1 32KHz Clock
32KHz clock needed TPS65950 OMAP3530 provided TPS65950 external 32KHz crystal, TPS65950 separate output Page
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from crystal drive OMAP3530 that buffers resulting 32-kHz signal provides 32KCLKOUT, which provided OMAP3530 ball AE25. default mode 32KCLKOUT signal active, disabled desired under control. 32.768-kHz clock drives embedded TPS65950. enabled default; host processor must correct date time enable RTC.
8.8.2 26MHz Clock
This section describes 26MHz clock section BeagleBoard.
8.8.2.1 26MHz Source
BeagleBoard designed support suppliers 26MHz oscillator. 26MHz clock provided onboard oscillator, TPS65950 receives external HFCLKIN signal ball uses synchronize generate clocks required operate TPS65950 subsystems. TPS65950 must have this clock order function point where power BeagleBoard. This reason 26MHz clock routed through TPS65950.
8.8.2.2 TPS65950 Setup
When TPS65950 enters active state, OMAP3530 must immediately indicate HFCLKIN frequency MHz) setting HFCLK_FREQ field (bits [1:0]) CFG_BOOT register TPS65950. HFCLK_FREQ default being programmed, that condition, subsection does work. three DCDC switching supplies (VIO, VDD1, VDD2) operate from their free-running 3-MHz (RC) oscillators, registers accessed default 1.5-M byte. HFCLK_FREQ must OMAP3530 during initial power-up sequence. BeagleBoard, this done internal boot startup.
8.8.2.3 OMAP3530 26MHz
26MHz clock OMAP3530 provided TPS65950 ball through R38, resistor providing minimize reflections clock line. clock signal enters ball AE17 OMAP3530.
8.8.3 McBSP_CLKS
additional clock also provided TPS65950 called McBSP_CLKS. This clock provided OMAP3530 order insure synchronization interface between OMAP3530 TPS65950.
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BeagleBoard (On-the-Go) port. used port, Client port, Host port. main client port, that mode that will supply power needed power BeagleBoard.
NOTE: order Host mode, BeagleBoard must powered from supply.
8.9.1 Overview
supplement specification. standard uses master/slave architecture, host acting master peripheral acting slave. Only host schedule configuration data transfers over link. peripherals cannot initiate data transfers, they only respond instructions given host. works differently that gadgets don't need pure peripherals because they sometimes hosts. example might connecting keyboard printer BeagleBoard printer that knows grab documents from certain peripherals print them. compatible devices able initiate session, control connection exchange Host/Peripheral roles between each other. supplement does prevent hub, describes role swapping only case one-to-one connection where devices directly connected. standard used, supplement notes that using will lead losing role-swap capabilities making device Default-Host other Default-Peripheral until disconnected. combination OMAP3530 TPS65950 allows BeagleBoard work device desired. primary mode operation however, intended client mode order pull power from host which typically does have Host port, this port will used Host port many applications.
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8.9.2 Design
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Figure design port BeagleBoard.
VBUS_5V0 USB0HS_CLK USB0HS_STP USB0HS_DIR USB0HS_NXT USB0HS_DAT0 USB0HS_DAT1 USB0HS_DAT2 USB0HS_DAT3 USB0HS_DAT4 USB0HS_DAT5 USB0HS_DAT6 USB0HS_DAT7 VBUS_5V0 C127 4.7uf ,CER,0402 T2_VBUS 0,0603 VBUS UCLK DN/UART3.TXD STP/GPIO.9 DP/UART3.RXD DIR/GPIO.10 NXT/GPIO.11 DATA0/UART4.TXD DATA1/UART4.RXD DATA2/UART4.RTSI DATA3/UART4.CTSO/GPIO.12 DATA4/GPIO.14 DATA5/GPIO.3 DATA6/GPIO.4 DATA7/GPIO.5 PGB0010603MR JUMPER,DNI C129 0.1uF PGB0010603MR
USB_CLIENT_ID PGB0010603MR
USB_CLIENT
PGB0010603MR
TWL4030 TPS65950
Figure Design
8.9.3
ULPI Interface
ULPI interface standard high-speed systems. defines interface between link controller (OMAP3530) TPS65950 that drives actual bus. ULPI stands UTMI+ interface designed specifically reduce count discrete high-speed PHYs. count reductions minimize cost footprint chip reduce number pins dedicated link controller. Unlike full- low-speed systems, which utilize serial interfaces, high-speed requires parallel interface between controller order 480Mbps. This leads corresponding increase complexity count. ULPI used BeagleBoard keeps this down only signals because combines just three control signals, plus clock, with 8-bit bi-directional data bus. This also used packet transmission accessing register data ULPI PHY.
8.9.3.1 OMAP3530 Interface
controller ULPI interface OMAP3530. provides required signals drive interface. Table describes signals from OMAP3530 that used interface.
Table OMAP3530 ULPI Interface
Signal
hsusb0_clk
Description
Dedicated external transceiver 60-MHz clock input from
Type
Ball
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hsusb0_stp hsusb0_dir hsusb0_nxt hsusb0_data0 hsusb0_data1 hsusb0_data2 hsusb0_data3 hsusb0_data4 hsusb0_data5 hsusb0_data6 hsusb0_data7
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Dedicated external transceiver Stop signal Dedicated external transceiver Data direction control from Dedicated external transceiver Next signal from Transceiver Bidirectional data Transceiver Bidirectional data Transceiver Bidirectional data Transceiver Bidirectional data Transceiver Bidirectional data Transceiver Bidirectional data Transceiver Bidirectional data Transceiver Bidirectional data
8.9.3.2
TPS65950 Interface
TPS65950 interfaces OMAP3 over ULPI interface. Table list signals used TPS65950 ULPI interface.
Table OMAP3530 ULPI Interface
Signal
UCLK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
Description
High speed clock High speed stop High speed High speed direction High speed Data High speed Data High speed Data High speed Data High speed Data High speed Data High speed Data High speed Data
Type
Ball
8.9.4
Charge Pump
When TPS65950 acts A-device, charge pump used provide V/100 VBUS pin. When TPS65950 acts B-device, charge pump high impedance. used mode A-device, BeagleBoard will need powered from supply. acting B-device, there will voltage source port drive BeagleBoard. Table describes charge pump pins.
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Table
BeagleBoard System Reference Manual
Charge Pump Pins
Revision
Signal
CP.IN CP.CAPP CP.CAPM CP.GND
Description
charge pump input voltage. Connected VBAT. charge pump flying capacitor plus. charge pump flying capacitor minus. charge pump ground.
Type
Power
Ball
charge pump powered VBAT voltage rail. charge pump generates 4.8-V (nominal) power supply voltage VBUS pin. input voltage range 4.2V VBAT within this range. charge pump operating frequency MHz. charge pump integrates short-circuit current limitation
8.9.5 Connector
interface accessed through miniAB connector. want port Host, connector must grounded. version Beagle provides jumper pad, that allows small piece solder placed pads perform this function. should noted that with Host port Beagle, need convert port host mode greatly diminished.
8.9.6 Protection
Each lead port protection. order interface meet Specification Diagram, these protection devices must capacitance. 8.10 Host Port
equipped with High Speed Host interface connected ULPI port OMAP3530. uses SMSC physical interface provides power control connector. This port High Speed only port will support speed full speed devices plugged directly into connector. Figure design Host port.
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VBAT DC_5V
Revision
TP20 TESTPT1
VDD1.8
nEN_USB_PWR
HOST_nOC
0,0603
TPS2061 (DGN)
HOST INTERFACE
CLKOUT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 RESETB REFCLK VBUS RBIAS USB33_VBUS USB33_ID USB33_RBIAS 8.064k 0.1uF 22uF,CER,0805 USB33_VDD3.3 VDD1.8 C105 C104 C103 0.1uF C102 4.7uf ,CER,0402 30MHZ_50mA VBAT 0,0603,DNI C107 0.1uF C106 4.7uf ,CER,0402 VIO_1V8 VDD_EHCI C101 100uf 6.3V HOST_VBUS HOST_DHOST_D+ USB-A Conn. 87520-xx1xx VBUS
SHIELD
USB2HS_STP USB2HS_DIR USB2HS_NXT USB2HS_DAT0 USB2HS_DAT1 USB2HS_DAT2 USB2HS_DAT3 USB2HS_DAT4 USB2HS_DAT5 USB2HS_DAT6 USB2HS_DAT7
10K,0603
Power Control
VDD3.3 VDD1.8 VBAT
SHIELD
USB2HS_nRST USB2HS_CLK
USB3322 (CSP) R111
Host Connector
Figure Host Design
8.10.1 Host OMAP3 Interface
interface OMAP3 HSUSB2 interface. signals used this interface contained Table
Table
Signal Hsusb2_clk Hsusb2_stp Hsusb2_dir Hsusb2_nxt Hsusb2_data0 Hsusb2_data1 Hsusb2_data2
Hsusb2_data3 Hsusb2_data4 Hsusb2_data5 Hsusb2_data6 Hsusb2_data7 Gpio_147
Host Port OMAP Signals
Input/Output
Description External transceiver 60-MHz clock output External transceiver Stop signal Transceiver data direction control from Next signal from
Bidirectional data signal 12-pin ULPI operation Bidirectional data signal 12-pin ULPI operation Bidirectional data signal 12-pin ULPI operation Bidirectional data signal 12-pin ULPI operation Bidirectional data signal 12-pin ULPI operation Bidirectional data signal 12-pin ULPI operation Bidirectional data signal 12-pin ULPI operation Bidirectional data signal 12-pin ULPI operation Enable/reset line PHY.
husb2_clk signal output only used support that supports input clock mode. SMSC device supports this mode used Beagle.
8.10.2 Host
used design USB3322/26 series device from SMSC. USB3322 highly integrated Hi-Speed USB2.0 Transceiver (PHY) that meets electrical Page
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requirements used Hi-Speed Host, Device, On-the-Go (OTG) transceiver. this design, only host mode operation being supported. USB3322 uses industry standard UTMI+ Interface (ULPI) connect OMAP3. ULPI uses method in-band signaling status byte transfers between Link facilitate session with only pins. order interface OMAP3530, device must used 60MHz clock mode. This done tying CLKOUT signal VIO_1V8. zero series resistor added. This required, added "just case" option CLKOUT signal source noise PHY. proven case. clock derived from 60MHz signal generated OMAP3530. signals their functions align with descriptions found OMAP3530 interface section. USB3322 device requires voltages, VIO_1V8 rail power rails VBAT, which needs between 3.1V 5.1V, power rest device. board VBAT regulated 4.2V 3.3V rail device generated internally requires filter bypass connected externally. Unlike version, version derives 1.8V from VAUX2 rail supplied TPS65950 PMIC. also uses ferrite bead, R67, provide additional filtering noise. This EHCI noise issue. There option connect 1.8V rail VIO_1V8 rail, that been populated design. RBIAS block consists internal bandgap reference circuit used generating driver current biasing analog circuits. This block requires external 8.06K, tolerance, reference resistor connected from RBIAS ground. nominal voltage RBIAS 0.8V therefore resistor will dissipate approximately 80µW power. USB3322 detect grounded floating determine cable been inserted. plug will ground while plug will float pin. using this device support protocol instead host device, ground force into Host mode times. signal present connector. USB3322 transceiver fully integrates termination resistors both This includes 1.5k pull-up resistors, pull-down resistors high speed termination resistors. These resistors require tuning trimming.
8.10.3 Host Connector
connector used Type receptacle provides connections four signals, VBUS, Ground. This same connector will back hub. will notice that there external devices connector. protection integrated into PHY.
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8.10.4 Host Power Control
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Power provided through Host connector power devices that plugged into host connector. This power controlled OMAP3530 TPS2061 power switch. TPS2061 power-distribution switch intended applications where heavy capacitive loads short-circuits likely encountered. This device incorporates 70-mW N-channel MOSFET power switch. Gate drive provided internal charge pump designed control power-switch rise times fall times minimize current surges during switching. switch controlled TPS65950 using LED.A signal. OMAP3530 uses interface activate signal TPS65950. amount available current supplied depends remaining current available when mode supply. switch will able supply more current than available from source being used. TPS2061 also provides overcurrent indicator protection circuit. When output load exceeds current-limit threshold short present, device limits output current safe level switching into constant-current mode, pulling overcurrent (OC) logic output low. This read TPS65950 pin. generate interrupt OMAP3530 alert this condition. When continuous heavy overloads short-circuits increase power dissipation switch, causing junction temperature rise, thermal protection circuit shuts switch prevent damage. Recovery from thermal shutdown automatic once device cooled sufficiently. Internal circuitry ensures that switch remains until valid input voltage present. This power-distribution switch designed current limit typically. mentioned, amount current available depends current source. 8.11 SD/MMC
board provides SD/MMC interface. primary proving boot source used other things such cameras Wireless cards. Typical users prefer port these functions such, card function primary this connector. connector supports different types cards. Secure Digital (SD) flash memory card format developed Matsushita, SanDisk Toshiba portable devices. 2007, card capacities range from Several companies have announced cards with Cards with 4-32 considered high-capacity. format proven very popular. However, compatibility issues between older devices
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newer larger cards SDHC format have caused considerable confusion some users. card have write protect prevent data from being overwritten. supports 1-bit 4-bit modes. miniSD- same features with exceptions that smaller size support 4-bit mode optional amongst suppliers. SDIO SDIO stands Secure Digital Input Output. slots actually used more than flash memory cards. Devices that support SDIO small devices designed form factor, like receivers, Wi-Fi Bluetooth adapters, modems, Ethernet adapters, barcode readers, IrDA adapters, radio tuners, tuners, RFID readers, digital cameras, other mass storage media such hard drives. SDIO cards fully compatible with Memory Card host controller (including mechanical, electrical, power, signaling software). When SDIO card inserted into SDIO-aware host, will cause physical damage disruption device host controller. should noted that topology mandatory SDIO, unlike Memory most Memory commands supported SDIO. Figure example SDIO camera card.
Figure Example SDIO Card
MMC- Multi Media Card (MMC) flash memory card standard. Unveiled 1997 Siemens SanDisk, based Toshiba's NAND-based flash memory, therefore much smaller than earlier systems based Intel NORbased memory such CompactFlash. about size postage stamp: Page
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originally used 1-bit serial interface, newer versions specification allow transfers time. MMCs currently available sizes including models. MMCplus- version standard, introduced 2005, brought very significant changes compete against cards. These were support running higher speeds (26MHz, 52MHz) than original (20MHz) (25MHz, 50MHz). Version cards fully backward compatible with existing readers require updated hardware/software their capabilities; even though wide high-speed modes operation deliberately electrically compatible with initialization protocol different, firmware/software updates required allow these features enabled when card used reader. MMCmobile basically same MMCplus except that supports data mode. RS-MMC -This alternate form factor known Reduced-Size MultiMediaCard, RS-MMC, introduced 2004. This form factor smaller form factor, about half size: RS-MMCs simply smaller MMCs. RS-MMCs currently available sizes including Nokia used RS-MMC Nokia Internet Tablet. Figure side side comparison RS-MMC card.
Figure RS-MMC Card
Figure SD/MMC interface design BeagleBoard.
8.11.1 Power
SD/MMC connector supplied power from TPS65950 using VMMC1 rail. default setting this rail 3.0V Boot under control, 1.80V with 1.8V cards. maximum current this rail provide
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220mA determined TPS65950 regulator. Maximum current limited overall current available from interface
8.11.2 OMAP3530 Interface
There external buffers required SD/MC operation. OMAP3530 provides required interfaces SD/MMC interface. main features MMC/SD/SDIO host controller are: Full compliance with command/response sets defined Multimedia Card System Specification, v4.0 Full compliance with command/response sets defined Memory Card Specifications, v1.10d Full compliance with SDIO command/response sets interrupt/read-wait mode defined SDIO Card Specification, Part v1.10 Compliance with sets defined Card Specification, Part Host Controller Standard Specification, v1.00 Full compliance with testing procedure defined Multimedia Card System Specification, v4.0 Full compliance with CE-ATA command/response sets defined CE-ATA Standard Specification Full compliance with MMCA specification Flexible architecture allowing support command structure Support: 1-bit 4-bit transfer mode specifications SDIO cards 1-bit, 4-bit, 8-bit transfer mode specifications cards Built-in 1024-byte buffer read write 32-bit-wide access maximize throughput Single interrupt line multiple interrupt source events slave channels Programmable clock generation Support SDIO Read Wait Suspend/Resume functions Support Stop block Support command completion signal (CCS) command completion signal disable (CCSD) management specified CE-ATA Standard Specification
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TWL4030
VMMC1 VMMC1.OUT 0.1uF VIO_1V8 10UF 0.1uF
MMC1_DAT3 MMC1_CMD
MHC-W21-601 #1_MMC+/MMCM/RSMMC/MMC/SD #2_MMC+/MMCM/RSMMC/MMC/SD #3_MMC+/MMCM/RSMMC/MMC/SD #4_MMC+/MMCM/RSMMC/MMC/SD #5_MMC+/MMCM/RSMMC/MMC/SD #6_MMC+/MMCM/RSMMC/MMC/SD #7_MMC+/MMCM/RSMMC/MMC/SD #8_MMC+/MMCM/SD #9_MMC+/MMCM/SD #10_MMC+/MMCM #11_MMC+/MMCM #12_MMC+/MMCM #13_MMC+/MMCM #1_miniSD #2_miniSD #3_miniSD #4_miniSD #5_miniSD #6_miniSD #7_miniSD #8_miniSD #9_miniSD #10_miniSD #11_miniSD GND1 GND2 SD_WP
OMAP35xx
MMC1_CLK MMC1_DAT0 MMC1_DAT1 MMC1_DAT2 MMC1_DAT4 MMC1_DAT5 MMC1_DAT6 MMC1_DAT7 GPIO_23
OMAP35xx_ES2.0
SD/MMC Connector MMC+, MMCMobile, MMC, miniSD, RS-MMC
Figure SD/MMC Interface
known limitations follows: built-in hardware support error correction codes (ECC). Multimedia Card System Specification, v4.0, Memory Card Specifications, v1.10d, details about ECC. maximum block size defined Memory Card Specifications, v1.10d that host driver read write buffer host controller 2048 bytes. supports maximum block size 1024 bytes. byte transfers, buffer considered double buffering with ping-pong management; half buffer written while other part read. 1024 byte transfers, entire buffer dedicated transfer (read only write only).
Table provides description signals card.
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Table
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SD/MMC OMAP Signals
Revision
Signal Name
MMC1_CLK MMC1_CMD MMC1_DAT(0.7) MMC_WP
Description
SD/MMC Clock output. SD/MMC Command SD/MMC Data pins Write Protect detect
N27,N26,N25,P28,P27, P26,R27,R25
8.11.3 Card Detect
When card inserted into SD/MMC connector, Card Detect grounded. This detected TPS65950. interrupt, enabled, sent OMAP3530 interrupt pin. written such that system comes sleep reduced frequency mode when card detected.
8.11.4 Write Protect
card inserted into SD/MMC connector write protect active, Write Detect grounded. This detected GPIO_29 OMAP3530. then determine card write protected accordingly.
8.11.5 Mode
BeagleBoard also supports 8-bit cards. upper bits supplied VDD_SIM power rail such 8-bit mode only supported 1.8V modes. This requires that both VMMC1 VDD_SIM rails must 1.8V when using cards.
8.11.6 Booting From SD/MMC Cards
code supports booting from cards with some limitations: Support MMC/SD cards compliant with Multimedia Card System Specification v4.2 from MMCA Technical Committee Secure Digital Card Specification v2.0 from Association. Including high-capacity (size >2GB) cards: HC-SD MMC. power supply, voltage port Initial 1-bit mode, 4-bit mode. Clock frequency: Identification mode: Data transfer mode: Only card connected FAT12/16/32 support, with without master boot sector (MBR). Page
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high-speed MMC/SD/SDIO host controllers handle physical layer while code handles simplified logical protocol layer (read-only protocol). limited range commands implemented code. MMC/SD specification defines operating voltages standard high-speed cards. code only supports standard operating voltage range (3-V) (both modes supported). code reads booting file from card file system boots from 8.12 Audio Interface
BeagleBoard supports stereo through TPS65950 which provides audio CODEC. Figure Audio circuitry design BeagleBoard.
TPS65950 HSOL HSOR OMAP3530 HSOL INTER_HSOL 47uF,CER INTER_HSOR 47uF,CER CONN_HSOL CONN_HSOR PHONOJACK STEREO-R
AUDIO_OUT
HSOR
OMAP3
47pF 47pF I2S.CLK I2S.SYNC I2S.DIN I2S.DOUT CLK256FS AUXL AUXR AUXL AUXR 0.1uF,CER 0.1uF,CER 47pF 47pF
DIO_V5.5MLA0603
McBSP2_FSX McBSP2_CLKX McBSP2_DR McBSP2_DX McBSP_CLKS
DIO_V5.5MLA0603
AUDIO_IN
CONN_AUXL CONN_AUXR
PHONOJACK STEREO-R
DIO_V5.5MLA0603 DIO_V5.5MLA0603
Figure Audio Circuitry 8.12.1 OMAP3530 Audio Interface
There five McBSP modules called McBSP1 through McBSP5 OMAP3530. McBSP2 provides full-duplex, direct serial interface between CODEC inside TPS65950. supports format TPS65950. Table signals used OMAP3530 interface CODEC.
Table OMAP3530 Audio Signals
Signal Name
mcbsp2_dr mcbsp2_dx mcbsp2_clkx mcbsp2_fsx Mcbsp_clks
Description
Received serial data Transmitted serial data Combined serial clock Combined frame synchronization External clock input. Used synchronize with TPS65950
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8.12.2 TPS65950 Audio Interface
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TPS65950 acts master slave interface. TPS65950 master, must provide frame synchronization (I2S_SYNC) clock (I2S_CLK) OMAP3530. slave, TPS65950 receives frame synchronization clock. TPS65950 supports left-justified right-justified data formats, doesn't support slave mode. Table signals used interface OMAP3530.
Table OMAP3530 Audio Signals
Signal Name
I2S.CLK I2S.SYNC I2S.DIN I2S. DOUT CLK256FS
Description
Clock signal (audio port) Synchronization signal (audio port) Data receive (audio port) Data transmit (audio port) Synchronization frame sync OMAP3530
8.12.3 Audio Output Jack
single 3.5mm jack provided BeagleBoard support external stereo audio output devices such headphones powered speakers.
8.12.4 Audio Input Jack
single 3.5mm jack supplied support external audio inputs including stereo mono. 8.13 DVI-D Interface
interface OMAP3530 accessible from DVI-D interface connector board. Figure DVI-D interface design.
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3.3V FERRITE, MMZ1608R301A FERRITE, MMZ1608R301A DVI_PVDD TVDD C119 C120 C121 C122 C123 C124 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Revision
DVI_DVDD FERRITE, MMZ1608R301A VIO_1V8
DC_5V RXEF010 100Ma
Adjusted
OMAP3 DVI_VREF
10K,0603 TFP410 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 IDCK+ IDCKDE VSYNC HSYNC VREF ISEL BSEL DSEL
10K,0603
TXD2TXD2+ TXD2TXD2+
DSS_D0 DSS_D1 DSS_D2 DSS_D3 DSS_D4 DSS_D5 DSS_D6 DSS_D7 DSS_D8 DSS_D9 DSS_D10 DSS_D11 DSS_D12 DSS_D13 DSS_D14 DSS_D15 DSS_D16 DSS_D17 DSS_D18 DSS_D19 DSS_D20 DSS_D21 DSS_D22 DSS_D23 DSS_PCLK
AG22 AH22 AG23 AH23 AG24 AH24 AD28 AD27 AB28 AB27 AA28 AA27 AC27 AC28 AF14 AG14 3.3V
R101 R102 R103 R104 R105
DVI_DATA0 DVI_DATA1 DVI_DATA2 DVI_DATA3 DVI_DATA4 DVI_DATA5 DVI_DATA6 DVI_DATA7 DVI_DATA8 DVI_DATA9 DVI_DATA10 DVI_DATA11 DVI_DATA12 DVI_DATA13 DVI_DATA14 DVI_DATA15 DVI_DATA16 DVI_DATA17 DVI_DATA18 DVI_DATA19 DVI_DATA20 DVI_DATA21 DVI_DATA22 DVI_DATA23 DVI_CLK+ DVI_DEN DVI_VSYNC DVI_HSYNC
DVDD DVDD DVDD TVDD TVDD PVDD
DAT2DAT2+ DAT2_S DAT1DAT1+ DAT1_S DDC/CEC HPLG DAT0DAT0+ DAT0_S CLK_S CLK+ CLKCEC
TXD1TXD1+
TXD1TXD1+ 3.3V
DVI_+5v
OMAP3
EDGE TXD0TXD0+
TXD0TXD0+
TXC+ TXC-
TXC+ TXC3.3V VIO_1V8
HDMI_Conn
DSS_ACBIAS DSS_VSY DSS_HSY GPIO_170 I2C3_SCL I2C3_SDA
DKEN 410_NC 4.7K MSEN 4.7K R100
ISEL
TGND TGND TGND DGND DGND DGND
R109
SN74LVC2G07DCKR VIO_1V8 C126 0.1uF
PGND
1K,0603 1K,0603 1K,0603
BSEL DVI_DSEL
TFADJ DKEN RSVD2 MSEN
TFADJ
C125 VCCA VCCB TXS0102 (YZP) 0.1uF
DDC_I2C3_SCL DDC_I2C3_SDA
Figure DVI-D Interface
8.13.1 OMAP3530 Interface
main driver DVI-D interface originates OMAP3530 pins. OMAP3530 provides bits data DVI-D framer chip, TFP410. There three other signals used control DVI-D that originate OMAP3530. These I2C3_SCL, I2C3_SDA, GPIO_170. signals used described Table
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Table
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OMAP3530 Signals
Revision
Signal Name
dss_pclk dss_hsync dss_vsync dss_acbias dss_data0 dss_data1 dss_data2 dss_data3 dss_data4 dss_data5 dss_data6 dss_data7 dss_data8 dss_data9 dss_data10 dss_data11 dss_data12 dss_data13 dss_data14 dss_data15 dss_data16 dss_data17 dss_data18 dss_data19 dss_data20 dss_data21 dss_data22 dss_data23 GPIO_170 I2C3_SCL I2C3_SDA
Description
Pixel Clock Horizontal Synchronization Vertical Synchronization Pixel data enable (TFT) output Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Powers down TFP410 when TFP410 active when I2C3 clock line. Used communicate with monitor determine setting information. I2C3 data line. Used communicate with monitor determine setting information.
Type
Ball
AG22 AH22 AG23 AH23 AG24 AH24 AD28 AD27 AB28 AA28 AA27 AC27 AC28 AF14 AG14
BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7
10ohm series resistors provide signal path minimize reflections high frequency signals from OMAP3530 TFP410. These resistors form resistor packs BeagleBoard. maximum clock frequency these signals 65MHz.
8.13.2 OMAP3530 Power
order outputs operate correctly OMAP3530, voltage rails must active, VIO_1V8 VDD_PLL2. Both these rails controlled TPS65950 must 1.8V. default, VDD_PLL2 turned must activated Otherwise some bits will have power supplied them.
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8.13.3 TFP410 Framer
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TFP410 provides universal interface allow glue-less connection provide DVI-D digital interface drive external panels. adjustable 1.1-V 1.8-V digital interface provides low-EMI, high-speed that connects seamlessly with 1.8V 24-bit interface output OMAP3530. interface BeagleBoard supports flat panel display resolutions 24-bit true color pixel format. Table description interface control pins TFP410 they used BeagleBoard.
Table TFP410 Interface Signals
Signal Name
DATA[23:12] DATA[11:0] IDCK+ IDCKDE HSYNC VSYNC MSEN ISEL BSEL DSEL EDGE DKEN VREF TGADJ
Description
upper bits 24-bit pixel bus. bottom bits 24-bit pixel bus. Single ended clock input. Tied ground support single ended mode. Data enable. During active video high), transmitter encodes pixel data, DATA[23:0]. During blanking interval low), transmitter encodes HSYNC VSYNC. Horizontal sync input Vertical sync input These three inputs de-skew inputs DK[3:1], used adjust setup hold times pixel data inputs DATA[23:0], relative clock input IDCK±. level indicates powered receiver detected differential outputs. high level indicates powered receiver detected. This disables mode chip. Configuration specified configuration pins (BSEL, DSEL, EDGE, VREF) state pins (PD, DKEN). Selects 24bit single-edge clock mode. select single ended clock mode. high level selects primary latch occur rising edge input clock IDCK level enables de-skew controlled DK[1:3] Sets level input signals from OMAP3530. selects normal operation selects powerdown mode. This controls amplitude output voltage swing, determined value pullup resistor RTFADJ connected 3.3V.
Type
Ball
36-47 50-55.5653
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8.13.4 TFP410 Power
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Power TFP410 supplied from 3.3V regulator TPS2141. order insure noise free signal, there three inductors, that used filter 3.3V rail into TFP410.
8.13.5 TFP410 Control Pins
There twelve control pins that TFP410 operate with OMAP3530. Most these pins require intervention OMAP3530 them.
8.13.5.1 ISEL
ISEL pulled place TFP410 control mode with feature disabled. This allows other modes TFP410 other control pins.
8.13.5.2 BSEL
BSEL pulled select mode Pixel Data interface from OMAP3530.
8.13.5.3 DSEL
DSEL pulled select single ended clock mode from OMAP3530.
8.13.5.4 EDGE
EDGE signal pulled through select rising edge IDCK+ lead which pixel clock from OMAP3530.
8.13.5.5 DKEN
DKEN signal pulled enable de-skew pins. de-skew pins, DK1-DK3, pulled internal pulldown resistors TFP410. This default mode operation. desired, resistors installed pull signals high. However, expected that resistors will need installed. DK1-DK3 pins adjust timing clock relates data signals.
8.13.5.6 MSEN
MSEN signal, when low, indicates that there powered monitor plugged into DVI-D connector. This signal connected OMAP3530 provided test point only.
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8.13.5.7 VREF
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VREF signal sets voltage level DATA, VSYNC, HSYNC, IDCK+ leads from OMAP3530. OMAP3530 1.8V, level R65.
8.13.5.8
signal originates from OMAP3530 GPIO_170 pin. Because signal TFP410 3.3V referenced, this signal must converted 3.3V. This done SN74LVC2G07, non-inverting open drain buffer. GPIO_170 then open drain signal inactive, causing signal pulled R98. When GPIO_170 taken low, output will also placing TFP410 power down mode. Even though running 1.8V match OMAP3530, output will support being pulled 3.3V. power TFP410 disabled R109, resistor. When OMAP3530 powers comes safe mode, meaning being driven. R109 insures that signal pulled putting TFP410 power down mode.
8.13.5.9 TFADJ
TFADJ signal controls amplitude output voltage swing, determined value R95.
8.13.5.10 RSVD2
This unused terminated ground directed TFP410 data manual.
8.13.5.11
This unused pulled directed TFP410 data manual.
8.13.6 DVI-D Connector
order minimize board size, HDMI connector selected DVI-D connection. BeagleBoard does support HDMI only DVI-D component HDMI. Cable supplied with BeagleBoard available from numerous cable suppliers required connect display BeagleBoard.
8.13.6.1 Shield Wire
Each signal shield wire that used cable provide signal protection each differential pair. This signal tied directly ground.
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8.13.6.2 DAT0+/DAT0-
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differential signal pair DAT0+/DAT0- transmits 8-bit blue pixel data during active video HSYNC VSYNC during blanking interval.
8.13.6.3 DAT1+/DAT1-
differential signal pair DAT1+/DAT1- transmits 8-bit green pixel data during active video.
8.13.6.4 DAT2+/DAT2-
differential signal pair DAT2+/DAT2- transmits 8-bit pixel data during active.
8.13.6.5 TXC+/TXC-
differential signal pair TXC+/TXC- transmits differential clock from TFP410.
8.13.6.6 Channel
Display Data Channel (sometimes referred EDID Enhanced Display digital connection between computer display OMAP3530 that allows display specifications read OMAP3530. standard created Video Electronics Standards Association (VESA). current version DDC, called DDC2B, based bus. monitor contains read-only memory (ROM) chip programmed manufacturer with information about graphics modes that monitor display. This interface panel powered connector through RT1, resetable fuse. OMAP3530 1.8V I/O, level translated U11, TXS0102. provides split rail allow signals interface both sides circuit. Inside TXS0102 pullup each signal, removing need external resistor.
8.13.6.7 HDMI Support
digital portion DVI-D interface compatible with HDMI electrically same. standard HDMI cable used connect HDMI input monitors televisions. Whether Beagle will support those monitors dependent timings that used BeagleBoard those that accepted monitor. This require change software running Beagle. audio encryption features HDMI supported BeagleBoard.
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8.13.6.8
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analog portion which provides analog signals supported BeagleBoard. Buying adapter connector will work display. will need active DVI-D adapter. Another option these signals find board that connects expansion connectors generates signals display.
8.14
Expansion Headers
Access provided allow access signals. Table shows signals that connector. will notice that signals logical order grouping. This routing where allowed routing take president route with addition layers design.
Table
Signals
Pin#
Signal
DC_5V DC_5V DVI_DATA1 DVI_DATA0 DVI_DATA3 DVI_DATA2 DVI_DATA5 DVI_DATA4 DVI_DATA12 DVI_DATA10 DVI_DATA23 DVI_DATA14 DVI_DATA19 DVI_DATA22 I2C3_SDA DVI_DATA11 DVI_VSYNC DVI_PUP
Description
rail from Main supply rail from Main supply Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data I2C3 Data Line Pixel Data Vertical Sync Signal Control signal controller. When enabled. used activate circuitry adapter board desired. Ground Ground
current available DC_5V rail limited available current that remains from supply that connected power jack board. Keep mind that some that power needed Host power rail more power
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needed expansion board, main power supply current capability need increased. signals 1.8V except DVI_PUP which 3.3V signal. Table shows signals that connector
Table Signals
Pin#
Signal
3.3V VIO_1V8 DVI_DATA20 DVI_DATA21 DVI_DATA17 DVI_DATA18 DVI_DATA15 DVI_DATA16 DVI_DATA7 DVI_DATA13 DVI_DATA8 DVI_DATA9 I2C3_SCL DVI_DATA6 DVI_CLK+ DVI_DEN DVI_HSYNC
Description
3.3V reference rail 1.8V buffer reference rail. Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data Pixel Data connect Pixel Data I2C3 Clock Line Pixel Data Clock Data Enable Horizontal Sync Ground Ground
1.8V rail level translation only should used power circuitry board. 3.3V rail also limited capacity power well. TFP410 disabled Beagle, then 80mA freed adapter card connected signals connectors. required that TFP410 disabled when running adapter card, power should taken into consideration when making this decision. suggested that rail used generate required voltages adapter card.
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REF: BB_SRM 8.15 S-Video
BeagleBoard System Reference Manual
Revision
single S-Video port provided BeagleBoard. Figure design SVideo interface.
TV_VFB1 47pF TV_VFB2 47pF C141 3.3uH C140 3.3uH TV_OUT2 TV_OUT2 TV_OUT1 TV_VREF OMAP35xx_ES3.0 TV_OUT2 TV_OUT1 TV_VFB1 TV_VFB2 TV_VREF U12B TV_OUT1
1.65K TV_VFB1
1.65K TV_VFB2
SVideoConn
TV/S-Video Conn
C142 0.1uF
Figure S-Video Interface
Table list signals S-Video interface their definitions.
Table S-Video Interface Signals
Signal tv_out1 tv_out2 tv_vref tv_vfb1 tv_vfb2
Description
analog output composite analog output S-VIDEO Reference output voltage from internal bandgap Amplifier feedback node Amplifier feedback node
Power internal supplied TPS65950 VDAC_1V8 rail. Figure reflects filtering that used these rails, including input VBAT rail. 47pf 3.3uh inductor across feedback resistors improve quality S-Video signal.
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REF: BB_SRM 8.16 RS232 Port
BeagleBoard System Reference Manual
Revision
single RS232 port provided BeagleBoard provides access lines UART3 OMAP3530. Figure shows design RS232 port.
3.3V
C114 0.1uF 232_C1+2 C115 0.1uF232_C1- 232_C2+5 C118 0.1uF232_C2- C1C2+ C2DIN ROUT FORCEON DOUT INVALID FORCEOFF
7232_V3 232_V+ C117 0.1uF RS232_TX1 C116 0.1uF
VIO_1V8 C110 TP21 TESTPT1 TP22 232OE VCCA VCCB TXS0102 (DCU) TESTPT1
3.3V C111 0.1uF UART3_TX_3V UART3_RX_3V
0.1uF UART3_TX UART3_RX
RS232_RX1
HEADER
UART3 Serial Port
SN65C3221EPW
Figure RS232 Interface Design 8.16.1 OMAP3530 Interface
lines, UART3_Tx UART3_Rx, provided OMAP3530. UART3 function contains programmable baud generator fixed dividers that divide 48-MHz clock input down expected baud rate also supports auto bauding.
8.16.2 OMAP3530 Level Translator
levels from OMAP3530 1.8V while transceiver used runs 3.3V. This requires that voltage levels translated. This accomplished TXS0102 which two-bit noninverting translator that uses separate configurable power-supply rails. port tracks VCCA, 1.8V port tracks VCCB, 3.3V. This allows low-voltage bidirectional translation between voltage nodes. When output-enable (OE) input low, outputs placed high-impedance state. this design, tied high resistor insure that always
8.16.3 RS232 Transceiver
RS232 transceiver used SN65C322 which consists line driver, line receiver, dual charge-pump circuit with ±15-kV protection (serial-port connection pins, including GND). These devices provide electrical interface between asynchronous communication controller serial-port connector. charge pump four small external capacitors allow operation from Page
REF: BB_SRM
BeagleBoard System Reference Manual
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single 5.5-V supply. SN65C3221 operates data signaling rates Mbit/s driver output slew rate V/ms V/ms. While OMAP3530 easily drive 1Mbit/S rate, your results vary based cabling, distance, loads drive capability other RS232 port. transceiver powered from 3.3V rail active power This allows port used UART based peripheral booting over port.
8.16.4 Connector
Access RS232 port through 10pin header, Connection header through D-sub cable. This header requires ATIEverex type cable. This only cable that will work. This cable readily available from number sources commonly found many motherboards supplied with BeagleBoard. Figure picture what cable assembly looks like.
Figure RS232 Cable
When purchasing, make sure ATI-Everex pass through cable ordered. 8.17 Indicators
There four green indicators BeagleBoard: Power PMU_STAT USER0 USER1 Page
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Three these programmable under software control fourth tied main power rail. Figure shows connection these indicators.
TPS65950 T2_LED_B PMU_STAT
VBAT VBAT VBAT VBAT
LEDB LEDGND
PMU_STAT
LTST-C150CKT
POWER
USER0
USR0_LEDR34 LED0_GPIO150 OMAP3530_ES3.0 GPIO_150 GPIO_149 LED1_GPIO149 RN1907
200.0603USR0_LED_R 0.125W
USER1
D5_RES
820,0603 USR1_LED 200.0603 USR1_LED_R 0.125W
OMAP3530
0.125W
RN1907
Figure Indicator Design
8.17.1 Power Indicator
This indicator, connects across VBAT supply ground. indicates that entire power path supplying power board. VBAT regulator driven from either Client port external 5VDC power supply. Indicator does indicate which power source being used supply main power board only that active.
8.17.2 Status Indicator
This output driven from TPS65950 using LED.B output. TPS65950 provides driver circuitry power circuits that provide user indicators. first circuit provide second, Each circuit independently controllable basic power (on/off) control illumination level (using PWM). second driver, LED.B, used drive that connected VBAT rail through resistor. inside TPS65950 used alter brightness desired turned OMAP3530 using bus. programmable, register-controlled, duty cycle based nominal 4-Hz cycle which
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BeagleBoard System Reference Manual
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derived from internal 32-kHz clock. possible flash automatically without software control desired.
8.17.3 User Indicators
There user LEDs that driven directly from GPIO OMAP3530. These used purpose software. output level OMAP3530 1.8V current sink capability enough drive with level brightness. transistor pair, RN1907 used drive LEDs from VBAT rail. logic level will turn 8.18 JTAG
JTAG header provided allow advanced debugging BeagleBoard using JTAG based debugger Figure shows interconnection OMAP3530 processor.
VIO_1V8 VIO_1V8 76385-407LF 0.1uF10V 100K 100K 100K 100K 100K JTAG_TMS JTAG_TDI JTAG_TDO JTAG_RTCK JTAG_TCK AA18 AA20 AA19 AA12 AA13 OMAP3530_ES3.0 JTAG_TMS JTAG_TDI JTAG_TDO JTAG_RTCK JTAG_TCK
OMAP3530
JTAG_EMU0
AA11 AA17 AA10
JTAG_nTRST JTAG_EMU1
JTAG_nTRST
Figure JTAG Interface
8.18.1 OMAP3530 Interface
JTAG interface connects directly OMAP processor. signals 1.8V level. Table describes signals JTAG connector.
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BeagleBoard System Reference Manual
Table JTAG Signals
Revision
Signal
JTAG_TMS JTAG_TDI JTAG_TDO JTAG_RTCK JTAG_TCK JTAG_nTRST JTAG_EMU0 JTAG_EMU1
Description
Test mode select Test data input Test Data Output Clock Emulation Test Clock Test reset Test emulation Test emulation
8.18.2 Connector
JTAG interface uses connector. JTAG emulator modules should able support this interface. Contact your emulator supplier further information adapter needed. 8.19 Expansion Header
expansion header provided allow limited number functions added BeagleBoard addition daughtercard. Figure design expansion connector interfaces OMAP3530.
DC_5V OMAP3_ES3.0 AB26 AA25 AA21 AF15 AE15 UART2_CTS MCBSP3_CLKX MCBSP3_FSX MCBSP3_DR MCBSP1_DX MCBSP1_CLKX MCBSP1_FSX MCBSP1_DR MCBSP1_CLKR MCBSP1_FSR I2C2_SCL nRESET
VIO_1V8 MMC2_DAT7 MMC2_DAT6 MMC2_DAT5 MMC2_DAT4 MMC2_DAT3 MMC2_DAT2 MMC2_DAT1 MMC2_DAT0 MMC2_CMD MMC2_CLKO I2C2_SDA nUSB_DC_EN OMAP3_ES3.0
OMAP3
Reset circuitry
McBSP3_DX McBSP3_CLKX McBSP3_FSX McBSP3_DR McBSP1_DX McBSP1_CLKX McBSP1_FSX McBSP1_DR McBSP1_CLKR McBSP1_FSR I2C2_SCL I2C2_SDA
MMC2_DAT7 MMC2_DAT6 MMC2_DAT5 MMC2_DAT4 MMC2_DAT3 MMC2_DAT2 MMC2_DAT1 MMC2_DAT0 MMC2_CMD MMC2_CLK
OMAP3
power circuitry
HEADER 14X2
Figure Expansion Header
NOTE: Expansion header itself provided BeagleBoard. This user installed option. This header populated BeagleBoard that based usage scenario user chooses; populated needed (Top, Bottom, right angle, Bottom Right angle). user should take care installing this header.
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CAUTION: voltage levels expansion header 1.8V. Exposure these signals higher voltage will result damage board voiding warranty.
8.19.1 OMAP3530 Interface
main purpose expansion connector route additional signals from OMAP3530 processor. Table shows signals that expansion header. OMAP3530 multiplexing feature, multiple signals connected certain pins additional options pertains signal available. Each individually different mode. This allows listed modes basis writing register software. Following legend Table
there signal connected when this mode selected this safe mode meaning neither input output. This default mode
power this indicates that there signal connected when this mode selected, useful purpose without other pins being available. Access these other pins provided expansion connector. first column number expansion connector. second column number OMAP3530 processor. columns labeled represent each modes that pin. setting this value control register, this signal will routed corresponding expansion connector. These setting basis. with register setting, applicable signal will routed expansion connector.
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Table
OMAP
BeagleBoard System Reference Manual
Expansion Connector Signals
VIO_1V8 DC_5V GPT9_PWMEVT GPT11_PWMEVT GPT10_PWMEVT McBSP3_DX McBSP3_CLKX McBSP3_FSX McBSP3_DR REGEN nRESET
Revision
AB26 AA25 AB25 AA21 AE15 AF15
MMC2_DAT7 UART2_CTS MMC2_DAT6 UART2_TX MMC2_DAT5 McBSP3_FSX MMC2_DAT4 UART2_RTS MMC2_DAT3 McBSP1_DX MMC2_DAT2 McBSP1_CLKX MMC2_DAT1 McBSP1_FSX MMC2_DAT0 McBSP1_DR MMC2_CMD McBSP1_CLKR MMC2_CLKO McBSP1_FSR I2C2_SDA I2C2_SCL
McBSP3_DX McBSP3_CLKX UART2_RX McBSP3_DR McSPI3_CS0 McSPI4_SIMO McSPI3_CS1 McSPI4_CS0 McSPI3_SOMI McSPI4_SOMI McSPI3_SIMO McSPI4_CLK McSPI3_CLK
GPIO_139 GPIO_144 GPIO_138 GPIO_146 GPIO_137 GPIO_143 GPIO_136 GPIO_145 GPIO_135 GPIO_158 GPIO_134 GPIO_162 GPIO_133 GPIO_161 GPIO_132 GPIO_159 GPIO_131 GPIO_156 GPIO_130 GPIO_157 GPIO_183 GPIO_168
8.19.2 Expansion Signals
This section provides more detail each signals available expansion connector. They grouped functions Table along with description each signal setting activate pin. these signals their respective groups that only function use, signals available. Whether signals need available, depends muxing function per-pin basis. Only signal available time.
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REF: BB_SRM
Table
Signal MMC2_DAT7 MMC2_DAT6 MMC2_DAT5 MMC2_DAT4 MMC2_DAT3 MMC2_DAT2 MMC2_DAT1 MMC2_DAT0 MMC2_CMD MMC_CLKO McBSP1_DR McBSP1_CLKS McBSP1_FSR McBSP1_DX McBSP1_CLKX McBSP1_FSX McBSP1_CLKR I2C2_SDA I2C2_SCL McBSP3_DR McBSP3_DX McBSP3_CLKX McBSP3_FSX GPIO_130 GPIO_131 GPIO_132 GPIO_133 GPIO_134 GPIO_135 GPIO_136 GPIO_137 GPIO_138 GPIO_139 GPIO_143 GPIO_144 GPIO_145 GPIO_146 GPIO_156 GPIO_158 GPIO_159 GPIO_161 GPIO_162 GPIO_168 GPIO_183 McSPI3_CS0 McSPI3_CS1 McSPI3_SIMO McSPI3_SOMI McSPI3_CLK McSPI4_SIMO McSPI4_SOMI McSPI4_CS0 McSPI4_CLK UART2_CTS UART2_RTS
BeagleBoard System Reference Manual
Expansion Connector Signal Groups
Description SD/MMC Port SD/MMC data SD/MMC data SD/MMC data SD/MMC data SD/MMC data SD/MMC data SD/MMC data SD/MMC data SD/MMC command signal. SD/MMC clock signal. McBSP Port Multi channel buffered serial port receive -Multi channel buffered serial port transmit frame sync Multi channel buffered serial port transmit Multi channel buffered serial port transmit clock Multi channel buffered serial port transmit frame sync Multi channel buffered serial port receive clock Port data line. clock line McBSP Port Multi channel buffered serial port receive Multi channel buffered serial port transmit Multi channel buffered serial port receive clock Multi channel buffered serial port frame sync transmit General Purpose Pins Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. Input/Output pin. used interrupt pin. McSPI Port Multi channel chip select Multi channel chip select Multi channel slave master Multi channel slave master Multi channel clock McSPI Port Multi channel slave master Multi channel slave master Multi channel chip select Multi channel clock UART Port UART clear send. UART request send 10,18 4,12 6,14 8,16
Revision
OMAP
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BeagleBoard System Reference Manual
UART receive UART transmit event timer event timer event timer
Revision
UART2_RX UART2_TX GPT9_PWMEVT GPT11_PWMEVT GPT10_PWMEVT
8.19.3 Power
expansion connector provides power rails. first VIO_1.8V rail which supplied TPS65950. This rail limited current supply from TPS65950 what remains from current consumed BeagleBoard intended used provide rail voltage level conversion only. intended power circuitry expansion board. signals from BeagleBoard 1.8V. other rail DC_5V. same restriction exits this rail mentioned section. amount available power expansion board depends available power from supply supply from
8.19.4 Reset
nRESET signal main board reset signal. When board powers this signal will input reset circuitry expansion board. After power system reset generated expansion board taking this signal low. This signal 1.8V level signal.
8.19.5 Power Control
There additional open-drain signal connector called REGEN. purpose this signal provide means control power circuitry expansion card turn voltages. This insures that power expansion board turned appropriate time. Depending what circuitry provided expansion board, additional delay needed added before circuitry activated. Refer OMAP3530 TPS65950 documentation more information. 8.20 Additional Expansion Header
choose headers access signals DVI-D interface, they also used other functions board based setting each pin. Table shows options Table shows options MUX: column indicates which mode must each make respective signals accessible pins OMAP3530.
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Table
BeagleBoard System Reference Manual
GPIO Signals MUX:0
DATA1 DATA0 DATA3 DATA2 DATA5 DATA4 DATA12 DATA10 DATA23 DATA14 DATA19 DATA22 I2C3_SDA DATA11 VSYNC DVI_PUP
Revision
Pin#
Signal
DVI_DATA1 DVI_DATA0 DVI_DATA3 DVI_DATA2 DVI_DATA5 DVI_DATA4 DVI_DATA12 DVI_DATA10 DVI_DATA23 DVI_DATA14 DVI_DATA19 DVI_DATA22 I2C3_SDA DVI_DATA11 DVI_VSYNC DVI_PUP
MUX:2
UART1_RTS UART1_CTS UART3_TX UART3_RX McSPI3_SIMO McSPI3_CS1
MUX:4
GPIO71 GPIO70 GPIO73 GPIO72 GPIO75 GPIO74 GPIO82 GPIO79 GPIO93 GPIO84 GPIO89 GPIO92 GPIO81 GPIO68
Table
GPIO Signals MUX:0
DATA20 DATA21 DATA17 DATA18 DATA15 DATA16 DATA7 DATA13 DATA8 DATA9 I2C3_SCL DATA6 PCLK HSYNC
Pin#
Signal
DVI_DATA20 DVI_DATA
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