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Low-Power Embedded Pentium® Processor with MMXTechnology
Advance Information Datasheet
Support MMXTechnology Low-Power 0.25 Micron Process Technology (166/266 MHz) Core Supply PPGA (166 MHz) (266 MHz) Core Supply HL-PBGA Interface (166/266 MHz) 32-Bit with 64-Bit Data Fractional Operation 166-MHz Core/66-MHz 266-MHz Core/66-MHz Superscalar Architecture Enhanced Pipelines Pipelined Integer Units Capable Instructions/Clock Pipelined Technology Pipelined Floating-Point Unit
Separate Code Data Caches 16-Kbyte Code, 16-Kbyte Write-Back Data MESI Cache Protocol Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 4-Mbyte Pages Increased Rate IEEE 1149.1 Boundary Scan Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions Internal Error Detection Features On-Chip Local APIC Controller Power Management Features System Management Mode Clock Control 296-pin PPGA 352-ball HL-PBGA
Notice: This document contains information products sampling initial production phases development. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 273184-001 October, 1998
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Low-Power Embedded Pentium® Processor with MMXTechnology contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1998 *Third-party brands names property their respective owners.
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Contents
Overview Introduction Microprocessor Architecture Overview
Pentium® Processor Family Architecture Pentium® Processor with MMXTechnology 3.2.1 Full Support Intel MMXTechnology 3.2.2 16-Kbyte Code Data Caches.13 3.2.3 Improved Branch Prediction 3.2.4 Enhanced Pipeline 3.2.5 Deeper Write Buffers 0.25 Micron Technology
Package Information
4.10 Differences from Desktop Processors. PPGA Pinout Descriptions HL-PBGA Pinout Descriptions Design Notes. Quick Reference Fraction (BF) Selection CPUID Instruction Boundary Scan Chain List. Reference Tables.32 Grouping According Function.
Electrical Specifications
Absolute Maximum Ratings. Specifications 5.2.1 Power Sequencing Specifications 5.3.1 Power Ground 5.3.2 Decoupling Recommendations 5.3.3 Connection Specifications 5.3.4 Timings Buffer Models 5.4.1 Buffer Model Parameters Signal Quality Specifications 5.5.1 Overshoot 5.5.2 Undershoot. 5.5.3 Ringback 5.5.4 Settling Time 5.5.5 Measurement Methodology. Measuring Maximum Overshoot, Undershoot Ringback. Measuring Overshoot Threshold Duration Measuring Undershoot Threshold Duration
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Low-Power Embedded Pentium® Processor with MMXTechnology
Mechanical Specifications
PPGA Package Mechanical Diagrams. HL-PBGA Package Mechanical Diagrams
Thermal Specifications
Measuring Thermal Values 7.1.1 Thermal Equations Data 7.1.2 Airflow Calculations Maximum Typical Power. PPGA Package Thermal Resistance Information HL-PBGA Package Thermal Resistance Information
Figures
Pentium® Processor with MMXTechnology Block Diagram. PPGA Package Side View PPGA Package Side View HL-PBGA Package Side View HL-PBGA Package Side View Assignments CPUID Assignments CPUID. Clock Waveform Valid Delay Timings Float Delay Timings Setup Hold Timings Reset Configuration Timings Test Timings. Test Reset Timings First Order Input Buffer Model. First Order Output Buffer Model. Maximum Overshoot Level, Overshoot Threshold Level Overshoot Threshold Duration Maximum Undershoot Level, Undershoot Threshold Level Undershoot Threshold Duration Maximum Ringback Associated with Signal High State Maximum Ringback Associated with Signal State. Settling Time PPGA Package Dimensions HL-PBGA Package Dimensions. Technique Measuring Thermal Resistance Heatsink Height, PPGA Packages Thermal Resistance Airflow HL-PBGA Package
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Tables
Signals Removed from Low-Power Embedded Pentium® Processor with MMXTechnology Cross Reference Name (PPGA Package) Connect, Power Supply Ground Cross Reference (PPGA Package) Cross Reference Name (HL-PBGA Package) Connect, Power Supply Ground Cross Reference (HL-PBGA Package) Quick Reference Frequency Selection Assignment Definitions CPUID Assignment Definitions CPUID Output Pins. Input Pins Input/Output Pins.34 Functional Grouping. Absolute Maximum Ratings. TCASE Specifications. Specifications Specifications Power Dissipation Requirements Thermal Design. Input Output Characteristics Low-Power Embedded Pentium® Processor with MMXTechnology Specifications APIC Specifications. Notes Tables Parameters Used Specification First Order Input Buffer Model.48 Parameters Used Specification First Order Output Buffer Model. Signal Buffer Type. Input, Output Bidirectional Buffer Model Parameters PPGA Package. Preliminary Input, Output Bidirectional Buffer Model Parameters HL-PBGA Package Input Buffer Model Parameters: (Diodes) Overshoot Specification Summary Undershoot Specification Summary PPGA Package Dimensions. HL-PBGA Package Dimensions. Thermal Resistances PPGA Packages. Thermal Resistances HL-PBGA Packages
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Overview
Low-Power Embedded Pentium Processor with MMXTechnology extends Pentium processor family, providing additional performance power embedded applications. low-power embedded Pentium processor with technology compatible with entire installed base applications MS-DOS*, Windows*, OS/2*, UNIX* major microprocessors support Intel technology. Furthermore, low-power embedded Pentium processor with technology superscalar architecture which execute instructions clock cycle, enhanced branch prediction separate caches also increase performance. pipelined floating-point unit delivers workstation level performance. Separate code data caches reduce cache conflicts while remaining software transparent. low-power embedded Pentium processor with technology million transistors, built Intel's 0.25 micron manufacturing process technology full Enhanced power management features including System Management Mode (SMM) clock control. lowpower embedded Pentium processor with technology available 296-pin Plastic Grid Array (PPGA) 352-ball High-Thermal Low-Profile-Plastic Ball Grid Array (HL-PBGA). HL-PBGA package allows designers surface mount technology create small formfactor designs. additional Enhanced features, low-power dissipation PPGA HL-PBGA package make low-power embedded Pentium processor with technology ideal embedded designs.
Introduction
low-power embedded Pentium processors with technology high performance embedded applications (166 MHz) fully compatible with existing Pentium processors with technology (200 MHz) with following differences: voltage supplies, power consumption, performance. Additionally, Pentium processors with technology socket compatible with Pentium processor (100, 133, MHz), making possible design flexible motherboard that supports both Pentium processor embedded Pentium processors with technology (166-266 MHz). low-power embedded Pentium processor with technology advanced architectural internal features desktop version Pentium processor with technology, except that several features have been eliminated. differences specified "Differences from Desktop Processors" page low-power embedded Pentium processor with technology several features which allow high-performance embedded designs. These features include following:
core (PPGA 166/266 MHz) core (HL-PBGA 166), core (HL-PBGA 266) buffer VCC3 inputs reduce power consumption Enhanced feature
This document should used conjunction with Embedded Pentium® Processor Family Developer's Manual (order number 273204).
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Microprocessor Architecture Overview
low-power embedded Pentium processor with technology extends family Pentium processors with technology. binary compatible with 8086/88, 80286, Intel386DX, Intel386 Intel486SX, IntelDX2TM, IntelDX4TM, Pentium processors with voltage reduction technology (75-150 MHz). embedded Pentium processor family consists embedded Pentium processor (100, 133, MHz), embedded Pentium processor with voltage reduction technology (133 MHz), embedded Pentium processor with technology (200, MHz), low-power embedded Pentium processor with technology (166, MHz). low-power embedded Pentium processor with technology contains features previous Intel architecture processors provides significant enhancements additions, including following:
Support MMXTechnology Superscalar Architecture Enhanced Branch Prediction Algorithm Pipelined Floating-Point Unit Improved Instruction Execution Time Separate 16-Kbyte Code Cache 16-Kbyte Data Cache Writeback MESI Protocol Data Cache 64-Bit Data Enhanced Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions 0.25 Micron Process Technology Power Management Features Pool Four Write Buffers Used Both Pipes
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Pentium® Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 family instruction with extensions accommodate some additional functionality Pentium processors. application software written Intel386 Intel486 family microprocessors will Pentium processors without modification. on-chip memory management unit (MMU) completely compatible with Intel386 Intel486 families processors. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit Pentium processors capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, Pentium processors implement prefetch buffers, that prefetches code linear fashion, that prefetches code according Branch Target Buffer (BTB) that code almost always prefetched before needed execution. floating-point unit been completely redesigned over Intel486 processor. Faster algorithms provide speed-up common operations including add, multiply, load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache 32-byte line size 4-way associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable writeback writethrough line-by-line basis follows MESI protocol. data cache tags triple ported support data transfers inquire cycle same clock. code cache inherently write-protected cache. code cache tags also triple ported support snooping split line accesses. Individual pages configured cacheable non-cacheable software hardware. caches enabled disabled software hardware. Pentium processors have increased data bits improve data transfer rate. Burst read burst writeback cycles supported Pentium processors. addition, cycle pipelining been added allow cycles progress simultaneously. Pentium processors' contains optional extensions architecture that allow 4-Kbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception.
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
more more functions integrated on-chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors have specified four breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap virtual 8086 monitor. Figure shows block diagram Pentium processor with technology. block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions. separate code data caches shown. data cache ports, each pipes (the tags triple ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache.
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Figure Pentium® Processor with MMXTechnology Block Diagram
Branch Prefetch Target Buffer Address
Code Cache Kbytes
Instruction Pointer Branch Verif. Target Addr.
Prefetch Buffers Instruction Decode Control
64-Bit Data 32-Bit Address
Control Unit Page Unit Unit
Pipeline Connection Pipeline Connection
Floating-Point Unit Control
Control
Address Generate
Address Generate
MMXTechnology Unit
Register File Divide Multiply
Pipeline) Pipeline)
Integer Register File
Pipeline) Barrel Shifter 64-Bit Data Data Control 32-Bit Address
Pipeline)
Data Cache Kbytes
APIC
A5920-01
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
code cache, branch target buffer prefetch buffers responsible getting instructions into execution units Pentium processor. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit decodes prefetched instructions Pentium processor execute instruction. control contains microcode which controls sequence operations that must performed implement Pentium processor architecture. control unit direct control over both pipelines. Pentium processor contains pipelined floating-point unit that provides significant floatingpoint performance advantage over previous generations processors. addition features described above, Pentium processor supports clock control. When clock processor stopped, power dissipation virtually eliminated. combination these improvements makes Pentium processor good choice low-power embedded designs. Pentium processor supports fractional operation. This allows internal processor core operate high frequencies, while communicating with external lower frequencies. low-power embedded Pentium processor with technology contains on-chip advanced programmable interrupt controller (APIC). This function reserved future multi-processing function. architectural features introduced this section more fully described Embedded Pentium Processor Family Developer's Manual (order number 273204).
Pentium® Processor with MMXTechnology
Pentium processor with technology high-performance embedded designs significant addition Pentium processor family. Available 166, 200, 233, MHz, first microprocessor support Intel technology. Pentium processor with technology both software compatible with previous members Pentium processor family. contains million transistors manufactured lntel's enhanced 0.35 micron (200/233 MHz) 0.25 micron (166/266 MHz) CMOS process, which allows voltage reduction technology power high density. addition architecture described previous section Pentium processor family, Pentium processor with technology several additional micro-architectural enhancements, which described next section.
3.2.1
Full Support Intel MMXTechnology
technology based SIMD technique (Single Instruction, Multiple Data) which enables increased performance wide variety multimedia communications applications. Fifty-seven instructions four 64-bit data types supported Pentium processor with technology. existing operating system application software fullycompatible.
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Low-Power Embedded Pentium® Processor with MMXTechnology
3.2.2
16-Kbyte Code Data Caches
On-chip level-1 data code cache sizes Kbytes each 4-way associative Pentium processor with technology. Large separate internal caches improve performance reducing average memory access time providing fast access recently-used instructions data. instruction data caches accessed simultaneously while data cache supports data references simultaneously. data cache supports write-back alternatively, writethrough, line-by-line basis) policy memory updates.
3.2.3
Improved Branch Prediction
Dynamic branch prediction uses Branch Target Buffer (BTB) boost performance predicting most likely instructions executed. been improved Pentium processor with technology increase accuracy. This processor four prefetch buffers that hold four successive code streams.
3.2.4
Enhanced Pipeline
additional pipeline stage been added pipeline been enhanced improve performance. integration technology pipeline with integer pipeline very similar that floating-point pipeline. Under some circumstances, instructions integer instruction paired issued clock cycle increase throughput. enhanced pipeline described more detail Embedded Pentium® Processor Family Developer's Manual (order number 273204).
3.2.5
Deeper Write Buffers
pool four write buffers shared between dual pipelines improve memory write performance.
0.25 Micron Technology
0.25 micron technology state-of-the-art CMOS manufacturing process Intel unveiled April 1997, enabling lower core supply sub-2 result, low-power embedded Pentium processor with technology consumes significantly less power even higher speeds.
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Package Information
Differences from Desktop Processors
following features have been eliminated low-power embedded Pentium processor with technology: Upgrade, Dual Processing (DP), Master/Checker functional redundancy. Table lists corresponding pins that exist Pentium processor with technology have been removed low-power embedded Pentium processor with technology.
Table
Signals Removed from Low-Power Embedded Pentium® Processor with MMXTechnology
Signal ADSC# Function Additional Address Status. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Additional Burst Ready. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Type. This signal used dual processing systems. Dual/Primary processor identification. This signal only used upgrade processor. Functional Redundancy Checking. This signal only used error detection processor redundancy requires Pentium processors (master/checker). Private Grant. This signal only used dual processing systems. Private Request. This signal used only dual processing systems. Private Hit. This signal only used dual processing systems. Private Modified Hit. This signal only used dual processing systems.
BRDYC# CPUTYP D/P# FRCMC# PBGNT# PBREQ# PHIT# PHITM#
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
PPGA Pinout Descriptions
text orientation side view drawings this section represents orientation mark actual packages. (Note that text shown this section actual text that will marked packages).
Figure PPGA Package Side View
VCC3 VCC3 VCC3 VCC3 INTR VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2
VCC2 FLUSH# W/R#
EADS#
SCYC
BE6#
BE4#
BE2#
BE0# BUSCHK# HITM# A20M# HIT#
VCC2DET BREQ
RESET
BE7#
BE5#
BE3#
BE1#
D/C# HLDA
ADS#
LOCK#
SMIACT# VCC2 PCHK# APCHK# PRDY VCC2 VCC2
R/S#
SMI# INIT
BUSCHK# HOLD WB/WT# VCC2
VCC3 IGNNE# VCC3 VCC3
PEN#
BOFF# BOFF#
BRDYC# VCC2 VCC2
BRDY# KEN#
EWBE#
STPCLK# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 TRST# VCC3
AHOLD#
Side View
INV#
CACHE# VCC2 VCC2
VCC3
MI/O#
PM1BP1
FERR# PM0BP0# VCC2 IERR# VCC2 VCC2 VCC2 VCC2
PICD1
VCC3 VCC3
PICD0
PICCLK DP19
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
000260
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Figure PPGA Package Side View
BREQ
VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 INTR VCC3 VCC3 VCC3 VCC3
FLUSH# VCC2 W/R#
EADS#
VCC2DET
HITM# BUSCHK# BE0# HIT# A20M#
BE2#
BE4#
BE6#
SCYC
D/C# HLDA
BE1#
BE3#
BE5#
BE7#
RESET
ADS#
LOCK#
VCC2 SMIACT# VCC2 VCC2 PCHK# APCHK# PRDY
R/S#
BUSCHK# HOLD VCC2 WB/WT#
SMI# INIT
IGNNE#
BOFF#
PEN#
VCC3 VCC3
VCC2 BRDYC# VCC2
BRDY# KEN#
EWBE#
AHOLD# INV#
STPCLK#
VCC2 CACHE# VCC2
Side View
VCC3
VCC3 VCC3
MI/O#
VCC3 TRST#
PM1BP1
VCC2 PM0BP0# FERR# VCC2 VCC2 VCC2 VCC2 DP19 IERR#
VCC3
VCC3 VCC3
VCC3 PICD0
PICD1
VCC3 VCC3 VCC3
PICCLK
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
000261
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Table
Cross Reference Name (PPGA Package) (Sheet
Location Location Address AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 AK26 AL25 AK24 AL23 Data Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# AK08 AJ05 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# AJ01 AL07 AK04 AM04 HITM# HLDA HOLD IERR# IGNNE# INIT INTR/ LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# AL05 AJ03 AB04 AA35 AA33 AD34 AH04 AC33 AG05 AF04 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# VCC2DET# W/R# AC05 AL03 AC35 AK20 AL17 AB34 AG03 AL01 AM06 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33 Location Location
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Table
Cross Reference Name (PPGA Package) (Sheet
BRDY# Location FLUSH# HIT# Location AN07 AK06 PEN# PM0/BP0 APIC PICCLK PICD0 PICD1 [APICEN] Location WB/WT# Location AA05
Clock Control STPCLK# AK18
Table
Connect, Power Supply Ground Cross Reference (PPGA Package)
VCC2 VCC3 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
Connect (NC) AA03 AC03 AD04 AE03 AE35 AL19 AM02 AN01 AN03 AN05 AN35
NOTE: Shaded pins differ functionally from Pentium® Processor with MMXTechnology pinout.
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
HL-PBGA Pinout Descriptions
Figure HL-PBGA Package Side View
LOCK#
HOLD
BOFF# KEN# AHOLD M/IO# PM1/BP1 IERR# WB/WT# EWBE# PM0/BP0 VCC2 BRDY# VCC2 CACHE# FERR#
APCHK# PRDY
SMIACT#
VCC3
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
HLDA
BREQ PCHK# VCC2 VCC3 VCC2 VCC3 VCC3
VCC2 VCC3
VCC2 VCC3 VCC2
VCC2 VCC3 VCC3
VCC2 VCC2
VCC3 VCC2 VCC3 VCC2
VCC3 VCC2
D/C#
EADS#
W/R#
ADS#
FLUSH# HIT# HITM# VCC3 BE0# BE2# BUSCHK# BE1# A20M# VCC3 VCC3 VCC3 VCC2 VCC3 VCC2 VCC3 VCC3
BE3# BE5#
BE4# BE7#
BE6#
View
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
SCYC RESET VCC2
VCC3 VCC3
VCC2 VCC2 VCC2
VCC2
VCC3 VCC2 VCC3
VCC3 VCC2
VCC3 VCC3
VCC3
VCC2
VCC2
VCC2 VCC2
VCC3 VCC2 VCC2 VCC2
VCC2 VCC2
VCC3 VCC2
PICD[0]
SMI# NMI/LINT1
INIT
BF[0] BF[2]
VCC2 VCC2
PICCLK
IGNNE# PEN# BF[1] STPCLK# INTR/LINT0
TRST#
PICD[1]
A4694-01
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Figure HL-PBGA Package Side View
IERR#
PM1/BP1 M/IO# EWBE# AHOLD KEN# BOFF# HOLD PM0/BP0 WB/WT# CACHE# BRDY# VCC2 VCC2 VCC2 VCC2 SMIACT#
VCC2
FERR#
PRDY APCHK# BREQ VCC2
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
VCC2 VCC3
PCHK# VCC3 VCC2 VCC3 VCC3
HLDA
VCC3 VCC2
VCC3 VCC2 VCC3 VCC2 VCC2 VCC3 VCC3
VCC3 VCC2
LOCK#
D/C#
EADS#
ADS#
W/R#
VCC3 HITM# HIT# FLUSH# VCC3 VCC3 BE0# BUSCHK# BE2#
A20M# BE1#
BE4# BE7#
BE3# BE5#
Bottom View
VCC3
BE6#
VCC2 VCC2 RESET SCYC VCC3 VCC2 VCC3 VCC3
VCC2 VCC3 VCC3
VCC3 VCC2 VCC2 VCC2
VCC2
VCC3
VCC2
VCC2 VCC2 VCC2 VCC2
VCC3 VCC2 VCC2 VCC2
VCC2 VCC2
VCC3 VCC3
VCC3 VCC2 VCC3
VCC2 VCC3 VCC3
VCC2
PICD[0]
PICCLK
VCC2
BF[2]
BF[0]
INIT
SMI#
NMI/LINT1
PICD[1]
TRST#
STPCLK# BF[1] PEN# IGNNE# INTR/LINT0
A4695-01
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Table
Cross Reference Name (HL-PBGA Package) (Sheet
Location Location Address Data AC24 AC25 AB24 AB25 AA24 AA25 Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/ LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# AF14 AE14 AF13 AE12 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT# AF12 AE13 AE22 AE21 AF21 AF20 AF19 AF11 AE11 AF10 AE10 Location Location
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Table
Cross Reference Name (HL-PBGA Package) (Sheet
BRDY# Location FLUSH# HIT# Location PEN# PM0/BP0 APIC PICCLK AE23 PICD0 AD23 PICD1 [APICEN] AF22 Location AF15 Location
Clock Control STPCLK# AE15 AF17 AF16 AE16
Table
Connect, Power Supply Ground Cross Reference (HL-PBGA Package)
VCC2 VCC3 AA23 AD10 AD11 AD13 AD14 AD15 AD16 AD17 AD18 AD20 AD21 AD22 AD24 AE19 AE20 AC10 AC11 AC17 AC22 AB23 AC13 AC14 AC15 AC16 AC18 AC19 AC20 AC21 AC23 AD19 AE17 AE18
Connect (NC) AF18 Internal Connect (INC) AA26 AB26 AC12 AC26 AD12 AD25 AD26 AE24 AE25 AE26 AF23 AF24 AF25 AF26
Advance Information Datasheet
Low-Power Embedded Pentium® Processor with MMXTechnology
Design Notes
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected CC3. Unused active high inputs should connected (VSS). Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
Quick Reference
This section gives brief functional description each pin. detailed description, Hardware Interface chapter Embedded Pentium® Processor Family Developer's Manual. Note: input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET. pins classified Input Output based their function Master Mode. Error Detection chapter Embedded Pentium® Processor Family Developer's Manual (order number 273204) further information.
Table
Quick Reference (Sheet
Symbol Type Name Function When address mask asserted, Pentium® processor with MMXtechnology emulates address wraparound Mbyte, which occurs 8086. When A20M# asserted, processor masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address status indicates that valid cycle currently being driven processor. response assertion address hold, processor will stop driving address lines (A31-A3) next clock. rest will remain active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock that address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated. address parity check status asserted clocks after EADS# sampled active processor detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected. byte enable pins used determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31-3).
A20M#
A31-A3
ADS#
AHOLD
APCHK#
BE7#-BE5# BE4#-BE0#
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Low-Power Embedded Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function Frequency pins determine bus-to-core frequency ratio. [2:0] sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF[2:0] must change values while RESET active. Table Frequency Selection. BF2-BF0 order override internal defaults guarantee that BF[2:0] inputs remain stable while RESET active, these pins should strapped directly through pullup/pulldown resistor VCC3 ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. During power RESET should asserted prior ramped simultaneously with core voltage supply processor. backoff input used abort outstanding cycles that have completed. response BOFF#, processor will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor will latch address control signals machine check registers. addition, set, processor will vector machine check exception. BUSCHK# assure that BUSCHK# will always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor will vector exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, processor will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external requires levels. external timing parameters except TDI, TDO, TMS, TRST# PICD0-1 specified with respect rising edge CLK. This V-tolerant-only low-power embedded Pentium processor with technology. recommended that begin after reaches proper operating level. This recommendation only assure long term reliability device.
BOFF#
[APICEN] PICD1
BP3-BP2 PM/BP1-BP0
BRDY#
BREQ
CACHE#
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Table
Quick Reference (Sheet
Symbol D/C# Type Name Function data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back Pentium processor with voltage reduction technology these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56; applies D7-D0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write EWBE# sampled inactive, processor will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using MS-DOS type floating-point error reporting. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated processor indicating completion writeback invalidation. FLUSH# sampled when RESET transitions from high low, three-state test mode entered. indication driven reflect outcome inquire cycle. inquire cycle hits valid line either data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive processor will resume driving bus. processor cycle pending, will driven same clock that HLDA de-asserted. response hold request, processor will float most output input/output pins assert HLDA after completing outstanding cycles. processor will maintain this state until HOLD de-asserted. HOLD recognized during LOCK cycles. processor will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, processor will assert IERR# clock then shutdown.
D63-D0
DP7-DP0
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IERR#
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Table
Quick Reference (Sheet
Symbol Type Name Function This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, processor will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will stop execution wait external interrupt. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, processor will perform built-in self test prior start program execution. active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, processor will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle. lock indicates that current cycle locked. processor will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed de-asserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor will issue ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. page cache disable reflects state CR3; Page Directory Entry Page Table Entry. purpose provide external cacheability indication page-by-page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned.
IGNNE#
INIT
INTR
KEN#
LOCK#
M/IO#
PCHK#
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Table
Quick Reference (Sheet
Symbol Type Name Function parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock, data parity error detected. processor will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", processor will vector machine check exception before beginning next instruction. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input Pentium processor with technology. Programmable interrupt controller data lines Pentium processor with technology comprise data portion APIC 3-wire bus. They opendrain outputs that require external pull-up resistor. These signals multiplexed with APICEN. These pins function part performance monitoring feature. PM/BP[1:0] breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. probe ready output indicates that processor stopped normal execution response R/S# going active Probe Mode being entered. page writethrough reflects state CR3, page directory entry, page table entry. used provide external writeback indication page-by-page basis. run/stop input provided with Intel debug port. Please refer Embedded Pentium® Processor Family Developer's Manual (Order Number 273204) more details. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine three-state test mode will entered BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock Pentium processor with voltage reduction technology thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate Stop Grant Acknowledge cycle. When STPCLK# asserted, processor will still respond external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state.
PEN#
PICCLK PICD0- PICD1 [APICEN]
PRDY
R/S#
RESET
SCYC
SMI#
SMIACT#
STPCLK#
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Table
Quick Reference (Sheet
Symbol Type Name Function test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. Differentiate between Pentium Processor with technology lowpower embedded Pentium processor with technology. This Internal Connect (INC) low-power embedded Pentium processor with technology. This defined HL-PBGA package. These pins power inputs core: input 166/266 PPGA; HL-PBGA; HL-PBGA. These pins power inputs I/O. These pins ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line-by-line basis. result, determines whether cache line initially state data cache.
TRST#
VCC2DET#
VCC2 W/R#
WB/WT#
Fraction (BF) Selection
Each low-power embedded Pentium processor with technology must externally configured with BF2-BF0 pins operate specified fraction mode. Operation specification supported. example, low-power embedded Pentium processor with technology supports only fraction mode mode. configuration pins provided select allowable bus/core ratios 1/4. low-power embedded Pentium processor with technology multiplies input achieve higher internal core frequencies. internal clock generator requires constant frequency input within ±250 therefore, input cannot changed dynamically. external frequency during power-up Reset through pin. low-power embedded Pentium processor with technology samples BF0, pins falling edge RESET determine which bus/core ratio use. Table summarizes operation pins low-power embedded Pentium processor with technology. Note: pins must meet setup time falling edge RESET must change value while RESET active. Once frequency selected, changed with warm reset. Changing this speed ratio requires "power RESET pulse initialization.
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Table
Frequency Selection
Bus/Core Ratio Bus/Core Frequency (MHz) 66/166 66/266
NOTE: other BF2-BF0 settings reserved low-power embedded Pentium processor with technology.
CPUID Instruction
CPUID instruction allows software determine type features processor which executing. When executing CPUID, low-power embedded Pentium processor with technology behaves like Pentium processor Pentium processor with technology follows:
value `0', then 12-byte ASCII string "Genuine Intel" (little endian)
returned EBX, ECX. Also, returned EAX.
value `1', then processor version returned processor
capabilities returned EDX. values low-power embedded Pentium processor with technology given below.
value neither `1', low-power embedded Pentium processor with
technology writes registers. following values defined CPUID instruction executed with `1'. processor version assignments given Figure assignments shown Figure Figure Assignments CPUID
(Reserved)
Type Family
Model Stepping
000250
Figure Assignments CPUID
Rsvd
000251
Reserved
Reserved
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type field low-power embedded Pentium processor with technology same Pentium processor with technology (type 00H). family field same other Pentium processors (family 5H). However, model field different: Pentium processor model number Pentium processor with technology model number low-power embedded Pentium processor with technology model number stepping field indicates revision number model. stepping A-step lowpower embedded Pentium processor with technology Stepping will documented low-power embedded Pentium processor with technology stepping information. After masking reserve bits, low-power embedded Pentium processor with technology-based products will value 0x008003BF (assuming APIC enabled boot), 0x008001BF (when APIC disabled, using APICEN boot pin) upon completion CPUID instruction. Table Assignment Definitions CPUID
Value Comments FPU: Floating-point Unit on-chip VME: Virtual-8086 Mode Enhancements Debugging Extensions PSE: Page Size Extension TSC: Time Stamp Counter Pentium® Processor PAE: Physical Address Extension MCE: Machine Check Exception
Table
Assignment Definitions CPUID
10-11 15-22 24-31 Value Comments CX8: CMPXCHG8B Instruction APIC: APIC on-chip Reserved write these bits rely their values MTRR: Memory Type Range Registers PGE: Page Global Enable MCA: Machine Check Architecture Reserved write these bits rely their values Intel Architecture with MMXtechnology supported Reserved write these bits rely their values
Indicates that APIC present hardware enabled (software disabling does affect this bit).
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Boundary Scan Chain List
boundary scan chain list low-power embedded Pentium processor with technology different than Pentium processor with technology removal some pins. boundary scan register low-power embedded Pentium processor with technology contains cell each pin. Following order low-power embedded Pentium processor with technology boundary scan register (left right, bottom): disapsba, PICD1, PICD0, Reserved, PICCLK, DP0, D10, D11, D12, D13, D14, D15, DP1, D16, D17, D18, D19, D20, D21, D22, D23, DP2, D24, D25, D26, D27, D28, D29, D30, D31, DP3, D32, D33, D34, D35, D36, D37, D38, D39, DP4, D40, D41, D42, D43, D44, D45, D46, diswr D47, DP5, D48, D49, D50, D51, D52, D53, D54, D55, DP6, D56, D57, D58, D59, D60, D61, D62, D63, DP7, IERR#, FERR#, PM0BP0, PM1BP1, BP2, BP3, MIO#, CACHE#, EWBE#, INV, AHOLD, KEN#, BRDYC#, BRDY#, BOFF#, NA#, WBWT#, HOLD, disbus, disbusl, dismisc, dismisca, SMIACT#, PRDY, PCHK#, APCHK#, BREQ, HLDA, LOCK#, PCD, PWT, DC#, EADS#, ADS#, HITM#, HIT#, WR#, BUSCHK#, FLUSH#, A20M#, BE0#, BE1#, BE2#, BE3#, BE4#, BE5#, BE6#, BE7#, SCYC, CLK, RESET, disabus A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A31, A30, A29, A28, A27, A26, A25, A24, A23, A22, A21, NMI, RS#, INTR, SMI#, IGNNE#, INIT, PEN#, Reserved, BF0, BF1, BF2, STPCLK#, Reserved, Reserved, Reserved, Reserved "Reserved" includes connect "NC" signals low-power embedded Pentium processor with technology. cells marked with dagger control cells that used select direction bidirectional pins three-state output pins. loaded into control cell, associated pin(s) three-stated selected input. following lists control cells their corresponding pins: Disabus: Disbus: Disbusl: Dismisc: Dismisca: Diswr: Disapsba: A31-A3, BE7#-BE0#, CACHE#, SCYC, M/IO#, D/C#, W/R#, PWT, ADS#, LOCK#, ADSC# APCHK#, PCHK#, PRDY, BP3, BP2, PM1/BP1, PM0/BP0, FERR#, SMIACT#, BREQ, HLDA, HIT#, HITM# IERR# D63-D0, DP7-DP0 PICD1-PICD0
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Reference Tables
Table Output Pins
Name ADS# APCHK# BE7#-BE4# BREQ CACHE# FERR# HIT# HITM#(2) HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-BP2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT# VCC2DET#(3) Active Level High High High High High High states except Shift-DR Shift-IR Differentiates between Pentium® processor with MMXtechnology low-power embedded Pentium processor with technology Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated
NOTE: output input/output pins floated during three-state test mode (except TDO). HITM# internal pull-up resistor. This HL-PBGA pinout.
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Table Input Pins
Name A20M# AHOLD BOFF# BRDY# BUSCHK# EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# Pullup Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Pullup Pullup State T2,T12,T2P BRDY# Pulldown Pullup Pulldown Internal Resistor Qualified
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Table Input/Output Pins
Name A31-A3 BE3#-BE0# D63-D0 DP7-DP0 PICD0 PICD1[APICEN] Active Level When Floated(1) Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown(2) Internal Resistor
NOTE: output input/output pins floated during three-state test mode (except TDO). BE3#-BE0# have pulldowns during RESET only.
4.10
Grouping According Function
Table Functional Grouping
Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating-point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Debugging RESET, INIT, BF[2:0] A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# PICCLK, PICD0-PICD1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-BP2 STPCLK# R/S#, PRDY Pins
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Electrical Specifications
This section contains preliminary information products production. specifications subject change without notice.
Warning:
Absolute Maximum Ratings
following values stress ratings only. Functional operation maximum ratings implied guaranteed. Functional operating conditions given specification tables. Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor with technology contains protective circuitry resist damage from Electrostatic Discharge (ESD), always take precautions avoid high static voltages electric fields.
Table Absolute Maximum Ratings
Parameter Case temperature under bias Storage temperature VCC3 supply voltage with respect VCC2 supply voltage with respect only buffer input voltage -65° 110° -65° 150° -0.5 +3.2 -0.5 +2.8 -0.5 VCC3+0.5 (not exceed VCC3 max) Maximum Rating
Specifications
Tables list specifications which apply low-power embedded Pentium processor with technology.
5.2.1
Power Sequencing
There specific sequence required powering powering down VCC3 power supplies. However, recommended that VCC2 VCC3 power supplies either both both within second each other. voltage VCC3 core voltage VCC2 PPGA. core voltage HL-PBGA package type (166 MHz) (266 MHz).
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Table TCASE Specifications
Package TCASE Supply VCC2 VCC3 VCC2 HL-PBGA 95°C VCC2 VCC3 Voltage 1.750 2.375 1.665 1.85 2.375 Voltage 2.04 2.625 1.935 2.15 2.625 Voltage Tolerance 7.5% 7.5% 7.5% Frequency 166/266 166/266 166/266
PPGA
85°C
Table Specifications
Symbol VIH3 VOL3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage VCC3 VCC3 VCC3 Unit Level Level, Level, Level, Notes
-0.3
VCC3
NOTES: Parameter measured Parameter measured Parameter measured 100% tested, guaranteed design.
values Table should used power supply design. values were determined using worst case instruction maximum VCC. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes. Table Specifications
Symbol ICC2 ICC3 Parameter Power Supply Current 2.35 (HL-PBGA) (PPGA) 4.00 0.38 0.38 Unit Notes
Power Supply Current
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Table Power Dissipation Requirements Thermal Design
Parameter Thermal Design Power Active Power(3) Stop Grant/Auto Halt Powerdown Power Dissipation(4) Stop Clock Power(5) 0.70 0.70 0.06 0.06 Typical(1) Max(2) (HL-PBGA) (PPGA) Unit Watts Watts Watts Watts Watts Watts Watts Watts Watts Frequency
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device specified voltage running typical applications. This value dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum thermal design power unless system uses thermal feedback limit processor's maximum power. maximum thermal design power determined using worst-case instruction also takes into account thermal time constant package. Active power average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. Stop Grant/Auto Halt Powerdown Power Dissipation determined asserting STPCLK# executing HALT instruction. When this mode, processor feature which allows power down additional circuitry enable lower power dissipation. This power without snooping specified voltage with TR12 set. order enable this feature, TR12 must (the default disabled). Stop grant/Auto Halt Powerdown power dissipation without TR12 higher. rating changed future specification updates. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. This specified TCASE
Table Input Output Characteristics
Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input High Leakage Current Input Leakage Current -400 Unit 0<VIN <VIL, VIH< <VCC3, 0<VIN <VIL, VIH< <VCC3, VCC3 Notes
NOTES: This parameter inputs/outputs without internal pull pull down. This parameter inputs with internal pull This parameter inputs with internal pull down. Guaranteed design. This specification applies HITM# when driven input (e.g., JTAG mode).
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Specifications
specifications low-power embedded Pentium processor with technology consist setup times, hold times, valid delays
5.3.1
Power Ground
clean on-chip power distribution, PPGA (core power), VCC3 (I/O power) (ground) inputs. HL-PBGA package, there VCC3, VCC2 inputs. Power ground connections must made external VCC2, VCC3 pins. circuit board, VCC2 pins must connected proper voltage VCC2 plane island (core voltage determined package type/frequency). pins must connected VCC3, plane. pins must connected plane. Please refer Table page list VCC2, VCC3 pins.
5.3.2
Decoupling Recommendations
Liberal decoupling capacitance should placed near processor. processor's large address data buses cause transient power surges, particularly when driving large capacitive loads. inductance capacitors interconnects recommended best high frequency electrical performance. Inductance reduced shortening circuit board traces between processor decoupling capacitors much possible. These capacitors should evenly distributed around each component power plane. Capacitor values should chosen ensure they eliminate both high frequency noise components. Power transients also occur processor rapidly transitions from level power consumption high level high power transition). typical example would entering exiting Stop Grant state. Another example would executing HALT instruction, causing processor enter Auto HALT Powerdown state, transitioning from HALT Normal state. these examples cause abrupt changes power being consumed processor. Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel. These capacitors should placed near processor both VCC2 plane VCC3 plane ensure that supply voltages stay within specified limits during changes supply current during operation.
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5.3.3
Connection Specifications
NC/INC pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected ground.
5.3.4
Timings
specifications given Table consist output delays, input setup requirements input hold requirements standard external bus. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced VCC3/VCC2 both logic levels unless otherwise specified. Within sampling window, asynchronous inputs must stable correct operation. Each valid delay specified load. system designer should buffer modeling account signal flight time delays. select fraction clock speed which will cause processor exceed internal maximum frequency. following specifications apply standard signals used with Pentium processor family:
input test waveforms assumed transitions with V/ns rise fall
times.
V/ns input rise/fall time V/ns. timings referenced from CC3/VCC2.
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Table Low-Power Embedded Pentium® Processor with MMXTechnology Specifications (Sheet
(See Table TCASE assumptions.) Symbol Parameter Frequency Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, CACHE# Valid Delay Valid Delay LOCK#, Valid Delay ADS# Valid Delay A31-A3 Valid Delay M/IO# Valid Delay BE7#-BE0#, D/C#, SCYC Valid Delay ADS#, A31-A3, PWT, PCD, BE7#-BE0#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM1-PM0, BP3-BP0 Valid Delay PRDY Valid Delay D63-D0, DP7-DP0 Write Data Valid Delay D63-D0, DP3-0 Write Data Float Delay A31-A5 Setup Time A31-A5 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time 0.15 0.15 33.33 15.0 66.6 30.0 ±250 Unit @VCC3 @0.5 VCC3 VCC3 -0.7 Figure Notes (see Table
10.0
t10a t10b t11a t11b t16a t16b
10.0 10.0
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Table Low-Power Embedded Pentium Processor with MMXTechnology Specifications (Sheet
(See Table TCASE assumptions.) Symbol t18a t18b t24a t24b t25a t25b Parameter KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D63-D0, DP7-0 Read Data Setup Time D63-D0, DP7-0 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable 4.75 Unit Figure Notes (see Table
15.0
CLKs CLKs CLKs
(10, (10,
(10) Power
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Table Low-Power Embedded Pentium® Processor with MMXTechnology Specifications (Sheet
(See Table TCASE assumptions.) Symbol Parameter Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. BF2-BF0 Setup Time BF2-BF0 Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 40.0 13.0 20.0 25.0 20.0 25.0 Unit Figure Notes (see Table
t42a
CLKs
RESET falling edge,
t42b t43a t43b t43c t43d
CLKs
RESET falling edge RESET falling edge, (10) RESET falling edge, (12) RESET falling edge RESET falling edge
62.5 25.0 25.0 16.0
CLKs CLKs CLKs
@VCC3 -0.7 @0.5 VCC3 -0.7 VCC3 -0.7 Asynchronous, (15) (15) (13) (13, (15, (15,
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Table APIC Specifications
Symbol t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay PICD0-1 High Time PICCLK Setup Time PICCLK Hold Time PICCLK Ratio (CLK/PICCLK) 0.15 0.15 16.66 Unit PICCLK PICCLK From PICCLK, (18) From PICCLK, (18) (19) Figure Notes
Table Notes Tables
input frequency must either 33.33 MHz) 66.6 MHz). Operation range between 33.33 66.6 supported. percent tested. Guaranteed design. These signals measured rising edge adjacent CLKs VCC3/VCC2. ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. internal clock generator requires constant frequency input within +250 therefore input cannot changed dynamically. 0.87 V/ns input rise/fall time V/ns. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions. Timing (t14) required external snooping (e.g., address setup which EADS# sampled active). Setup time required guarantee recognition specific clock. This input driven asynchronously. Hold time required guarantee recognition specific clock. 10.When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must de-asserted (inactive) minimum clocks before being returned active. guarantee proper asynchronous recognition, signal must have been de-asserted (inactive) minimum clocks before being returned active must meet minimum pulse width. 12.BF2-BF0 should strapped VCC3 VSS. 13.Referenced falling edge. 14.1 added maximum rise fall times every frequency below MHz. 15.Referenced rising edge. 16.Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. 17.During probe mode operation, boundary scan timings (t55-t58). 18.This assumes external pull-up resistor lumped capacitive load. pull-up resistor must between capacitance must between product must between 19.The PICCLK ratio integer ratio (CLK/PICCLK) cannot smaller than
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Figure Clock Waveform
Vcc3-0.7V 0.5V t49, t60e t48, t60f t46, t60c t45, t60b t47, t60d
PP0051
Figure Valid Delay Timings
Vcc3/2
max.
Signal Signal
min.
Vcc3/2
VALID
t10, t11, t12, t60i
PP0052
Figure Float Delay Timings
Vcc3/2
Signal
t6min, t12min
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Figure Setup Hold Timings
Vcc3/2
Signal
VALID
t14, t16, t18, t20, t22, t24, t26, t28, t31, t34, t60g PICCLK), t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t60h PICCLK),
Figure Reset Configuration Timings
RESET
Vcc3/2
Vcc3/2
Config =t42, t43c, t43e, t43b, t43d, t43f, t38, VALID
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Figure Test Timings
Vcc3/2
Output Signals
Input Signals
Figure Test Reset Timings
TRST#
Vcc3/2
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Buffer Models
This section describes buffer models low-power embedded Pentium processor with technology. first order buffer model simplified representation complex input output buffers used. Figure shows structure input buffer model Figure shows output buffer model. Table show parameters used specify these models. Although simplified, these buffer models will accurately model flight time signal quality. these parameters, there very little added accuracy complete transistor model. addition input output buffer parameters, input protection diode models provided added accuracy. These diodes have been optimized provide protection provide some level clamping. Although diodes required simulation, more difficult meet specifications without them. Note, however, some signal quality specifications require that diodes removed from input model. series resistors (RS) part diode model. Remove these when removing diodes from input model.
Figure First Order Input Buffer Model
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Table Parameters Used Specification First Order Input Buffer Model
Parameter Description Minimum Maximum value capacitance input buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance Diode Series Resistance Ideal Diodes
Figure First Order Output Buffer Model
Table Parameters Used Specification First Order Output Buffer Model
Parameter dV/dt Description Minimum maximum value rate change open circuit voltage source used output buffer model Minimum maximum value output impedance output buffer model Minimum Maximum value capacitance output buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance
5.4.1
Buffer Model Parameters
This section gives parameters each input, output bidirectional buffers. input, output bidirectional buffer values processor listed Table These tables contain listings three types, them confused during simulation. When bidirectional operating input, CIN, values; operating driver, data parameters. Please refer Table groupings buffers. input, output bidirectional buffer's values listed below. These tables contain listings three types. When bidirectional operating input, just values, operating driver data parameters.
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Table Signal Buffer Type
Signals A20M#, AHOLD, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, PICCLK, R/S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT# APCHK#, BE7-BE5#, BP3-BP2, BREQ, FERR#, IERR#, PCD, PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#, A31-A3, BE4#-BE0#, CACHE#, D/C#, D63-D0, DP8-DP0, HLDA, LOCK#, M/IO#, SCYC, ADS#, HITM#, HIT#, W/R#, PICD0, PICD1 Type Driver Buffer Type Receiver Buffer Type
Table Input, Output Bidirectional Buffer Model Parameters PPGA Package
Buffer Type Transition dV/dt (V/nsec) (input) (output) (bidir) Rising Falling Rising Falling Rising Falling 2.2/2.2 2.2/2.9 2.2/2.2 2.2/2.9 2.7/0.15 2.7/0.22 2.7/0.15 2.7/0.22 21.6 17.5 21.6 17.5 (Ohms) (pF) (nH) 15.3 15.3 16.3 16.3 18.4 18.4 CO/C (pF)
Table Preliminary Input, Output Bidirectional Buffer Model Parameters HL-PBGA Package
Buffer Type Transition dV/dt (V/nsec) (input) (output) (bidir) Rising Falling Rising Falling Rising Falling 2.2/2.2 2.2/2.9 2.2/2.2 2.2/2.9 2.7/0.15 2.7/0.22 2.7/0.15 2.7/0.22 21.6 17.5 21.6 17.5 (Ohms) (pF) (nH) 11.3 11.3 11.7 11.7 10.3 10.3 CO/CIN (pF)
NOTE: data this table based preliminary design information. Input, output bidirectional buffer values being characterized this time.
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Table Input Buffer Model Parameters: (Diodes)
Symbol Parameter Saturation Current Emission Coefficient Series Resistance Transit Time Potential Zero Bias Capacitance Grading Coefficient 1.4e-14A 1.19 0.983 0.281 0.385 2.78e-16A 1.00 0.967 0.365 0.376
Signal Quality Specifications
Signals driven system into low-power embedded Pentium processor with technology must meet signal quality specifications guarantee that components read data properly ensure that incoming signals affect reliability component.
5.5.1
Overshoot
maximum overshoot overshoot threshold duration specifications inputs lowpower embedded Pentium processor with technology described follows:
Maximum overshoot specification: maximum overshoot CLK/PICCLK signals
should exceed VCC2, nominal +0.6 maximum overshoot other input signals should exceed VCC3, nominal +1.0
Overshoot threshold duration specification: overshoot threshold duration defined
time during which input signal above VCC3, nominal +0.3 within single clock period. overshoot threshold duration must exceed period. Refer Table summary overshoot specifications low-power embedded Pentium processor with technology. Table Overshoot Specification Summary
Specification Name Threshold Level Maximum Overshoot Level (CLK PICCLK) Maximum Overshoot Level (all other inputs) Maximum Threshold Duration Maximum Ringback NOTES: VCC3, nominal refers voltage measured VCC3 pins. "Measurement Methodology" page details. Figure Figure Value VCC3, nominal +0.3 VCC3, nominal +0.6 VCC3, nominal +1.0 clock period above threshold voltage VCC3, nominal -0.7 Units Notes
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Figure Maximum Overshoot Level, Overshoot Threshold Level Overshoot Threshold Duration
Maximum Overshoot Level Overshoot Threshold Level VCC3, Nominal
Overshoot Threshold Duration
000272
5.5.2
Undershoot
maximum undershoot undershoot threshold duration specifications inputs lowpower embedded Pentium processor with technology described follows:
Maximum undershoot specification: maximum undershoot CLK/PICCLK signals
must drop below -0.6 maximum undershoot other input signals must drop below -1.0
Undershoot threshold duration specification: undershoot threshold duration defined
time during which input signal below -0.3 within single clock period. undershoot threshold duration must exceed period. Refer Table summary undershoot specifications low-power embedded Pentium processor with technology. Table Undershoot Specification Summary
Specification Name Threshold Level Minimum Undershoot Level (CLK PICCLK) Minimum Undershoot Level (all other inputs) Maximum Threshold Duration Maximum Ringback NOTE: Figure Figure -0.3 -0.6 -1.0 clock period below threshold voltage Value Units Notes
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Figure Maximum Undershoot Level, Undershoot Threshold Level Undershoot Threshold Duration
Undershoot Threshold Duration
Nominal Undershoot Threshold Level Maximum Undershoot Level
000273
5.5.3
Ringback
Excessive ringback contribute long-term reliability degradation low-power embedded Pentium processor with technology, cause false signal detection. Ringback simulated input component using input buffer model. Ringback simulated with without diodes that input buffer model. Ringback absolute value maximum voltage receiving below above VSS) relative VCC3 VSS) level after signal reached maximum voltage level. input diodes assumed present. simulated without input diodes, follow Maximum Overshoot/Undershoot specifications. meeting overshoot/undershoot specifications, signal guaranteed ringback excessively. simulated with diodes present input model, follow maximum ringback specification. maximum ringback specification inputs low-power embedded Pentium processor with technology described follows:
Maximum ringback specification: maximum ringback inputs associated with their high
states (overshoot) must drop below VCC3 -1.0 shown Figure Similarly, maximum ringback inputs associated with their states (undershoot) must exceed shown Figure
Overshoot (undershoot) absolute value maximum voltage above (below
VSS). guideline assumes absence diodes input.
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Figure Maximum Ringback Associated with Signal High State
VCC3, Nominal
Maximum Ringback
000274
Figure Maximum Ringback Associated with Signal State
Maximum Undershoot Level Nominal
000275
5.5.4
Settling Time
settling time defined time signal requires receiver settle within percent VCC3 VSS. Settling time maximum time allowed signal reach within percent final value. Most available simulation tools unable simulate settling time that accurately reflects silicon measurements. Second order, other, effects physical board serve dampen signal receiver. Because these concerns, settling time recommendation tool layout tuning specification. make sure that there impact flight times signals waveform settled, settling time simulated slow corner. Settling time simulated with diodes included excluded from input buffer model. diodes included, settling time recommendations will easier meet.
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Although simulated settling time shown good correlation with physical, measured settling time, settling time simulations still used tool tune layouts. following procedure verify board simulation tuning with concerns settling time: Simulate settling time slow corner particular signal. settling time violations occur (signal requires more than 12.5 settle ±10% final value), simulate signal trace with diodes place receiver pin. diode behaves almost identically actual (non-linear) diode part long excessive overshoot does occur. settling time violations still occur, simulate flight times five consecutive cycles that particular signal. flight time values consistent over five simulations, settling time should concern. however, flight times consistent over five consecutive cycles, tuning layout required. Note that, signals that allocated cycles flight time, recommended settling time doubled. Maximum Settling Time within percent 12.5 MHz. Figure Settling Time
VIH3 +10% VIH3 -10%
2.5V
Settling Time
000276
5.5.5
Measurement Methodology
waveform input signals should measured processor pins using oscilloscope with bandwidth least (100 ms/s digital sampling rate). There should short isolation ground lead attached processor bottom side board. probe with loading less than recommended. measurement should taken input pins their nearest pins.
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Measuring Maximum Overshoot, Undershoot Ringback
display should show continuous sampling (e.g., infinite persistence) waveform mV/div ns/div (for CLK) ns/div (for other inputs) recommended duration approximately five seconds. Adjust vertical position measure maximum overshoot associated ringback with largest possible granularity. Similarly, readjust vertical position measure maximum undershoot associated ringback. There allowance crossing maximum overshoot, maximum undershoot maximum ringback specifications.
Measuring Overshoot Threshold Duration
snapshot input signal should taken mV/div ps/div (for CLK) ns/div (for other inputs). Adjust vertical position horizontal offset position view threshold duration. overshoot threshold duration defined time during which input signal above VCC3 nominal within single clock period. overshoot threshold duration must exceed period.
Measuring Undershoot Threshold Duration
snapshot input signal should taken mV/div ps/div (for CLK) ns/div (for other inputs). Adjust vertical position horizontal offset position view threshold duration. undershoot threshold duration defined time during which clock signal below -0.3 within single clock period. undershoot threshold duration must exceed period.
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Mechanical Specifications
mechanical terms, low-power embedded Pentium processor with technology 296-lead Plastic Staggered Grid Array (PPGA) completely identical Pentium processor with technology PPGA package. pins arranged 37x37 matrix package dimensions 1.95" 1.95" (4.95 4.95 cm). Package summary information PPGA device provided Table Figure shows package dimensions. HL-PBGA version low-power embedded Pentium processor with technology package type Pentium processor family. Package summary information HLPBGA device provided Table Figure shows package dimensions.
PPGA Package Mechanical Diagrams
Figure PPGA Package Dimensions
Seating Plane
Solder Resist Chip Capacitor
1.65 (Ref)
2.29 1.52 Chamfer (Index Corner)
Heat Slug
measurements
A5771-01
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Table PPGA Package Dimensions
Millimeters Symbol 1.52 0.40 49.43 45.59 23.44 2.29 3.05 2.54 0.060 2.72 1.83 1.00 Nominal 0.51 49.63 45.85 23.95 2.79 3.30 0.016 1.946 1.795 0.923 0.090 0.120 0.100 3.33 2.23 0.107 0.072 0.039 Nominal 0.020 1.954 1.805 0.943 0.110 0.130 0.131 0.088 Inches
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HL-PBGA Package Mechanical Diagrams
Figure shows ceramic HL-PBGA package. dimensions listed Table
Figure HL-PBGA Package Dimensions
Corner Corner
I.D. Dia. View
Bottom View
Side View
Seating Plane
Note: Dimensions Millimeters
A5830-01
Table HL-PBGA Package Dimensions
Millimeters Symbol
1.67 0.70 0.90 0.97 35.10 35.10 1.27 1.63
1.41 0.56 0.60 0.85 34.90 34.90
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Thermal Specifications
low-power embedded Pentium processor with technology specified proper operation when case temperature, TCASE (TC), within specified range PPGA package, HL-PBGA package.
Measuring Thermal Values
verify that proper maintained, should measured center package surface (opposite pins). measurement made same with without heatsink attached. When heatsink attached, hole (smaller than 0.150" diameter) should drilled through heatsink allow probing center package. Figure illustration measure minimize measurement errors, recommended following approach:
36-gauge finer diameter type thermocouples. laboratory testing done
using thermocouple made Omega* (part number 5TC-TTK-36-36).
Attach thermocouple bead junction center package surface using high
thermal conductivity cements. laboratory testing done using Omega Bond (part number OB-101).
thermocouple should attached 90-degree angle shown Figure hole size should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heatsink base. contact
will affect thermocouple reading.
7.1.1
Thermal Equations Data
low-power embedded Pentium processor with technology, ambient temperature, (air temperature around processor), specified directly. only restriction that met. equation used calculate
Where: Ambient case temperature (°C) Case-to-ambient thermal resistance (°C/Watt) Maximum power consumption (Watt)
thermal resistance from package case. values shown Tables typical values. actual values depend actual thermal conductivity process attach. thermal resistance from package case ambient. values shown these
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tables typical values. actual values depend heatsink design, interface between heatsink package, airflow system, thermal interactions between processor surrounding components through ambient. Figure Technique Measuring
000262
7.1.2
Airflow Calculations Maximum Typical Power
Below example determining airflow required during maximum power consumption low-power embedded Pentium processor with technology assuming ambient temperature (HL-PBGA) PHL-PBGA (HL-PBGA, without heat sink) 10.98 °C/W Figure indicates that this example would require about without heat sink, about with heat sink vertical orientation. Below example determining airflow required during typical power consumption low-power embedded Pentium processor with technology assuming ambient temperature (HL-PBGA) PHL-PBGA (HL-PBGA, without heat sink) 15.52 °C/W Figure indicates that this example would require about without heat sink. heat sink necessary typical power ambient conditions.
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PPGA Package Thermal Resistance Information
Table lists values low-power embedded Pentium processor with technology PPGA package with passive heatsinks.
Table Thermal Resistances PPGA Packages
Heatsink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None (°C/watt) 12.9 (°C/watt) Laminar Airflow (linear ft/min) 12.2 11.2
NOTES: Heatsinks omni-directional aluminum alloy. Features were based standard extrusion practices given height: size ranged from mils; spacing ranged from mils; base thickness ranged from mils. Heatsink attach 0.005" thermal grease. Attach thickness 0.002" will improve performance approximately watt.
Figure Thermal Resistance Heatsink Height, PPGA Packages
(°C/watt) Airflow Rate (LFM)
Heatsink Height (inches)
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HL-PBGA Package Thermal Resistance Information
Table lists values low-power embedded Pentium processor with technology HL-PBGA package. thermal data collection conditions were:
bidirectional anodized aluminum alloy heat sink used. Heat sink height 7mm. horizontal orientation component mounted flush with motherboard. vertical orientation component mounted add-in card perpendicular motherboard.
Table Thermal Resistances HL-PBGA Packages
Heatsink/ Orientation Heat Sink Horizontal Vertical (°C/watt) 0.76 0.76 0.76 (°C/watt) Laminar Airflow (linear ft/min) 15.66 12.09 11.33 12.33 8.57 8.34 10.3 6.52 6.38 8.85 4.82 4.69 7.89 4.06 3.95
Figure Thermal Resistance Airflow HL-PBGA Package
Airflow (LFM) Horizontal Heat Sink Vertical Heat Sink Heat Sink
(°C/W)
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