1211 ADS1210 ADS1211 SBAS034B JANUARY 1996 REVISED SEPTEMBER
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SBAS034B JANUARY 1996 REVISED SEPTEMBER 2005
24-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
DELTA-SIGMA CONVERTER BITS EFFECTIVE RESOLUTION 10Hz BITS 1000Hz DIFFERENTIAL INPUTS PROGRAMMABLE GAIN AMPLIFIER FLEXIBLE SPITM-COMPATIBLE INTERFACE WITH 2-WIRE MODE PROGRAMMABLE CUT-OFF FREQUENCY 15.6kHz INTERNAL/EXTERNAL REFERENCE ON-CHIP SELF-CALIBRATION ADS1211 INCLUDES 4-CHANNEL
DESCRIPTION
ADS1210 ADS1211 precision, wide dynamic range, delta-sigma Analog-to-Digital (A/D) converters with 24-bit resolution operating from single supply. differential inputs ideal direct connection transducers low-level voltage signals. delta-sigma architecture used wide dynamic range ensure bits no-missing-code performance. effective resolution bits achieved through very low-noise input amplifier conversion rates 10Hz. Effective resolutions bits maintained sample rate 1kHz through unique Turbo modulator mode operation. dynamic range converters further increased providing low-noise programmable gain amplifier with gain range binary steps. ADS1210 ADS1211 designed high resolution measurement applications smart transmitters, industrial process control, weigh scales, chromatography, portable instrumentation. Both converters include flexible synchronous serial interface that SPI-compatible also offers two-wire control mode cost isolation. ADS1210 single-channel converter offered both 18-pin 18-lead SOIC packages. ADS1211 includes 4-channel input multiplexer available 24pin DIP, 24-lead SOIC, 28-lead SSOP packages.
REFIN VBIAS XOUT
APPLICATIONS
INDUSTRIAL PROCESS CONTROL INSTRUMENTATION BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS
AGND AVDD REFOUT
AIN1P AIN1N AIN2P AIN2N AIN3P AIN3N AIN4P AIN4N AINP
+2.5V Reference
+3.3V Bias Generator
Clock Generator
DGND DVDD
Micro Controller Second-Order Modulator Third-Order Digital Filter Instruction Register Command Register Data Output Register Offset Register Full-Scale Register SCLK SDIO SDOUT
AINN
Modulator Control
Serial Interface
ADS1211 Only
ADS1210/11
DSYNC
MODE
DRDY
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1996-2005, Texas Instruments Incorporated
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SPECIFICATIONS
specifications TMIN TMAX, AVDD DVDD +5V, fXIN 10MHz, programmable gain amplifier setting Turbo Mode Rate REFOUT disabled,VBIAS disabled, external 2.5V reference, unless otherwise specified. ADS1210U, P/ADS1211U, PARAMETER ANALOG INPUT Input Voltage Range(1) Input Impedance Programmable Gain Amplifier Input Capacitance Input Leakage Current SYSTEMS PERFORMANCE Resolution Missing Codes Integral Linearity fDATA Unipolar Offset Error(4) Unipolar Offset Drift(6) Gain Error(4) Gain Error Drift(6) Common-Mode Rejection(9) With VBIAS(2) Gain, Turbo Mode Rate User Programmable: +25°C TMIN TMAX CONDITIONS UNITS
4/(G TMR)(3)
Bits Bits %FSR %FSR µV/°C µV/°C
fDATA 60Hz fDATA 60Hz 1000Hz, ±0.0015 ±0.0015 Note Note
Normal-Mode Rejection Output Noise Power Supply Rejection VOLTAGE REFERENCE Internal Reference (REFOUT) Drift Noise Load Current Output Impedance External Reference (REFIN) Load Current VBIAS Output Drift Load Current DIGITAL INPUT/OUTPUT Logic Family Logic Level: (all except XIN) Input Levels: Frequency Range (fXIN) Output Data Rate (fDATA) Data Format SYSTEM CALIBRATION Offset Full-Scale Limits
+25°C TMIN TMAX 50Hz, fDATA 50Hz(7) 60Hz, fDATA 60Hz(7) 50Hz, fDATA 50Hz(7) 60Hz, fDATA 60Hz(7) 50Hz, 60Hz
Typical Performance Curves
Source Sink Using Internal Reference Source Sink Compatible CMOS +5µA +5µA Loads Loads -0.3 -0.3 0.12 Two's Complement Offset Binary REFIN)/G 3.15
3.45 10mA
ppm/°C µVp-p ppm/°C
DVDD +0.3 DVDD +0.3 15,625
User Programmable fXIN 500kHz User Programmable
Full-Scale Differential Voltage(8) Offset Differential Voltage(8)
REFIN)/G
ADS1210, ADS1211
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SBAS034B
SPECIFICATIONS
(CONT)
specifications TMIN TMAX, AVDD DVDD +5V, fXIN 10MHz, programmable gain amplifier setting Turbo Mode Rate REFOUT disabled,VBIAS disabled, external 2.5V reference, unless otherwise specified. ADS1210U, P/ADS1211U, PARAMETER POWER SUPPLY REQUIREMENTS Power Supply Voltage Power Supply Current: Analog Current Digital Current Additional Analog Current with REFOUT Enabled VBIAS Enabled Power Dissipation CONDITIONS 4.75 5.25 UNITS
Load fXIN 2.5MHz 2.5MHz, Sleep Mode
fXIN TEMPERATURE RANGE Specified Storage
+125
NOTES: order achieve converter's full-scale range, input must fully differential (AINN REFIN AINP). input single-ended (AINN AINP fixed), then full-scale range one-half that differential range. This range with external resistors VBIAS described text). Other ranges possible. Input impedance higher with lower fXIN. Applies after calibration. After system calibration, these errors will order effective resolution converter. Refer Typical Performance Curves which apply desired mode operation. Recalibration remove these errors. specification also applies fDATA where etc. Voltages analog inputs must remain within AGND AVDD. commonmode rejection test performed with 100mV differential input.
ABSOLUTE MAXIMUM RATINGS
Analog Input: Current ±100mA, Momentary ±10mA, Continuous Voltage AGND -0.3V AVDD +0.3V AVDD DVDD -0.3V AVDD AGND -0.3V DVDD DGND -0.3V AGND DGND ±0.3V REFIN Voltage AGND -0.3V AVDD +0.3V Digital Input Voltage DGND -0.3V DVDD +0.3V Digital Output Voltage DGND -0.3V DVDD +0.3V Lead Temperature (soldering, 10s) +300°C Power Dissipation (Any package) 500mW
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PACKAGE/ORDERING INFORMATION
most current package ordering information, Package Option Addendum located this data sheet.
ADS1210, ADS1211
SBAS034B
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ADS1210 SIMPLIFIED BLOCK DIAGRAM
AGND AVDD +2.5V Reference VBIAS +3.3V Bias Generator XOUT Clock Generator Micro Controller Second-Order Modulator Third-Order Digital Filter Instruction Register Command Register Data Output Register Offset Register Full-Scale Register Modulator Control Serial Interface DSYNC MODE DRDY SCLK SDIO SDOUT DGND DVDD
AINP AINN
ADS1210 CONFIGURATION
VIEW DIP/SOIC
ADS1210 DEFINITIONS
NAME AINP AINN AGND VBIAS DSYNC XOUT DGND DVDD SCLK SDIO SDOUT DRDY MODE AVDD REFOUT REFIN DESCRIPTION Noninverting Input. Inverting Input. Analog Ground. Bias Voltage Output, +3.3V nominal. Chip Select Input. Control Input Synchronize Serial Output Data. System Clock Input. System Clock Output (for Crystal Resonator). Digital Ground. Digital Supply, nominal. Clock Input/Output serial data transfer. Serial Data Input (can also function Serial Data Output). Serial Data Output. Data Ready. SCLK Control Input (Master Slave Analog Supply, nominal. Reference Output, +2.5V nominal. Reference Input.
AINP AINN AGND VBIAS DSYNC XOUT DGND
ADS1210
REFIN REFOUT AVDD MODE DRDY SDOUT SDIO
SCLK DVDD
ADS1210, ADS1211
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SBAS034B
ADS1211 SIMPLIFIED BLOCK DIAGRAM
AGND AVDD REFOUT +2.5V Reference REFIN VBIAS +3.3V Bias Generator XOUT Clock Generator Micro Controller Second-Order Modulator Third-Order Digital Filter Instruction Register Command Register Data Output Register Offset Register Full-Scale Register DRDY SCLK SDIO SDOUT DGND DVDD
AIN1P AIN1N AIN2P AIN2N AIN3P AIN3N AIN4P AIN4N
Modulator Control
Serial Interface DSYNC MODE
ADS1211P ADS1211U CONFIGURATION
VIEW DIP/SOIC
ADS1211P ADS1211U DEFINITIONS
NAME AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS DSYNC XOUT DGND DVDD SCLK SDIO SDOUT DRDY MODE AVDD REFOUT REFIN AIN4P AIN4N AIN3P DESCRIPTION Inverting Input Channel Noninverting Input Channel Inverting Input Channel Noninverting Input Channel Inverting Input Channel Analog Ground. Bias Voltage Output, +3.3V nominal. Chip Select Input. Control Input Synchronize Serial Output Data. System Clock Input. System Clock Output (for Crystal Resonator). Digital Ground. Digital Supply, nominal. Clock Input/Output serial data transfer. Serial Data Input (can also function Serial Data Output). Serial Data Output. Data Ready. SCLK Control Input (Master Slave Analog Supply, nominal. Reference Output: +2.5V nominal. Reference Input. Noninverting Input Channel Inverting Input Channel Noninverting Input Channel
AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS DSYNC
ADS1211P ADS1211U
AIN3P AIN4N AIN4P REFIN REFOUT AVDD MODE DRDY SDOUT SDIO SCLK DVDD
XOUT DGND
ADS1210, ADS1211
SBAS034B
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ADS1211E CONFIGURATION
VIEW SSOP
ADS1211E DEFINITIONS
NAME AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS DSYNC XOUT DGND DVDD SCLK SDIO SDOUT DRDY MODE AVDD REFOUT REFIN AIN4P AIN4N AIN3P DESCRIPTION Inverting Input Channel Noninverting Input Channel Inverting Input Channel Noninverting Input Channel Inverting Input Channel Analog Ground. Bias Voltage Output, +3.3V nominal. Internally Connected. Internally Connected. Chip Select Input. Control Input Synchronize Serial Output Data. System Clock Input. System Clock Output (for Crystal Resonator). Digital Ground. Digital Supply, nominal. Clock Input/Output serial data transfer. Serial Data Input (can also function Serial Data Output). Serial Data Output. Data Ready. Internally Connected. Internally Connected. SCLK Control Input (Master Slave Analog Supply, nominal. Reference Output: +2.5V nominal. Reference Input. Noninverting Input Channel Inverting Input Channel Noninverting Input Channel
AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS
ADS1211E
AIN3P AIN4N AIN4P REFIN REFOUT AVDD MODE DRDY SDOUT SDIO SCLK DVDD
DSYNC XOUT DGND
ADS1210, ADS1211
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SBAS034B
TYPICAL PERFORMANCE CURVES
+25°C, AVDD DVDD +5V, fXIN 10MHz, programmable gain amplifier setting Turbo Mode Rate one, REFOUT disabled, VBIAS disabled, external 2.5V reference, unless otherwise noted.
EFFECTIVE RESOLUTION DATA RATE (1MHz Clock)
EFFECTIVE RESOLUTION DATA RATE (2.5MHz Clock)
Effective Resolution Bits (rms)
Turbo Turbo Turbo Data Rate (Hz) Turbo
Effective Resolution Bits (rms)
Turbo
Turbo Turbo Data Rate (Hz) Turbo Turbo
Turbo
EFFECTIVE RESOLUTION DATA RATE (5MHz Clock)
EFFECTIVE RESOLUTION DATA RATE (10MHz Clock)
Effective Resolution Bits (rms)
Turbo Turbo Turbo Turbo Data Rate (Hz)
Effective Resolution Bits (rms)
Turbo
Turbo Data Rate (Hz) Turbo
Turbo
Turbo Turbo
EFFECTIVE RESOLUTION DATA RATE
Effective Resolution Bits (rms)
NOISE INPUT VOLTAGE LEVEL (60Hz Data Rate)
Noise (ppm)
Data Rate (Hz)
-5.0 -4.0 -3.0 -2.0 -1.0
Analog Input Differential Voltage
ADS1210, ADS1211
SBAS034B
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TYPICAL PERFORMANCE CURVES
(CONT)
+25°C, AVDD DVDD +5V, fXIN 10MHz, programmable gain amplifier setting Turbo Mode Rate REFOUT disabled, VBIAS disabled, external 2.5V reference, unless otherwise noted.
POWER DISSIPATION TURBO MODE RATE (REFOUT Enabled) 50.0 40.0
POWER DISSIPATION TURBO MODE RATE (External Reference; REFOUT)
Power Dissipation (mW)
40.0 10MHz 30.0 5MHz 2.5MHz 1MHz 20.0 Turbo Mode Rate
Power Dissipation (mW)
30.0 10MHz 5MHz 20.0 2.5MHz 1MHz 10.0 Turbo Mode Rate
PSRR FREQUENCY 85.0 120.0
CMRR FREQUENCY
80.0
CMRR (dB)
PSRR (dB)
75.0
115.0
70.0
65.0 Frequency (Hz) 100k
110.0 Frequency (Hz)
LINEARITY TEMPERATURE (60Hz Data Rate) -40°C -5°C +25°C +55°C +85°C
Integral Nonlinearity (ppm)
Analog Input Differential Voltage
ADS1210, ADS1211
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SBAS034B
THEORY OPERATION
ADS1210 ADS1211 precision, high dynamic range, self-calibrating, 24-bit, delta-sigma converters capable achieving very high resolution digital results. Each contains programmable gain amplifier (PGA); second-order delta-sigma modulator; programmable digital filter; microcontroller including Instruction, Command Calibration registers; serial interface; clock generator circuit; internal 2.5V reference. ADS1211 includes 4-channel input multiplexer. order provide system noise, common-mode rejection 115dB excellent power supply rejection, design topology based fully differential switched capacitor architecture. Turbo Mode, unique feature ADS1210/11, used boost sampling rate input capacitor, which normally 19.5kHz with 10MHz clock. programming Command Register, sampling rate increased 39kHz, 78kHz, 156kHz, 312kHz. Each increase sample rate results increase performance when maintaining same output data rate. programmable gain amplifier (PGA) ADS1210/ gain 16-substantially increasing dynamic range converter simplifying interface more common transducers (see Table This gain implemented increasing number samples taken input capacitor from 19.5kHz gain 312kHz gain Since Turbo Mode functions both implemented varying sampling frequency input capacitor, combination gain Turbo Mode Rate limited (see Table II). example, when using Turbo Mode Rate (156kHz 10MHz), maximum gain setting
ANALOG INPUT(1) FULLSCALE RANGE 1.25 0.625 EXAMPLE VOLTAGE RANGE(3) 1.25 1.88 2.19 2.34 3.75 3.13 2.81 2.66 ANALOG INPUT UTILIZING VBIAS(1,2) FULLSCALE RANGE EXAMPLE VOLTAGE RANGE(3) ±2.5 ±1.25 ±0.625
output data rate ADS1210/11 varied from hertz much 15,625kHz, trading lower resolution results higher data rates. addition, data rate determines first null digital filter sets -3dB point input bandwidth (see Digital Filter section). Changing data rate ADS1210/11 does result change sampling rate input capacitor. data rate effectively sets number samples which used digital filter obtain each conversion result. lower data rate results higher resolution, lower input bandwidth, different notch frequencies than higher data rate. does result change input impedance modulator frequency, appreciable change power consumption. ADS1210/11 also includes complete on-board calibration that correct internal offset gain errors limited external system errors. Internal calibration when needed, automatically continuously background. System calibration needed appropriate input voltages must provided ADS1210/ this reason, there continuous System Calibration Mode. calibration registers fully readable writable. This feature allows switching between various configurations-different data rates, Turbo Mode Rates, gain settings-without re-calibrating. various settings, rates, modes, registers ADS1210/11 read written synchronous serial interface. This interface operate either self-clocked mode (Master Mode) externally clocked mode (Slave Mode). Master Mode, serial clock (SCLK) frequency one-half ADS1210/11 clock frequency. This important consideration many systems determine maximum ADS1210/11 clock that used. high resolution flexibility ADS1210/11 allow these converters fill wide variety conversion tasks. order ensure that particular configuration will meet design goals, there several important items which must considered. These include (but certainly limited needed resolution, required linearity, desired input bandwidth, power consumption goal, sensor output voltage. remainder this data sheet discusses operation ADS1210/11 detail. order allow easier comparison different configurations, "effective resolution" used figure merit most tables graphs. example, Table shows comparison between data rate (and -3dB input bandwidth) versus setting Turbo Mode Rate clock rate 10MHz. Definition Terms section definition effective resolution.
GAIN SETTING
NOTE: With 2.5V reference, such internal reference. This example utilizes circuit Figure Other input ranges possible. ADS1210/11 allows common-mode voltage long absolute input voltage AINP AINN does below AGND above AVDD.
TABLE Full-Scale Range Setting.
TURBO MODE RATE AVAILABLE SETTINGS
TABLE Available Settings Turbo Mode Rate.
ADS1210, ADS1211
SBAS034B
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DATA RATE (HZ) 1000
-3DB FREQUENCY (HZ) 2.62 6.55 7.86 13.1 15.7 26.2 65.5
EFFECTIVE RESOLUTION (BITS RMS) 21.5 20.5 20.5 20.0 19.5 18.0 15.0 12.5 10.0 21.0 20.5 20.5 20.0 19.5 18.0 15.0 12.5 10.5 21.0 20.5 20.5 20.0 19.5 18.0 15.0 12.5 10.0 21.0 20.0 20.0 19.5 19.0 18.0 15.0 12.5 10.0 20.0 19.5 19.5 19.0 19.0 18.0 15.0 12.5 10.0
example, when converter configured with 2.5V reference placed gain setting typical input voltage range 1.25V 3.75V. However, input range 2.5V 2.5V would also cover converter's full-scale range. Voltage Span-This simply magnitude typical analog input voltage range. example, when converter configured with 2.5V reference placed gain setting input voltage span 2.5V. Least Significant (LSB) Weight-This theoretical amount voltage that differential voltage analog input would have change order observe change output data least significant bit. computed follows: Weight Full-Scale Range
TABLE III. Effective Resolution Data Rate Gain Setting. (Turbo Mode Rate 10MHz clock.) DEFINITION TERMS attempt been made consistent with terminology used this data sheet. that regard, definition each term given follows: Analog Input Differential Voltage-For analog signal that fully differential, voltage range compared that instrumentation amplifier. example, both analog inputs ADS1210 2.5V, then differential voltage other then differential voltage magnitude But, this case regardless which input which while digital output result quite different. analog input differential voltage given following equation: AINP AINN. Thus, positive digital output produced whenever analog input differential voltage positive, while negative digital output produced whenever differential negative. example, when converter configured with 2.5V reference placed gain setting positive fullscale output produced when analog input differential 2.5V. negative full-scale output produced when differential -2.5V. each case, actual input voltages must remain within AGND AVDD range (see Table Actual Analog Input Voltage-The voltage analog input relative AGND. Full-Scale Range (FSR)-As with most converters, full-scale range ADS1210/11 defined "input" which produces positive full-scale digital output minus "input" which produces negative full-scale digital output. example, when converter configured with 2.5V reference placed gain setting full-scale range [2.5V (positive full scale) minus -2.5V (negative full scale)] Typical Analog Input Voltage Range-This term describes actual voltage range analog inputs which will cover converter's full-scale range, assuming that each input common-mode voltage that greater than REFIN/PGA smaller than (AVDD REFIN/PGA).
where number bits digital output. Effective Resolution-The effective resolution ADS1210/11 particular configuration expressed different units: bits (referenced output) microvolts (referenced input). Computed directly from converter's output data, each statistical calculation based given number results. Knowing one, other computed follows:
Vrms bits
Vrms bits
figure each calculation represents full-scale range ADS1210/11 gain setting This means that both units absolute expressions resolution-the performance different configurations directly compared regardless units. Comparing resolution different gain settings expressed bits requires accounting setting. Main Controller-A generic term external microcontroller, microprocessor, digital signal processor which controlling operation ADS1210/11 receiving output data.
ADS1210, ADS1211
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SBAS034B
fXIN-The frequency crystal oscillator CMOS compatible input signal input ADS1210/11. fMOD-The frequency speed which modulator ADS1210/11 running, given following equation:
Gain (dB)
NORMALIZED DIGITAL FILTER RESPONSE -100 -120 -140 -160 Frequency (Hz)
Turbo Mode
fSAMP-The frequency switching speed input sampling capacitor. value given following equation: SAMP Turbo Mode Gain Setting
fDATA, tDATA-The frequency digital output data produced ADS1210/11 inverse this (the period), respectively, fDATA also referred data rate. DATA Turbo Mode DATA DATA Decimation Ratio
FIGURE Normalized Digital Filter Response.
FILTER RESPONSE
Gain (dB)
-100 -120 -140 -160 Frequency (Hz)
Gain (dB)
Conversion Cycle-The term "conversion cycle" usually refers discrete conversion operation, such that performed successive approximation converter. used here, conversion cycle refers tDATA time period. However, each digital output actually based modulator results from last three tDATA time periods. DIGITAL FILTER digital filter ADS1210/11 computes output result based most recent results from delta-sigma modulator. number modulator results that used depend decimation ratio Command Register. most basic level, digital filter thought simply averaging modulator results presenting this average digital output. While decimation ratio determines number modulator results use, modulator runs faster higher Turbo Modes. These items, together with ADS1210/11 clock frequency, determine output data rate: DATA Turbo Mode Decimation Ratio
FILTER RESPONSE -100 -120 -140 -160 Frequency (Hz)
FIGURE Digital Filter Response Data Rate 50Hz.
FILTER RESPONSE
Gain (dB)
-100 -120 -140 -160 Frequency (Hz)
FILTER RESPONSE
Gain (dB)
-100 -120 -140 -160 Frequency (Hz)
Also, since conversion result essentially average, data rate determines where resulting notches digital filter. example, output data rate 1kHz, then 1kHz input frequency will average zero during conversion cycle. Likewise, 2kHz input frequency will average zero, etc. this manner, data rate used specific notch frequencies digital filter response (see Figure normalized response digital filter). example, rejection power line frequencies desired, then data rate simply power line frequency. Figures show digital filter response data rate 50Hz 60Hz, respectively.
FIGURE Digital Filter Response Data Rate 60Hz. effective resolution 50Hz 60Hz data rate adequate particular application, then power line frequencies could still rejected operating ADS1210/11 25/30Hz, 16.7/20Hz, 12.5/15Hz, etc. higher data rate needed, then power line frequencies must either rejected before conversion (with analog notch filter) after conversion (with digital notch filter running main controller).
ADS1210, ADS1211
SBAS034B
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Filter Equation digital filter described following transfer function:
where Decimation Ratio.
effective resolution output data given data rate, there also increase power dissipation. Turbo Mode Rates increase slight. rates increase more substantial. Typical Performance Curves more information. Turbo Mode Rate ADS1210/11 offer bits effective resolution 1kHz data rate. comparison effective resolution versus Turbo Mode Rates output data rates shown Table while Table shows corresponding noise level µVrms.
EFFECTIVE RESOLUTION (BITS RMS) DATA RATE (HZ) 1000 TURBO MODE RATE 21.5 21.0 20.0 20.0 19.5 18.0 10.0 TURBO MODE RATE 22.0 22.0 21.5 21.5 21.0 20.0 12.5 TURBO MODE RATE 22.5 22.0 22.0 21.5 21.5 21.0 15.0 TURBO MODE RATE 22.5 22.5 22.0 22.0 21.5 17.5 TURBO MODE RATE
This filter (sin(x)/x)3 response referred sinc3 filter. ADS1210/11, this type filter allows data rate changed over very wide range (nearly four orders magnitude). However, -3dB point filter 0.262 times data rate. And, seen Figures rejection stopband (frequencies higher than first notch frequency) only -40dB. These factors must considered overall system design. example, with 50Hz data rate, significant signal 75Hz alias back into passband 25Hz. analog front designed provide needed attenuation prevent aliasing, system simply provide this inherently. Another possibility increasing data rate then post filtering with digital filter main controller. Filter Settling number modulator results used compute each conversion result three times Decimation Ratio. This means that step change channel change ADS1211) will require least three conversions fully settle. However, change occurs asynchronously, then least four conversions required ensure complete settling. example, ADS1211, fourth conversion result after channel change will valid (see Figure
Significant Analog Input Change ADS1211 Channel Change Data Valid Data Valid Data Valid
23.0 23.0 23.0 22.5 20.0
TABLE Effective Resolution Data Rate Turbo Mode Rate. (Gain setting 10MHz clock.)
NOISE LEVEL (µVrms) DATA RATE (Hz) 1000 TURBO MODE RATE 10.5 26.9 6909.7 TURBO MODE RATE 1354.5 TURBO MODE RATE 238.4 TURBO MODE RATE 46.6 TURBO MODE RATE
TABLE Noise Level Data Rate Turbo Mode Rate. (Gain setting 10MHz clock.) Turbo Mode feature allows trade-offs made between ADS1210/11 clock frequency, power dissipation, effective resolution. 5MHz clock available 10MHz clock needed achieve desired performance, Turbo Mode Rate will result same effective resolution. Table provides comparison effective resolution various clock frequencies, data rates, Turbo Mode Rates.
DATA RATE (Hz) CLOCK FREQUENCY (MHz) 1.25 0.625 1.25 0.625 TURBO MODE RATE EFFECTIVE RESOLUTION (Bits rms) 19.5 19.5 19.5 19.5 19.5 18.0 18.0 18.0 18.0 18.0
Valid Data DRDY
Valid Data
Valid Data
Valid Data
Serial tDATA
FIGURE Asynchronous ADS1210/11 Analog Input Voltage Step ADS1211 Channel Change Fully Settled Output Data. TURBO MODE ADS1210/11 offers unique Turbo Mode feature which used increase modulator sampling rate times normal. With increase modulator sampling frequency, there substantial increase
TABLE Effective Resolution Data Rate, Clock Frequency, Turbo Mode Rate. (Gain setting
ADS1210, ADS1211
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SBAS034B
Turbo Mode Rate (TMR) programmed Sampling Frequency bits Command Register. increase input capacitor sampling frequency, higher Turbo Mode settings result lower analog input impedance; Impedance where gain setting. Because modulator rate also changes direct relation Turbo Mode setting, higher values result lower impedance REFIN input: REFIN Impedance Turbo Mode Rate Consult graphs shown Typical Performance Curves full details performance ADS1210/11 operating different Turbo Mode Rates. Keep mind that higher Turbo Mode Rates result fewer available gain settings shown Table PROGRAMMABLE GAIN AMPLIFIER programmable gain amplifier gain setting programmed Gain bits Command Register. Changes gain setting programmable gain amplifier results increase input capacitor sampling frequency. Thus, higher gain settings result lower analog input impedance: Impedance where Turbo Mode Rate. Because modulator speed does depend gain setting, input impedance seen REFIN does change. gains These gain settings with their resulting full-scale range typical voltage range shown Table Keep mind that higher Turbo Mode Rates result fewer available gain settings shown Table SOFTWARE GAIN excellent performance, flexibility, cost ADS1210/11 allow converter considered designs which would normally need 24-bit ADC. example, many designs utilize 12-bit converter highgain digitizing amplitude signals. some these cases, ADS1210/11 itself solution, even though maximum gain limited around gain limitation, digital result simply shifted bits main controller- resulting gain times where gain setting. While this type manipulation output data obvious, easy miss much gain increased this manner 24-bit converter. example, shifting result three bits when ADS1210/11 gain results effective gain 128. lower data rates, converter easily provide more than bits resolution. Even higher gains possible. limitation combination needed data rate, desired noise performance, desired linearity.
CALIBRATION ADS1210/11 offers several different types calibration, particular calibration desired programmed Command Register. case Background Calibration, calibration will repeat regular intervals indefinitely. others, calibration performed once then normal operation resumed. Each type calibration covered detail respective section. general, calibration recommended immediately after power-on whenever there "significant" change operating environment. amount change which should cause re-calibration dependent application, effective resolution, etc. Where high accuracy important, re-calibration should done changes temperature power supply. cases, re-calibration should done when gain, Turbo Mode, data rate changed. After calibration been accomplished, Offset Calibration Register Full-Scale Calibration Register contain results calibration. data these registers accurate effective resolution ADS1210/11's mode operation during calibration. Thus, these values will show variation noise) equivalent regular conversion result. those cases where this error must reduced, tempting consider running calibration slower data rate then increasing converter's data rate after calibration complete. Unfortunately, this will work expected. reason that results calculated slower data rate would valid higher data rate. Instead, calibration should done repeatedly. After each calibration, results read stored. After desired number calibrations, main controller compute average write this value into calibration registers. resulting error calibration values will reduced square root number calibrations which were averaged. calibration registers also used provide system offset gain corrections separate from those computed ADS1210/11. example, these might burned into E2PROM during final product testing. power-on, main controller would load these values into calibration registers. further possibility look-up table based current temperature. Note that values calibration registers will vary from configuration configuration from part part. There method reliably computing what particular calibration register should correct given amount system error. possible present ADS1210/11 with known amount error, perform calibration, read desired calibration register, change error value, perform another calibration, read value these values interpolate intermediate value.
ADS1210, ADS1211
SBAS034B
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Normal Mode Valid Data DRDY SC(1) Serial tDATA Valid Data Offset Calibration Internal Offset(2)
Self-Calibration Mode Full-Scale Calibration Internal Full-Scale Analog Input Conversion
Normal Mode Valid Data Valid Data
NOTES: Self-Calibration instruction. Slave Mode, this function requires cycles.
FIGURE Self-Calibration Timing. Self-Calibration self-calibration performed after bits have been written Command Register Operation Mode bits (MD2 through MD0). This initiates following sequence start next conversion cycle (see Figure DRDY signal will will remain HIGH will continue remain HIGH throughout calibration sequence. inputs sampling capacitor disconnected from converter's analog inputs shorted together. offset calibration performed over next three conversion periods (four Slave Mode). Then, input sampling capacitor connected across REFIN, full-scale calibration performed over next three conversions. After this, Operation Mode bits reset (normal mode) input capacitor reconnected input. Conversions proceed usual over next three cycles order fill digital filter. DRDY remains HIGH during this time. start fourth cycle, DRDY goes indicating valid data resumption normal operation. System Offset Calibration system offset calibration performed after bits have been written Command Register Operation Mode bits (MD2 through MD0). This initiates following sequence (see Figure start next conversion cycle, DRDY signal will will remain HIGH will continue remain HIGH throughout calibration sequence. offset calibration will performed differential input voltage present converter's input over next three conversion periods (four Slave Mode). When this done, Operation Mode bits reset (Normal Mode). single conversion done with DRDY HIGH. After this conversion, DRDY signal goes indicating resumption normal operation. Normal operation returns within single conversion cycle because assumed that input voltage converter's input removed immediately after offset calibration performed. this case, digital filter already contains valid result. full system calibration, offset calibration must performed first then full-scale calibration. addition, offset calibration error will conversion error noise system offset voltage. System Calibration Limits section information regarding limits magnitude system offset voltage. System Full-Scale Calibration system full-scale calibration performed after bits have been written Command Register Operation Mode bits (MD2 through MD0). This initiates following sequence (see Figure start next conversion cycle, DRDY signal will will remain HIGH will continue remain HIGH throughout calibration sequence. full-scale calibration will performed differential input voltage REFIN/G) present converter's input over next three conversion periods (four Slave Mode). When this done, Operation Mode bits reset (Normal Mode). single conversion done with DRDY HIGH. After this conversion, DRDY signal goes indicating resumption normal operation.
Normal Mode Valid Data DRDY SOC(1) Serial tDATA Valid Data
System Offset Calibration Mode Offset Calibration System Offset(2)
Normal Mode Analog Possibly Valid Input Conversion Data Possibly Valid Data
Normal Mode Valid Data DRDY SFSC(1) Serial tDATA Valid Data
System Full-Scale Calibration Mode Full-Scale Calibration System Full-Scale(2)
Normal Mode Analog Possibly Valid Input Conversion Data Possibly Valid Data
NOTES: System Offset Calibration instruction. Slave Mode, this function requires cycles.
NOTES: SFSC System Full-Scale Calibration instruction. Slave Mode, this function requires cycles.
FIGURE System Offset Calibration Timing.
FIGURE System Full-Scale Calibration Timing.
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Normal operation returns within single conversion cycle because assumed that input voltage converter's input removed immediately after full-scale calibration performed. this case, digital filter already contains valid result. full system calibration, offset calibration must performed first then full-scale calibration. calibration error will noise conversion result input signal noise. System Calibration Limits section information regarding limits magnitude system full-scale voltage. Pseudo System Calibration Pseudo System Calibration performed after bits have been written Command Register Operation Mode bits (MD2 through MD0). This initiates following sequence (see Figure start next conversion cycle, DRDY signal will will remain HIGH will continue remain HIGH throughout calibration sequence. offset calibration will performed differential input voltage present converter's input over next three conversion periods (four Slave Mode). Then, input sampling capacitor disconnected from converter's analog input connected across REFIN. gain calibration performed over next three conversions. After this, Operation Mode bits reset (normal mode) input capacitor then reconnected
input. Conversions proceed usual over next three cycles order fill digital filter. DRDY remains HIGH during this time. next cycle, DRDY signal goes indicating valid data resumption normal operation. system offset calibration range ADS1210/11 limited listed Specifications Table. more information these specifications, System Calibration Limits section. calculate VOS, REFIN GAIN VFS. Background Calibration Background Calibration Mode entered after bits have been written Command Register Operation Mode bits (MD2 through MD0). This initiates following continuous sequence (see Figure start next conversion cycle, DRDY signal will will remain HIGH. inputs sampling capacitor disconnected from converter's analog input shorted together. offset calibration performed over next three conversion periods Slave Mode, very first offset calibration requires four periods subsequent offset calibrations require three periods). Then, input capacitor reconnected input. Conversions proceed usual over next three cycles order fill digital filter. DRDY remains HIGH during this time. next cycle, DRDY signal goes indicating valid data.
Normal Mode Valid Data DRDY PSC(1) Serial tDATA Valid Data Offset Calibration System Offset(2)
Pseudo System Calibration Mode Full-Scale Calibration Internal Full-Scale Analog Input Conversion
Normal Mode Valid Data Valid Data
NOTES: Pseudo System Calibration instruction. Slave Mode, this function requires cycles.
FIGURE Pseudo System Calibration Timing.
Normal Mode Valid Data DRDY BC(1) Serial tDATA Valid Data
Background Calibration Mode Offset Calibration Internal Offset(2) Analog Input Conversion Full-Scale Calibration Internal Full-Scale Analog Input Conversion Cycle Repeats with Offset Calibration
NOTES: Background Calibration instruction. Slave Mode, very first offset calibration will require cycles. subsequent offset calibrations will require cycles.
FIGURE Background Calibration Timing.
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Also, during this cycle, sampling capacitor disconnected from converter's analog input connected across REFIN. gain calibration initiated proceeds over next three conversions. After this, input capacitor once again connected analog input. Conversions proceed usual over next three cycles order fill digital filter. DRDY remains HIGH during this time. next cycle, DRDY signal goes indicating valid data, input sampling capacitor shorted, offset calibration initiated. this point, Background Calibration sequence repeats. essence, Background Calibration Mode performs continuous self-calibration where offset gain calibrations interleaved with regular conversions. Thus, data rate reduced factor advantage that converter continuously adjusting environmental changes such ambient component temperature (due airflow variations). ADS1210/11 will remain Background Calibration Mode indefinitely. move other mode, Command Register Operation Mode bits (MD2 through MD0) must appropriate values. System Calibration Offset Full-Scale Calibration Limits System Offset Full-Scale Calibration range ADS1210/11 limited listed Specifications Table. range specified (VFS REFIN)/GAIN (VFS REFIN)/GAIN where system full-scale voltage absolute value system offset voltage. following discussion, keep mind that these voltages differential voltages. example, with internal reference (2.5V) gain two, previous equations become (after some manipulation): 3.25 1.75 perfect 2.5V (positive full-scale), then must greater than -0.75V less than 0.75V. Thus, when offset calibration performed, positive input more than 0.75V below above negative input. this range exceeded, ADS1210/11 calibrate properly. This calculation method works gains other than one. gain internal reference (2.5V), equation becomes: With positive full-scale input, must greater than -1.5V less than 1.5V. Since offset represents common-mode voltage input voltage range gain common-mode voltage will cause actual input voltage possibly below above specifications also show that specifications valid, input voltage must below AGND more than 30mV above AVDD more than 30mV.
This will important consideration many systems which 2.5V greater reference, input range constrained expected power supply variations. addition, expected full-scale voltage will impact allowable offset voltage (and vice-versa) combination must remain within power supply ground potentials, regardless results obtained range calculation shown previously. There only solutions this constraint: either system design must ensure that full-scale offset voltage variations will remain within power supply ground potentials, part must used gain greater. SLEEP MODE Sleep Mode entered after bits have been written Command Register Operation Mode bits (MD2 through MD0). This mode exited entering mode into MD2-MD0 bits. Sleep Mode causes analog section good deal digital section power down. full analog power down, VBIAS generator internal reference must also powered down setting BIAS REFO bits Command Register accordingly. power dissipation shown Specifications Table with internal reference VBIAS generator disabled. initiate serial communication with converter while Sleep Mode, following procedures must used: being used, simply taking will enable serial communication proceed normally. being used (tied LOW) ADS1210/11 Master Mode, then falling edge must produced SDIO line. SDIO LOW, SDIO line must taken HIGH tXIN periods (minimum) then taken LOW. Alternatively, SDIO forced HIGH after putting ADS1210/11 "sleep" then taken when Sleep Mode exited. Finally, being used (tied LOW) ADS1210/11 Slave Mode, then simply sending normal Instruction Register command will re-establish communication. Once serial communication resumed, Sleep Mode exited changing MD2-MD0 bits other mode. When mode (other than Sleep) been entered, ADS1210/11 will execute very brief internal power-up sequence analog digital circuitry. Once this been done, normal conversion cycle performed before mode actually entered. this conversion cycle, mode takes effect converter will respond accordingly. DRDY signal will remain HIGH through first conversion cycle. will also remain HIGH through second, even mode Normal Mode. VBIAS generator and/or internal reference have been disabled, then they must manually re-enabled appropriate bits Command Register. addition, internal reference will have charge external bypass capacitor(s) possibly other circuitry. There also
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considerations associated with VBIAS settling external circuitry. these must taken into account when determining amount time required resume normal operation. timing diagram shown Figure does take into account settling external circuitry.
Sleep Mode
Change Normal Mode Occurs Here (Other Normal Modes Conversion Start Here) Data Valid Valid Data(1) Valid Data(1)
DRDY Serial tDATA NOTE: Assuming that external circuitry been stable previous three tDATA periods.
FIGURE Sleep Mode Normal Mode Timing.
ANALOG OPERATION
ANALOG INPUT input impedance analog input changes with ADS1210/11 clock frequency (fXIN), gain (G), Turbo Mode Rate (TMR). relationship Impedance Figure shows basic input structure ADS1210. ADS1211 includes input multiplexer, this little impact analysis input structure. impedance directly related sampling frequency input capacitor. clock rate sets basic sampling rate gain Turbo Mode Rate Higher gains higher Turbo Mode Rates result increase sampling rate, while slower clock (XIN) frequencies result decrease.
analog signal must reside within this range, linearity ADS1210/11 only ensured when actual analog input voltage resides within range defined AGND 30mV AVDD +30mV. This leakage paths which occur within part when AGND AVDD exceeded. this reason, input range (gain with 2.5V reference) must used with caution. Should AVDD 4.75V, analog input signal would swing outside tested specifications device. Designs utilizing this mode operation should consider limiting span slightly smaller range. Common-mode voltages also significant concern this mode must carefully analyzed. input voltage range 0.75V 4.25V smallest span that allowed full system calibration will performed (see Calibration section more details). This also assumes offset error zero. better choice would 0.5V 4.5V full-scale range 9V). This span would allow some offset error, gain error, power supply drift, common-mode voltage while still providing full system calibration over reasonable variation each these parameters. actual input voltage exceeding AGND AVDD should concern higher gain settings input voltage range will reside well within This true unless common-mode voltage large enough place positive fullscale negative full-scale outside AGND AVDD range. REFERENCE INPUT input impedance REFIN input changes with clock frequency (fXIN) Turbo Mode Rate (TMR). relationship REFIN Impedance Unlike analog input, reference input impedance negligible dependency gain setting. reference input voltage vary between nominal voltage 2.5V appears REFOUT, this directly connected REFIN. Higher reference voltages will cause full-scale range increase while internal circuit noise converter remains approximately same. This will increase weight internal noise, resulting increased signal-to-noise ratio effective resolution. Likewise, lower reference voltages will decrease signal-to-noise ratio effective resolution. REFERENCE OUTPUT ADS1210/11 contains internal +2.5V reference. Tolerances, drift, noise, other specifications this reference given Specification Table. Note that designed sink source more than current. addition, loading reference with dynamic variable load recommended. This result small changes reference voltage load changes. Finally, designs approaching exceeding bits effective resolution, low-noise external reference recommended internal reference provide adequate performance.
typical)
High Impedance CINT Typical
Switching Frequency fSAMP
FIGURE Analog Input Structure. This input impedance become major point consideration some designs. source impedance input signal significant there passive filtering prior ADS1210/11, then significant portion signal lost across this external impedance. significant this effect depends desired system performance. There restrictions analog input signal ADS1210/11. Under conditions should current into analog inputs exceed 10mA. addition, while
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±10V ±10V AINP AINN AGND VBIAS DVDD 12pF REFIN REFOUT AVDD MODE ADS1210 DRDY DGND DSYNC XTAL 12pF DGND XOUT DGND SDOUT SDIO SCLK DVDD DVDD AVDD AGND 1.0µF
DGND
FIGURE ±10V Input Configuration Using VBIAS. circuitry which generates +2.5V reference disabled Command Register will result lower power dissipation. reference circuitry consumes little over 1.6mA current with external load. When ADS1210/11 default state, internal reference enabled. VBIAS VBIAS output voltage dependent reference input (REFIN) voltage approximately 1.33 times great. This output used bias input signals such that bipolar signals with spans greater than scaled match input range ADS1210/11. Figure shows connection diagram which will allow ADS1210/11 accept ±10V input signal (40V full-scale range). This method scaling offsetting ±20V differential input signal will concern those requiring minimum power dissipation. VBIAS will supply 1.68mA every channel connected shown. ADS1211, current draw within specifications VBIAS, but, 12mW, power dissipation significant. this concern, resistors This will reduce power dissipation one-third. addition, these resistors also values which will provide arbitrary input range. cases, maximum current into VBIAS should exceed specification 10mA. Note that connection diagram shown Figure causes constant amount current sourced VBIAS. This will very important higher resolution designs voltage VBIAS will change with loading, load constant. However, input signal single-ended side input grounded, load will constant VBIAS will change slightly with input signal. Also, cases, note that noise VBIAS introduces common-mode error signal which rejected converter. resistors should used part anti-alias filter with capacitor across inputs. ADS1210 samples charge from capacitor which effect introducing offset measurement. This might acceptable relative differential measurements. circuitry generate VBIAS disabled when ADS1210/11 default state, must enabled, Command Register, order VBIAS voltage present. When enabled, VBIAS circuitry consumes approximately with external load. power-up, external signals present before VBIAS enabled. This create situation which negative voltage applied analog inputs (-2.5V circuit shown Figure 12), reverse biasing negative input protection diode. This situation should problem long resistors limit current being sourced each analog input under 10mA potential analog input should used calculation).
DIGITAL OPERATION
SYSTEM CONFIGURATION Micro Controller (MC) consists register bank. states: power-on reset convert. power-on reset state, resets registers their default state, sets modulator stable state, performs self-calibration 850Hz data rate. After this, enters convert mode, which normal mode operation ADS1210/11. ADS1210/11 internal registers, shown Table VII. these, Instruction Register Command Register, control operation converter. Data Output Register (DOR) contains result from most recent conversion. Offset Full-Scale Calibration Registers (OCR FCR) contain data used correcting internal conversion result before placed into DOR. data these registers result calibration routine, they values which have been written directly serial interface.
INSR Instruction Register Data Output Register Command Register Offset Calibration Register Full-Scale Calibration Register Bits Bits Bits Bits Bits
TABLE VII. ADS1210/11 Registers. Communication with ADS1210/11 controlled Instruction Register (INSR). Under normal operation, INSR written first part each serial communication. instruction that sent determines what type communication will occur next. possible read INSR.
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Command Register (CMR) controls ADS1210/ 11's options operating modes. These include gain setting, Turbo Mode Rate, output data rate (decimation ratio), etc. only 32-bit register within ADS1210/11. remaining registers, read from written Instruction Register (INSR) INSR 8-bit register which commands serial interface either read write bytes beginning specified register location. Table VIII shows format INSR.
Each serial communication starts with 8-bits INSR being sent ADS1210/11. This directs remainder communication cycle, which consists bytes being read from written ADS1210/11. read/write bit, number bytes starting register address defined, shown Table VIII. When bytes have been transferred, INSR complete. communication cycle initiated sending INSR (under restrictions outlined Interfacing section). Command Register (CMR) controls functionality ADS1210/ configuration takes effect negative transition SCLK last each byte data being written command register. organization shown Table
Most Significant Byte DSYNC(1) BIAS REFO DRDY Defaults
TABLE VIII. Instruction Register. (Read/Write) Bit-For write operation occur, this INSR must read, this must follows:
Write Read
Two's Biplr MSByte SDIO
NOTE: DSYNC Write only, DRDY Read only. Byte Gain Byte DR12 DR11 DR10 00000 Byte Least Significant Defaults Defaults Defaults
Normal Mode
Channel
MB1, (Multiple Bytes) Bits-These bits used control word length (number bytes) read write operation, follows:
Byte Bytes Bytes Bytes
Turbo Mode Rate
(00000) 0001 0110 (22) Data Rate 849Hz
A3-A0 (Address) Bits-These four bits select beginning register location which will read from written shown Table Each subsequent byte will read from written next higher location. Command Register set, each subsequent byte will read from next lower location. This does affect write operation.) next location defined Table then results unknown. Reading writing continues until number bytes specified have been transferred.
REGISTER BYTE Data Output Register Byte (MSB) Data Output Register Byte Data Output Register Byte (LSB) Command Register Byte (MSB) Command Register Byte Command Register Byte Command Register Byte (LSB) Offset Register Byte (MSB) Offset Register Byte Offset Register Byte (LSB) Full-Scale Register Byte (MSB) Full-Scale Register Byte Full-Scale Register Byte (LSB)
TABLE Organization Command Register Default Status. BIAS (Bias Voltage) Bit-The BIAS controls VBIAS output state-either (1.33 REFIN) (disabled), follows:
BIAS VBIAS GENERATOR VBIAS STATUS Disabled Default
VBIAS circuitry consumes approximately steady state current with external load. VBIAS section full details. When internal reference (REFOUT) connected reference input (REFIN), VBIAS 3.3V, nominal. REFO (Reference Output) Bit-The REFO controls internal reference (REFOUT) state, either (2.5V) (disabled), follows:
REFO INTERNAL REFERENCE REFOUT STATUS High Impedance 2.5V Default
Note: Most Significant Byte, Least Significant Byte
TABLE A3-A0 Addressing.
internal reference circuitry consumes approximately 1.6mA steady state current with external load. Reference Output section full details internal reference.
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(Data Format) Bit-The controls format output data, either Two's Complement Offset Binary, follows:
FORMAT Two's Complement Offset Binary ANALOG INPUT +Full-Scale Zero -Full-Scale +Full-Scale Zero -Full-scale DIGITAL OUTPUT 7FFFFFH 000000H 800000H FFFFFFH 800000H 000000H Default
(Serial Data Line) Bit-The controls which ADS1210/11 will used serial data output pin, either SDIO SDOUT, follows:
SERIAL DATA OUTPUT SDIO SDOUT Default
These formats same bits except most significant, which simply inverted format other. This only applies Data Output Register-it effect other registers. (Unipolar) Bit-The controls limits imposed output data, follows:
MODE Bipolar Unipolar LIMITS None Zero +Full-Scale only Default
LOW, then SDIO will used both input output serial data-see Timing section more details SDIO transitions between these states. addition, SDOUT will remain tri-state condition times. Important Note: Since default condition LOW, SDIO potential becoming output once every data output cycle ADS1210/11 Master Mode. This will occur until Command Register written HIGH. Interfacing section more information. DRDY (Data Ready) Bit-The DRDY read-only which reflects state ADS1210/11's DRDY output pin, follows:
DRDY MEANING Data Ready Data Ready
particular mode effect actual full-scale range ADS1210/11, data format, data format input voltage. bipolar mode, ADS1210/11 operates normally. unipolar mode, conversion result limited positive values only (zero included). This only controls what placed Data Output Register. effect internal data. When cleared, very next conversion will produce valid bipolar result. (Byte Order) Bit-The controls order which bytes data read, either most significant byte first least significant byte, follows:
BYTE ACCESS ORDER Most Significant Least Significant Byte Least Significant Most Significant Byte Default
DSYNC (Data Synchronization) Bit-The DSYNC write-only which occupies same location DRDY. When `one' written this location, effect ADS1210/11 same DSYNC input been taken returned HIGH. That modulator count current conversion cycle will reset zero.
DSYNC MEANING Change Modulator Count Modulator Count Reset Zero
Note that when clear multi-byte read initiated, A3-A0 Instruction Register address most significant byte subsequent bytes reside higher addresses. set, then A3-A0 address least significant byte subsequent bytes reside lower addresses. only affects read operations; effect write operations. (Bit Order) Bit-The controls order which bits within byte data read, either most significant first least significant bit, follows:
ORDER Most Significant First Least Significant First Default
DSYNC provided order reduce number interface signals that needed between ADS1210/11 main controller. Consult "Making DSYNC" Serial Interface section more information. MD2-MD0 (Operating Mode) Bits-The MD2-MD0 bits initiate enable various calibration sequences, follows:
OPERATING MODE Normal Mode Self-Calibration System Offset Calibration System Full-Scale Calibration Pseudo System Calibration Background Calibration Sleep Reserved
only affects read operations; effect write operations.
Normal Mode, Background Calibration Mode, Sleep Mode permanent modes ADS1210/11 will remain these modes indefinitely. other modes temporary will revert Normal Mode once appropriate actions complete. Calibration Sleep Mode sections more information.
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DATA RATE (HZ) 1000
DECIMATION RATIO 1952
DR12
DR11
DR10
Table Decimation Ratios Data Rates (Turbo Mode rate 10MHz clock). G2-G0 (PGA Control) Bits-The G2-G0 bits control gain setting PGA, follows:
GAIN SETTING AVAILABLE TURBO MODE RATES Default
input capacitor sampling frequency modulator rate calculated from following equations: fSAMP fXIN fMOD fXIN where gain setting Turbo Mode Rate. sampling frequency input capacitor directly relates analog input impedance. modulator rate relates power consumption ADS1210/11 output data rate. Turbo Mode, Analog Input, Reference Input sections more details. DR12-DR0 (Decimation Ratio) Bits-The DR12-DR0 bits control decimation ratio ADS1210/11. essence, these bits number modulator results which used digital filter compute each individual conversion result. Since modulator rate depends both ADS1210/11 clock frequency Turbo Mode Rate, actual output data rate given following equation: fDATA fXIN (512 (Decimation Ratio where Turbo Mode Rate. Table shows various data rates corresponding decimation ratios (with 10MHz clock). Valid decimation ratios from 8000. Outside this range, digital filter will compute results incorrectly inadequate much data. Data Output Register (DOR) 24-bit register which contains most recent conversion result (see Table XII). This register updated with result just prior DRDY going LOW. contents read within period time defined 1/fDATA then conversion result will overwrite old. (DRDY forced HIGH prior update, unless read progress).
Most Significant DOR23 DOR22 DOR21 Byte DOR20 DOR19 DOR18 DOR17 DOR16
gain partially implemented increasing input capacitor sampling frequency, which given following equation: fSAMP fXIN where gain setting Turbo Mode Rate. product cannot exceed sampling frequency input capacitor directly relates analog input impedance. Programmable Gain Amplifier Analog Input sections more details. CH1-CH0 (Channel Selection) Bits-The bits control input multiplexer ADS1211, follows:
ACTIVE INPUT Channel Channel Channel Channel Default
(For ADS1210, must always zero.) channel change takes effect when last byte been written Command Register. Output data will valid next three conversions despite DRDY signal indicating that data ready. fourth time that DRDY goes after channel change been written Command Register, valid data will present Data Output Register (see Figure SF2-SF0 (Turbo Mode Rate) Bits-The SF2-SF0 bits control input capacitor sampling frequency modulator rate, follows:
TURBO MODE RATE AVAILABLE SETTINGS Default
Byte DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR9 DOR8
Byte DOR7 DOR6 DOR5 DOR4 DOR3
Least Significant DOR2 DOR1 DOR0
TABLE XII. Data Output Register. contents Two's Complement Offset Binary format. This controlled Command Register. addition, contents limited unipolar data only with Command Register.
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Offset Calibration Register (OCR) 24-bit register which contains offset correction factor that applied conversion result before placed Data Output Register (see Table XIII). most applications, contents this register will result either self-calibration system calibration. both readable writeable serial interface. applications requiring more accurate offset calibration, multiple calibrations performed, each resulting value read, results averaged, more precise offset calibration value written back OCR. actual value will change from part-to-part with configuration, temperature, power supply. Thus, actual value arbitrary situation cannot accurately predicted. That given system offset could corrected simply measuring error externally, computing correction factor, writing that value OCR. addition, aware that contents used directly correct conversion result. Rather, correction function value. This function linear known points used basis interpolating intermediate values OCR. Consult Calibration section more details.
Most Significant OCR23 OCR22 OCR21 Byte OCR20 OCR19 OCR18 OCR17 OCR16
actual value will change from part-to-part with configuration, temperature, power supply. Thus, actual value arbitrary situation cannot accurately predicted. That given system full-scale error cannot corrected simply measuring error externally, computing correction factor, writing that value FCR. addition, aware that contents used directly correct conversion result. Rather, correction function value. This function linear known points used basis interpolating intermediate values FCR. Consult Calibration section more details. contents unsigned binary format. This affected Command Register. TIMING Table Figures through define basic digital timing characteristics ADS1210/11. Figure associated timing symbols apply input signal. Figures through associated timing symbols apply serial interface signals (SCLK, SDIO, SDOUT, their relationship DRDY. serial interface discussed detail Serial Interface section. Figure associated timing symbols apply maximum DRDY rise fall times.
tXIN
Byte OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR9 OCR8
Byte OCR7 OCR6 OCR5 OCR4 OCR3
Least Significant OCR2 OCR1 OCR0
TABLE XIII. Offset Calibration Register. contents Two's Complement format. This affected Command Register. Full-Scale Calibration Register (FCR) 24-bit register which contains full-scale correction factor that applied conversion result before placed Data Output Register (see Table XIV). most applications, contents this register will result either self-calibration system calibration.
Most Significant FSR23 FSR22 FSR21 Byte FSR20 Byte FSR15 FSR14 FSR13 FSR12 Byte FSR7 FSR6 FSR5 FSR4 FSR3 FSR11 FSR10 FSR9 FSR8 FSR19 FSR18 FSR17 FSR16
FIGURE Clock Timing.
SCLK (Internal) SDIO input) SDOUT SDlO output)
FIGURE Serial Input/Output Timing, Master Mode.
Least Significant FSR2 FSR1 FSR0
SCLK (External) SDIO input) SDOUT SDlO output)
TABLE XIV. Full-Scale Calibration Register. both readable writable serial interface. applications requiring more accurate full-scale calibration, multiple calibrations performed, each resulting value read, results averaged, more precise calibration value written back FCR.
FIGURE Serial Input/Output Timing, Slave Mode.
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SYMBOL fXIN tXIN
DESCRIPTION Clock Frequency Clock Period Clock High Clock Internal Serial Clock HIGH Internal Serial Clock Data Valid Internal SCLK Falling Edge (Setup) Internal SCLK Falling Edge Data Valid (Hold) Data Valid Internal SCLK Falling Edge (Setup) Internal SCLK Falling Edge Data Valid (Hold) External Serial Clock HIGH External Serial Clock Data Valid External SCLK Falling Edge (Setup) External SCLK Falling Edge Data Valid (Hold) Data Valid External SCLK Falling Edge (Setup) External SCLK Falling Edge Data Valid (Hold) Falling Edge DRDY First SCLK Rising Edge (Master Mode, Tied LOW) Falling Edge Last SCLK INSR Rising Edge First SCLK Register Data (Master Mode) Falling Edge Last SCLK Register Data Rising Edge DRDY (Master Mode) Falling Edge Last SCLK INSR Rising Edge First SCLK Register Data (Slave Mode) Falling Edge Last SCLK Register Data Rising Edge DRDY (Slave Mode) Falling Edge DRDY Falling Edge (Master Slave Mode) Falling Edge Rising Edge SCLK (Master Mode) Rising Edge DRDY Rising Edge (Master Slave Mode) Falling Edge Rising Edge SCLK (Slave Mode) Falling Edge Last SCLK INSR SDIO Tri-state (Master Mode) SDIO Output Rising Edge First SCLK Register Data (Master Slave Modes) Falling Edge Last SCLK INSR SDIO Tri-state (Slave Mode) SDIO Tri-state Time (Master Slave Modes) Falling Edge Last SCLK Register Data SDIO Tri-State (Master Mode) Falling Edge Last SCLK Register Data SDIO Tri-state (Slave Mode) DRDY Fall Time DRDY Rise Time Minimum DSYNC Time DSYNC Valid HIGH Falling Edge (for Exact Synchronization Multiple Converters only) Falling Edge DSYNC Valid (for Exact Synchronization Multiple Converters only) Falling Edge Last SCLK Register Data Rising Edge First SCLK next INSR (Slave Mode, Tied LOW) Rising Edge Falling Edge (Slave Mode, Using Falling Edge DRDY First SCLK Rising Edge (Slave Mode, Tied LOW)
tXIN tXIN
2000
UNITS
tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN tXIN 10.5 tXIN 20.5 tXIN 10.5 tXIN tXIN tXIN tXIN tXIN
TABLE Digital Timing Characteristics.
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DRDY SCLK SDIO
Write Register Data SDIO OUOUT1 OUT0
Read Register Data using SDIO SDIO
SDOUT
OURead Register Data using SDOUT
OUT1
OUT0
FIGURE Serial Interface Timing LOW), Master Mode.
DRDY SCLK SDIO
Write Register Data SDIO OUOUT1 OUT0
Read Register Data using SDIO SDIO
SDOUT
OURead Register Data using SDOUT
OUT1
OUT0
FIGURE Serial Interface Timing LOW), Slave Mode.
DRDY SCLK SDIO Write Register Data SDIO OUOUT1 OUT0
Read Register Data using SDIO SDIO SDOUT OURead Register Data using SDOUT OUT1 OUT0
DRDY SCLK SDIO OUOUT1 OUT0
Continuous Read Data Output Register using SDIO SDOUT OUOUT1 OUT0
Continuous Read Data Output Register using SDOUT
FIGURE Serial Interface Timing (Using CS), Master Mode.
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DRDY SCLK SDIO Write Register Data SDIO OUOUT1 OUT0
Read Register Data Using SDIO SDIO SDOUT OURead Register Data Using SDOUT OUT1 OUT0
DRDY SCLK SDIO OUOUT1 OUT0
Continuous Read Data Output Register using SDIO SDOUT OUOUT1 OUT0
Continuous Read Data Output Register using SDOUT
FIGURE Serial Interface Timing (Using CS), Slave Mode.
DRDY CS(1) Master Mode SCLK SDIO SCLK Slave Mode SDIO SDIO input NOTE: optional. SDIO output OUT0 OUT0
FIGURE SDIO Input Output Transition Timing.
DRDY
FIGURE DRDY Rise Fall Time.
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Synchronizing Multiple Converters negative going pulse DSYNC used synchronize multiple ADS1210/11s. This assumes that each ADS1210/11 driven from same master clock same Decimation Ratio Turbo Mode Rate. effect that this signal data output timing general discussed Serial Interface section. concern here what happens DSYNC input completely asynchronous this master clock. DSYNC input rises critical point relation master clock input, then some ADS1210/11s start-up clock cycle before others. Thus, output data will synchronized, only within clock cycle. many applications, this will more than adequate. these cases, timing symbols which relate DSYNC signal signal ignored. other multipleconverter applications, this clock cycle difference could problem. These types applications would include using DRDY and/or SCLK output from ADS1210/11 "master" signal converters. ensure exact synchronization same edge, timing relationship between DSYNC signals, shown Figure must observed. Figure shows simple circuit which used clock multiple ADS1210/11s from ADS1210/11, well ensure that asynchronous DSYNC signal will exactly synchronize converters.
SERIAL INTERFACE ADS1210/11 includes flexible serial interface which connected microcontrollers digital signal processors variety ways. Along with this flexibility, there also good deal complexity. This section describes trade-offs between different types interfacing methods top-down approach-starting with overall flow control serial data, moving specific interface examples, then providing information various issues related serial interface. Multiple Instructions general timing diagrams which appear throughout this data sheet show serial communication from ADS1210/11 occurring during DRDY period (see Figures through Figure 36). This communication represents instruction that executed ADS1210/ resulting single read write register data. However, more than instruction executed ADS1210/11 during given conversion period (see Figure 24). Note that DRDY remains HIGH during subsequent instructions. There several important restrictions when multiple instructions issued during conversion period.
Internal Update
tXIN
DRDY
DSYNC
Serial
FIGURE Timing Data Output Register Update. first restriction that converter must Slave Mode. There provision multiple instructions when ADS1210/11 operating Master Mode. second that some instructions will produce invalid results started conversion period carried into start next conversion period.
FIGURE DSYNC Timing Synchronizing Mutliple ADS1210/11s.
Asynchronous DSYNC Strobe
74AHC74
74AHC04 12pF XTAL 12pF
DSYNC XOUT DGND
SDOUT SDIO SCLK DVDD
DSYNC XOUT DGND
SDOUT SDIO SCLK DVDD
DSYNC XOUT DGND
SDOUT SDIO SCLK DVDD
DGND
ADS1210/11
ADS1210/11
ADS1210/11
FIGURE Exactly Synchronizing Multiple ADS1210/11s Asynchronous DSYNC Signal.
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example, Figure shows that just prior DRDY signal going LOW, internal Data Output Register (DOR) updated. This update involves Offset Calibration Register (OCR) Full-Scale Register (FSR). being written, their final value correct, result placed into will certainly valid. Problems also arise certain bits Command Register being changed. Note that reading Data Output Register exception. being read when internal update
initiated, update blocked. output data will remain data will lost. data will remain valid until read operation completed. general, multiple instructions issued, last conversion period should complete within clock periods next DRDY time. this usage, "complete" refers point where DRDY rises Figures Timing Section). Consult Figures flow serial data during conversion period.
Start Reading
Start Writing
ADS1210/11 drives DRDY
ADS1210/11 drives DRDY state HIGH state HIGH
state HIGH ADS1210/11 generates serial clock cycles receives Instruction Register data SDIO ADS1210/11 generates serial clock cycles receives Instruction Register data SDIO
Continuous Read Mode?
ADS1210/11 generates serial clock cycles receives specified register data SDIO
SDIO output?
SDOUT becomes active from tri-state SDIO input output transition
ADS1210/11 drives DRDY HIGH
ADS1210/11 generates serial clock cycles transmits specified register data SDOUT
ADS1210/11 generates serial clock cycles transmits specified register data SDIO
SDOUT returns tri-state condition
SDIO transitions tri-state condition
ADS1210/11 drives DRDY HIGH
FIGURE Flowchart Writing Reading Register Data, Master Mode.
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Start Reading
Start Writing
From Read Flowchart
ADS1210/11 drives DRDY Write Flowchart
ADS1210/11 drives DRDY
taken HIGH 10.5 periods minimum (see text tied LOW).
state
HIGH
taken HIGH 10.5 tXIN periods minimum (see text tied LOW).
state HIGH
state
HIGH
Continuous Read Mode?
state
External device generates serial clock cycles transmits instruction register data SDIO
HIGH
External device generates serial clock cycles transmits receives instruction register data SDIO
External device generates serial clock cycles transmits specified register data SDIO
SDIO output?
ADS1210/11 drives DRDY HIGH SDOUT becomes active SDIO input output transition
More Instructions? text restrictions
Next Instruction Read?
External device generates serial clock cycles transmits specified register data SDOUT
External device generates serial clock cycles receives specified register data SDIO
SDOUT returns tri-state condition SDIO transitions tri-state condition
Read Flowchart ADS1210/11 drives DRDY HIGH
More Instructions?
text restrictions
Next Instruction Write?
Write Flowchart
FIGURE Flowchart Writing Reading Register Data, Slave Mode.
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Using Continuous Read Mode serial interface make signal, this input simply tied LOW. There several issues associated with choosing other. signal does directly control tri-state condition SDOUT SDIO output. These signals normally tri-state condition. They only become active when serial data being transmitted from ADS1210/11. ADS1210/11 middle serial transfer SDOUT SDIO output, taking HIGH will tri-state output signal. there multiple serial peripherals utilizing same serial lines communication occur with peripheral time, then signal must used. ADS1210/11 Master Mode Slave Mode. Master Mode, signal used hold-off serial communication with "ready" (DRDY LOW) ADS1210/11 until main controller accommodate communication. Slave Mode, signal used enable communication with ADS1210/11. input another use. state left after read Data Output Register been performed, then next time that DRDY goes LOW, ADS1210/11 Instruction Register will entered. Instead, Instruction Register contents will re-used, contents Data Output Register, some part thereof, will transmitted. This will occur long toggled. This mode operation called Continuous Read Mode shown read flowcharts Figures also shown Timing Diagrams Figures Timing section. Note that once been taken HIGH, Continuous Read Mode will enabled (but entered) never disabled. mode actually entered exited described above. Power-On Conditions SDIO Even SDIO connection will used only input, there important item consider regarding SDIO. This only applies when ADS1210/11 Master Mode will tied LOW. power-up, serial lines most microcontrollers digital signal processors will tri-state condition, they will configured inputs. When power applied ADS1210/11, will begin operating defined default condition Command Register (see Table System Configuration section). This condition defines SDIO data output pin. Since ADS1210/11 Master Mode tied LOW, serial clock will whenever DRDY instruction will entered executed. SDIO line HIGH, might with active pull-up, then instruction read operation SDIO will become output every DRDY period-for serial clock cycles. When serial port main controller enabled, signal contention could result.
recommended solution this problem actively pull SDIO LOW. SDIO when ADS1210/11 enters instruction byte, then resulting instruction write byte data Data Output Register, which results internal operation. SDIO signal cannot actively pulled LOW, then another possibility time initialization controller's serial port such that becomes active between adjacent DRDY periods. default configuration ADS1210/11 produces data rate 814Hz-a conversion period 1.2ms. This time should more than adequate most microcontrollers DSPs monitor DRDY initialize serial port appropriate time. Master Mode Master Mode active when MODE input HIGH. serial clock cycles will produced ADS1210/11 this mode, SCLK configured output. frequency serial clock will one-half frequency. Multiple instructions cannot issued during single conversion period this mode-only instruction conversion cycle possible. Master Mode will difficult some microcontrollers, particularly when input frequency greater than MHz, serial clock exceed microcontroller's maximum serial clock frequency. majority digital signal processors, this will much less concern. addition, SDIO being used input output, then transition time from input output concern. This will true both microcontrollers DSPs. Figure Timing section. Note that tied LOW, there special considerations regarding SDIO outlined previously this section. Also note that being used control flow data from ADS1210/11 remains HIGH more conversion periods, ADS1210/11 will operate properly. However, result Data Output Register will lost when overwritten each result. Just prior this update, DRDY will forced HIGH will return after update. Slave Mode Most systems will ADS1210/11 Slave Mode. This mode allows multiple instructions issued conversion period well allowing main controller serial clock frequency pace serial data transfer. ADS1210/11 Slave Mode when MODE input LOW. There several important items regarding serial clock this mode operation. maximum serial clock frequency cannot exceed ADS1210/11 frequency divided (see Figure Timing section). When using SDIO serial output, falling edge last serial clock cycle instruction byte will cause SDIO begin transition from input output. Between three four cycles after this falling edge, SDIO will become output. This transition fast some microcontrollers digital signal processors.
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serial communication does occur during conversion period, ADS1210/11 will continue operate properly. However, results Data Output Register will lost when they overwritten result start next conversion period. Just prior this update, DRDY will forced HIGH will return after update. Making DSYNC DSYNC input DSYNC write Command Register reset current modulator count zero. This causes current conversion cycle proceed normal, modulator outputs from last data output point where DSYNC asserted discarded. Note that previous data outputs still present ADS1210/11 internal memory. Both will used compute next conversion result, most recent will used compute result conversions later. DSYNC does reset internal data zero. There main uses DSYNC. first case, DSYNC allows synchronization multiple converters. regards DSYNC input pin, this case discussed under "Synchronizing Multiple Converters" Timing section. regards DSYNC bit, will difficult converter's DSYNC bits same time unless converters Slave Mode same instruction sent converters same time. second DSYNC reset modulator count zero order obtain valid data quickly possible. example, input channel changed ADS1211, current conversion cycle will channel channels. Thus, four conversions needed order ensure valid data. However, channel changed then DSYNC used reset modulator count, modulator data current conversion cycle will entirely from channel. After additional conversion cycles, output data will completely valid. Note that conversion cycle which DSYNC used will slightly longer than normal. length will depend when DSYNC set. Reset, Power-On Reset, Brown-Out ADS1210/11 contains internal power-on reset circuit. power supply ramp rate greater than 50mV/ms, this circuit will adequate ensure that device powers correctly. (Due oscillator settling considerations, commu-
nication from ADS1210/11 should occur least 25ms after power stable.) this requirement cannot circuit brown-out considerations, timing diagram Figure used reset ADS1210/11. This timing applies only when ADS1210/11 Slave Mode accomplishes reset controlling duty cycle SCLK input. general, reset required after power-up, after brown-out been detected, when watchdog timer event occured. ADS1210/11 Master Mode, reset device possible. power supply does meet minimum ramp rate requirement, brown-out concern, on-resistance MOSFETs equivalent should used control power ADS1210/11. When powered down, device should left unpowered least 300ms before power reapplied. alternate method would control MODE temporarily place ADS1210/11 Slave Mode while reset initiated shown Figure Two-Wire Interface two-wire interface, Master Mode operation preferable. this mode, serial communication occurs only when data ready, informing main controller status ADS1210/11. disadvantages that ADS1210/11 must have dedicated serial port main controller, only instruction issued data ready period, serial clock define maximum clock frequency converter. Slave Mode, main controller must read write ADS1210/11 "blindly." Writes internal registers, such Command Register Offset Calibration Register, might occur during update Data Output Register. This result invalid data DOR. twowire interface used main controller read and/or write converter, either much slower much faster that data rate. example, much faster, main controller DRDY determine when data becoming valid (polling multiple times during conversion cycle). Thus, controller obtains some idea when write internal register. much slower, then reads might always return valid data (multiple conversions have occurred since last read since write internal registers).
Reset Occurs Falling Edge SCLK
tXIN tXIN tXIN tXIN tXIN 1024 tXIN 1200 tXIN
FIGURE Resetting ADS1210/11 (Slave Mode only).
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Three-Wire Interface Figure shows three-wire interface with 8xC32 microprocessor. Note that Slave Mode being selected SDIO being used input output.
Figure shows different type three-wire interface with 8xC51 microprocessor. Here, Master Mode used. interface signals consist SDOUT, SDIO, SCLK.
P1.0 P1.1 P1.2 AVDD P1.3 P1.4 AINP AINN AGND AGND DVDD VBIAS ADS1210 REFIN REFOUT AVDD MODE DRDY DGND INT0 INT1 DVDD DGND 27pF XTAL 27pF AGND 1.0µF P1.5 P1.6 P1.7 RESET
8xC32
DSYNC XOUT DGND
SDOUT SDIO SCLK DVDD
74HC74
74HC74
FIGURE Three-Wire Interface with 8xC32 Microprocessor.
P1.0 P1.1 P1.2 AVDD AINP AINN AGND AGND DVDD 12pF XTAL 12pF DGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD P1.3 P1.4 1.0µF AGND P1.5 P1.6 P1.7
8xC51
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6
DSYNC XOUT DGND
DGND
FIGURE Three-Wire Interface with 8xC51 Microprocessor.
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Four-Wire Interface Figure shows four-wire interface with 8xC32 microprocessor. Again, Slave Mode being used. Multi-Wire Interface Figures show multi-wire interfaces with 8xC51 68HC11 microprocessor. these interfaces, mode ADS1210/11 actually controlled dynamically. This could extremely useful when ADS1210/11 used wide variety ways. example, might desirable have ADS1210/11 produce data steady rate have converter operating Continuous Read Mode. system calibration, Slave Mode might preferred because multiple instructions issued conversion period. Note that MODE input should changed middle serial transfer. This could result misoperation device. Master/Slave Mode change will affect output data.
Note that input also controlled. possible with some microcontrollers digital signal processors produce continuous serial clock, which could connected input. frequency clock often settable over some range. Thus, power dissipation ADS1210/11 could dynamically varied changing both Turbo Mode input, trading conversion speed resolution power consumption. Recovery serial communication stops during instruction data transfer longer than tDATA, ADS1210/11 will reset serial interface. This will affect internal registers. main controller must continue transfer after this event, must restart transfer from beginning. This feature very useful main controller reset point. After reset, simply wait tDATA before starting serial communication.
P1.0 P1.1 P1.2 AVDD P1.3 P1.4 AINP AINN AGND AGND DVDD VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD 27pF DGND INT0 INT1 27pF XTAL AGND 1.0µF P1.5 P1.6 P1.7 RESET
8xC32
DSYNC XOUT DGND
DGND
74HC74
74HC74
FIGURE Four-Wire Interface with 8xC32 Microprocessor.
AVDD AINP AINN AGND AGND 12pF XTAL 12pF DGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD AGND P1.0 1.0µF P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 8xC51 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6
DSYNC XOUT DGND
DGND
FIGURE Full Interface with 8xC51 Microprocessor.
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68HC11
XIRQ RESET XTAL 12pF XTAL 12pF AGND AINP AINN AGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD AGND 1.0µF AVDD
DSYNC XOUT DGND
DGND
FIGURE Full Interface with 68HC11 Microprocessor.
VDD2 DRDY DGND
R/T2B R/T1B
R/T2A
AINP AINN AGND AGND VDD1 12pF XTAL 12pF DGND VBIAS
REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO
1.0µF AGND VDD1 DGND VDD1
VDD1 SDOUT VDD2 VDD2 SDIN DGND
DSYNC XOUT DGND
R/T2A
R/T2B R/T1B
SCLK DVDD
DGND
R/T1A
ISO150
VDD1 SCLK DGND VDD2
FIGURE Isolated Four-Wire Interface. Isolation serial interface ADS1210/11 provides simple isolation methods. example isolated four-wire interface shown Figure ISO150 used transmit digital signals over isolation barrier. addition, digital outputs ADS1210/11 can, some cases, drive opto-isolators directly. Figures show voltage SDOUT versus source sink current under worst-case conditions. Worst-case conditions source current occur when analog input differential
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AVDD
R/T1A
ISO150
SOURCE CURRENT
AIN3N AIN2P AIN3P AIN4N AIN4P REFIN REFOUT ADS1211U, AVDD MODE DRDY SDOUT SDIO SCLK DVDD AVDD 1.0µF REF1004 +2.5V 49.9k AIN2N AIN1P
25°C 85°C
-40°C
IOUT (mA)
AIN1N AGND
VBIAS DSYNC XTAL 12pF DGND XOUT DGND
DGND
12pF
FIGURE Source Current SDOUT Under Worst-Case Conditions.
SINK CURRENT -40°C 25°C 85°C
AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS ADS1211U, AIN3P AIN4N AIN4P REFIN REFOUT AVDD MODE DRDY SDOUT SDIO SCLK DVDD AVDD 1.0µF REF1004 +2.5V 49.9k
IOUT (mA)
12pF DGND 12pF XTAL
DSYNC XOUT DGND
DGND
FIGURE Sink Current SDOUT Under Worst-Case Conditions. voltage output format Offset Binary (FFFFFFH). sink current, worst-case condition occurs when analog input differential voltage output format Two's Complement (000000H). Note that SDOUT tri-stated majority conversion period opto-isolator connection must take this into account. Synchronization Multiple Converters DSYNC input used synchronize output data multiple ADS1210/11s. Synchronization involves configuring each ADS1210/11 same Decimation Ratio Turbo Mode setting, providing common signal inputs. Then, DSYNC signal pulsed (see Figure Timing section). This results internal reset modulator count current conversion. Thus, converters start counting from zero same time, producing DRDY signal approximately same point (see Figure 36). Note that asynchronous DSYNC input cause multiple converters different from another clock cycle. This should concern most applications. However, Timing section contains information exactly synchronizing multiple converters same clock cycle.
tDATA DRDY tDATA DRDY tDATA DRDY
DSYNC tDATA
FIGURE Effect Synchronization Output Data Timing.
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LAYOUT
POWER SUPPLIES ADS1210/11 requires digital supply (DVDD) greater than analog supply (AVDD) +0.3V. majority systems, this means that analog supply must come first, followed digital supply. Failure observe this condition could cause permanent damage ADS1210/11. Inputs ADS1210/11, such SDIO, AIN, REFIN, should present before analog digital supplies Violating this condition could cause latch-up. these signals present before supplies series resistors should used limit input current (see Analog Input VBIAS sections this data sheet more details concerning these inputs). best scheme power analog section design AVDD ADS1210/11 from supply digital section (and DVDD) from separate supply. analog supply should come first. This will ensure that REFIN exceed AVDD that digital inputs present only after AVDD been established, that they exceed DVDD. analog supply should well-regulated low-noise. designs requiring very high resolution from ADS1210/11, power supply rejection will concern. PSRR Frequency curve Typical Performance Curves section this data sheet more information. requirements digital supply strict. However, high frequency noise DVDD capacitively couple into analog portion ADS1210/11. This noise originate from switching power supplies, very fast microprocessors digital signal processors. either supply, high frequency noise will generally rejected digital filter except interger multiplies fMOD. Just below above these frequencies, noise will alias back into passband digital filter, affecting conversion result. supply must used power ADS1210/11, AVDD supply should used power DVDD. This connection made resistor which, along with decoupling capacitors, will provide some filtering between DVDD AVDD. some systems, direct connection made. Experimentation best determine appropriate connection between AVDD DVDD. GROUNDING analog digital sections design should carefully cleanly partitioned. Each section should have ground plane with overlap between them. AGND should connected analog ground plane well other analog grounds. DGND should connected digital ground plane digital signals referenced this plane. ADS1210/11 pinout such that converter cleanly separated into analog digital portion. This should allow simple layout analog digital sections design.
single converter system, AGND DGND ADS1210/11 should connected together, underneath converter. join ground planes, connect with moderate signal trace. multiple converters, connect ground planes location central converters possible. some cases, experimentation required find best point connect planes together. printed circuit board designed provide different analog/digital ground connections short jumpers. initial prototype used establish which connection works best. DECOUPLING Good decoupling practices should used ADS1210/ components design. decoupling capacitors, specifically 0.1µF ceramic capacitors, should placed close possible being decoupled. 10µF capacitor, parallel with 0.1µF ceramic capacitor, should used decouple AVDD AGND. minimum, 0.1µF ceramic capacitor should used decouple DVDD DGND, well digital supply each digital component. SYSTEM CONSIDERATIONS recommendations power supplies grounding will change depending requirements specific design overall system. Achieving bits more effective resolution great deal more difficult than achieving bits. general, system broken into four different stages: Analog Processing Analog Portion ADS1210/11 Digital Portion ADS1210/11 Digital Processing simplest system consisting minimal analog signal processing (basic filtering gain), self-contained microcontroller, clock source, high-resolution could achieved powering components common power supply. addition, components could share common ground plane. Thus, there would distinctions between "analog" "digital" power ground. layout should still include power plane, ground plane, careful decoupling. more extreme case, design could include: multiple ADS1210/11s; extensive analog signal processing; more microcontrollers, digital signal processors, microprocessors; many different clock sources; interconnections various other systems. High resolution will very difficult achieve this design. approach would break system into many different parts possible. example, each ADS1210/11 have "analog" processing front end, analog power ground (possibly shared with analog front end), "digital" power ground. converter's "digital" power ground would separate from power ground system's processors, RAM, ROM, "glue" logic.
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APPLICATIONS
ADS1210/11 used broad range data acquisition tasks. following application diagrams show ADS1210 and/or ADS1211 being used bridge transducer measurements, temperature measurement, 4-20mA receiver applications.
OPA1013 AGND AINP AINN AGND AGND DVDD 12pF XTAL 12pF DGND AGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD AGND 1.0µF AVDD
DSYNC XOUT DGND
DGND
FIGURE Bridge Transducer Interface with Voltage Excitation.
INA118 AINP AINN AGND AGND VBIAS DVDD REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD DGND AVDD AGND
1.0µF
100µA
100µA
REF200
12pF
DSYNC XTAL XOUT DGND
DGND
12pF DGND
AGND
FIGURE Bridge Transducer Interface with Current Excitation.
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REF200 100µA 100µA
INA118 AINP AINN AGND AGND DVDD AGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD DGND AVDD AGND 1.0µF
12pF XTAL 12pF DGND
DSYNC
AGND DGND
XOUT DGND
FIGURE PT100 Interface.
+15V 4-20mA -15V 12pF XTAL 12pF DGND AGND DVDD RCV420 AINP AINN AGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD DGND AVDD AGND
1.0µF
DSYNC XOUT DGND
DGND
FIGURE Complete 4-20mA Receiver.
Termination INA128
AINP AINN AGND AGND DVDD 12pF XTAL 12pF DGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD DGND AGND 1.0µF
AGND
DSYNC XOUT DGND
DGND
FIGURE Single Supply, High-Accuracy Thermocouple.
ADS1210, ADS1211
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INA128 AGND DVDD 12pF XTAL 12pF DGND AINP AINN AGND VBIAS REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD DGND AGND 1.0µF
AGND
DSYNC XOUT DGND
DGND
FIGURE Dual Supply, High-Accuracy Thermocouple.
INA118 AGND AIN3N AIN2P AIN2N AIN1P AGND AIN1N AGND AGND ADS1211U, AIN3P AIN4N AIN4P REFIN REFOUT AVDD MODE DRDY DGND DSYNC XTAL 12pF DGND XOUT DGND SDOUT SDIO SCLK DVDD DVDD AGND AGND 1.0µF
1N4148 AGND
12pF
VBIAS DVDD
DGND
FIGURE Single Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
ADS1210, ADS1211
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INA118 AIN3N AIN2P AIN2N AIN1P AIN1N AIN3P AIN4N AIN4P AGND REFIN REFOUT ADS1211U, AVDD MODE DRDY DGND DSYNC XTAL 12pF DGND XOUT DGND SDOUT SDIO SCLK DVDD DVDD AGND 1.0µF
AGND
AGND AGND VBIAS DVDD 12pF
1N4148 AGND
DGND
FIGURE Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
AINP AINN AGND REFIN REFOUT AVDD MODE ADS1210 DRDY SDOUT SDIO SCLK DVDD DVDD AVDD AGND 1.0µF
AVDD 100µA 100µA REF200 DVDD 12pF XTAL DGND 12pF
AGND
VBIAS
DSYNC XOUT DGND
DGND AGND
FIGURE Low-Cost Bridge Transducer Interface with Current Excitation.
ADS1210, ADS1211
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TOPIC INDEX
TOPIC PAGE
TOPIC
PAGE
FEATURES APPLICATIONS DESCRIPTION SPECIFICATIONS
ANALOG OPERATION
ANALOG INPUT REFERENCE INPUT REFERENCE OUTPUT VBIAS
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY PACKAGE INFORMATION ORDERING INFORMATION ADS1210 SIMPLIFIED BLOCK DIAGRAM ADS1210 CONFIGURATION ADS1210 DEFINITIONS ADS1211 SIMPLIFIED BLOCK DIAGRAM ADS1211P ADS1211U CONFIGURATION ADS1211P ADS1211U DEFINITIONS ADS1211E CONFIGURATION ADS1211E DEFINITIONS
DIGITAL OPERATION
SYSTEM CONFIGURATION Instruction Register (INSR) Command Register (CMR) Data Output Register (DOR) Offset Calibration Register (OCR) Full-Scale Calibration Register (FCR) TIMING Synchronizing Multiple Converters SERIAL INTERFACE Multiple Instructions Using Continuous Read Mode Power-On Conditions SDIO Master Mode Slave Mode Making DSYNC Reset, Power-On Reset, Brown-Out Two-Wire Interface Three-Wire Interface Four-Wire Interface Multi-Wire Interface Recovery Isolation Synchronization Multiple Converters
TYPICAL PERFORMANCE CURVES THEORY OPERATION
DEFINITION TERMS DIGITAL FILTER Filter Equation Filter Settling TURBO MODE PROGRAMMABLE GAIN AMPLIFIER SOFTWARE GAIN CALIBRATION Self-Calibration System Offset Calibration System Full-Scale Calibration Pseudo System Calibration Background Calibration System Calibration Offset Full-Scale Calibration Limits SLEEP MODE
LAYOUT
POWER SUPPLIES GROUNDING DECOUPLING SYSTEM CONSIDERATIONS
APPLICATIONS
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FIGURE INDEX
FIGURE
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
TABLE INDEX
PAGE TABLE
Table Table Table Table Table Table Table Table VIII Table Table Table Table Table XIII Table Table
TITLE
TITLE
PAGE
Normalized Digital Filter Response Digital Filter Response Data Rate 50Hz Digital Filter Response Data Rate 60Hz Asynchronous ADS1210/11 Analog Input Voltage Step ADS1211 Channel Change Fully Settled Output Data Self-Calibration Timing System Offset Calibration Timing System Full-Scale Calibration Pseudo System Calibration Timing Background Calibration Sleep Mode Normal Mode Timing Analog Input Structure ±10V Input Configuration Using VBIAS Clock Timing Serial Input/Output Timing, Master Mode Serial Input/Output Timing, Slave Mode Serial Interface Timing LOW), Master Mode Serial Interface Timing LOW), Slave Mode Serial Interface Timing (Using CS), Master Mode Serial Interface Timing (Using CS), Slave Mode SDIO Input Output Transition Timing DRDY Rise Fall Time DSYNC Timing Synchronizing Multiple ADS1210/11s Exactly Synchronizing Multiple ADS1210/11s Asynchronous DSYNC Signal Timing Data Output Register Update Flowchart Writing Reading Register Data, Master Mode Flowchart Writing Reading Register Data, Slave Mode Resetting ADS1210/11 (Slave Mode Only) Three-Wire Interface with 8xC32 Microprocessor Three-Wire Interface with 8xC51 Microprocessor Four-Wire Interface with 8xC32 Microprocessor Full Interface with 8xC51 Microprocessor Full Interface with 68HC11 Microprocessor Isolated Four-Wire Interface Source Current SDOUT Under Worst-Case Conditions Sink Current SDOUT Under Worst-Case Conditions Effect Synchronization Output Data Timing Bridge Transducer Interface with Voltage Excitation Bridge Transducer Interface with Current Excitation PT100 Interface Complete 4-20mA Receiver Single Supply, High-Accuracy Thermocouple Dual Supply, High-Accuracy Thermocouple Single Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation Low-Cost Bridge Transducer Interface with Current Excitation
Full-Scale Range Setting Available Settings Turbo Mode Rate Effective Resolution Data Rate Gain Setting Effective Resolution Data Rate Turbo Mode Rate Noise Level Data Rate Turbo Mode Rate Effective Resolution Data Rate, Clock Frequency, Turbo Mode Rate ADS1210/11 Registers Instruction Register A3-A0 Addressing Organization Command Register Default Status Decimation Ratios Data Rates Data Output Register Offset Calibration Register Full-Scale Calibration Register Digital Timing Characteristics
ADS1210, ADS1211
SBAS034B
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PACKAGE OPTION ADDENDUM
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31-Oct-2005
PACKAGING INFORMATION
Orderable Device ADS1210P ADS1210U ADS1210U/1K ADS1210U/1KG4 ADS1210UG4 ADS1211E ADS1211E/1K ADS1211E/1KG4 ADS1211P ADS1211U ADS1211U/1K ADS1211U/1KG4 ADS1211UG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type PDIP SSOP SSOP SSOP PDIP SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU SNPB NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-NA-NA-NA Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-NA-NA-NA Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
1000 Green (RoHS Sb/Br) 1000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
1000 Green (RoHS Sb/Br) 1000 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
1000 Green (RoHS Sb/Br) 1000 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold
Addendum-Page
PACKAGE OPTION ADDENDUM
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31-Oct-2005
Customer annual basis.
Addendum-Page
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
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