OPA682 OPA6 Wideband, Fixed Gain BUFFER AMPLIFIER With Disab

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OPA682 OPA6 Wideband, Fixed Gain BUFFER AMPLIFIER With Disab

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OPA682
OPA6
Wideband, Fixed Gain BUFFER AMPLIFIER With Disable
FEATURES
INTERNALLY FIXED GAIN: HIGH BANDWIDTH +2): 240MHz SUPPLY CURRENT: DISABLED CURRENT: 320µA HIGH OUTPUT CURRENT: 150mA OUTPUT VOLTAGE SWING: ±4.0V SINGLE OPERATION SOT23-6 AVAILABLE
APPLICATIONS
BROADBAND VIDEO LINE DRIVERS VIDEO MULTIPLEXERS MULTIPLE LINE VIDEO PORTABLE INSTRUMENTS BUFFERS ACTIVE FILTERS
DESCRIPTION
OPA682 provides easy use, broadband fixed gain buffer amplifier. Depending external connections, internal resistor network used provide either fixed gain video buffer gain voltage buffer. Operating very supply current, OPA682 offers slew rate output power normally associated with much higher supply current. output stage architecture delivers high output current with minimal headroom crossover distortion. This gives exceptional single supply operation. Using single supply, OPA682 deliver output swing with over 100mA drive current 200MHz bandwidth. This combination features makes OPA682 ideal line driver single supply input driver.
OPA682's supply current precisely trimmed 25°C. This trim, along with drift over temperature, guarantees lower maximum supply current than competing products that report only room temperature nominal supply current. System power further reduced using optional disable control pin. Leaving this disable open, holding high, gives normal operation. pulled low, OPA682 supply current drops less than 320µA while output goes into high impedance state. This feature used either power savings video applications.
OPA682 RELATED PRODUCTS
SINGLES Voltage Feedback Current Feedback Fixed Gain OPA680 OPA681 OPA682 DUALS OPA2680 OPA2681 OPA2682 TRIPLES OPA3680 OPA3681 OPA3682
OPA682 Video 8-Pin DIP, SO-8 RG-59 RG-59 RG-59 RG-59
Video
240MHz, 4-Output Component Video
nternational Airport Industrial Park Mailing Address: 11400, Tucson, 85734 Street Address: 6730 Tucson Blvd., Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1999 Burr-Brown Corporation
PDS-1428C
Printed U.S.A. September, 1999
SBOS085
SPECIFICATIONS:
(-IN grounded) (Figure performance only), unless otherwise noted. OPA682P, +25°C +25°C GUARANTEED(1) 70°C -40°C +85°C MIN/ TEST LEVEL(2
PARAMETER PERFORMANCE (Figure Small-Signal Bandwidth 0.5Vp-p)
CONDITIONS
UNITS
2100 0.001 0.008 0.01 0.05 ±0.2 ±0.3 ±0.2 1600 1600 1200
V/µs nV/Hz pA/Hz pA/Hz
Bandwidth 0.1dB Gain Flatness Peaking Gain Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time 0.02% 0.1% Harmonic Distortion Harmonic Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase PERFORMANCE(3) Gain Error
0.5Vp-p 0.5Vp-p 5Vp-p Step 0.5V Step Step Step Step 5MHz, 2Vp-p 1MHz 1MHz 1MHz NTSC, NTSC, 37.5 NTSC, NTSC, 37.5
±1.5
±1.5 0.13 0.13 ±6.5 -400 -125 0.13 ±7.5 -450 -150 ±3.2
%/C° µV/°C nA/°C nA°C
Internal Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range Non-Inverting Input Impedance OUTPUT Voltage Output Swing Current Output, Sourcing Sinking Closed-Loop Output Impedance 100kHz Load Load ±4.0 ±3.9 +190 -150 0.03 ±3.5 ±1.3
±3.4
±3.3
±3.8 ±3.7
+160 -135
±3.7 ±3.6 +140 -130
±3.6 ±3.3
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
OPA682
SPECIFICATIONS: (Cont.)
(-IN grounded) (Figure performance only), unless otherwise noted. OPA682P, +25°C -320 5MHz VDIS +25°C GUARANTEED(1) 70°C -40°C +85°C MIN/ TEST LEVEL(2)
PARAMETER DISABLE/POWER DOWN (DIS Pin) Power Down Supply Current (+VS) Disable Time Enable Time Isolation Output Capacitance Disable Turn Glitch Turn Glitch Enable Voltage Disable Voltage Control Input Bias Current POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Quiescent Current Quiescent Current Power Supply Rejection Ratio (-PSRR) TEMPERATURE RANGE Specification: Thermal Resistance, 8-Pin
CONDITIONS VDIS
UNITS
Input Referred
°C/W °C/W °C/W
SO-8 SOT23-6
NOTES: Junction temperature ambient temperature temperature limit 25°C guaranteed specifications. Junction temperature ambient temperature +23°C high temperature limit guaranteed specifications. Test Levels: 100% tested 25°C. Over temperature limits characterization simulation. Limits characterization simulation. Typical value only information. Current considered positive out-of-node. input commonmode voltage.
OPA682
SPECIFICATIONS:
(-IN grounded though 0.1µF) VS/2 (Figure performance only), unless otherwise noted. OPA682P, +25°C +25°C GUARANTEED(1) 70°C -40°C +85°C MIN/ TEST LEVEL(2)
PARAMETER PERFORMANCE (Figure Small-Signal Bandwidth 0.5Vp-p)
CONDITIONS
UNITS
Bandwidth 0.1dB Gain Flatness Peaking Gain Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time 0.02% 0.1% Harmonic Distortion Harmonic Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise PERFORMANCE(3) Gain Error
0.5Vp-p 0.5Vp-p 2Vp-p Step 0.5V Step Step Step Step 5MHz, 2Vp-p 1MHz 1MHz 1MHz
±0.2 ±0.3 ±0.2
V/µs nV/Hz pA/Hz pA/Hz
±1.5
±1.5 0.13 0.13 -300 -125 0.13 -350 -175
%/C° µV/°C nA/°C nA°C
Internal Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Non-Inverting Input Impedance OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Sinking Output Impedance Load Load 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
+150 -110 0.03
+110
+110
100kHz
OPA682
SPECIFICATIONS: (Cont.)
(-IN grounded though 0.1µF) VS/2 (Figure performance only), unless otherwise noted. OPA682P, +25°C -270 Input Referred +25°C GUARANTEED(1) 70°C -40°C +85°C MIN/ TEST LEVEL(2)
PARAMETER DISABLE/POWER DOWN (DIS Pin) Power Down Supply Current (+VS) Disable Time Enable Time Isolation Output Capacitance Disable Turn Glitch Turn Glitch Enable Voltage Disable Voltage Control Input Bias Current (DIS) POWER SUPPLY Specified Single Supply Operating Voltage Maximum Single Supply Operating Voltage Quiescent Current Quiescent Current Power Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: Thermal Resistance, 8-Pin SO-8 SOT23-6
CONDITIONS VDIS
UNITS °C/W °C/W °C/W
5MHz 150, 2.5V 150, 2.5V
VDIS
NOTES: Junction temperature ambient temperature temperature limit 25°C guaranteed specifications. Junction temperature ambient temperature +23°C high temperature limit guaranteed specifications. Test Levels: 100% tested 25°C. Over temperature limits characterization simulation. Limits characterization simulation. Typical value only information. Current considered positive out-of-node. input commonmode voltage.
OPA682
ABSOLUTE MAXIMUM RATINGS
Power Supply ±6.5VDC Internal Power Dissipation(1) Thermal Information Differential Input Voltage ±1.2V Input Voltage Range Storage Temperature Range: -40°C +125°C Lead Temperature (soldering, 10s) +300°C Junction Temperature +175°C NOTE:: Packages must derated based specified Maximum must observed.
ELECTROSTATIC DISCHARGE SENSITIVITY
Electrostatic discharge cause damage ranging from performance degradation complete device failure. Burr-Brown Corporation recommends that integrated circuits handled stored using appropriate protection methods. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
CONFIGURATION
View DIP/SO-8 View SOT23-6
Output
Output
Connection
Orientation/Package Marking
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER(1) TEMPERATURE RANGE -40°C +85°C -40°C +85°C PACKAGE MARKING OPA682P OPA682U ORDERING NUMBER(2) OPA682P OPA682U OPA682U/2K5 OPA682N/250 OPA682N/3K TRANSPORT MEDIA Rails Rails Tape Reel Tape Reel Tape Reel
PRODUCT OPA682P OPA682U
PACKAGE 8-Pin Plastic SO-8 Surface Mount
OPA682N
6-Lead SOT23
-40°C +85°C
NOTES: detailed drawing dimension table, please data sheet. Models with slash available only Tape Reel quantities indicated (e.g., /2K5 indicates 2500 devices reel). Ordering 2500 pieces "OPA682U/2K5" will single 2500-piece Tape Reel.
OPA682
TYPICAL PERFORMANCE CURVES:
100, unless otherwise noted (see Figure
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
Gain (1dB/div)
7Vp-p 4Vp-p
2Vp-p
1Vp-p
250MHz Frequency (50MHz/div)
500MHz
125MHz Frequency (25MHz/div)
250MHz
SMALL-SIGNAL PULSE RESPONSE
Output Voltage (100mV/div)
LARGE-SIGNAL PULSE RESPONSE 5Vp-p
-100 -200 -300 -400 Time (5ns/div)
0.5Vp-p
Output Voltage (1V/div)
Time (5ns/div)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE VDIS (2V/div) VDIS Output Voltage (400mV/div) Time (50ns/div) Output Voltage
DISABLED FEEDTHROUGH FREQUENCY VDIS
Feedthrough (5dB/div)
Frequency (MHz) Forward Reverse
OPA682
TYPICAL PERFORMANCE CURVES: (Cont.)
100, unless otherwise noted (see Figure
5MHz HARMONIC DISTORTION OUTPUT VOLTAGE 5MHz HARMONIC DISTORTION OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
Output Voltage Swing (Vp-p)
Output Voltage Swing (Vp-p)
10MHz HARMONIC DISTORTION OUTPUT VOLTAGE
10MHz HARMONIC DISTORTION OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Output Voltage Swing (Vp-p)
Harmonic Distortion (dBc)
Output Voltage Swing (Vp-p)
20MHz HARMONIC DISTORTION OUTPUT VOLTAGE
20MHz HARMONIC DISTORTION OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
Output Voltage Swing (Vp-p)
Output Voltage Swing (Vp-p)
OPA682
TYPICAL PERFORMANCE CURVES:
100, unless otherwise noted (see Figure
(Cont.)
HARMONIC DISTORTION FREQUENCY 2Vp-p
HARMONIC DISTORTION FREQUENCY 2Vp-p
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
Frequency (MHz)
Frequency (MHz)
INPUT VOLTAGE CURRENT NOISE DENSITY
TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS below carriers 50MHz
Inverting Input Current Noise 15pA/Hz
Non-Inverting Input Current Noise
12pA/Hz
3rd-Order Spurious Level (dBc)
Current Noise (pA/Hz) Voltage Noise (nV/Hz)
20MHz
Voltage Noise
2.2nV/Hz 100k
10MHz Load Power Matched Load
Frequency (Hz)
Single-Tone Load Power (dBm)
RECOMMENDED CAPACITIVE LOAD Capacitive Load (pF)
FREQUENCY RESPONSE CAPACITIVE LOAD
Gain Capacitive Load (3dB/div)
OPA682
10pF 22pF 47pF
optional.
100pF 300MHz
150MHz Frequency (30MHz/div)
OPA682
TYPICAL PERFORMANCE CURVES:
100, unless otherwise noted (see Figure
(Cont.)
POWER SUPPLY REJECTION RATIO FREQUENCY +PSRR
SUPPLY OUTPUT CURRENT TEMPERATURE
Supply Current (2.5mA/div)
Sourcing Output Current Sinking Output Current
Output Current (mA)
-PSRR
Rejection Ratio (dB)
Frequency (Hz)
Quiescent Supply Current
Ambient Temperature (°C)
COMPOSITE VIDEO dG/dP 0.05 Positive Video Negative Sync
TYPICAL DRIFT OVER TEMPERATURE Non-Inverting Input Bias Current
Input Offset Voltage (mV)
Inverting Input Bias Current
Ambient Temperature (°C)
0.03
0.02
0.01 Number Loads
OUTPUT VOLTAGE CURRENT LIMITATIONS Internal Power Limit Output Current Limited
CLOSED-LOOP OUTPUT IMPEDANCE
Output Impedance
OPA682
(Volts)
-300 -200 -100 (mA) Output Current Limit
Load Line Load Line Load Line
Internal Power Limit 0.01 100k Frequency (Hz) 100M
OPA682
Input Bias Currents (µA)
0.04
dG/dP (%/°)
TYPICAL PERFORMANCE CURVES:
+2.5V, unless otherwise noted (see Figure
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE 2.5V 0.5Vp-p
Normalized Gain (1dB/div)
Gain (1dB/div)
2Vp-p
1Vp-p
250MHz Frequency (50MHz/div)
500MHz
Frequency (25MHz/div)
SMALL-SIGNAL PULSE RESPONSE 2.10 0.5Vp-p Output Voltage (400mV/div)
LARGE-SIGNAL PULSE RESPONSE 2Vp-p
Output Voltage (100mV/div)
Time (5ns/div)
Time (5ns/div)
RECOMMENDED CAPACITIVE LOAD Gain Capacitive Load (3dB/div)
FREQUENCY RESPONSE CAPACITIVE LOAD 47pF 10pF 22pF
0.1µF 57.6 OPA682 optional)
Capacitive Load (pF)
0.1µF
100pF 100MHz Frequency (20MHz/div) 200MHz
OPA682
TYPICAL PERFORMANCE CURVES:
+2.5V, unless otherwise noted (see Figure
(Cont.)
HARMONIC DISTORTION FREQUENCY
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
HARMONIC DISTORTION FREQUENCY 2Vp-p
2Vp-p
Frequency (MHz)
Frequency (MHz)
HARMONIC DISTORTION FREQUENCY
HARMONIC DISTORTION FREQUENCY 2Vp-p
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
2Vp-p
Loads 2.5V Frequency (MHz)
Loads 2.5V Frequency (MHz)
TWO-TONE, 3rd-ORDER SPURIOUS LEVEL Below Carriers
3rd-Order Spurious (dBc)
50MHz 20MHz 10MHz Load Power Matched Load Single-Tone Load Power (dBm)
OPA682
APPLICATIONS INFORMATION
WIDEBAND BUFFER OPERATION OPA682 gives exceptional performance wideband current feedback with highly linear, high power output stage. features internal resistors which make easy select gain without external resistors. Requiring only quiescent current, OPA682 will swing within either supply rail deliver excess 135mA guaranteed room temperature. This output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. OPA682 will deliver greater than 200MHz bandwidth driving 2Vp-p output into single supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion output current goes through zero. OPA682 achieves comparable power gain with much better linearity. primary advantage current feedback over voltage feedback that performance (bandwidth distortion) relatively independent signal gain. Figure shows coupled, gain dual power supply circuit configuration used basis Specifications Typical Performance Curves. test purposes, input impedance with resistor ground output impedance with series output resistor. Voltage swings reported specifications taken directly input output pins while load powers (dBm) defined matched load. circuit Figure total effective load will disable control line (DIS) typically left open guarantee normal amplifier operation. addition usual power supply decoupling capacitors ground, 0.1µF capacitor included between power supply pins. This optional added capacitor will typically improve harmonic distortion performance 6dB.
0.1µF Source Load 6.8µF
Figure shows coupled, gain single-supply circuit configuration used basis Specifications Typical Performance Curves. Though "railto-rail" design, OPA682 requires minimal input output voltage headroom compared other very wideband current feedback amps. will deliver 3Vp-p output swing single supply with greater than 150MHz bandwidth. requirement broadband single-supply operation maintain input output signal swings within usable voltage ranges both input output. circuit Figure establishes input midpoint bias using simple resistive divider from supply (two resistors). input signal then AC-coupled into this midpoint voltage bias. input voltage swing within 1.5V either supply pin, giving 2Vp-p input signal range centered between supply pins. input impedance matching resistor (57.6) used testing adjusted give input match when parallel combination biasing divider network included. gain resistor (RG) AC-coupled, giving circuit gain +1-which puts input bias voltage (2.5V) output well. Again, single supply, output voltage swing within either supply while delivering more than 80mA output current. demanding load midpoint bias used this characterization circuit. output stage used OPA682 deliver large bipolar output currents into this midpoint load with minimal crossover distortion, shown supply, harmonic distortion plots.
0.1µF Source 0.1µF 57.6
6.8µF
VS/2
OPA682
0.1µF
OPA682
FIGURE AC-Coupled, Single Supply Specification Test Circuit. SINGLE-SUPPLY CONVERTER INTERFACE
0.1µF 6.8µF
FIGURE DC-Coupled, Bipolar Supply, Specification Test Circuit.
Most modern, high performance converters (such Burr-Brown ADS8xx ADS9xx series) operate single lower) power supply. been considerable challenge single-supply amps deliver distortion input signal input signal frequen
OPA682
cies exceeding 5MHz. high slew rate, exceptional output swing high linearity OPA682 make ideal single-supply driver. Figure shows example input interface very high performance 10-bit, 60MSPS CMOS converter. OPA682 circuit Figure provides 240MHz bandwidth operating signal gain with 2Vp-p output swing. non-inverting input bias voltage referenced midpoint signal range dividing bottom internal reference ladder. With gain resistor (RG) AC-coupled, this bias voltage gain output, centering output voltage
swing well. Tested performance 20MHz analog input frequency 60MSPS clock rate converter gives 58dBc SFDR. WIDEBAND VIDEO MULTIPLEXING common application video speed amplifiers which include disable wire multiple amplifier outputs together, then select which several possible video inputs source onto single line. This simple "Wired-OR Video Multiplexer" easily implemented using OPA682 shown Figure
0.1µF OPA682 1Vp-p 0.1µF +2.5V Bias +3.5V REFT 0.1µF +1.5V REFB 0.1µF 2Vp-p 22pF Input Input Clock ADS823 10-Bit 60MSPS
FIGURE Wideband, AC-Coupled, Single-Supply Driver.
VDIS |VOUT| 2.6V
Video
OPA682
68.1
Cable VOUT 68.1 RG-59
Video
OPA682
FIGURE Two-Channel Video Multiplexer.
OPA682
Typically, channel switching performed either sync retrace time video signal. inputs approximately equal this time. "make-before-break" disable characteristic OPA682 ensures that there always amplifier controlling line when using wired-OR circuit like that shown Figure Since both inputs short period during transition between channels, outputs combined through output impedance matching resistors (68.1 this case). When channel disabled, feedback network forms part output impedance slightly attenuates signal getting onto cable. matching resistors have been signal gain load while providing 20dB return loss load. video multiplexer connection (Figure also insures that maximum differential voltage across inputs unselected channel exceed rated ±1.2V maximum standard video signal levels. case, VOUT must ±2.6Vp-p order exceed absolute maximum differential input voltage (±1.2V) disabled part. section Disable Operation shows turn-on turn-off switching glitches using grounded input
single channel typically less than ±50mV. Where outputs switched shown Figure output line always under control amplifier other "make-before-break" disable timing. this case, switching glitches inputs drop 20mV. DELAY-EQUALIZED LOWPASS FILTER circuit Figure realizes 5th-order Butterworth lowpass filter with -3dB bandwidth 20MHz group delay equalization. This filter based active filter topology using amplifiers with fixed positive gain OPA682 makes good amplifier this type filter. first stage group delay equalizer, which based gain second stage high-Q pole, uses gain minimum component sensitivity. second stage also produces real pole. last stage low-Q pole, uses gain minimum component sensitivity. component values have been pre-distorted compensate amps's parasitic effects. low-Q pole section placed last minimize noise peaking passband, while maintaining good dynamic range performance.
56pF 220pF 27pF 49.9
OPA682
OPA682
100pF
68pF 95.3
39pF
OPA682
VOUT
(Open)
FIGURE Butterworth Filter with Delay Equalization.
OPA682
PRECISION VOLTAGE BUFFER precision buffer Figure combines precision noise OPA227 with high speed performance OPA682. 80.6k resistor makes high frequency frequency nominal gains equal. OPA682 takes over from OPA227 approximately 32kHz.
OPERATING SUGGESTIONS
GAIN SETTING Setting gain with OPA682 very easy. gain ground drive with signal. gain leave open drive with signal. gain ground drive with signal. Since internal resistor values (but their ratio) change significantly over temperature process, external resistors should used modify gain. OUTPUT CURRENT VOLTAGE OPA682 provides output voltage current capabilities that unsurpassed cost monolithic amp. Under no-load conditions 25°C, output voltage typically swings closer than either supply rail; guaranteed swing limit within 1.2V either rail. Into load (the minimum tested load), guaranteed deliver more than ±135mA. specifications described above, though familiar industry, consider voltage current limits separately. many applications, voltage current, product, which more relevant circuit operation. Refer "Output Voltage Current Limitations" plot Typical Performance Curves. axes this graph show zero-voltage output current limit zero-current output voltage limit, respectively. four quadrants give more detailed view OPA682's output drive capabilities, noting that graph bounded "Safe Operating Area" maximum internal power dissipation. Superimposing resistor load lines onto plot shows that OPA682 drive ±2.5V into ±3.5V into without exceeding output capabilities dissipation limit. load line (the standard test circuit load) shows full ±3.9V output swing capability, shown Typical Specifications. minimum specified output voltage current over temperature worst-case simulations cold temperature extreme. Only cold startup will output current voltage decrease numbers shown guaranteed tables. output transistors deliver power, their junction temperatures will increase, decreasing their VBE's (increasing available output voltage swing) increasing their current gains (increasing available output current). steady-state operation, available output voltage current will always greater than that shown over-temperature specifications since output stage junction temperatures will higher than minimum specified operating ambient. maintain maximum output stage linearity, output short-circuit protection provided. This will normally problem since most applications include series matching resistor output that will limit internal power dissipation output side this resistor shorted ground. However, shorting output directly adjacent positive power supply will, most cases, destroy amplifier. additional short-circuit protection required, consider small series resistor power supply
OPA682
80.6k
VOUT
2.7nF
OPA227
2.7nF
FIGURE Precision Wideband, Unity Gain Buffer.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS Several boards available assist initial evaluation circuit performance using OPA682 three package styles. these available free unpopulated board delivered with descriptive documentation. summary information these boards shown table below.
BOARD PART NUMBER DEM-OPA68xP DEM-OPA68xU DEM-OPA68xN LITERATURE REQUEST NUMBER MKT-350 MKT-351 MKT-348
PRODUCT OPA682P OPA682U OPA682N
PACKAGE 8-Pin 8-Lead SO-8 6-Lead SOT23-6
Contact Burr-Brown applications support line request these boards. MACROMODELS APPLICATIONS SUPPORT Computer simulation circuit performance using SPICE often useful when analyzing performance analog circuits systems. This particularly true video amplifier circuits where parasitic capacitance inductance have major effect circuit performance. SPICE model OPA682 available through BurrBrown Internet page (http://www.burr-brown.com). These models good predicting small-signal transient performance under wide variety operating conditions. They well predicting harmonic distortions, temperature dG/d characteristics. These models attempt distinguish between package types their small-signal performance.
OPA682
leads. This will, under heavy output loads, reduce available output voltage swing. series resistor each power supply lead will limit internal power dissipation less than output short circuit while decreasing available output voltage swing only 0.5V 100mA desired load currents. Always place 0.1µF power supply decoupling capacitors after these supply current limiting resistors directly supply pins. DRIVING CAPACITIVE LOADS most demanding very common load conditions capacitive loading. Often, capacitive load input converter-including additional external capacitance which recommended improve linearity. high-speed amplifier like OPA682 very susceptible decreased stability frequency response peaking when capacitive load placed directly output pin. When amplifier's open-loop output resistance considered, this capacitive load introduces additional pole signal path that decrease phase margin. Several external solutions this problem have been suggested. When primary considerations frequency response flatness, pulse response fidelity and/or distortion, simplest most effective solution isolate capacitive load from feedback loop inserting series isolation resistor between amplifier output capacitive load. This does eliminate pole from loop response, rather shifts adds zero higher frequency. additional zero acts cancel phase from capacitive load pole, thus increasing phase margin improving stability. Typical Performance Curves show recommended Capacitive Load resulting frequency response load. Parasitic capacitive loads greater than begin degrade performance OPA682. Long board traces, unmatched cables, connections multiple devices easily cause this value exceeded. Always consider this effect carefully, recommended series resistor close possible OPA682 output (see Board Layout Guidelines). DISTORTION PERFORMANCE OPA682 provides good distortion performance into load supplies. Relative alternative solutions, provides exceptional performance into lighter loads and/or operating single supply. Generally, until fundamental signal reaches very high frequency power levels, harmonic will dominate distortion with negligible harmonic component. Focusing then harmonic, increasing load impedance improves distortion directly. Remember that total load includes feedback networkin non-inverting configuration (Figure this while inverting configuration just Also, providing additional supply decoupling capacitor (0.1µF) between supply pins (for bipolar operation) improves 2nd-order distortion slightly (3dB 6dB). most amps, increasing output voltage swing increases harmonic distortion directly. Typical Performance
Curves show harmonic increasing little less than expected rate while harmonic increases little less than expected rate. Where test power doubles, difference between harmonic decreases less than expected while difference between decreases less than expected 12dB. This also shows 2-tone, 3rd-order intermodulation spurious (IM3) response curves. 3rdorder spurious levels extremely output power levels. output stage continues hold them even fundamental power reaches very high levels. Typical Performance Curves show, spurious intermodulation powers increase predicted traditional intercept model. fundamental power level increases, dynamic range does decrease significantly. tones centered 20MHz, with 10dBm/tone into matched load (i.e., 2Vp-p each tone load, which requires 8Vp-p overall 2-tone envelope output pin), Typical Performance Curves show 62dBc difference between test-tone power 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating lower frequencies. NOISE PERFORMANCE OPA682 offers excellent balance between voltage current noise terms achieve output noise. inverting current noise (15pA/Hz) significantly lower than earlier solutions while input voltage noise (2.2nVHz) lower than most unity gain stable, wideband, voltage feedback amps. This input voltage noise achieved price higher non-inverting input current noise (12pA/Hz). long source impedance looking noninverting node less than 100, this current noise will contribute significantly total output noise. input voltage noise input current noise terms combine give output noise gain settings, available using OPA682. Figure shows noise analysis model with noise terms included. this model, noise terms taken noise voltage current density terms either nV/Hz pA/Hz. total output spot noise voltage computed square root squared output noise voltage contributors. Equation shows general form output noise voltage using terms shown Figure
OPA682
4kTRS 4kTRF 1.6E -20J 290°K
FIGURE Noise Model.
OPA682
Eq.1
4kTR 4kTR
left unconnected, OPA682 will operate normally. disable, control must asserted low. Figure shows simplified internal circuit disable control feature.
Dividing this expression noise gain (1+RF/RG)) will give equivalent input-referred spot noise voltage non-inverting input shown Equation
4kTR 4kTR
Evaluating these equations OPA682 circuit component values shown Figure will give total output spot noise voltage 8.4nV/Hz total equivalent input spot noise voltage 4.2nV/Hz. This total input-referred spot noise voltage higher than 2.2nV/Hz specification voltage noise alone. This reflects noise added output inverting current noise times feedback resistor. ACCURACY OPA682 provides exceptional bandwidth high gains, giving fast pulse settling only moderate accuracy. Typical Specifications show input offset voltage comparable high speed voltage feedback amplifiers. However, input bias currents somewhat higher unmatched. Bias current cancellation techniques will reduce output offset OPA682. Since input bias currents unrelated both magnitude polarity, matching source impedance looking each input reduce their error contribution output ineffective. Evaluating configuration Figure using worst-case +25°C input offset voltage input bias currents, gives worst-case output offset range equal ±(NG VOS(max)) (IBN RS/2 (IBI where non-inverting signal gain 5.0mV) (55µA (480 40µA) ±10mV 2.8mV 19.2mV -26.4mV +32.0mV Minimizing resistance seen non-inverting input will give best offset performance. significantly improved accuracy, consider precision buffer circuit shown Figure DISABLE OPERATION OPA682 provides optional disable feature that used either reduce system power implement simple channel multiplexing operation. control
VDIS Control
110k
FIGURE Simplified Disable Control Circuit. normal operation, base current provided through 110k resistor while emitter current through resistor sets voltage drop that inadequate turn diodes Q1's emitter. VDIS pulled low, additional current pulled through resistor eventually turning these diodes 100µA). this point, further current pulled VDIS goes through those diodes holding emitter-base voltage approximately zero volts. This shuts collector current turning amplifier off. supply current disable mode only that required operate circuit Figure Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, output input nodes high impedance state. OPA682 operating gain this will show very high impedance (4pF output exceptional signal isolation. operating gain total feedback network resistance will appear impedance looking back into output, circuit will still show very high forward reverse isolation. configured gain input output will connected through feedback network resistance giving relatively poor input output isolation. parameter disable operation output glitch when switching disabled mode. Figure shows these glitches circuit Figure with input signal zero volts. glitch waveform output plotted along with voltage.
OPA682
Output Voltage (20mV/div)
Output Voltage Input)
4.8V VDIS 0.2V
Although this still well below specified maximum junction temperature, system reliability considerations require lower guaranteed junction temperatures. Remember, this worst-case internal power dissipation-use your actual signal load compute PDL. highest possible internal dissipation will occur load requires current forced into output positive output voltages sourced from output negative output voltages. This puts high current through large internal voltage drop output transistors. Output Voltage Current Limitations plot shown Typical Performance Curves include boundary maximum internal power dissipation under these conditions. BOARD LAYOUT GUIDELINES
Time (20ns/div)
FIGURE Disable/Enable Glitch. transition edge rate (dV/dt) control line will influence this glitch. plot Figure edge rate reduced until further reduction glitch amplitude observed. This approximately 1V/ns maximum slew rate achieved adding simple filter into VDIS from higher speed logic line. extremely fast transition logic used, series resistor between logic gate input will provide adequate bandlimiting using just parasitic input capacitance while still ensuring adequate logic level swing. THERMAL ANALYSIS high output power capability OPA682, heatsinking forced airflow required under extreme operating conditions. Maximum desired junction temperature will maximum allowed internal power dissipation described below. case should maximum junction temperature allowed exceed 175°C. Operating junction temperature (TJ) given total internal power dissipation (PD) quiescent power (PDQ) additional power dissipated output stage (PDL) deliver load power. Quiescent power simply specified no-load supply current times total supply voltage across part. will depend required output signal load would, grounded resistive load, maximum when output fixed voltage equal either supply voltage (for equal bipolar supplies). Under this condition VS2/(4 where includes feedback network loading. Note that power output stage load that determines internal power dissipation. worst-case example, compute maximum using OPA682N (SOT23-6 package) circuit Figure operating maximum specified ambient temperature +85°C driving grounded load +2.5V 7.2mA 52/(4 800)) 392mW Maximum +85°C (0.39W 150°C/W) 144°C
Achieving optimum performance with high frequency amplifier like OPA682 requires careful attention board layout parasitics external component types. Recommendations that will optimize performance include: Minimize parasitic capacitance ground signal pins. Parasitic capacitance output cause instability: non-inverting input, react with source impedance cause unintentional bandlimiting. reduce unwanted capacitance, window around signal pins should opened ground power planes around those pins. Otherwise, ground power planes should unbroken elsewhere board. Minimize distance 0.25") from power supply pins high frequency 0.1µF decoupling capacitors. device pins, ground power plane layout should close proximity signal pins. Avoid narrow power ground traces minimize inductance between pins decoupling capacitors. power supply connections pins should always decoupled with these capacitors. optional supply decoupling capacitor across power supplies (for bipolar operation) will improve harmonic distortion performance. Larger (2.2µF 6.8µF) decoupling capacitors, effective lower frequency, should also used main supply pins. These placed somewhat farther from device shared among several devices same area board. Careful selection placement external components will preserve high frequency performance OPA682. external resistors should very reactance type. Surface-mount resistors work best allow tighter overall layout. Metal-film carbon composition, axially-leaded resistors also provide good high frequency performance. Again, keep their leads board trace length short possible. Never wirewound type resistors high frequency application. external components should also placed close package.
OPA682
Connections other wideband devices board made with short direct traces through onboard transmission lines. short connections, consider trace input next device lumped capacitive load. Relatively wide traces (50mils 100mils) should used, preferably with ground power planes opened around them. Estimate total capacitive load from plot recommended Capacitive Load. parasitic capacitive loads 5pF) need since OPA682 nominally compensated operate with parasitic load. long trace required, signal loss intrinsic doubly-terminated transmission line acceptable, implement matched impedance transmission line using microstrip stripline techniques (consult design handbook microstrip stripline layout techniques). environment normally necessary board, fact, higher impedance environment will improve distortion shown Distortion Load plots. With characteristic board trace impedance defined based board material trace dimensions, matching series resistor into trace from output OPA682 used well terminating shunt resistor input destination device. Remember also that terminating impedance will parallel combination shunt resistor input impedance destination device: this total effective impedance should match trace impedance. high output voltage current capability OPA682 allows multiple destination devices handled separate transmission lines, each with their series shunt terminations. attenuation doubly-terminated transmission line unacceptable, long trace series-terminated source only. Treat trace capacitive load this case series resistor value shown plot Capacitive Load. This will preserve signal integrity well doubly-terminated line. input impedance destination device low, there will some signal attenuation voltage divider formed series output into terminating impedance.
Socketing high speed part like OPA682 recommended. additional lead length pin-to-pin capacitance introduced socket create extremely troublesome parasitic network which make almost impossible achieve smooth, stable frequency response. Best results obtained soldering OPA682 onto board. socketing package desired, high frequency flush-mount pins (e.g., McKenzie Technology #710C) give good results. INPUT PROTECTION OPA682 built using very high speed complementary bipolar process. internal junction breakdown voltages relatively these very small geometry devices. These breakdowns reflected Absolute Maximum Ratings table. device pins have limited protection using internal diodes power supplies shown Figure These diodes provide moderate protection input overdrive voltages above supplies well. protection diodes typically support 30mA continuous current. Where higher currents possible (e.g., systems with ±15V supply parts driving into OPA682), current-limiting series resistors should added into inputs. Keep these resistor values possible since high values degrade both noise performance frequency response.
External
Internal Circuitry
FIGURE Internal Protection.
OPA682
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE OPA682N/250 OPA682N/3K OPA682P OPA682U OPA682U/2K5 STATUS(1) OBSOLETE OBSOLETE OBSOLETE OBSOLETE OBSOLETE PACKAGE TYPE PDIP SOIC SOIC PACKAGE DRAWING PINS PACKAGE
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
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