@echelon Corporation 005-0154-01 Echelon, LON, LONWORKS, Lon
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3120 3150 Power Line Smart Transceiver Data Book
@echelon Corporation
005-0154-01
Echelon, LON, LONWORKS, LonBuilder, NodeBuilder, LonManager, LonTalk, Neuron, LONMARK, 3120, 3150, Echelon logo, LONMARK logo registered trademarks Echelon Corporation. LonMaker, LNS, i.LON, ShortStack, LonSupport trademarks Echelon Corporation. Other brand product names trademarks registered trademarks their respective holders. Smart Transceivers, Neuron Chips, other Products were designed equipment systems which involve danger human health safety risk property damage Echelon assumes responsibility liability Smart Transceivers Neuron Chips such applications. Echelon Corporation developed patented certain methods implementing circuitry external 3120® 3150® Power Line Smart Transceiver chips. These patents licensed pursuant Echelon 3120 3150 Power Line Smart Transceiver Development Support License Agreement. Parts manufactured vendors other than Echelon referenced this document have been described illustrative purposes only, have been tested Echelon. responsibility customer determine suitability these parts each application. ECHELON MAKES RECEIVE WARRANTIES CONDITIONS, EXPRESS, IMPLIED, STATUTORY COMMUNICATION WITH YOU, ECHELON SPECIFICALLY DISCLAIMS IMPLIED WARRANTY MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Except expressly permitted herein, part this publication reproduced, stored retrieval system, transmitted, form means, electronic, mechanical, photocopying, recording, otherwise, without prior written permission Echelon Corporation. Printed United States America. Copyright ©1996-2003 Echelon Corporation. Echelon Corporation www.echelon.com
Table Contents
Chapter -Introduction .1-1 Introduction .1-2 Product Overview .1-2 LonWorks Networks.1-3 Product Families.1-4 Power Line Signaling .1-4 Dual Carrier Frequency Operation.1-5 Forward Error Correction.1-6 Powerful Output Amplifier.1-6 Wide Dynamic Range .1-7 Current Consumption.1-7 Compliant with Regulations Worldwide .1-7 Integrated, Low-Cost Small Form Factor Design.1-8 Electric Utility Home/Commercial/Industrial Applications .1-9 Extensive Development Resources.1-10 Audience .1-10 Content .1-10 Related Documentation.1-10 Chapter -Hardware Resources.2-1 Neuron Processor Architecture .2-3 Memory .2-10 Memory Allocation Overview .2-10 3150 Smart Transceiver Memory Allocation .2-10 3120 Smart Transceiver Memory Allocation .2-11 EEPROM .2-12 Static .2-14 Pre-programmed .2-15 External Memory Interface 3150 Smart Transceiver Only) .2-15 Input/Output .2-16 Twelve Bidirectional Pins .2-16 16-Bit Timer/Counters.2-16 Clock Input .2-17 Band-In-Use (BIU) Packet Detect (PKD) Connections .2-19 TXON Output Signal .2-20 Additional Functions.2-20 Reset Function .2-20
RESET .2-22 Power Sequence.2-23 Software Controlled Reset .2-23 Watchdog Timer .2-24 Considerations .2-24 Reset Processes Timing.2-24 SERVICE .2-31 Integrity Mechanisms .2-33 Memory Integrity Using Checksums .2-33 Reboot Integrity Options Word .2-35 Reset Processing .2-36 Signatures .2-36 Chapter Input/Output Interfaces .3-1 Introduction .3-2 Hardware Considerations .3-3 Timing Issues .3-9 Scheduler-Related Timing Information.3-9 Firmware Hardware Related Timing Information.3-11 Direct Objects .3-12 Input/Output.3-12 Byte Input/Output .3-14 Leveldetect Input .3-15 Nibble Input/Output .3-16 Parallel Objects .3-18 Muxbus Input/Output.3-18 Parallel Input/Output .3-20 Master/Slave Mode .3-20 Slave Mode .3-24 Serial Objects .3-27 Bitshift Input/Output .3-27 Input/Output .3-30 Magcard Input .3-32 Magtrack1 Input .3-34 Magcard Bitstream Input.3-36 Neurowire Input/Output Object.3-37 Neurowire Master Mode .3-38 Neurowire Slave Mode .3-40 Serial Input/Output .3-42
Touch Input/Output .3-44 Wiegand Input .3-47 (UART) Input/Output .3-49 Input/Output .3-50 Timer/Counter Input Objects .3-56 Dualslope Input .3-57 Edgelog Input.3-59 Infrared Input .3-61 Ontime Input .3-62 Period Input .3-63 Pulsecount Input.3-65 Quadrature Input .3-67 Totalcount Input .3-69 Timer/Counter Output Objects.3-71 Edgedivide Output.3-71 Frequency Output.3-73 Infrared Pattern Output.3-74 Oneshot Output .3-75 Pulsecount Output .3-77 Pulsewidth Output .3-79 Triac Output.3-81 Triggered Count Output.3-83 Notes .3-85 Chapter -Coupling Circuits.4-1 Introduction .4-2 Power Line Communications .4-2 Coupling Techniques .4-4 Power Line Coupling Basics.4-4 Power Line Coupling Details.4-8 Safety Issues.4-12 Safety Isolation Considerations .4-12 Ground Leakage Currents.4-14 Capacitor Charge Storage .4-15 Line Surge Protection .4-15 Fuse Selection .4-18 3-Phase Coupling Circuits .4-19 Wall-Plug Coupler Power Supply .4-21 Recommended Coupling Circuit Schematics .4-22
Example 1:Line-to-Neutral (L-to-N), Non-Isolated Coupling Circuit .4-24 Example 2:Line-to-Neutral (L-N), Transformer-Isolated Coupling Circuit4-26 Example 3:Line-to-Earth (L-to-E), Non-Isolated Coupling Circuit.4-28 Example 4:Line-to-Earth (L-E), Transformer-Isolated Coupling Circuit .4-30 Example 5:3-Phase Non-Isolated Coupling Circuit .4-32 Example 6:3-Phase, Transformer-Isolated Coupling Circuit .4-34 Example 13:Line-to-Neutral (L-to-N), Isolated Wall-Plug Power Supply/ Coupler .4-36 Chapter -Power Supplies Smart Transceivers .5-1 Introduction .5-2 Power Supply Design Considerations .5-3 Power Supply-Induced Attenuation.5-3 Power Supply Noise .5-3 Power Supply Voltage Range .5-4 Energy Storage Power Supplies .5-5 Energy Storage Capacitor-Input Power Supplies .5-7 Energy Storage Linear Supplies .5-12 Traditional Linear Power Supplies .5-13 Switching Power Supplies.5-14 Power Supply-Induced Attenuation.5-14 Noise Power Supply Input .5-18 Switching Power Supply Frequency Selection .5-18 Switching Power Supply Input Noise Masks .5-18 Switching Power Supply Output Noise Masks.5-27 Options .5-29 Pre-designed Switching Supplies .5-30 Off-the-Shelf Switching Supplies .5-30 Custom Switching Supplies .5-31 Chapter -Design Test Electromagnetic Compatibility.6-1 Introduction .6-2 Design Issues .6-2 Designing Systems (Electromagnetic Compatibility) .6-2 Design Issues .6-5 Designing Systems Immunity.6-5 Conducted Emissions Testing.6-6
Chapter -Communication Performance Verification.7-1 Introduction .7-2 Verify Communication Performance? .7-2 Verification Strategy .7-3 Power Line Test Isolator .7-3 Test Equipment .7-5 Good Citizen Verification .7-7 Unintentional Output Noise Verification .7-7 Excessive Loading Verification .7-9 Transmit Performance Verification.7-12 Receive Performance Verification.7-14 Packet Error Measurement with Nodeutil .7-14 Verification Procedure .7-15 Chapter -Transceiver Programming.8-1 Introduction .8-2 Dual Carrier Frequency Mode.8-2 CENELEC Access Protocol .8-3 Power Management.8-4 Standard Transceiver Types.8-6 NodeBuilder Tool Support .8-7 3120/PL 3150 Smart Transceiver Channel Definitions .8-7 3120/PL 3150 Smart Transceiver Clock Speed Selection .8-8 Appendix 3120 3150 Smart Transceiver Reference Designs Introduction Reference Design Specifications Appendix 3120/PL 3150 Smart Transceiver-Based Device Checklist. 3120/PL 3150 Smart Transceiver-based Device Checklist. Appendix 3120/PL 3150 Smart Transceiver Isolation Transformer Specifications 12mH-Leakage Transformer Specifications Low-Leakage Transformer Specifications.
Appendix 3120/PL 3150 Smart Transceiver Manufacturing Test Handling Guidelines. Production Test Guidelines. Introduction Physical Layer Production Test Production Test Strategy In-Circuit Test (ICT) Transmitter Performance Verification. Receiver Performance Verification. A/D, based Test System. System Overview. Hardware Description. Software Description. Notes Missed Messages. D-13 Query Waveform D-13 Test System Verification. D-13 Verification Background Noise D-13 Verification Query Message Amplitude D-14 Manufacturing Handling Guidelines D-15 Board Soldering Considerations D-15 Handling Precautions Electrostatic Discharge. D-15 Recommended Reading D-19 Chapter -References. Introduction
Introduction
3120 3150 Power Line Smart Transceiver Data Book
Introduction
Introduction
This manual provides detailed technical specifications electrical interfaces, mechanical interfaces, operating environment characteristics 3120® 3150® Power Line Smart Transceivers ("PL Smart Transceivers"). This manual also provides guidelines migrating applications Smart Transceiver using NodeBuilder® Development Tool. some cases, vendor sources included this manual simplify task integrating Smart Transceivers with application electronics. list related documentation provided section 1.5, Related Documentation, this chapter. documents listed this section found Echelon's site www.echelon.com unless otherwise noted.
Product Overview
3120 3150 Power Line Smart Transceivers provide simple, costeffective method adding LONWORKS® power line signaling networking everyday devices. Compliant with open ANSI/EIA standards, smart transceivers ideal networked appliance, audio/video, lighting, heating/cooling, security, metering, irrigation applications. Representing breakthrough price, performance packaging size, 3120 3150 Power Line Smart Transceivers integrate Neuron® processor core with power line transceiver that fully compatible with LONMARK® PL-20 channel type. Essentially system-on-a-chip, smart transceivers feature highly reliable ANSI/EIA 709.2 compliant, narrow-band power line transceiver, ANSI/EIA 709.1 compliant Neuron processor core running applications managing network communications, choice on-board external memory, extremely small form factor. wide variety pre-designed, low-cost coupling circuit designs enable 3120 3150 Power Line Smart Transceivers communicate over virtually power mains, well over unpowered twisted pair.
3120 3150 Power Line Smart Transceiver Data Book
LonWorks Networks
LONWORKS Networks
almost every industry today, there trend away from proprietary control schemes centralized systems. migration towards open, distributed, peer-topeer LONWORKS networks being driven interoperability, robust technology, faster development time, scale economies afforded LONWORKS based solutions. everyday devices LONWORKS network communicate using ANSI/EIA 709.1 protocol standard. This seven-layer protocol provides services that allow application program device send receive messages from other devices network without needing know topology network functions other devices. LONWORKS networks provide complete suite messaging services, including end-toend acknowledgement, authentication, priority message delivery. Network management services allow network tools interact with devices over network, including local remote reconfiguration network addresses parameters, downloading application programs, reporting network problems, start/stop/ reset device application programs. Neuron Chips, family microprocessors originally designed Echelon licensed third party semiconductor manufacturers, combine ANSI/EIA 709.1 compliant processor core running applications managing network communications, with media-independent communication port, memory, I/O, 48-bit identification number (Neuron that unique every device. communication port permits short distance Neuron Chip-to-Neuron Chip communications, also used with external line drivers transceivers almost type. Neuron 3120 Chip family includes self-contained application program memory external memory bus) real-time operating system (RTOS) application libraries pre-programmed ROM. Neuron 3150 Chip family includes both internal memory external memory bus. Echelon's Smart Transceivers integrate Neuron processor core with ANSI/ 709.2 compliant power line transceiver within single eliminating need external transceiver. variants Smart Transceivers available: 3120 chip includes self-contained application program memory, RTOS, application library pre-programmed ROM. 3150 chip includes both internal memory external memory bus.
3120 3150 Power Line Smart Transceiver Data Book Preliminary Information
Introduction
Product Families
versions 3120 3150 Power Line Smart Transceivers available meet wide range applications packaging requirements.
Maximum Input Clock
10MHz 10MHz
Product Name
Model Number
EEPROM
4Kbytes 0.5Kbytes
2Kbytes 2Kbytes
24Kbytes
External Memory Interface
Package
TSSOP LQFP
3120- E4T10 15310-100 3150-L10 15320-960
3120 Power Line Smart Transceivers targeted small form factor designs that require TSSOP package application code. 3120 operates either 6.5536MHz (A-band) 10.0MHz (C-band), includes EEPROM RAM. Neuron system firmware (RTOS) along with application libraries contained on-chip ROM. applications that require more memory, 3150 Power Line Smart Transceivers operate either 6.5536MHz (A-band) 10.0MHz (C-band), provide 0.5KB EEPROM RAM, LQFP package. Through external memory bus, 3150 Smart Transceiver address 58KB external memory, which 16KB dedicated Neuron system firmware. embedded EEPROM both 3120 3150 devices written 10,000 times with data loss. Data stored EEPROM will retained least years. Both Smart Transceivers have pins which configured operate more predefined standard input/output modes. Combining wide range models with on-board timer/counters hardware SCI/SPI UART enables Smart Transceivers interface application circuits with minimal external logic software development.
Power Line Signaling
underlying signaling technology used 3120 3150 Power Line Smart Transceivers developed optimized through more than years
3120 3150 Power Line Smart Transceiver Data Book
Power Line Signaling
field-testing. Millions Echelon's narrow band transceivers have been deployed wide range consumer, utility, building, industrial, transportation applications worldwide. Features such narrow-band BPSK signaling, dual carrier frequency operation, adaptive carrier data correlation, impulse noise cancellation, tone rejection low-overhead error correction provide superior reliability face interfering noise sources. 3120 3150 Power Line Smart Transceivers communicate with products based Echelon's earlier generation PLT-22, PLT-21 PLT-20 power line transceivers operating same band.
Dual Carrier Frequency Operation
3120 3150 Smart Transceivers utilize dual-carrier frequency signaling technology provide superior communication reliability face interfering noise sources. case acknowledged messaging, packets initially transmitted primary frequency acknowledgement received packet retransmitted secondary frequency. case unacknowledgedrepeat messaging, packets alternately transmitted primary secondary frequencies. utility applications primary secondary communication frequencies within A-band shown Figure 1.1. non-utility applications, primary communication frequency lies C-band shown Figure while secondary frequency actually lies what called B-band CENELEC nomenclature. Figure illustrates primary secondary communications into various frequency bands.
3120 3150 Power Line Smart Transceiver Data Book Preliminary Information
Introduction
Band Designations
Electricity Suppliers
Restricted
20kHz
40kHz
60kHz
80kHz
100kHz
120kHz
140kHz
160kHz
Figure CENELEC Frequency Band Designations
Utility Applications A-Band Communication Non-utility Applications C-Band Communication
Restricted
Secondary Frequency Primary Frequency
Secondary Frequency Primary Frequency
20kHz
40kHz
60kHz
80kHz
100kHz
120kHz
140kHz
160kHz
Figure Dual-Carrier Frequency Operation
3120 3150 Power Line Smart Transceiver Data Book
Power Line Signaling
Forward Error Correction
Many noise sources interfere with power line signaling corrupting data packets. 3120 3150 Smart Transceivers highly efficient, low-overhead forward error correction (FEC) algorithm addition cyclical redundancy check (CRC) overcome packet errors.
Powerful Output Amplifier
external, high performance amplifier design developed with Smart Transceivers provides output impedance 1Ap-p current capability drive high output levels into impedance circuits, while maintaining extremely signal distortion levels necessary meet stringent international regulations.
Wide Dynamic Range
Dynamic range relates sensitivity receiver. 3120 3150 Smart Transceivers have dynamic range 80dB. quiet line Power Line Smart Transceivers receive signals that have been attenuated factor 10,000.
Current Consumption
3120 3150 Power line Smart Transceivers their associated power amplifier circuitry powered user-supplied +8.5 +18VDC (VA) +5VDC (VDD5) power supplies. Built-in power management features, combined with wide supply range, benefits when designing inexpensive power supplies. Power management especially useful high volume, cost consumer products such electrical switches, outlets, incandescent light dimmers. Very receive mode current consumption just 350µA typical from supply typical from VDD5 supply reduces power supply size cost. 3120 3150 Smart Transceivers communicate rate 5.4kbps (C-band) 3.6kbps (A-band), corresponding maximum packet rates packets second, respectively. This high throughput makes transceivers well suited residential, commercial, industrial automation applications.
3120 3150 Power Line Smart Transceiver Data Book Preliminary Information
Introduction
Compliant with Regulations Worldwide
3120 3150 Power Line Smart Transceivers designed comply with [1], Industry Canada, Japan MPT, European CENELEC EN50065-1 regulations [2], allowing them used applications worldwide. CENELEC communications protocol fully implemented Smart Transceivers, eliminating need users develop complex timing access algorithms mandated under CENELEC EN50065-1. Additionally, Smart Transceivers operate either CENELEC utility (A-band) consumer (C-band) bands. Figure above shows CENELEC frequency restrictions that mandatory countries observed many non-EU countries well. FCC, Industry Canada Japan regulations less strict than CENELEC requirements. frequency allocations these countries summarized Figure 1.3.
Restrictions Under Consideration
Restricted
100kHz
200kHz
300kHz
400kHz
500kHz
600kHz
700kHz
Figure FCC, Industry Canada, Japan Power-line Signaling
Integrated, Low-Cost Small Form Factor Design
small number inexpensive external components required create complete Smart Transceiver-based device. Figure illustrates block diagram Smart Transceiver based device. comprehensive Development Support (DSK) that includes schematics, printed circuit board (PCB) layouts, bills materials, with which customers implement this interface circuitry, available from Echelon.
3120 3150 Power Line Smart Transceiver Data Book
Electric Utility Home/Commercial/Industrial Applications
3120 3150 Smart Transceiver Reference Design Appendix
Coupling Circuit Chapter
Power Mains
User's Application Electronics
VDD5
Power Supply Chapter
LonWorks Node Chapters 6,7,8
Figure LONWORKS Device Block Diagram
Electric Utility Home/Commercial/Industrial Applications
3120 3150 Power Line Smart Transceivers designed operate frequency ranges (LONWORKS channels) depending application. When configured electric utility applications, smart transceivers communicate A-band frequency range. home/commercial/industrial applications, they communicate C-band frequency range. separate operating frequency bands utility non-utility applications originated Europe since become facto standard because numerous benefits provides terms bandwidth management, security privacy.
3120 3150 Power Line Smart Transceiver Data Book Preliminary Information
Introduction
Extensive Development Resources
wide assortment technical documentation, diagnostic tools, support programs, training courses available assist customers with their projects. Additionally, Echelon offers fee-based pre-production design reviews customer's products, schematics, layouts, bills material verify that they comply with published guidelines. Performance verification testing provided customers submit working devices.
Audience
3120/PL 3150 Power Line Smart Transceiver Databook provides specifications user instructions 3120 3150 Power Line Smart Transceiver customers.
Content
This User's Guide describes Smart Transceivers both utility (Aband) home/commercial/industrial (C-band) applications.
Related Documentation
following documents suggested reading: 3120 3150 Smart Transceiver Data Sheet (003-0250-01) Neuron Programmer's Guide (078-0002-02F) Neuron Reference Guide (078-0140-02D) Neuron 3150 Chip External Memory Interface Engineering Bulletin (005-0013-01D) LONWORKS Microprocessor Interface Program User's Guide (078-0017-01)
1-10
3120 3150 Power Line Smart Transceiver Data Book
Related Documentation
NodeBuilder User's Guide (078-0141-01D) Parallel Interface Neuron Chip Engineering Bulletin (005-0021-01C) PLCA-22 Power Line Communication Analyzer User's Guide (078-0147-01) Power Line SLTA Adapter Power Line PSG/3 User's Guide (078-0188-01A) LONWORKS PCLTA-20 Interface User's Guide (078-0179-01C) Neuron Chip Quadrature Input Function Interface Engineering Bulletin (005-0003-01)
3120 3150 Power Line Smart Transceiver Data Book Preliminary Information
1-11
Introduction
1-12
3120 3150 Power Line Smart Transceiver Data Book
Hardware Resources
3120 3150 Power Line Smart Transceiver Data Book
Hardware Resources
3120 Smart Transceiver complete system-on-a-chip designs that require memory while 3150 Smart Transceiver supports external memory more complex applications. major hardware blocks both processors same, except where noted; Table Figure 2.1. Table Comparison Smart Transceivers
Characteristic Bytes Bytes EEPROM Bytes General purpose pins 16-Bit Timer/Counters External Memory Interface Package 3150 Smart Transceiver 2,048 LQFP 3120 Smart Transceiver 2,048 24,576 4,096 TSSOP
3120/PL 3150 Smart Transceiver Power Line Transceiver Neuron Core
Media Access Control, Network, Application Processor Internal Data (0:7) Transmitter Receiver
External Circuitry TXDAC VCORE TXBIAS TXSENSE RXIN INTIN INTOUT
Coupling Circuit
Power Mains
Internal Address (0:15)
Block
IO11
Timer/ Counters
EEPROM (0.5 EEPROM 3150)
Oscillator, Clock, Control
3120 only)
XOUT SERVICE RESET External Address/Data 3150 Smart Transceiver Only)
Figure Smart Transceiver Block Diagram
3120 3150 Power Line Smart Transceiver Data Book
Neuron Processor Architecture
Neuron Processor Architecture
Neuron core composed three processors. These processors assigned following functions Neuron firmware. Processor layer processor that handles layers 7-layer LonTalk® protocol stack. This includes driving communications subsystem hardware executing media access control algorithm. Processor communicates with Processor using network buffers located shared memory. Processor network processor that implements layers through LonTalk protocol stack. handles network variable processing, addressing, transaction processing, authentication, background diagnostics, software timers, network management, routing functions. Processor uses network buffers shared memory communicate with Processor application buffers communicate with Processor These buffers also located shared memory. Access them mediated with hardware semaphores resolve contention when updating shared data.
Communications Port Input/Output
Processor
Network Processor
Application Processor
Network Buffers
Application Buffers
Shared
Figure Processor Shared Memory Allocation
3120 3150 Smart Transceiver Data Book
Hardware Resources
Processor application processor. executes code written user, together with operating system services called user code. primary programming language used applications Neuron derivative ANSI language optimized enhanced LONWORKS distributed control applications. major enhancements following (see Neuron Programmer's Guide details):
network communication model, based functional blocks network variables, that simplifies promotes data sharing between like disparate devices.
network configuration model, based functional blocks configuration properties, that
facilitates interoperable network configuration tools.
type model based standard user resource files that expands market interoperable devices simplifying integration devices from multiple manufacturers.
extensive drivers that support capabilities Neuron core. Powerful event driven programming extensions that provide easy handling network, I/O,
timer events. support these capabilities part Neuron firmware, does need written programmer. Each three identical processors register (Table 2.2), three processors share data, ALUs (arithmetic logic units) memory access circuitry (Figure 2.3). 3150 Smart Transceiver, internal address, data, signals reflected corresponding external lines when utilized internal processors. Each minor cycle consists three system clock cycles, phases; each system clock cycle input clock cycles. minor cycles three processors offset from another system clock cycle, that each processor access memory ALUs once during each instruction cycle. Figure shows active elements each processor during three phases minor cycle. Therefore, system pipelines three processors, reducing hardware requirements without affecting performance. This allows execution three processes parallel without time-consuming interrupts context switching.
3120 3150 Power Line Smart Transceiver Data Book
Neuron Processor Architecture
Table Register
Mnemonic FLAGS Bits Contents Number, Fast Select, Carry Next Instruction Pointer Address 256-byte Base Page Data Stack Pointer Within Base Page Return Stack Pointer Within Base Page Data Stack, Input
Processor Registers
Processor Registers
Processor Registers
ALUs
Active elements Processor Latch Active elements Processor Memory
Active elements Processor
Latch
Figure Processor/Memory Activity During Three System Clock Cycles Minor Cycle
3120 3150 Smart Transceiver Data Book
Hardware Resources
architecture stack-oriented; 8-bit wide stack used data references, operates (Top Stack) register next entry data stack which RAM. second stack stores return addresses CALL instructions, also used temporary data storage. This stack architecture leads very compact code. Tables 2.3, 2.4, outline instruction set. Figure shows layout base page, which bytes long. Each three processors uses different base page, whose address given contents register that processor. data stack 8-bit register, next element data stack location within base page offset given contents register. data stack grows from memory towards high memory. assembler shorthand symbol NEXT refers contents location (BP+DSP) memory, which actual processor register. Pushing byte data onto data stack involves following steps: incrementing register, storing current contents address (BP+DSP) memory, moving byte data TOS. Popping byte data from data stack involves following steps: moving destination, moving contents address (BP+DSP) memory TOS, decrementing register. return stack grows from high memory towards memory. Executing subroutine call involves following steps: storing high byte instruction pointer register address (BP+RSP) memory, decrementing RSP, storing byte address (BP+RSP) memory, decrementing RSP, moving destination address register.
3120 3150 Power Line Smart Transceiver Data Book
Neuron Processor Architecture
Similarly, returning from subroutine involves following steps: incrementing RSP, moving contents (BP+RSP) byte register, incrementing RSP, moving contents (BP+RSP) high byte
Return Stack BP+RSP BP+DSP NEXT Data Stack BP+0x18 BP+0x17 Sixteen Byte Registers BP+0x8 BP+0x7 Four 16-bit Pointer Registers Base Page.
Figure Base Page Memory Layout
processor instruction cycle three system clock cycles, input clock (XIN) cycles. Most instructions take between seven processor instruction cycles. input clock rate 10MHz, instruction times vary between Execution time scales inversely with input clock rate. formula instruction time (Instruction Time) Cycles) (Input Clock) Tables 2.3, 2.4, list processor instructions, their timings cycles) sizes bytes). This provided purposes calculating execution time size code sequences. programming Smart Transceiver done with Neuron using NodeBuilder development tool. Neuron compiler optionally produce assembly listing, examining this listing help programmer optimize Neuron source code.
3120 3150 Smart Transceiver Data Book
Hardware Resources
Table Program Control Instructions
Mnemonic BR/BRC/ BRNC SBRZ/SBRNZ BRZ/BRNZ BRNEQ DBRNZ Cycles Size (bytes) Description operation Short unconditional branch Branch, branch (not) carry Short branch (not) zero Unconditional branch Branch (not) zero Return from subroutine Branch equal (taken/not taken) Decrement [RSP] branch zero Call subroutine relative Call subroutine Call subroutine Offset Offset -128 +127 Offset Drops Absolute address Offset -128 +127. Drops Drops bytes from return stack Offset -128 +127. Drops equal Offset -128 +127. taken, drops byte from return stack Offset -128 +127. Pushes bytes return stack Address 8KB. Pushes bytes return stack Absolute address. Pushes bytes return stack Comments
CALLR CALL CALLF
3120 3150 Power Line Smart Transceiver Data Book
Neuron Processor Architecture
Table Memory/Stack Instructions
Mnemonic PUSH DROP DROP_R PUSH (NEXT, DSP, RSP, FLAGS) (DSP, RSP, FLAGS) DROP NEXT DROP_R NEXT PUSH/POP PUSH !TOS !TOS PUSH [RSP] DROP [RSP] PUSHS #literal PUSH #literal PUSHPOP POPPUSH LDBP address PUSH/POP [DSP][-D] PUSHD #literal PUSHD [PTR] POPD [PTR] PUSH/POP [PTR][TOS] PUSH/POP [PTR][D] PUSH/POP absolute IN/OUT Cycles Size (bytes) Comments Effective Address (EA) Increment DSP, duplicate into NEXT Move NEXT TOS, decrement Move NEXT TOS, decrement DSP, return from call Push processor register processor register Decrement Decrement return from call Byte register TOS, push byte NEXT TOS, byte from NEXT Push from return stack data stack, unchanged Increment Push short literal value Push 8-bit literal value 255] from return stack, push data stack from data stack, push return stack Load base page pointer with 16-bit value displacement 16-bit literal value (high byte first) Push from 16-bit pointer high byte first 16-bit pointer byte first (16-bit pointer) (16-bit pointer) displacement 255] Absolute memory address Fast instruction, transfer bytes
3120 3150 Smart Transceiver Data Book
Hardware Resources
Table Instructions
Mnemonic INC/DEC/NOT ROLC/RORC SHL/SHR SHLA/SHRA ADD/AND/OR/XOR/ADC ADD/AND/OR/XOR #literal (ADD/AND/OR/XOR)_R ALLOC #literal DEALLOC_R #literal NEXT,TOS NEXT, TOS,NEXT [PTR] Cycles Size (bytes) Operation Increment/decrement/negate Rotate left/right through carry Unsigned left/right shift TOS, clear carry Signed left/right shift into carry Operate with NEXT TOS, drop NEXT Operate with literal Operate with NEXT TOS, drop NEXT return data stack pointer Subtract from data stack pointer return NEXT TOS, drop NEXT NEXT carry, drop NEXT NEXT, drop NEXT Exchange NEXT Increment 16-bit pointer
Memory
Memory Allocation Overview
3150 Smart Transceiver Memory Allocation
Figure memory 3150 Smart Transceiver.
bytes in-circuit programmable EEPROM that store following:
Network configuration addressing information. Unique 48-bit Neuron written factory. User-written application code read-mostly data. Table available EEPROM space.
2,048 bytes static that store following:
Stack segment, application, system data. Network application buffers.
2-10
3120 3150 Power Line Smart Transceiver Data Book
Memory
processor access 59,392 bytes available 65,536 bytes memory address space
external memory interface. remaining 6,144 bytes memory address space mapped internally.
16,384 bytes external memory (59,392 bytes total) required store following:
Neuron firmware, including system firmware executed Network processors, executive supporting application program.
rest external memory (43,008 bytes) available for:
User-written application code. Additional application read/write non-volatile data. Additional network buffers application buffers.
3120 Smart Transceiver Memory Allocation
Figure memory 3120 Smart Transceiver.
4,096 bytes in-circuit programmable EEPROM that store:
Network configuration addressing information. Unique 48-bit Neuron written factory. User-written application code read-mostly data.
2,048 bytes static that store following:
Stack segment, application, system data. Network buffers application buffers.
24,576 bytes that store following:
Neuron firmware, including system firmware executed network processors, executive supporting application program, application libraries.
3120 3150 Smart Transceiver Data Book
2-11
Hardware Resources
FFFF FC00 FBFF
FFFF Reserved Space Memory Mapped 2.5KB Reserved Space FC00 FBFF
Reserved Space Memory Mapped
F200 F1FF F000 EFFF
Internal 0.5KB EEPROM F000 EFFF EEPROM Internal
E800 E7FF 42KB Memory Space Available User External 4000 3FFF 16KB Neuron Firmware Reserved Space
E800 Unavailable 83FF EEPROM 8000 Unavailable
5FFF 0000 24KB Neuron Firmware (ROM)
0000
Figure 3150 Smart Transceiver Memory
Figure 3120 Smart Transceiver Memory
EEPROM
Both versions Smart Transceiver have internal EEPROM containing:
Network configuration addressing information. Unique 48-bit Neuron Optional user-written application code data tables.
bytes EEPROM written under program control using onchip charge pump generate required programming voltage. charge pump operation transparent user. remaining bytes written during
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Memory
manufacture, contain unique 48-bit identifier each part called Neuron plus bits chip manufacturer's device code. Each byte EEPROM region written 10,000 times. both 3120 3150 Smart Transceivers, EEPROM stores installation-specific information such network addresses communications parameters. 3120 Smart Transceiver, EEPROM also stores application program generated NodeBuilder development tool. application code 3150 Smart Transceiver stored either on-chip EEPROM memory off-chip external memory depending size application code. Table available EEPROM space. write operations internal EEPROM, Neuron firmware automatically compares value EEPROM location with value written. same, write operation performed. This prevents unnecessary write cycles EEPROM, reduces average EEPROM write cycle latency. When Smart Transceiver within specified power supply voltage range, pending on-going EEPROM write guaranteed. Smart Transceiver contains built-in low-voltage interruption (LVI) circuit that holds chip reset when VDD5 below certain voltage. 3120 3150 Smart Transceiver Datasheet trip points. This reduces risk EEPROM data corruption. 3150 Smart Transceiver devices with external FLASH memory external pulse stretching required. RESET section more information circuitry. event fault, on-chip EEPROM 3150 Smart Transceiver reset factory default state executing EEBLANK program. program appropriate EEBLANK file into external memory device, temporarily replace application's external flash with chip that EEBLANK loaded, power device. EEBLANK files named eeb<n>.nri where Neuron input clock rate following: 20000, 10000, 05000, 02500, 01250, 00625. using input clock between these speeds, select next slower version EEBLANK. After around seconds less depending clock speed), device's service should come solid, indicating that EEPROM been blanked. Then replace original application flash. EEBLANK files distributed with NodeBuilder newer development tools. Versions EEBLANK distributed with prior releases LonBuilder NodeBuilder tools should used with 3150 Smart Transceiver.
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Hardware Resources
set_eeprom_lock() function also used additional protection against accidental EEPROM data corruption. This function allows application program state lock checksummed portion EEPROM. Refer Neuron Reference Guide more information. internal EEPROM Smart Transceiver will contain fixed amount overhead network image (configuration), addition user code user data. following table shows maximum amount EEPROM space available user code user data assuming minimally-sized network image. Also shown minimum segment size user data. Constant data assumed part code space. Table Memory Usage
Device 3120 Smart Transceiver 3150 Smart Transceiver Firmware Version newer EEPROM Space (Bytes) 3969 Segment Size (Bytes)
EEPROM must allocated increments device's segment size, smallest unit EEPROM that allocated variable space. example, there three 3-byte variables used, there must bytes variable space. 3120 Smart Transceiver, this would result allocation bytes variable space, bytes lowest increment device segment size bytes) that store three 3-byte variables. 3150 Smart Transceiver, this would result allocation bytes variable space, bytes lowest increment device segment size bytes) that store three 3-byte variables.
Static
3120 3150 Smart Transceivers contain 2048 bytes static RAM. used store following:
Stack segment, application, system data Network buffers application buffers
state retained long power applied device. After reset, releasing Smart Transceiver initialization sequence will clear (see Reset Process Timing section later this chapter).
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Memory
Pre-programmed
3120 Smart Transceiver contains 24,576 bytes pre-programmed ROM. This memory contains Neuron firmware, including LonTalk protocol stack, real time task scheduler, system function libraries. Neuron firmware 3150 Smart Transceiver stored external memory. object code supplied with NodeBuilder tool.
External Memory Interface 3150 Smart Transceiver Only)
This interface supports Bytes external memory space additional user program data. total address space Bytes. However, upper address space reserved internal RAM, EEPROM, memory-mapped (see Figures 2.6), leaving Bytes external address space. this space, Bytes used Neuron firmware. external memory space populated with RAM, ROM, PROM, EPROM, EEPROM, flash memory increments bytes. memory 3150 Smart Transceiver shown Figure 2.5. bidirectional data lines address lines driven processor. interface lines (R/W used external memory access. Refer 3150 Smart Transceiver Datasheet required access times external memory used. input clock rates supported 3150 Smart Transceiver 10MHz 6.5536MHz. Enable Clock runs system clock rate, which one-half input clock rate. memory, both internal external, accessed three processors appropriate phase instruction cycle. Since instruction cycles three processors offset one-third cycle with respect each other, memory used only processor time. Neuron 3150 Chip External Memory Interface engineering bulletin provides guidelines interfacing 3150 Smart Transceiver different types memory. minimum hardware configuration would external (PROM EPROM), containing both Neuron firmware user application code. This configuration would allow system engineer change application code over network after installation. network image (network address connection information) however, could altered because this information resides internal EEPROM. application downloads over network requirement maintenance upgrade application code will into internal EEPROM, then external EEPROM flash will necessary. Refer Neuron Programmer's Guide guidelines reduce code size. pins used interface with external memory listed Table 2.7. clock signal used generate read write) signals external memory.
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Hardware Resources
(address line programmable array logic (PAL) decoded signal gated with used generate read signals external memory. Table External Memory Interface Pins
Designation Direction Output Input/Output Output Output Function Address Pins Data Pins Enable Clock Read/Write Select
preferred method interfacing Smart Transceiver another through pins using serial parallel connection, through dual-ported device such Cypress CY7C144, CY7C138, CY7C1342. There predefined serial parallel models this purpose which easily implemented using Neuron programming language firmware used simplify interface. more details dual-ported interfacing, Appendix LONWORKS Microprocessor Interface Program User's Guide (Echelon 078-0017-01).
Input/Output
Twelve Bidirectional Pins
These pins usable several different configurations provide flexible interfacing external hardware access internal timer/counters. logic level output pins read back application processor. Pins IO11 have programmable pull-up current sources. They enabled disabled with compiler directive (see Neuron Reference Guide). Pins have high current sink capability others have sink capability pins (IO0 IO11) have level inputs with hysteresis. Pins also have level detect latches.
16-Bit Timer/Counters
timer/counters implemented load register writable processor, 16bit counter, latch readable processor. 16-bit registers accessed byte time. Both 3150 3120 Smart Transceivers have timer/
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Clock Input
counter whose input selectable among pins IO7, whose output IO0, second timer/counter with input from output (Figure 2.7). pins dedicated timer/counter functions. example, Timer/Counter used input signals only, then available other input output functions. Timer/counter clock enable inputs from external pins, from scaled clocks derived from system clock; clock rates timer/ counters independent each other. External clock actions occur optionally rising edge, falling edge, both rising falling edges input.
System Clock Divide Chain
System Clock Divide Chain
Control Logic
Timer/Counter
Control Logic
Timer/Counter
Figure Timer/Counter Circuits
Clock Input
3120 3150 Smart Transceivers require input clock 6.5536MHz A-band operation 10.0000MHz C-band operation. input clock provided connection appropriate parallel resonant crystal, unbuffered inverter resistor XOUT pins Smart Transceiver shown Figure 2.8.
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Hardware Resources
VCORE 6.5536MHz A-band (10.000MHz C-band) XOUT Toshiba TC7SLU04FU ohms
3120/PL 3150 Smart Transceiver
Figure Smart Transceiver crystal clock connections
load capacitance provided combination Smart Transceiver, Toshiba TC7SLU04 unbuffered inverter capacitance each reference design from Appendix 18pF from XOUT. correct frequency oscillation achieved parallel resonant crystal with load capacitance rating 18pF used. Smart Transceiver requires clock with frequency accuracy ±200ppm over full range component tolerances operating conditions. load variation Smart Transceiver uses portion overall ±200ppm budget. remaining portion error budget allocated total crystal uncertainty ±85ppm (assuming that selected crystal load capacitance specification which matches circuit loading described above). Total crystal uncertainty combination crystal's initial frequency tolerance plus temperature aging tolerances. load capacitance specification crystal matched circuit then there will nominal frequency error that will reduce portion error budget that available crystal uncertainty. example using 20pF crystal HC49U package will result nominal frequency about 40ppm above specified nominal frequency. Thus using crystal with load capacitance different from actual circuit load (20pF 18pF) constrains total available crystal tolerance just +45/-125ppm.
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Band-In-Use (BIU) Packet Detect (PKD) Connections
10.0000MHz clock signal already available elsewhere C-band circuit board (6.5536MHz A-band board) then used clock source Smart Transceiver long clock signal meets several requirements. First clock must have accuracy ±200ppm over operating conditions. duty cycle symmetry must worse than 60/40% when connected 33pF load measured using 0.9V threshold. addition voltage swing clock signal must within VDD5 supply rails Smart Transceiver. this clock option appropriate clock signal connected 3120 3150 Smart Transceiver, unbuffered inverter resistor shown Figure eliminated XOUT Smart Transceiver left open. Note also that appropriate high frequency clock distribution techniques must used ensure that clean clock signal present Smart Transceiver. accuracy clock oscillator should checked during design verification phase every Smart Transceiver based product. This measurement must made without adding capacitance either XOUT pins Smart Transceiver. Holding probe near touching clock lines then connecting this probe spectrum analyzer with accurate time-base provides make this measurement without affecting frequency oscillation.
Band-In-Use (BIU) Packet Detect (PKD) Connections
Smart Transceiver supplies output signals, BIU, that intended drive low-current light-emitting diodes (LEDs). Both signals activehigh must connected separate LEDs, with series current-limiting resistors added between LEDs ground. Band-In-Use detector, defined under CENELEC 50065-1:2001, must active whenever signal that exceeds 86dBµVrms anywhere frequency range 131.5kHz 133.5kHz present least 4ms. Band-In-Use detector defined CENELEC 50065-1:2001 part CENELEC access protocol. 3120/ 3150 Smart Transceiver incorporates CENELEC access protocol, Smart Transceiver programmed enable disable operation (See CENELEC Access Protocol Chapter When Smart Transceiver programmed such that CENELEC access protocol enabled, signal active high whenever CENELEC-defined conditions Band-In-Use met. When CENELEC access protocol disabled, active signal does prevent Smart Transceiver from transmitting.
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Hardware Resources
Band-In-Use function defined CENELEC C-band required A-band operation. When Smart Transceiver programmed with proper A-band transceiver parameters, described Chapter active signal does prevent Smart Transceiver from transmitting. signal active whenever LonTalk packet addressed device being received Smart Transceiver. receive sensitivity transceiver considerably greater than that indicator. signal will active when 3120/PL 3150 Smart Transceiver receives packets whose signal level small 36dBµVrms. Thus uncommon indicator signal that packet present without indicator turning this occurs cases where received packet signal strength less than threshold. protection diodes should connected applications where signals drive LEDs that could subject exceeding 2kV. Refer Design Issues section Chapter recommendations regarding protection. applications where LEDs surrounded metallic ground plane, such hole grounded metal enclosure, diodes necessary.
TXON Output Signal
TXON buffered version internal signal used control transceiver's output amplifier. TXON signal output active high when Smart Transceiver transmits packets. TXON used drive low-current indicate transmit activity. series current-limiting resistor required between ground. protection diodes should connected this applications where TXON signal line could subject exceeding
Additional Functions
Reset Function
reset function critical operation embedded microcontroller. case 3120/PL 3150 Smart Transceivers, reset function plays role following conditions:
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Additional Functions
Initial VDD5 power (ensures proper initialization Smart Transceiver). VDD5 power fluctuations (manages proper recovery Smart Transceiver after VDD5 stabilizes). Program recovery application gets lost corruption address data, external
reset used recovery watchdog timer could timeout, causing watchdog reset).
VDD5 power down (ensures proper shut down). Helps protect EEPROM from major corruption.
Smart Transceivers have four mechanisms initiate reset:
RESET pulled then returned high. Watchdog timeout occurs during application execution (the timeout period 840ms 10MHz;
this figure scales inversely with clock frequency).
Software command either from application program from network. circuit detects drop power supply below level.
When reset, Smart Transceiver's pins states described list below. Figure 2.10 shows state pins during reset initialization sequence just after reset.
Oscillator continues processor functions stop SERVICE goes high impedance pins high impedance address pins 0xFFFF 3150 Smart Transceiver only) data pins become outputs with states 3150 Smart Transceiver only) clock goes high 3150 Smart Transceiver only) goes 3150 Smart Transceiver only)
When RESET released back high state, Smart Transceiver begins initialization procedure starting address 0x0001. time takes Smart Transceiver complete initialization differs between Smart Transceivers, different firmware versions that being run, memory space used application (code data). This will discussed later this section.
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Hardware Resources
RESET
RESET both input output. input, RESET internally pulled high current source acting pull-up resistor. RESET becomes output when following events occur:
Watchdog Timer timeout. Software reset. Internal detects voltage. RESET drops below internal trip point.
some cases, external circuitry required RESET line. additional device connected RESET line, capacitor least 100pF less than 1000pF should connected between RESET ground provide noise immunity. Examples additional devices pushbuttons, microcontrollers, external pulse stretching LVIs. capacitance must exceed 1000pF order guarantee Smart Transceiver successfully drive RESET below 0.8V. even greater noise immunity, capacitors (totaling <1000pF) used with from RESET ground other from RESET VDD5. in-circuitry test during manufacturing, single test point recommended with very short trace length control RESET. 3120 Smart Transceiver with devices attached RESET pin, external capacitance required noise immunity. 3150 Smart Transceiver, external pulse-stretching greater than should used (Echelon recommends using Dallas Semiconductor Part DS1233-5). capacitor least 100pF less than 1000pF should also connected between RESET ground provide noise immunity. Figure shows typical circuit 3150 Smart Transceiver. Important: RESET should hard wired ground "pogo pin" during board level testing such circuit testing). 3120/PL 3150 Smart Transceivers sensitive disruptions VDD5 transients RESET during time performing initial (one time) boot initialization sequence. WARNING: proper external reset circuitry used, Smart Transceiver applicationless unconfigured. applicationless unconfigured state occurs when checksum error verification routine detects corruption memory which could have falsely been detected improper reset sequence noise
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Additional Functions
power supply. Several options exist NodeBuilder tool allow reboot checksum failure.
Power Sequence
During power sequences, RESET will held internal until power supply stable, prevent start-up malfunctioning. Likewise, when powering down, Smart Transceiver RESET will state when power supply goes below minimum operating voltage Smart Transceiver.
Software Controlled Reset
When watchdog timer expires, software command reset occurs, RESET pulled clock cycles.
Smart Transceiver
VDD5 Other Devices
RESET
RESET
Switch
external pulse-stretching must always used with 3150 Smart Transceiver (Dallas DS1233-5).
(100 1000 Max)
Figure Example Reset Circuit with Additional Device RESET Line
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Hardware Resources
Watchdog Timer
Smart Transceivers protected against malfunctioning software memory faults three watchdog timers, each processor that makes Neuron core. application system software fails reset these timers periodically, entire Smart Transceiver automatically reset. watchdog period approximately 10MHz input clock rate scales inversely with input clock rate. Watchdog Timer circuit cannot disabled.
Considerations
3120 3150 Smart Transceivers include internal ensure that they only operate above minimum voltage threshold. 3120 3150 Smart Transceiver Datasheets trip points. When using external oscillator drive 3150 3120 Smart Transceivers, power-on-pulse-stretching needed ensure that external oscillator stabilized before Smart Transceiver released from reset. Since RESET Smart Transceiver bidirectional, external must have open-drain open-collector output. external actively drives RESET high, then Smart Transceiver will able reliably assert RESET (low) during internal resets. This contention Smart Transceiver RESET cause anomalous behavior, from applicationless errors physical damage Smart Transceiver reset circuitry.
Reset Processes Timing
During reset period, pins high-impedance state. 3150 Smart Transceiver address lines forced 0xFFFF, forced forced data lines driven low, they will float draw excess current. SERVICE high impedance during reset internal pullup disabled. Reset overrides effect clock data lines that, normal operations data only driven write cycle during clock portion cycle, while reset forces data driven. steps followed preparing Smart Transceiver execute application code discussed below. These steps summarized Figure 2.10.
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Additional Functions
After RESET released, Smart Transceiver performs hardware firmware initialization before executing application programs. These tasks are:
Oscillator start-up Oscillator stabilization Stack initialization built-in self-test (BIST) SERVICE initialization State initialization Off-chip initialization Random number seed calculation System setup Communication port initialization Checksum initialization One-second timer initialization Scheduler initialization
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Hardware Resources
Specified Application
Specified Application
Scheduler Init One-Second Timer Init Checksum Init Comm Port Init System Setup Random Number Seed Calc
Stable Address Reflecting Firmware Execution Stable Data Reflecting Firmware Execution Stable Reflecting Firmware Execution
Off-Chip
Oscillates Divide CLK1
State Init
Pull-Ups Disabled
SERVICE Init Stack Init BIST Oscillator Stabilization*
Oscillates
Oscillator Start-Up*
3150 ONLY
DATA [7:0]
[11, 7:4]
*NOTE: power oscillator will start running before RESET released.
Figure 2.10 RESET Timeline 3120 3150 Smart Transceivers 2-26 3120 3150 Power Line Smart Transceiver Data Book
[10:8, 3:0]
ADDR [15:0]
SERVICE
RESET
WARNING: SCALE
Additional Functions
During internal oscillator start (after power up), Smart Transceiver waits oscillator signal amplitude grow before using oscillator waveform system clock. This period depends type oscillator used frequency, begins soon power applied oscillator independent RESET pin. After oscillator started Smart Transceiver counts additional transitions allow oscillator's frequency stabilize. From time RESET asserted until oscillator stabilization period, pins high-impedance state. signal goes inactive (high) immediately after reset goes low, address becomes high (0xFFFF) deselect external devices. stack initialization BIST task tests on-chip RAM, timer/counter logic, counter logic. test pass, three processors must functioning. flag indicate whether Smart Transceiver passed failed BIST. cleared this step. SERVICE oscillates between solid weak high. memory interface signals reflect execution these tasks. self-test fails, device goes offline, service comes solid, error logged device's status structure. Self-test results available first byte (0xE800) follows:
Value Description Failure failure Timer/counter failure Counter failure Configured input clock rate exceeds chip maximum
SERVICE initialization task turns SERVICE (high state). state initialization task determines Smart Transceiver boot required 3150 Smart Transceiver only), performs boot required. Smart Transceiver decides perform boot blank, boot does match boot ROM. off-chip initialization task checks memory determine offchip present then either tests clears off-chip optionally, clears application area only. This choice controlled
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Hardware Resources
application program Neuron compiler directive. This task applies only 3150 Smart Transceiver. random number seed calculation task creates seed random number generator. system setup task sets internal system pointers well linked lists system buffers. checksum initialization task generates checks checksums nonvolatile writable memories. boot process executed configured unconfigured states, state initialization task, then checksums generated; otherwise, they checked. This process includes on-chip EEPROM, offchip EEPROM, flash, off-chip nonvolatile RAM. There checksums, configuration image application image. each case, checksum negated two's complement values image. one-second timer initialization task initializes one-second timer. this point, network processor available accept incoming packets. scheduler initialization task allows application processor perform application-related initialization follows:
State wait wait device leave applicationless state. Pointer initialization perform global pointer initialization. Initialization step execute initialization task, which created compiler/linker handle initialization static variables timer/counters.
initialization step initialize pins based application definition. Prior this
point, pins high impedance.
State wait wait device leave unconfigured hard-offline state. waiting
required, flag indicate that device should come offline.
Parallel synchronization devices using parallel attempt execute master/slave
synchronization protocol this point.
Reset task execute application reset task (when (reset){}). offline flag set, offline execute offline task (when(offline){}). BIST
flag indicated failure, then SERVICE turned offline task executed. Otherwise, scheduler starts normal task scheduling loop. amount time required perform these steps depends many factors, including: Smart Transceiver model; input clock rate; whether device
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Additional Functions
performs boot process; whether device applicationless, configured, unconfigured; amount off-chip RAM; whether off-chip tested simply cleared; number buffers allocated; application initialization. Tables summarize number input clock cycles (XIN) required each these steps 3120 3150 Smart Transceivers. times approximate given functions most significant application variables. Table 3120 Smart Transceiver Reset Sequence Time
Step Stack Initialization BIST SERVICE Initialization State Initialization Off-Chip Initialization Random Number Seed Calculation System Set-up Communication Port Initialization Checksum Initialization One-Second Timer Initialization Scheduler Initialization Number Cycles 386,000 1000 (for boot) 2,275,000 (for boot) 21,000 600*B 3400 175*M 6100 7400 Notes
Notes: These tasks parallel with other tasks. number application and/or network buffers allocated. number bytes checksummed. Assumes trivial initialization task, reset task configured state.
example, timing each these steps shown 3120 Smart Transceiver application with following parameters: 10MHz input clock, crystal oscillator, boot required, least application and/or network buffers, bytes EEPROM checksummed.
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Stack Initialization BIST SERVICE Initialization State Initialization Off-Chip Initialization Random Number Seed Calculation System Setup Communication Port Initialization Checksum Initialization One-Second Timer Initialization Scheduler Initialization Total
38.6000 0.1000 0.0250 2.7000 0.0000 10.8000 0.6100 0.7400 53.5757
Table 3150 Smart Transceiver Reset Sequence Time
Step Stack Initialization BIST SERVICE Initialization State Initialization Off-Chip Initialization Random Number Seed Calculation System Setup Communication Port Initialization Checksum Initialization One-Second Timer Initialization Scheduler Initialization Number Cycles 425,000 1000 1300 (for boot) 70,000 ms*E (for boot) 24,000 214*R (for test clear) 24,000 152*Ra (for clear only) 50,000 27,000 1500*B 7200 175*M (for boot) 82,000 175*M (for boot) 6100 7400 Notes
Notes: number non-zero bytes being written (ranges from 504). number off-chip bytes. number non-system off-chip bytes. number application and/or network buffers allocated. These tasks parallel with other tasks. number bytes checksummed. Only booting configured unconfigured state; booting applicationless state, boot" equation. Assumes trivial initialization task, reset task, configured state.
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Additional Functions
example, timing each these steps shown 3150 Smart Transceiver application with following parameters: 10MHz input clock, crystal oscillator, boot required, bytes external RAM, test clear external RAM, least application and/or network buffers, bytes EEPROM checksummed. Stack Initialization BIST 42.50 SERVICE Initialization 0.10 State Initialization 0.13 Off-Chip Initialization 353.00 Random Number Seed Calculation 5.00 System Setup 4.20 Communication Port Initialization Checksum Initialization 12.50 One-Second Timer Initialization 0.61 Scheduler Initialization 0.74 Total 418.78 following compiler directive disable testing off-chip RAM: pragma ram_test_off
SERVICE
SERVICE alternates between input open-drain output rate with duty cycle with 10MHz input clock. 6.5536MHz, SERVICE alternates rate. When output, sink driving LED. When used exclusively input, optional on-chip pull-up bring input inactive-high state when pull-up resistor connected. Under control Neuron firmware, this used during configuration, installation, maintenance device containing Smart Transceiver. firmware flashes rate when Smart Transceiver been configured with network address information. Grounding SERVICE causes Smart Transceiver transmit network management message containing unique 48-bit Neuron application's program network. This information then used network tool install configure device. typical circuit SERVICE push-button shown Figure 2.11. During reset SERVICE state indeterminate. default state SERVICE pull-up enabled.
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Hardware Resources
3120/3150 Smart Transceiver
Config Pull-Up
SERVICE
Broadcast
Sink
Drive
driving duty cycle output. Waveform sampled external ground condition.
ThreeState SERVICE Signal
ThreeState
ThreeState
Firmware Samples
Figure 2.11 Smart Transceiver SERVICE Circuit
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Integrity Mechanisms
Table 2.10 Service Behavior During Different States
Device State Applicationless Unconfigured Unconfigured (but with Application) Configured, Hard Offline Configured 3150 Defective External Memory 0xF015 State Code Service Flashing
SERVICE active service message sent maximum once SERVICE transition. service message goes into next available priority non-priority output network buffer.
Integrity Mechanisms
Memory Integrity Using Checksums
ensure integrity Smart Transceiver's memory, Neuron firmware maintains number checksums. Each checksum single byte two's complement bytes covers. These checksums verified during reset processing also continual basis background diagnostic process. There three main checksums used verify integrity Smart Transceiver's memory:
Configuration image checksum Application image checksum System image checksum (off-chip system image only)
configuration image checksum covers network configuration information communication parameters residing on-chip EEPROM. default behavior that configuration checksum error causes device unconfigured state. Refer Table 2.12 other options. application image checksum covers application code both on-chip EEPROM application code off-chip EEPROM, NVRAM, flash memory. This checksum optionally extended cover application code off-chip well. default behavior that application checksum error causes device
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Hardware Resources
applicationless state. Application read/write data residing EEPROM, NVRAM, flash checksummed. Refer Table 2.12 other options. Table 2.11 Checksum Coverage Smart Transceiver Memory Areas
Memory Area Checksum System Application Application Application Configuration Application
System image (optionally covered application checksum 3150) off-chip code (optionally covered Application checksum 3150) off-chip flash, EEPROM, NVRAM code off-chip code Configuration image on-chip EEPROM code
3150 Smart Transceiver, memory areas listed Table 2.11 except onchip EEPROM code have their checksum that checksum errors further isolated. unconfigured configured device continually checks application checksum background rate byte iteration through network processor's main loop bytes millisecond when running 10MHz with network activity). system image checksum covers system image. only available when system image resides off-chip memory optional. system image checksum error always forces device applicationless state. checksum computed device applicationless state. checksums verified during reset processing network processor part background diagnostic process. background diagnostic process causes device reset when error detected; state change occurs. assumed that persistent error will found reset processing. Upon detecting checksum error, reset process will force appropriate state error error log. 3150 Smart Transceiver, checksum must fail twice during reset processing order deemed bad.
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Integrity Mechanisms
Reboot Integrity Options Word
3150 Smart Transceiver number options actions taken following checksum error other memory related fatal errors. 16-bit word that controls these options resides system image defined part device's export options NodeBuilder tool. recovery process relies fact that initial on-chip EEPROM image application, configuration, communication parameter data reside off-chip system image. During initial power system image data copied (booted) onchip EEPROM. recovery process recopies reboots suspect areas dictated error recovery options. changes made on-chip EEPROM (e.g., network application load network tool initiated reconfiguration) after initial boot lost recovery process. recovery action defined setting combination bits defined following masks (Table 2.12). Table 2.12 Recovery Action Masks
Recovery Word 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 Description Reboot application application fatal error. Always reboot application reset (see note). Reboot configuration configuration checksum fails. Reboot configuration application fatal error. Always reboot configuration reset. Reboot communication parameters configuration checksum fails. Reboot communication parameters type rate mismatch. Always reboot communication parameters reset. Reboot EEPROM variables when rebooting application. Applicationless state considered application fatal error. option 0x0001 0x0008 set, applicationless state will result reboot. Application fatal errors defined below (see note). Checksum code, including system image.
0x0400
Note: Applications exported with these options cannot loaded over network.
above options, "configuration" does include communication parameters since their recovery governed separately. Also, fatal application errors refer application image checksum errors, memory allocation failures, memory failures. Refer Loading Application Image NodeBuilder User's Guide (Release Revision later) more information.
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configuration will rebooted independently application only configuration table sizes match between EEPROM ROM. This avoids situation where application with different table sizes loaded over network, reboot configuration corrupts program. When EEPROM recovery occurs checksum failure other error, event will logged Smart Transceiver's error table. test command will show EEPROM recovery occurred last error logged.
Reset Processing
During reset processing, configuration checksum checked first. bad, configuration recovery options set, then configuration checksum error logged, checksum repaired, device state changed unconfigured. configuration recovery option set, configuration recovered. Next, application checksum checked. bad, checksum error system image, then system image checksum error logged device state changed applicationless. application checksum bad, application recovery options set, application checksum error logged device state changed applicationless. application checksum application recovery option boot application does contain references off-chip ROM, flash, EEPROM, NVRAM, code, there checksum errors these regions, then application recovered. Otherwise, application checksum error logged device goes applicationless.
Signatures
off-chip code areas have 2-byte cyclic redundancy check (CRC) called signature, immediately following area checksum. Signatures stored code area memory map. Mismatches between area signature memory copy signature result device going applicationless. This mechanism prevents partial application load over network which incompatible with unloaded code (such code ROM).
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Input/Output Interfaces
3120 3150 Power Line Smart Transceiver Data Book
Input/Output Interfaces
Introduction
3120 3150 Smart Transceivers connect application-specific external hardware pins, named IO0-IO11. These pins configured numerous ways provide flexible input output functions with minimal external circuitry. programming model (Neuron language) allows programmer declare more pins objects. object provides programmable access driver specified on-chip hardware configuration specified input output waveform definition. With exception (UART) model, user's program then refer these objects io_in io_out() system calls perform actual input/output function during execution program. Certain events associated with changes input values. task scheduler thus execute associated application code when these changes occur. There many different objects available with Smart Transceivers. Most Objects available 3150 3120 Smart Transceiver system images default. object that included default system image required application, development tool will link appropriate object(s) into available memory space. 3120 Smart Transceiver designs, this means that internal EEPROM space must used additional object. 3150 Smart Transceiver designs, object will added external flash region beyond 16KB space reserved system image. 3120 3150 Smart Transceivers have 16-bit timer/counters on-chip (see Figure 3.1). input timer/counter also called multiplexed timer/counter, selectable among pins IO7, programmable multiplexer (mux) output connected IO0. input timer/counter also called dedicated timer/counter, connected output IO1. timer/counters implemented 16-bit load register writable CPU, 16-bit counter, 16-bit latch readable CPU. load register latch accessed byte time. pins dedicated timer/counter functions. example, timer/counter used input signals only, then available other input output functions. Timer/counter clock enable inputs from external pins, from scaled clocks derived from system clock; clock rates timer/counters independent each other. External clock actions occur optionally rising edge, falling edge, both rising falling edges input. Multiple timer/counter input objects declared different pins within single application. calling io_select() function, application first timer/ counter implement four different input objects. timer/counter
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Hardware Considerations
configured implement output objects, configured quadrature input object, then reassigned another timer/counter object same application program.
IO10 IO11
Timer/Counter Timer/Counter System Clock Divide Chain
Sink Capability
Programmable Pull-Up Capability
Figure Smart Transceiver Timer/Counter External Connections
Hardware Considerations
Tables through list available objects. Various objects different types used simultaneously. Figure summarizes configuration each objects. electrical characteristics these pins, refer 3120 3150 Smart Transceiver Datasheets. following sections contain detailed descriptions objects. application program optionally specify initial values digital outputs. Pins configured outputs also read inputs, returning value pin". Pins IO11 have optional pull-up current sources that like pull-up resistors (see Figure 3.1). These enabled with Neuron compiler directive (#pragma enable_io_pullups). Pins have high sink capability. others have standard sink capability. Pins have low-level detect latches. latency timing values described later this section typical 10MHz. accuracy these values 10%. Most latency values scale inversely with clock rate. pull-ups enabled during stack initialization BIST task. pull-ups only enabled #pragma enable_io_pullups specified
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Input/Output Interfaces
Neuron application. used application, must either tied high board left unconnected configured output application order prevent unnecessary power consumption. This particularly important devices with energy storage power supplies. (See Chapter Table Summary Direct Objects
Object Input Output Byte Input Byte Output Leveldetect Input Nibble Input Nibble Output Applicable Pins IO11 IO11 adjacent adjacent Input/Output Value binary data binary data binary data binary data Logic level detected binary data binary data Page 3-12 3-12 3-14 3-14 3-15 3-16 3-16
Table Summary Parallel Objects
Object Muxbus Parallel Applicable Pins IO10 IO10 Input/Output Value Page
Parallel bidirectional port using mul- 3-18 tiplexed addressing Parallel bidirectional handshaking port 3-18
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Hardware Considerations
Table Summary Serial Objects
Object Bitshift Input Bitshift Output Magcard Input Applicable Pins adjacent pair (except IO10 IO11) adjacent pair (except IO10 IO11) (one IO7) Input/Output Value bits clocked data bits clocked data bytes bidirectional serial data Encoded ISO7811 track data stream from magnetic card reader Encoded ISO3554 track data stream from magnetic card reader Unprocessed serial data stream from magnetic card reader bits bidirectional serial data 8-bit characters 8-bit characters Page 3-27 3-27 3-30 3-32
Magtrack1
(one IO7)
3-34
Magcard Bitstream Neurowire Serial Input Serial Output Touch Wiegand Input (UART)
(one IO7) IO10 (one IO7) IO10 adjacent pair IO10 IO10 (IO7)
3-36 3-37 3-42 3-42
2048 bits input output 3-44 bits Encoded data stream from Wiegand card reader bytes input bytes output byes bidirectional data 3-47 3-49 3-50
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Input/Output Interfaces
Table Summary Timer/Counter Input Objects
Object Dualslope Input Edgelog Input Infrared Input Ontime Input Period Input Pulsecount Input Quadrature Input Totalcount Input Applicable Pins IO0, (one IO7) IO5, Input Signal Comparator output dualslope converter logic stream input transitions Encoded data stream from infrared demodulator Pulse width 1.678 Signal period 1.678 65,535 input edges during 0.839 16,383 binary Gray code transitions 65,535 input edges Page 3-57 3-59 3-61 3-62 3-63 3-65 3-67 3-69
Table Summary Timer/Counter Output Objects
Object Edgedivide Output Applicable Pins IO0, (one IO7) Output Signal Output frequency input frequency divided user-specified number Series timed repeating square wave output signals Square wave 2.5MHz Pulse duration 1.678 65,535 pulses 100% duty cycle pulse train Page 3-71
Infrared Pattern Output Frequency Output Oneshot Output Pulsecount Output Pulsewidth Output Triac Output TriggeredCount Output
IO0, IO0, IO0, IO0, IO0, IO0, (one IO7) IO0, (one IO7)
3-74 3-73 3-75 3-77 3-79
Delay output pulse with respect 3-81 input edge Output pulse controlled counting input edges 3-83
maintain provide consistent behavior external events prevent metastability, pins Smart Transceiver, when configured inputs, passed through hardware synchronization block sampled internal system clock. This always input clock divided (e.g. 10MHz 5MHz).
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Hardware Considerations
signal reliably synchronized with 10MHz input clock, must least 220ns duration (see Figure 3.2). inputs software sampled during when statement processing. latency sampling dependent object which being executed (see timing specification Neuron Programmer's Guide more information). These latency values scale inversely with input clock. Thus, event that lasts longer than 220ns will synchronized hardware, there will latency software sampling resulting delay detecting event. state changes faster rate than software sampling occur, then interim changes will undetected. There three exceptions synchronization block. First, chip select (CS) input used slave mode parallel object; this input will recognize rising edges asynchronously. Second, leveldetect input latched flip-flop with 200ns clock. level detect transition event will latched, there will delay software detection. Third, (UART) objects buffered byte boundaries hardware transferred memory using interrupt mechanism. input timer/counter functions also different, that events pins will accurately measured value returned register, regardless state application processor. However, application processor delayed reading register. Consult Neuron Programmer's Guide detailed programming information.
tsetup 20ns IO0-IO11 Inputs (220ns pulse) Internal System Clock (XIN Input Clock 10MHz divided thold
IO0-IO11 Inputs
Synchronized IO0-IO11 Inputs
Internal System Clock Input Synchronizer Structure
Figure Synchronization External Signals
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Input/Output Interfaces
DIRECT OBJECTS
Input, Output Byte Input, Byte Output Leveldetect Input Nibble Input, Nibble Output Four Adjacent Pins Data Pins Data Pins Data Pins Optional Timeout Optional Timeout Optional Timeout Optional Chip Select Optional Timeout Pins
PARALLEL OBJECTS Parallel
Muxbus Master/Slave Slave
Notes: Clock, Data Bitshift, I2C, Magcard, Magtrack, Neurowire Timer/Counter Devices IO_6 input quadrature IO_4 input edgelog IO_0 output [triac triggeredcount edgedivide] sync(IO_4.7) IO_0 output [frequency infrared_pattern oneshot pulsecount pulsewidth] four IO_4 input [ontime period pulsecount totalcount dualslope infrared] IO_5.7 input [ontime period pulsecount totalcount dualslope infrared] Timer/Counter Devices IO_4 input quadrature IO_4 input edgelog IO_1 output [triac triggeredcount edgedivide] sync(IO_4) IO_1 output [frequency infrared_pattern oneshot pulsecount pulsewidth] IO_4 input [ontime period pulsecount totalcount dualslope infrared]
Bitshift Input, Bitshift Output Magcard Input Magcard Bitstream
SERIAL OBJECTS
Magtrack1 Input
Neurowire
Master Slave
Serial Input Serial Output (UART) Touch Wiegand Input Dualslope Input Edgelog Input Infrared Input Ontime Input Period Input Pins (Optional Timeout) Control
TIMER/COUNTER INPUT OBJECTS
Pulsecount Input
Quadrature Input Totalcount Input
TIMER/ COUNTER OUTPUT OBJECTS
Edgedivide Output Frequency Output Infrared Pattern Output Oneshot Output Pulsecount Output Pulsewidth Output Triac Output Triggeredcount Output Control Control
Sync Input
Sync Input Sync Input Pull
High Sink
Pull
Standard
Figure Summary Objects
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Timing Issues
Timing Issues
Smart Transceiver timing influenced four separate, overlapping areas overall chip architecture:
scheduler object's firmware Smart Transceiver hardware Interrupts
contribution scheduler overall timing characteristic approximately uniform across function blocks since contribution overall timing relatively high functional level. contribution firmware hardware varies from object another (e.g., versus Neurowire I/O). contribution interrupts varies with nature data interrupting processor. (UART) section details.
Scheduler-Related Timing Information
part Smart Transceiver firmware, scheduler provides orderly predictable means facilitate evaluation user-defined events. when clause, provided Neuron language, used specify such events. more information operation scheduler, refer Neuron Programmer's Guide. There finite latency associated with operation scheduler. time required scheduler evaluate same when clause particular user application code large extent, function size user code, total number when clauses, state events associated with those when clauses. Therefore, impossible specify nominal value this latency, each application will have distinct behavior under different circumstances. best case latency viewed several ways, each exposing different aspect scheduler operation. simple example consists having application program consisting when clauses, both which always evaluate TRUE, shown below.
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Input/Output Interfaces
IO_0 output testbit; when (TRUE) io_out(testbit, when (TRUE) io_out (testbit,
Processing when clauses done round-robin fashion; therefore, Neuron code above performs alternating activation order isolate extract timing parameters associated with scheduler. waveform seen Smart Transceiver, result above code, shown Figure 3.4.
IO_out call IO_0
IO_out call tsol
IO_out call
TIME when when end-of-loop clause clause processing begins when clause (Not scale)
Symbol tsol
Description when-clause when-clause latency Scheduler overhead latency (see text)
10MHz
Figure when-Clause when-Clause Scheduler Overhead Latency
when-clause when-clause latency, tww, this case includes execution time io_out() function latency 10MHz) event that always evaluates TRUE. actual given application driven actual task within when statement well when event which evaluated.
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above example only measures best-case minimum latency between consecutive when clauses (whose events evaluate TRUE), tww, also reveals scheduler's end-of-loop overhead latency, tsol. shown Figure 3.4, offtime period output waveform tsol on-time output waveform, minus tww. This shows that scheduler overhead latency, scheduler end-ofloop latency, occurs just before execution last when clause program. latency associated with return from io_out() function small, relative that execution function call itself. NOTE: Some objects suspend application processing until task complete. This because they firmware-driven. These bitshift, Neurowire, parallel, software serial objects, I2C, magcard, magtrack, Touch I/O, Wiegand. They suspend network communication this handled network processor media access processor.
Firmware Hardware Related Timing Information
updates Smart Transceiver performed Neuron firmware using system image function calls. total latency given function call, from start end, broken down into separate parts. first processing time required before actual hardware update (read write) occurs. second delay associated with time required finish current function call return application program. Overall accuracy always related accuracy Smart Transceiver's input. Timing diagrams provided non-trivial cases clarify parameters given. more information operation each objects, refer Neuron Reference Guide.
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Input/Output Interfaces
Direct Objects
timing numbers shown this section valid both explicit call implicit call through when clause, assumed Smart Transceiver running 10MHz.
Input/Output
Pins IO11 individually configured single-bit input output ports. Inputs used sense TTL-level compatible logic signals from external logic, contact closures, like. Outputs used drive external CMOS level compatible logic, switch transistors very current relays actuate higher-current external devices such stepper motors lights. high (20mA) current sink capability pins allows these pins drive many devices directly (refer Figure 3.5). Figures show input output latency times, respectively. These times from which io_in() io_out() called, until value returned. direction ports changed between input output dynamically under application control. (io_set_direction())
IO10 IO11 High Current Sink Drivers
IO10 IO11 Optional Pull-Up Resistors
Figure
Note: After Reset, Smart Transceiver disables IO4-IO7 IO11 pull-up resistors. pull-up resistors turned until application initialization. Pullups only enabled when specified application configuration using Neuron directive. (#pragma enable_io_pullups)
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Direct Objects
tfin INPUT TIME START io_in() Symbol tfin Description Function call sample IO10 IO11 Return from function IO10 IO11
tret
INPUT SAMPLED
io_in() 10MHz 8.4µs 23.4 27.9 32.3 36.7 41.2 45.6 23.4 27.9
tret
Figure Input Latency Values
tfout OUTPUT TIME START OUTPUT io_out() UPDATED io_out() Symbol tfout Description Function call update IO5, IO11 others Return from function IO11 10MHz tret
tret
Figure Output Latency Values 3120 3150 Power Line Smart Transceiver Data Book 3-13
Input/Output Interfaces
Byte Input/Output
Pins configured byte-wide input output port, which read written using integers range 255. This useful driving devices that require ASCII data, other data, eight bits time. example, alphanumeric display panel byte function data, pins IO11 function control addressing. Figures Figures 3.8, 3.9, 3.10. represents data. direction byte port changed between input output dynamically under application control. (io_set_direction())
IO10 IO11 High Current Sink Drivers
IO10 IO11 Optional Pull-Up Resistors
Figure Byte
tfin INPUT TIME
tret
START INPUT io_in() SAMPLED
io_in()
Symbol tfin tret
Description Function call input sample Return from function
10MHz
Figure Byte Input Latency Values
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Direct Objects
tfout OUTPUT TIME START io_out()
tret
OUTPUT UPDATED
io_out()
Symbol tfout tret
Description Function call update Return from function
10MHz
Figure 3.10 Byte Output Latency Values
Leveldetect Input
Pins individually configured leveldetect input pins, which latch negative-going transition input level with minimal pulse width 200ns, with Smart Transceiver clocked 10MHz. application therefore detect short pulses input which might missed software polling. This useful reading devices, such proximity sensors. This only direct object which latched before sampled. latch cleared during when statement sampling again immediately after, another transition should occur. Figure 3.11.
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Input/Output Interfaces
tfin INPUT 200ns SYSTEM CLOCK 10MHz) INPUT LATCH TIME NEGATIVE TRANSITION LATCHED INPUT LATCH START SAMPLED THEN io_in() CLEARED
tret
IO10 IO11 Optional Pull-Up Resistors
NEGATIVE TRANSITION LATCHED
io_in()
Symbol tfin
Description Function call sample Return from function
10MHz 39.4 43.9 48.3 52.7 57.2 61.6
tret
Figure 3.11 Leveldetect Input Latency Values
Nibble Input/Output
Groups four consecutive pins between configured nibble-wide input output ports, which read written using integers range This useful driving devices that require data, other data four bits time. example, switch matrix scanned using nibble generate output (row select four rows), nibble read input from columns switch matrix. Figures Figures 3.12, 3.13, 3.14.
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Direct Objects
direction nibble ports changed between input output dynamically under application control (see Neuron Programmer's Guide). input data determined object declaration pins.
IO10 IO11 High Current Sink Drivers Optional Pull-Up Resistors
Figure 3.12 Nibble
tfin INPUT TIME
tret
START INPUT io_in() SAMPLED
io_in()
Symbol tfin tret
Description Function call sample Return from function
10MHz 22.8 27.5 32.3
Figure 3.13 Nibble Input Latency Values
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Input/Output Interfaces
tfout OUTPUT TIME
tret
START OUTPUT io_out() UPDATED io_out()
Symbol tfout
Description Function update Return from function
10MHz 89.8 101.5 113.3
tret
Figure 3.14 Nibble Output Latency Values
Parallel Objects
Muxbus Input/Output
This object provides means performing parallel data transfers between Smart Transceiver attached peripheral device processor (see Figure 3.15). Unlike parallel input/output object, which makes token-passing scheme ensuring synchronization, muxbus input/output enables Smart Transceiver essentially control read write operations times. This relieves burden protocol handling from attached device results easier-to-use interface expense data throughput capacity. data remains last state used.
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Parallel Objects
IO10 IO11 C_ALS C_WS C_RS
ADDR/ DATA C_ALS (IO8)
ADDR
DATA
ADDR
DATA trset
twas C_RS (IO10)
tahw tadrs
tahr
tdws twhold C_WS (IO9) twws tfout TIME START io_out() twret tfin
twrs
trhold
trret
io_out()
START io_in()
io_in()
NOTE: Data latched after falling edge C_RS.
Symbol
tfout tahw tahr twas twrs twws tdws trset twhold trhold tadrs tfin trret twret
Description
io_out() valid address Address valid address strobe Address hold write Address hold read Address strobe width Read strobe width Write strobe width Data valid write strobe Read setup time Write hold time Read hold time Address disable read strobe io_in() valid address Function return from read Function return from write
10.8
26.4 10.8 10.8 10.8 26.4
Figure 3.15 Muxbus Object
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Input/Output Interfaces
Parallel Input/Output
Pins IO10 configured bidirectional 8-bit data 3-bit control port connecting external processor. other processor computer, microcontroller, another Smart Transceiver (for gateway applications). parallel interface configured master, slave slave mode. Typically, Smart Transceivers interface master/slave mode Smart Transceiver interfaces with another microprocessor slave configuration, with other microprocessor master. Handshaking used both modes control instruction execution, application processing suspended duration transfer bytes/transfer). Consult Neuron Reference Guide detailed programming instructions. Upon reset condition, master processor monitors transition handshake (HS) line from slave, then passes CMD_RESYNC (0x5A) synchronization purposes. This must done within 0.84 seconds after reset goes high with Smart Transceiver slave running 10MHz, avoid watchdog reset error condition (see Neuron Programmer's Guide). CMD_RESYNC followed slave acknowledging with CMD_ACKSYNC (0x07). This synchronization ensures that both processors properly reset before data transfer occurs. When interfacing Smart Transceivers, these characters passed automatically (refer flow table illustrated later this section). However, when using parallel interface Smart Transceiver another microprocessor, that microprocessor must duplicate interface signals characters that automatically generated Smart Transceiver's parallel function. additional information, Parallel Interface Neuron Chip engineering bulletin. timing numbers shown this section valid both explicit call implicit call through when clause, assumed Smart Transceiver running 10MHz.
Master/Slave Mode
This mode recommended when interfacing Smart Transceivers. master/ slave configuration, master drives chip select specify read write cycle, slave drives IO10 handshake (HS) acknowledgment (see Figure 3.16). maximum data transfer rate byte processor instruction cycles, byte 10MHz input clock rate. data transfer rate scales proportionally input clock rate master write slave read). Timing
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Parallel Objects
case where Smart Transceiver master (Figure 3.17), refers measured output timing 10MHz. After every byte write byte read, line monitored master, verify slave completed processing (when slave ready next byte transfer. This done automatically Smart Transceiver-to-Smart Transceiver (master/slave mode) data transfers. line should pulled (inactive) with resistor ensure proper resynch behavior after slave resets. Slave timing shown Figure 3.18.
IO10 IO11 PARALLEL MASTER 10kohm VDD5
IO10 IO11 PARALLEL SLAVE
Figure 3.16 Parallel Master Slave
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Input/Output Interfaces
tmhscs tmcspw tmhsh tmrws tmrdz DATA tmrds DATA READ CYCLE Symbol tmrws tmrwh tmcspw tmhsh tmhsv tmrdz tmrds tmhscs tmrdh tmwdd tmhsdv tmwds tmwdh Description setup before falling edge (Note hold after rising edge pulse width (Note hold after falling edge checked firmware after rising edge (Note Master three-state DATA after rising edge (Notes Read data setup before falling edge (Note falling edge (Notes 4,6) Read data hold after falling edge Master drive DATA after falling edge (Notes 1,6) data valid (Note Write data setup before rising edge (Note Write data hold after rising edge (Note WRITE CYCLE CLK1 Note tmrdh tmwdd tmwdh tmwds tmrwh tmrws tmhsdv tmcspw tmhsv
tmhsv
tmhsh
Notes: Refer 3120 3150 Smart Transceiver Datasheet detailed measurement information. Smart Transceiver-to-Smart Transceiver operation, contention (tmrdz, tsawdd) eliminated firmware, ensuring that zero state present when token passed between master slave. Parallel Interface Neuron Chip engineering bulletin further information. high used slave busy flag. held low, maximum data transfer rate (2.4µs 10MHz) byte. used flag, caution should taken ensure master does initiate data transfer before slave ready. Parameters were added order interface design with Smart Transceiver. Master will hold output data valid during write until Slave device pulls high. represents period Smart Transceiver input clock (100ns 10MHz). master read, pulsing acts like handshake flag slave that data been latched
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Parallel Objects
Figure 3.17 Master Mode Timing
tsacspw tsahsh tsarws tsawd DATA tsawds DATA WRITE CYCLE (MASTER READ) Symbol tsarws tsarwh tsacspw tsahsh tsahsv tsawdd tsawds tsawdh tsardz tsards Description setup before falling edge hold after rising edge pulse width hold after rising edge valid after rising edge tsawdh tsarwh
tsahsv tsacspw tsahsh
tsahsv
tsarws
tsards
tsardh
tsardz
READ CYCLE (MASTER WRITE) (Note
Slave drive DATA after rising edge (Notes Write data valid before falling edge (Note Write data valid after rising edge (Note Slave three-state DATA after falling edge (Note Read data setup before rising edge
tsardh Read data hold after rising edge Notes: Refer 3120 3150 Smart Transceiver Datasheet detailed measurement information. Smart Transceiver-to-Smart Transceiver operation, contention (tmrdz, tsawdd) eliminated firmware, ensuring that zero state present when token passed between master slave. Parallel Interface Neuron Chip engineering bulletin further information. tsarwh 150ns, then tsawdh tsarwh. represents period Smart Transceiver input clock (100ns 10MHz).
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Input/Output Interfaces
slave mode, signal high minimum periods. typical time high during consecutive data reads consecutive data writes also periods.
Figure 3.18 Slave Mode Timing
Slave Mode
slave mode recommended interfacing Smart Transceiver acting slave another microprocessor acting master. When configured slave mode, Smart Transceiver accepts chip select specify whether master will read write, accepts IO10 register select input. When asserted either IO10 IO10 high low, pins form bidirectional data bus. When IO10 high, high, asserted, driven acknowledgment signal master. Smart Transceiver appear registers master's address space; registers being read/write data register, other being readonly status register. Therefore, reads master address access status register handshaking acknowledgments other reads writes access data register transfers. control register, which read through IO0, bit. master reads after every master read write. D0/HS line should pulled (inactive) with resistor ensure proper resynch behavior after resets. When acting slave different microprocessor, Smart Transceiver slave mode handles handshaking token passing automatically. However, master microprocessor must read after each transaction must also internally track token passing. This mode designed with master processor that uses memory-mapped I/O, master's address typically connected Smart Transceiver's IO10 pin. This illustrated Figures 3.19 3.20.
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Parallel Objects
READ ONLY STATUS REGISTER IO10
READ/WRITE DATA REGISTER HS/D0
SLAVE D0/HS IO10 IO11
IO10 IO10
Figure 3.19 Parallel Master/Slave Smart Transceiver MemoryMapped Device)
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Input/Output Interfaces
MASTER tsbcspw tsbah MASTER tsbas MASTER tsbrws LATCH MASTER DATA tsbwdv WRITE CYCLE (MASTER READ) Description setup before falling edge 3150 3120 Smart Transceivers hold after rising edge pulse width setup falling edge hold after rising edge write data valid Write data hold after rising edge (Notes rising edge Slave release data (Note Read data setup before rising edge tsbwdz tsbwdh READ CYCLE (MASTER WRITE) Note tsbrds tsbrdh tsbrwh tsbrws tsbcspw
SLAVE DATA Symbol tsbrws tsbrwh tsbcspw tsbas tsbah tsbwdv tsbwdh tsbwdz tsbrds
tsbrdh Read data hold after rising edge Notes: slave write cycle (master read) pulse width directly related slave write data valid parameter master read setup parameter. calculate write cycle duration needed special application use: tsbcspw tsbwdv master's read data setup before rising edge Refer master's specification data book master read setup parameter. slave read cycle minimum pulse width Refer 3120 3150 Smart Transceiver Datasheet detailed measurement information. data hold parameter, tsbwdh, measured disable levels shown 3120 3150 Smart Transceiver Datasheet, rather than traditional data invalid levels. slave write cycle timing parameters same control register (HS) write data write. Special applications: Both state determine slave write cycle. used data transfer, then toggling line used with changes hardware. other words, held during slave write cycle, positive pulse (low high low) execute data transfer. high transition causes slave drive data with same timing parameters tsbwdv (redefined write data valid). Likewise, falling edge causes slave release data with same timing limits rising edge tsbwdz. This scenario only true slave write cycle applicable slave read cycle slave data transitions. This application helpful master separate read write signals signal. Caution must taken ensure free before transfers avoid contention.
Figure 3.20 Slave Mode Timing 3-26 3120 3150 Power Line Smart Transceiver Data Book
Serial Objects
Serial Objects
timing numbers shown this section valid both explicit call implicit call through when clause, assumed Smart Transceiver running 10MHz.
Bitshift Input/Output
Pairs adjacent pins configured serial input output lines. first pair IO0-IO6, IO8, IO9, used clock (driven Smart Transceiver). adjacent higher-numbered then used bits serial data. rate configured 1kbps, 10kbps, 15kbps 10MHz input clock rate. rate scales proportionally input clock rate. active clock edge specified either rising falling. This object useful transferring data external logic employing shift registers. This function suspends application processing until operation complete. Figures Figures 3.21, 3.22, 3.23.
IO10 IO11 BITSHIFT OUTPUT
Data Data Data Data Data
IO10 IO11 BITSHIFT INPUT
Data Data Data Data Data
Figure 3.21 Bitshift Examples bitshift input, clock output deasserted inactive level) same time start first data. bitshift output, clock output initially inactive prior first data (unless overridden output overlay).
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Input/Output Interfaces
INPUT SAMPLED
thold tfin OUTPUT CLOCK tret DATA taet ttae
START io_in()
io_in()
Active clock edge assumed positive above diagram
Symbol tfin tret thold
Description Function call first edge Return from function Active clock edge sampling input data kbps rate kbps rate kbps rate Active clock edge next clock transition kbps rate kbps rate kbps rate Clock transition next active clock edge kbps rate kbps rate kbps rate Clock frequency 1/(taet ttae) kbps rate kbps rate kbps rate
10MHz 156.6 40.8 938.2 31.8 63.6 14.4 14.4 14.4 21.6 12.8 1.03
taet
ttae
Figure 3.22 Bitshift Input Latency Values
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Serial Objects
tsetup tfin OUTPUT CLOCK
taet
ttae
tret DATA
START io_in()
io_in()
Active clock edge assumed positive above diagram
Symbol tfin
Description Function call first data stable 16-bit shift count 1-bit shift count Return from function Data stable active clock edge kbps rate kbps rate kbps rate Active clock edge next clock transition kbps rate kbps rate kbps rate Clock transition next active clock edge kbps rate kbps rate kbps rate Clock frequency 1/(taet ttae) kbps rate kbps rate kbps rate
10MHz 185.3 337.6 10.8 10.8 10.8 10.8 10.2 939.5 34.8 34.8 34.8 1.02
tret tsetup
taet
ttae
Figure 3.23 Bitshift Output Latency Values
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Input/Output Interfaces
Input/Output
This object used interface Smart Transceiver device which adheres Philips Semiconductor's Inter-Integrated Circuit (I2C) protocol. Smart Transceiver always master, with being serial clock (SCL) serial data (SDA). Alternatively, used serial clock (SCL) serial data (SDA). These lines operated open-drain mode order accommodate special requirements protocol. With exception pull-up resistors, additional external components necessary interfacing Smart Transceiver device. bytes data transferred time. start transfers, rightjustified 7-bit address argument sent immediately after "start condition." more information this protocol, refer Philips Semiconductor's documentation.
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Serial Objects IO10 IO11 tdch tchcl tchd tdcl TIME INPUT DATA SAMPLED TRANSFER TIMING Parameter Description call start condition io_in() io_out() start condition io_in() io_out() start start address io_in() io_out() data io_out() Data high io_out() Clock high clock io_out() high data sampling io_in() Data sample io_in() Clock clock high io_in() Clock high data io_in() io_out() high return from function io_in() io_out() tclch TIME START io_in() io_out() 24.0 24.0 24.6 12.6 13.2 24.0 12.6 12.6 io_in() io_out() tret tcld tstart tcla tstop Clock Serial Data
START STOP TIMING 54.6 43.4
tstart
tcla
tcld tdch tchcl tchd tdcl tclch tstop
tret
Figure 3.24 Object 3120 3150 Power Line Smart Transceiver Data Book 3-31
Input/Output Interfaces
Magcard Input
This object used transfer synchronous serial data from 7811 Track magnetic stripe card reader real time. data presented data signal input IO9, clock, data strobe, signal input IO8. data clocked just following falling (negative) edge clock signal IO8, with first. addition, pins used timeout prevent lockup case abnormal abort input stream during input process. characters read time. Both parity Longitudinal Redundancy Check (LRC) checked Smart Transceiver.
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Serial Objects
IO10 IO11 DATA (IO9) thold tsetup CLOCK (IO8) tclk tlow TIMEOUT tret tfin TIME START io_in() thigh
Timeout
Clock Serial Data
twto
ttret io_in()
Symbol tfin thold tsetup tlow thigh twto tclk ttret tret
Description Function call first clock input Data hold Data setup Clock width Clock high width Width timeout pulse Clock period Return from timeout Return from function
21.6
45.0
81.6 301.8
Figure 3.25 Magcard Input Object
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Input/Output Interfaces
Smart Transceiver operating 10MHz process rate 8334 bits/ second density bits/inch). This equates card velocity inches/ second. Most magnetic card stripes contain 15-bit sequence zero data start card, allowing time application start card reading function. 8334 bits/second, this period about 1.8ms. scheduler latency greater than 1.8ms value, io_in() function will miss front data stream. rate processing capability scales with input clock rate.
Magtrack1 Input
This input object type used read synchronous serial data from ISO3554 magnetic stripe card reader. data input IO9, clock, data strobe, presented input IO8. data clocked just following falling edge clock signal IO7, with first.
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Serial Objects
IO10 IO11 (IO9) thold tsetup CLOCK (IO8) tlow tclk TIMEOUT tfin TIME START io_in() tret ttret thigh
Timeout
Clock Serial Data
twto
io_in()
Symbol tfin thold tsetup tlow thigh twto tclk ttret tret
Description Function call first clock input Data hold Data setup Clock width Clock high width Width timeout pulse Clock period Return from timeout Return from function
tlow 21.6
45.0
tclk 81.6 301.8
Figure 3.26 Magtrack1 Input Object
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3-35
Input/Output Interfaces
minimum period entire cycle (tclk greater than tlow thigh. setup thold times should such that data stable duration tlow. Data recognized IATA format series 6-bit characters plus even parity character. process begins when start sentinel (hex recognized, continues until sentinel (0x0F) recognized. more than characters, including sentinels character, will read. data stored right-justified bytes buffer space pointed buffer pointer argument io_in()function with parity stripped, includes start sentinels. This buffer should bytes long. magtrack1 input object optionally uses pins timeout/ abort pin. this feature suggested since io_in()function will update watchdog timer during clock wait states, could result lockup card were stop moving middle transfer process. logic level detected timeout pin, io_in()function will abort. This input oneshot timer counter output, circuit, DATA_VALID signal from card reader. Smart Transceiver with clock rate 10MHz process incoming rate 7246 bits/second when strobe signal duty cycle (thigh 46µs, 92µs). density bits/inch, this translates card speed 34.5 inches/second. rate processing capability scales with Smart Transceiver input clock rate.
Magcard Bitstream Input
magcard
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