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HardWire Array Initial Design Submittal Form
Company Name Date Customer Name E-mail Address City State/Province Country
Customer Internal Part Number FPGA File Name Revision Date (Line .LCA file) Xilinx HardWire Array Device
(see cross reference table HardWire Data Book correct part number)
Temp. Grade (Check One)
(Check One)
Package
Clock Frequency Application Device Actual Function Performed System
(information will used import/export purposes only)
Special Processing Requirements
(Tape Reel, Special Packaging, etc.)
Customer Specification
Annual Production Volume (estimate) Number sockets using this design_
Design Information Submitted Xilinx:
FPGA Design File Name _.XRP ("DRC informational") File Name Design Root Schematic/HDL Root Name Timing Diagram System I/Os Design Block Diagram
Development Methodology Used:
Design entry method used (Check that apply): Schematic (type) X-BLOX VHDL Simulation: done XABEL Verilog Synthesis type Other
Done with
FPGA Device Speed Grade Package Temperature Grade Check that apply: Peripherial Synchronous Peripherial Asynchronous Configuration Emulation Needed? IEEE1149.1 Boundary Scan Required? Master Serial Master Parallel Always Slave Serial Master Parallel Down (INSTANT_ON Only prior configuration (NO_PROM) Never Express
Mode
Description (Name, Size, Cycle, Time, etc.)
Xilinx Only
Marketing Application Engineer Code
FRC0189
Rev. (3/14/97)
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