Analyst Analyst optional graphical productivity tool Synplify syn
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Unique Tool Visualizing Synthesis Results
Analyst
Analyst optional graphical productivity tool Synplify synthesis environment that helps visualize results your FPGA CPLD designs, improve quality your source code, improve device performance area results.
Analyst provides benefits:
gives immediate understanding results produced your code, with links back source. quick easy learn HDL. Analyst unique ability generate block diagram design based your Verilog VHDL source code. addition this high-level graphical representation your design, Analyst provides technology-primitive representation your design (LUTs, CLBs, on). Analyst also provides environment where cross-probe between block diagram, technology-primitive schematics, source code. example, highlighting line text immediately high-
lights corresponding logic block diagram detailed schematic views. Conversely, double clicking logic graphical views highlights source code from which logic created. cross-probing capability Analyst enables visualize where coding changes addition timing constraints might increase performance reduce required logic resources. Furthermore, Analyst highlights isolates critical paths within your design, problem areas identified corrected adding timing constraints re-synthesizing. Success designing high-density FPGAs increasingly dependent upon availability high-quality synthesis software. Over years, Synplicity Xilinx have established excellent Alliance relationship which advanced state FPGA design. primary goal relationship provide with high-quality synthesis software productivity-enhancing tools such Analyst.
Cross-Probing Simplifies Understanding
Language Sensitive Editor (Describes functionality)
View (Graphical analysis)
Technology View (Mapping)
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