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APPLICATION NOTE U-143C CHIP PAIR PROVIDES ISOLATED DRIVE HIGH VO
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APPLICATION NOTE U-143C
CHIP PAIR PROVIDES ISOLATED DRIVE HIGH VOLTAGE IGBTs
Mickey McClure Application Engineer Motion Control Products
Recent advances design Insulated Gate Bipolar Transistors (IGBTs) have increased their capabilities point where they replacing power MOSFETs switching device choice high voltage/high current power supply motor drive systems. Although switching speeds IGBTs generally slower than those power MOSFETs, devices available with similar gate drive requirements. same time, these devices retain inherent superior conduction characteristics bipolar transistors. integrated circuit pair, UC3726/UC3727, provides cost-effective drive IGBTs "highside" isolated switching applications. This application note describes operation this chip pair, well unique problems associated with driving IGBTs. Many concepts presented here similar those presented Unitrode Application Note U-127, written John O'Connor, which describes UC3724/UC3725 power MOSFET driver pair. This application note replaces Unitrode Application Note U-143 specification changes UC3727.
IGBT OPERATION APPLICATIONS While power MOSFETs have many desirable features such high peak current capability, wide safe operating area (SOA), ruggedness, they have some inherent disadvantages. Among these conduction characteristics that strongly dependent temperature, voltage rating size. Furthermore, conduction characteristics power MOSFETs largely insensitive gate voltage, large values drain current, drain source voltage primarily linear function drain current. This effect severely limits maximum current capability MOSFETs since power loss squared function drain current (ID)2 IGBTs, other hand, function more like bipolar transistors than MOSFETs. IGBT equivalent circuit consists transistor driven voltage MOSFET pseudo-Darlington configuration. Since voltage drop across IGBT voltage drop across junction voltage drop across driving MOSFET, total voltage drop across IGBT never below diode drop. This leads greater power dissipation current levels than MOSFET. However, this disadvantage greatly offset fact that conduction characteristics IGBTs increase with increasing gate voltage. increase gate voltage leads increase channel current driving MOSFET. This
turn leads reduction voltage drop across PNP. Furthermore, since output behaves largely like bipolar transistor, voltage drop linear function collector current, which leads much lower power dissipation high current levels. Because these superior characteristics, IGBTs operate much higher current levels than power MOSFETs same size. OVERVIEW IGBT DRIVE REQUIREMENTS PROBLEM AREAS conduction characteristics IGBT similar those N-channel MOSFET that positive gate-to-emitter voltage required conduction. This characteristic leads problem gate biasing "high-side" drive applications. Since gate must biased above high voltage input, high side drive requirements lead costly complex gate circuits, gate must sometimes biased hundreds volts above system ground. addition biasing problem, other gate drive requirements include drive impedance reduce switching losses, well sufficient current charge gate fast enough achieve desired switching time. charge current requirement derived from total gate charge (Qg) specified IGBT data sheet. Additionally, since combination high voltage relatively fast switching speed results both high dv/dt di/dt, gate usually biased with negative voltage during turn prevent transient turn
This requirement results added complexity gate drive circuitry. Finally some method must implemented protect IGBT and/or other drive circuitry from damage during over current faults. Unitrode Application Note U-127 mentions several common approaches solving high side driver problem. Among common techniques used floating power supplies driver circuitry, charge pump circuits, high voltage driver ICs, optocoupler isolated driver circuits. Each these techniques have limitations, those limitations discussed detail U-127. UC3726/UC3727 DRIVER PAIR UC3726/UC3727 pair provides elegant, compact cost-effective solution problem driving IGBTs high side isolated applications. chip pair similar UC3724/ UC3725 chip pair, except optimized unique problems associated with driving IGBTs. Figure shows basic circuit configuration UC3726/UC3727 circuit pair. addition pair, passive components pulse transformer required complete circuit. Also, optocoupler used provide fault information UC3726 desired. optocoupler eliminated fault protection still provided UC3727 required pass fault information back system. This feature explained detail fault section this application note. UC3726 transmitter generates carrier signal that utilizes unique duty cycle modulation technique transmit both command signal power
UC3727. Operating carrier high frequency, 750kHz, allows minimum transformer cost size. Since high voltage isolation provided with magnetic element instead silicon, voltage used. This leads very cost effective simple solution high voltage gate drive problem. UC3727 comparator circuitry senses transmitted duty cycle decodes ON/OFF gate drive command. diode bridge rectifies carrier input provide power output gate drive signal phase with command, guaranteed 16V. Intermediate high drive clamp levels programmed various periods time limit surge current turn during short term fault conditions. bipolar voltage supply also provided supply negative gate drive insure that IGBT remains presence high common mode slew rates. UC3726 DRIVE TRANSMITTER Figure shows block diagram UC3726 drive transmitter major components circuit include tri-level output drivers with zero current sense detectors control logic, bias voltage generator with undervoltage lockout, retriggerable shot, compatible input with hysteresis, well fault sense circuitry control logic. circuit operates using unique duty cycle modulation technique simultaneously pass ON/OFF command information power UC3727 isolated IGBT high side driver. This technique originally developed UC3724/ UC3725 high side MOSFET driver pair. Application
Figure UC3726/UC3727 Circuit Pair
Figure Drive Transmitter Note U-127 describes operation that chip pair, many concepts similar. Specific differences primarily relate waveform timing. CARRIER FREQUENCY/TIMING/OUTPUT DRIVES/INPUT COMMAND choosing high frequency carrier, cost efficiency maximized. carrier frequency uses both shot pulse width pulse transformer reset time overall period. shot pulse width timing resistor (RT) capacitor (CT). During shot pulse time along with parallel parasitic capacitance, charged with constant current determined logic voltage VL/4RT this other equations this applications note, resistors ohms, capacitors farads, time seconds. parasitic capacitance approximately 50pF adds form total capacitance CTOT. This capacitance charges from initial value 0.22 until reaches threshold voltage which time one-shot pulse terminates. Using current/voltage relationship capacitor I=C(dv/dt) yields pulse width time: (CTOT )(0.5-0.22))/Ict (CTOT 0.25VL 4RT)/VL CTOT Notice that does appear final equation therefore tolerance does affect shot period. During shot period "full" output voltage applied across primary pulse transformer, with output held VCC-2.0V, other output held 0.3V. During this time, transformer magnetizing current rises linearly rate determined transformer inductance applied voltage: di/dt (VA-VB)/Lpri shot period, control logic reverses polarity applied voltage. During this time, output held 0.6, other output held 0.4V. result "half" voltage applied across transformer primary which opposite polarity "full" voltage, core reset. magnetizing current decreases linear rate which half rising rate. outputs held this state until current sense detectors determine that current transformer reached zero. that point, one-shot retriggered, cycle repeats. Since reset rate half energizing rate, reset time twice long energizing time. overall period carrier frequency therefore: Power transferred UC3727 only during shot period. During this time primary current magnetizing current load current. Since power transferred during reset period, primary current composed only demagnetizing current during this time. switching when current primary reaches
zero, UC3726 assures that core reset, there danger saturation. Figure shows steady state waveforms continuous logic input command. time shot pulse begins, voltage across charges until reaches threshold time magnetizing current primary builds linearly during this time. shot period ends, primary current begins decreasing. time zero current reached detectors retrigger shot, initiating next shot cycle. waveforms reflect half full voltage concepts described previously. downward slope result internal timing circuit which provides blanking interval which will allow output drivers switch states while inductor current decreasing until time period equal energizing period expired. This protection feature provided prevent switching transients from triggering state change output drivers prematurely. continuous high input commanded, waveforms interchanged, magnetizing current inverted. UC3727 determines command information sensing polarity full voltage transformer secondary.
This described detail later this application note. When command transition occurs, existing oscillator cycle terminated, cycle started applying full voltage opposite polarity. There danger saturating core, because current must fall zero before shot trigger occur. Newly incorporated circuitry prevents output jitter during command transition assuring equal propagation delay output regardless point cycle that transition occurs. FAULT/FAULT TIMING/FAULT RESET UC3726 contains special circuitry prevent drive information from being transmitted during fault conditions. FAULT input chip designed interface with UC3727 through optocoupler. power UC3726 FAULT pulled high through external resistor, fault logic reset UVLO circuitry. Once UVLO level exceeded, UC3727 drives FAULT low, fault logic enabled. After this point, UC3727 will keep FAULT unless fault indicated. Special fault detection circuitry UC3727 detects overcurrent conditions (faults) informs UC3726 through FAULT signal. recognized valid fault, FAULT signal must remain high during entire fault window. timing this window determined following equation: valid fault recognized, fault latch set, outputs will remain logic states until FRESET signal (input UC3726) toggled high. This signal should powered low, remain until valid fault recognized. Once fault cleared, FRESET signal should brought again. minimum pulse width FRESET guarantee reset 1µsec. Figure shows waveforms FAULT circuitry signals valid fault. should noted that this function requires "smart" system.
Figure Steady State Waveforms Continuous Logic Input
Figure Fault Circuitry Signals
fault latch must reset order operation continue once valid fault recognized. optocoupler used high level output capacitance, necessary provide reset pulse FRESET UC3726 after completed power sequence. Since high transition FAULT indicates valid fault, slow rising waveform this will result fault indication power this occurs, output drive UC3726 will latched until reset pulse provided. this level complexity desired required, FAULT input UC3726 permanently enabled tying low, allowing UVLO circuitry reset fault latch. UC3727 additional fault protection circuitry that will protect output IGBT independently, UC3726 will informed that fault occurred. Since FAULT input UC3726 tied through impedance, reset pulse after power required this case. SHUTDOWN/UVLO/LOGIC VOLTAGE OPERATION UC3726 provides shutdown (SHTDWN) which used place power shutdown mode. bringing this point high, internal reference disabled, supply current reduced 2.5mA typical. Since typical supply current when chip active 20mA, power savings substantial. While shutdown mode, both output drives held (ground). external logic supply used, must also disabled shutdown feature work. UC3726 also provides internal under voltage lockout (UVLO) circuitry. This feature will disable internal reference, disable output drivers (hold ground), below 6.5V. should noted, however, that must held high enough satisfy UVLO feature UC3727. pulse transformer turns ratio 1:1, must held guarantee proper operation UC3727. This requirement derived from maximum saturation drops UC3726, well UVLO, rectifier drops, specifications UC3727. operation with less than 28V, turns ratio transformer must adjusted provide enough voltage UC3727. This requirement explained further output drive section this application note, which provides detail pulse transformer selection design. UC3726 also brings logic voltage supply separate pin. external logic voltage supply used, reduced from 22mA typical 12mA typical. Regardless whether external logic supply used not, this must
passed ground with high quality ceramic capacitor least 0.1µF. UC3727 ISOLATED HIGH SIDE IGBT DRIVER Figure shows block diagram UC3727 high side IGBT driver major circuit components include Schottky diode rectifier bridge, differential sense comparator with hysteresis, bias reference generator including undervoltage lockout circuitry thermal shutdown, high current gate driver stage with programmable clamp drive level, negative gate drive voltage supply, fault detection shutdown circuitry. enable input also provided allow stand alone operation with external bipolar voltage supplies. SIGNAL POWER INPUT/NEGATIVE POWER SUPPLY shown Figure input stage UC3727 both rectifies input signal supply power demodulates input signal determine polarity gate drive command. Because rectifier bridge peak detects input signal, power only transferred storage capacitors during "full" voltage portion duty cycle. This operating mode prevents flow secondary current through pulse transformer during "half" voltage portion duty cycle. primary current therefore composed only demagnetizing current during reset "half" voltage portion cycle. Since waveform switched based zero current detection, transformer core completely reset each cycle. When "full" voltage applied, external storage capacitors charged through rectifier bridge. energy stored these capacitors used power UC3727 circuitry, provide instantaneous charge IGBT gate during turn detailed description proper capacitor selection provided decoupling section this application note. internal "GND" amplifier maintains floating common 16.5V below VCC. referencing this common point emitter IGBT, gate voltage driven negative voltage during turn off. internal hysteresis comparator UC3727 senses polarity input command determining polarity "full" input voltage. comparator threshold only reset input voltage exceeds 0.95 (VCC VEE) 0.95 (VEE VCC). IGBT gate turned "full" voltage positive with respect common, turned "full" voltage negative with respect common. Note that this represents logic
Figure UC3727 High Side IGBT Driver inversion account logic inversion UC3726. UC3727 provides separate inputs VCC, PVCC, VEE, PVEE. separating output driver supplies (PVCC PVEE) from power supplies rest circuitry, better noise immunity achieved. PVCC PVEE inputs should isolated from their respective current supplies bypassed IGBT emitter with 1.0µF capacitors shown Figure OUTPUT DRIVER STAGE output stage UC3727 consists high current, bipolar power amplifier. peak output current provides ability drive IGBT gates requiring large amounts gate charge. order provide controlled "soft" gate drive signal, gate drive programmed step turn waveform. turn drive amplifier waveform will rise user defined clamp level user defined time duration. benefits uses this clamp level explained further detail following section this application note. After time duration expires, drive waveform will then rise maximum level (approximately 15V). common output UC3727 designed referenced emitter IGBT allow gate driven negative during turn off. regulating this common point fixed level below VCC, remaining differential supply voltage (VCC VEE) (VCC VCOM) used generate negative bias. Under voltage lockout also featured UC3727. Because VCOM regulated point below VCC, differential input voltage must exceed maximum potential difference between VCOM, plus UVLO level between VCOM VEE, plus diode drops rectifier bridge. equation form this stated VEEUVLO differential input voltage supplied UC3726 through pulse transformer most cases). Consideration must given Equation when selecting supply voltage UC3726, during pulse transformer selection. worst case specifications considered, differential input voltage must greater than 25.3V guarantee proper operation UC3727. OUTPUT CLAMP/SOFT TURN common application IGBTs involves driving clamped inductive loads. this case, maximum allowable reverse recovery current clamp diode limiting factor. limit reverse recovery current provide soft turn IGBT gate. Since conduction
IGBT channel sensitive gate voltage, peak current through channel limited providing clamp level during turn Unfortunately, this will result greater switching losses. Considerable care must therefore taken when programming clamp level time duration. Tradeoffs must made system design level between reverse recovery current limitations switching losses. Referring Figure clamp level determined resistive divider between common. clamp level approximately voltage level clamp input pin. gate voltage rises, gate drive signal "caught" clamp circuit clamp level. Because significant amount charge rerouted through clamp circuit this point, clamp must bypassed common with high quality capacitor least 0.1µF, impedance clamp network should limited approximately ohms. Also referring Figure clamp time network input UC3727. When command received turn gate, gate drive circuit rises clamp level, voltage discharged internal current source. Once threshold VCC/4 reached, internal comparator trips, full gate voltage applied. clamp period determined RTRC 7600 RTRC CTRC RTRC-12400 This network also determines blanking time desaturation comparator. desaturation comparator used detect fault conditions which result IGBT coming saturation while gate drive high. turn delay IGBT, this comparator must ignored after command transition state until IGBT transitions into saturation. blanking time requirement derived from turn saturation characteristics IGBT.
Once clamp time period expired, output driver increases gate voltage fully level. voltage then allowed charge back VCC/2. total time takes discharge recharge capacitor defines blanking period determined RTRCCTRC Because have equations unknowns, clamp time blanking time programmed independently. Figure illustrates gate drive waveform voltage during positive gate drive transition. FAULT/FAULT TIMING/DESATURATION AMPLIFIER described previously, IGBTs offer several advantages over power MOSFETs their superior conduction characteristics. They also exhibit several advantages over bipolar transistors Darlingtons such lower power dissipation higher operating frequencies. Unfortunately, IGBT that been optimized superior conduction efficiency, generally vulnerable damage short circuits faults. Because their high conductivity, short circuit currents IGBTs quite high, making them susceptible damage excess power dissipation. When building short circuit protection into IGBT driver circuit, response protection circuit must fast enough insure that device shut before damage IGBT other part circuit occurs. same time, care must taken avoid nuisance triggering from short duration faults that result circuit damage. gate drive IGBT shut completely soon fault detected, result intolerable amount nuisance shut downs. Therefore, would advantageous program allowable short circuit time long possible. gate drive voltage reduced when fault detected, short circuit current reduced, therefore short circuit time stretched. However, reducing gate voltage also increases saturation voltage IGBT, which undesirable normal conduction. Therefore, ideal short circuit protection technique will reduce gate voltage only when fault condition detected, keep gate voltage reduced level long possible, before shutting down IGBT completely. order this technique work effectively, maximum short circuit time function gate voltage must known. Referring again Figure UC3727 provides desaturation comparator designed detect short circuit fault conditions, provide both short term long term protection IGBT.
Figure Gate Drive Waveforms Positive Gate Transition
DSAT+ input comparator biased level which higher than maximum saturation level IGBT plus diode drop. During normal operation, DSAT- input will pulled down saturation voltage IGBT plus diode drop. blanking period discussed previously protects against false trips desaturation comparator while IGBT turning fault occurs outside blanking interval, gate drive will reduced clamp level time period determined network UC3727. time period calculated following equation: RFRC CFRC ln((R 7600)/(R 12400)) soon fault detected FRPLY output UC3727 will high. UC3726 configured accept this signal input, through optocoupler level shift network, fault timing circuitry will activated. desaturation event ends before fault time expired, gate drive will driven back maximum level, FRPLY will back low. order insure that desaturation amplifier accurately determine that fault condition longer
exists, DSAT- input level must biased higher than desaturation level IGBT with reduced gate drive, plus diode drop. desaturation event does within fault time, output gate drive will driven completely off, chip will accept command drive gate high until delay period expired. equation delay period determined same network fault time: RFRC CFRC Again, since there equations unknowns, fault time delay time programmed independently. FRPLY will remain high entire delay period. UC3726 configured accept FRPLY input, will have ability prevent command turn gate from being transmitted until fault latch been reset. Figure shows waveforms fault signals both transient long term faults. ENABLE INPUT/STAND ALONE OPERATION UC3727 provides active enable input stand alone operation. This input useful operating chip high side driver with isolated power supplies. enable input also used control chip side driver applications external power supplies available. UC3727 used stand alone mode, i.e. driven UC3726, enable input should tied common. ENBL used command input, input should tied VCC, input should tied VEE. Note polarity change described previously. output gate drive will driven high when ENBL held same potential common, gate drive will held when ENBL tied VCC. side driver applications ENBL controlled discrete transistor operating conventional logic. high side driver applications, ENBL must controlled optocoupler, discrete transistor operating level shift network. Because optocoupler discrete transistor will function inverter this case, result will positive logic output. Therefore, turning optocoupler transistor will turn IGBT. Figure shows circuit diagram using ENBL input command input. external power supplies used grounded emitter side operation, common should never connected system ground. This point designed sink large amounts current flowing emitter IGBT. Both positive negative supplies should bypassed common with capacitors, common output should isolated from ground.
Figure Fault Signal Waveforms
clamp diodes. Component values support circuitry chosen based specific requirements system. What follows step step design procedure typical circuit. PULSE TRANSFORMER DESIGN CONSIDERATIONS Application note U-127 provides detailed explanation recommended transformer design criteria UC3724/UC3725 chip pair. Since transformer design procedure similar UC3726/UC3727 chip pair, theory repeated this application note. However, transformer been designed Coilcraft (Q3868-A) specifically with UC3726/UC3727 pair. This transformer been optimized operation 400kHz, resulting small size cost. Since maximum switching frequency IGBT transformer frequency, resulting 100kHz maximum IGBT frequency near typical maximum operating range power IGBTs. following calculations provide brief overview design Q3868-A transformer: Assuming UC3726 typical total saturation drops 2.3V output drivers, resulting voltage across transformer winding will 27.7V. Ignoring propagation delay, choosing peak magnetizing
Figure ENBL Used Command Input PRACTICAL DESIGN CONSIDERATIONS/EXAMPLE CIRCUIT Figure depicts typical high side IGBT driver circuit. features driver pair utilized provide maximum circuit protection flexibility. This configuration might used high side switch power supply, might form part H-bridge configuration motor driver. resistive load assumed order illustrate high switching speeds driver pair. Real systems would likely require driving clamped inductive loads, switching speed would purposely slowed protect external components such
Figure Typical High Side Driver Circuit
current 35mA, required primary inductance calculated using Equation U127: Lpri ((27.7V)(833ns))/0.035A 659µH 833ns represents period 400kHz carrier, which pulse width time defined Equation this document: 1/(3 400kHz) 833ns Using Equation U-127, initial value 2000mH/1000 turns, estimated number turns calculated: NTURNS ((659µH 109)/2000)1/2 turns From Equation U-127: ((27.7V)(833ns)(104)/((18 turns) (0.05T)) 0.256 Magnetics core, P-41206-TC chosen with following specifications: 2820mH/1000 turns 0.221 0.554 Recalculating number turns yields: NTURNS ((659µH)(109)/2820)1/2 15.3 turns, turns flux density transformer design then checked using Equation U-127: delta ((27.7V)(833ns)(104)/((15 turns) (0.221 cm3) 0.069T determine core loss magnetizing current, core loss flux density curve core consulted: 400kHz 0.069T, 400mW/cm3 Therefore, core loss calculated (400mW/cm3)(0.554 cm3) 222mW transformer wound with KYNAR wire. order minimize leakage inductance, primary secondary windings wound bifilar. maximum resistance primary winding 0.130 ohms, therefore resistive losses magnetizing current minimal. There will additional resistive losses bias current UC3727 gate drive current IGBT. IGBTs with large gate charge requirements, these losses become significant, transformer design must adjusted accordingly. some cases necessary damping resistor across transformer secondary minimize ringing eliminate false triggering hysteresis comparator.
Once transformer design been completed, operating frequency been chosen, values selected. Since wider selection resistors available than capacitors, choose 100pf. then Equation shot pulse width 833ns determine (833ns)/((100pF 50pF) 1.1) 5.1k Referring Figure this results 5.1k 100pF. OUTPUT DRIVE CONSIDERATIONS/CLAMP LEVEL BLANKING TIME order design gate drive portion IGBT driver circuit, several criteria must considered balance what sometimes conflicting requirements. ideal situation would involve switching IGBT fast possible minimize switching losses. However, there will cases when desirable reduce switching speed IGBT. example case would slowing down turn time limit reverse recovery current into free wheel diode when driving clamped inductive load. Another example might reducing turn time half bridge configuration prevent cross conduction. order evaluate drive requirements IGBT, gate charge characteristics device used. However, evaluating gate charge does lead good prediction switching times does with power MOSFETs. reason this fact that IGBTs minority carrier devices. This characteristics leads slower switching times than power MOSFETs base charge storage. turn time much slower than turn time, characterized "tail" current waveform. predict switching times IGBTs, manufacturers data sheets must consulted turn delay on), rise time (tr), turn delay off), fall time drive circuitry should designed that additional delay introduced gate charge requirements. example shown Figure APT50GL60BN IGBT used (500V, 60A). timing specifications this device follows: Total Gate Charge (Qg) 110nC Turn Delay 15ns Rise Time (tr) 50ns Turn Delay (td) 55ns Fall Time (tf) 350ns UC3727 output stage peak driver. time required charge gate therefore: 110nC/4A 27.5ns
Since this time about half turn delay time rise time, significantly reducing drive current will slow down turn time device. However fall time IGBT much longer (350ns), therefore gate drive current does significantly affect turn time. example circuit assumed that fastest switching speed possible desired. However, since UC3727 rated peak drive current, gate resistor used limit peak current. Taking into account rectifier saturation drops, maximum swing gate voltage 20.5 volts. gate resistor therefore chosen 21.5V/4A 5.1ohm, 5.6ohm circuits like half bridge amplifiers where cross conduction concern, diode used with dual gate resistors provide higher gate impedance turn than turn off, provide cross conduction protection. example this technique shown design example section this application note. circuits where collector IGBT subjected high dv/dt, gate resistor must sufficiently small prevent unwanted gate turn voltage drop across gate resistor when current flows through Miller capacitance presence high dv/dt. high current IGBTs, emitter inductance also cause transient turn presence high di/dt, pulling emitter node negative. These problems partially mitigated negative gate bias gate drive state, designer must aware additional limitations gate resistor selection large values gate resistors desired. large IGBTs power rating gate resistor must also considered. order determine average power dissipated gate resistor, energy supplied capacitor determined (2)(1/2) CGATE (QGATE QGATE factor comes from fact that gate must both charged discharged gate drive circuit. Each time gate charged discharged, gate drive circuit will dissipate amount energy which equal amount energy supplied gate. assume that gate drive signal running 15kHz, average power dissipated gate drive circuit PAVG (QGATE V)/T QGATE (110nC)(20.5V)(15kHz) 34mW Obviously this example power dissipation gate drive circuit problem. However, IGBTs with higher gate charge requirements, higher operating frequencies, power dissipation become significant, must taken into
consideration. select power rating gate resistor, assuming that power gate drive circuit dissipated gate drive resistor will lead conservative gate resistor rating. power resistor required, should have inductance. wirewound resistor recommended this application, used, must noninductively wound. output UC3727 should protected against adverse affects voltage overshoot gate drive signal clamping output circuit both with Schottky diodes. This done circuit shown Figure with UC3612 dual Schottky diode. detailed explanation this problem Unitrode Application Note U-111. Once gate drive resistor been selected, clamp level, clamp time, desaturation amplifier blanking time must selected. Choosing clamp level involves trade between soft turn requirements short circuit characteristics IGBT. Basically soft turn requirements derived from reverse recovery characteristics free wheel diode IGBT driving clamped inductive load. Since conductivity IGBT reduced lower gate voltage, maximum current that free wheel diode sees during reverse recovery controlled. Since this example assumes resistive load, short circuit characteristics IGBT will determine clamp requirements. Unfortunately, short circuit characteristics always well known. Considerable effort must expended test device determine safe clamp level clamp time. Test data suggested that IGBT used this example, reduction gate voltage will allow maximum short circuit time about 40µs with 200V. With full gate drive, short circuit time would worst case. However, secondary requirement clamp circuitry that protection circuitry must able recognize that device back saturation fault goes away during allowable fault period. gate drive voltage APT50GL60BN will remain saturation peak normal current load 20A. Therefore chosen conservative number clamp level. Once clamp level known, only other constraint that impedance must limited approximately ohms. With that mind, referring Figure have: (16.5V)(R14 /(R6
solution 5.1k will satisfy design requirements. clamp input also bypassed common with 0.1µF discussed output clamp section this application note. previously detailed, clamp time rising edge gate drive waveform only important when driving clamped inductive loads. purposes this example, this time arbitrarily chosen 0.5µs. blanking time desaturation amplifier limited maximum allowable short circuit time under full gate drive voltage. This requirement stems from fact that fault present before IGBT commanded UC3727 determining that fault present. Therefore, IGBT will drive into short circuit full gate voltage duration blanking time. Since maximum allowable short circuit time under these conditions 5µs, blanking time should less, selected. Equations solved simultaneously obtain 100pF, 91k. DESIGN CONSIDERATIONS FAULT CIRCUITRY program fault circuitry, short circuit characteristics IGBT again used. first consideration threshold desaturation comparator, which programmed inverting input. fast response, this trigger amplitude should possible. However, must also high enough allow comparator recognize fault gone away during fault window. detailed previous section, IGBT will operating under reduced gate voltage that time. data sheets APT50GL60BN indicate that gate voltage collector current 20A, collector emitter saturation voltage Allowing margin, plus maximum diode drop DSAT- input selected level programmed voltage divider formed R13, assuming minimum level 15.5V. This leads 51k. diode used fault circuit must chosen fast reverse recovery, capacitance, high breakdown voltage rating. reverse recovery time should least order magnitude faster than short circuit time rating IGBT. capacitance should enough prevent high currents from flowing into DSAT- input presence high dv/dt. Finally, breakdown voltage rating must obviously greater than maximum IGBT collector voltage. IGBT collector voltage relatively low, diode replaced with high value resistor. This solution advantages capacitance
reverse recovery problems. However, extreme care must exercised insure that resistor large enough prevent DSAT+ from overvoltage conditions formed resistive divider when IGBT off. Another alternative power applications more conventional current sense resistor emitter IGBT. DSAT+ input tied high side sense resistor, DSATinput biased some trip point proportional emitter current. This allows more precise control maximum current through IGBT. Usually voltage drop power dissipation sense resistor high make this practical solution though. example this technique shown examples section this application note. chosen provide adequate bias current diode insure that state when IGBT saturation. provides isolation between diode DSAT+ input. selection fairly arbitrary, reverse recovery capacitance characteristics diode must considered insure that excess current injected into DSAT+ input during switching transitions. next consideration selection time gate will held clamp level presence fault, referred fault window. Since allowable short circuit time with gate drive 40µs, fault window selected 10µs allow plenty margin. selection delay period should take into account relative slow speed optocouplers, timing requirements FRESET signal that must provided UC3726. blanking period chosen 100µs this example. Using equations this leads 10µs (R8)(C13) ln((R8 7600)/(R8 12400) 100µs (R8)(C13) These equations yield standard values when solved simultaneously. close solution 2200pF 91k. This results fault window 11.8µs blanking period 80µs. only remaining programmable option selection fault window timing UC3726. This time duration must long enough allow slow speed optocoupler. this example, optocoupler (CNY17) typical switching time 10µs. Choosing 2200pF solving Equation results fault window 23µsec. FILTER/DECOUPLING CAPACITOR CONSIDERATIONS
Proper bypass capacitor selection essential insure proper operation UC3726/UC3727 chip pair. UC3726 does have high peak current requirements that UC3727 does therefore high quality ceramic capacitor about usually sufficient. This capacitor must located close pins chip possible. UC3727 other hand must supply high peak currents during charging discharging IGBT gate. While average current gate drive ultimately supplied UC3726 through pulse transformer, circuit inductances force most instantaneous peak current come from bypass capacitors. insufficient bypassing used, ripple voltage UC3727 large enough trip under voltage lockout circuitry. order determine maximum allowable ripple voltage, Equation used. margin allowed Equation becomes maximum ripple voltage. Since ripple voltage results from charging IGBT gate, equation leads bypass requirements PVCC PVEE: Vripple (VCC VEEUVLO ripple voltage will composed gate charge component component. gate charge component results from voltage drop bypass capacitor gate charge requirements. resulting voltage drop decoupling capacitor gate charge requirements expressed follows: dVCHARGE QG/CBYPASS ripple component loss directly proportional peak gate current. expressed dVESR IPEAK Equation represents equivalent series resistance bypass capacitor. voltage drops represented Equations must exceed maximum ripple voltage. example shown Figure Equation yields maximum ripple voltage 1.6V. peak gate current limited therefore calculate maximum allowable from Equation maximum allowable loss 0.5V have: 0.5V/4A 0.125 (max) Allowing 0.5V charge component ripple voltage sets minimum value bypass capacitance: CBYPASS 110nC/0.5V 0.22µF (min) this circuit single capacitor both
PVCC PVEE pins UC3727 sufficient. larger values gate charge solution would involve small ceramic capacitor larger electrolytic capacitor parallel supply gate charge. conservative, 10µF electrolytic capacitor added between PVCC PVEE. pins also bypassed described earlier this application note resistive isolation provided between high power power voltage supplies. added balance supply currents ensure active start presence slowly rising supply voltages. These equations only describe minimum bypass requirements. system particularly noisy, significantly more bypass capacitance required. TEST CIRCUIT RESULTS example circuit built tested verify operation, with results shown Figure waveforms shown. Notice characteristic "tail" turn waveforms both current voltage. tail results from fact that IGBTs minority carrier devices, therefore have stored charge. beginning turn off, collector emitter current decreases rapidly level hole recombination current device. this point di/dt decreases, voltage current waveforms tail much slower rate. reason bump voltage waveform that di/dt decreases, inductive voltage drops also decrease, therefore
Figure Test Circuit Waveforms (VPD 375V)
more voltage dropped across IGBT start tail. Figure shows waveforms same circuit when tested with 375V. Notice slower switching times higher output voltage current.
there diode protection circuit therefore reverse recovery problems worry about. Also with this technique, more precise control current limit possible. drawback this approach that filter time constant required long IGBTs that tolerate fault conditions very long. Also, high power applications power requirement sense resistor impractical. HALF BRIDGE OUTPUT CIRCUIT
Figure Detecting Faults with Current Sense Resistor
Figure Test Circuit Waveforms (VPD 375V) DESIGN EXAMPLES/APPLICATIONS example circuit described earlier this application note provides good baseline calculating component values required support circuitry IGBT driver pair. Many other circuit topologies used with this chip set, same general rules apply example circuit. individual system designer must evaluate particular requirements, make component selections accordingly. This section illustrates some general circuit topologies which encountered typical system designer. SENSING FAULTS WITH CURRENT SENSE RESISTOR Figure shows detecting faults with current sense resistor. desaturation comparator used detect over current conditions. Using resistor divider network from allows trip level SAT- input comparator. Current sensed emitter IGBT, with filtered voltage across current sense resistor into DSAT+ input. This approach advantage power applications because
Figure shows half bridge output circuit with dual secondary transformer. side bridge driven UC3727 with polarity reversed from upper side driver. Cross conduction controlled providing dual gate resistors both upper lower IGBTs. Carefully selecting provide fast turn-off slow turn-on. more accurate dead time between commands upper lower IGBTs required, ENBL inputs used. Using optocou-
Figure Half Bridge Output Circuit
Figure Dual High Side Driver Circuit pler level shift network, ENBL input controlled separately assure that cross conduction prevented. MULTIPLE ISOLATED DRIVER CIRCUIT Figure shows dual isolated driver circuit topology. using multiple secondary winding transformer, several IGBTs driven simultaneously. Isolation, command signal, power provided each IGBT single transformer. Obviously power dissipation UC3726 consideration, ultimately will limiting factor determining maximum number IGBTs that driven. ENBL inputs also used provide dead time between IGBTs required. UC3726/UC3727 IGBT EVALUATION Unitrode Integrated Circuits designed evaluation which used demonstrate UC3726/UC3727 IGBT driver pair. consists custom board, each UC3726 UC3727, UC3612 Schottky diode pair, Coilcraft Q3868-A transformer. purpose this evaluation provide user with quickly demonstrating driver pair individual application. schematic, silkscreen, artwork evaluation board shown Figures respectively. schematic evaluation board identical schematic shown example circuit (Figure except some additional components which required evaluate certain conditions. Table shows list materials demo board building example circuit. desired evaluate other requirements than those deREFERENCES Andreycak, "PRACTICAL CONSIDERATIONS CURRENT MODE POWER SUPPLIES", UNITRODE APPLICATION NOTE #U-111. Andreycak, "HIGH PERFORMANCE MOSFET, IGBT, DRIVERS", UNITRODE APPLICATION NOTE #U-137. O'Connor, "UNIQUE CHIP PAIR SIMPLIFIES ISOLATED HIGH SIDE SWITCH DRIVE", UNITRODE APPLICATION NOTE #U-127. Clemente, Dubhashi, Pelly, "IGBT CHARACTERISTICS APPLICATIONS", INTERNATIONAL RECTIFIER APPLICATION NOTE #983. International Rectifier, Segundo, California (213) 772-2000. APT50GL60BN IGBT Data Sheet, Advanced Power Technology, Bend, Oregon (908) 776-8272. Coilcraft telephone number 1-800-322-COIL scribed this application note, same equations should used determine component values. more information obtaining this demo kit, contact Unitrode Integrated Circuits (603) 4298610. SUMMARY utilizing UC3726/UC3727 IGBT driver chip pair, practical cost-effective solution problem driving high-side IGBTs realized. This chip pair incorporates several special features provide fault protection optimum gate drive. Using high voltage isolation transformer precludes need high voltage integrated circuits. This chip pair ideally suited wide range isolated IGBT driver applications.
Figure IGBT Driver Pair Evaluation Board Schematic
TABLE UC3726/UC3727 IGBT ISOLATED DRIVER PAIR DEMO LIST MATERIALS CAPACITORS C14, DIODES UF4007, 1000V (General Instrument) 100pF, 2200pF, 0.1µF, 1µF, 1µF, 10µF, INTEGRATED CIRCUITS UC3726Isolated Drive Transmitter UC3727Isolated High Side IGBT Driver CNY17 Optocoupler, 10µs UC3612 Schottky Diode Pair 1/4W 5.1k, 1/4W 10k, 1/4W 91k, 1/4W 5.6, 18k, 1/4W 51k, 1/4W 3.3, 1/4W
R11, Ropt R10, R15, R16, MAGNETICS
Coilcraft Q3868-A *Included with demo kit.
Figure Component Side
Figure Solder Side
UNITRODE CORPORATION CONTINENTAL BLVD. MERRIMACK, 03054 TEL. (603) 424-2410 (603) 424-3460
Unitrode Corporation makes representation that interconnection circuits described herein will infringe existing future patent rights, descriptions contained herein imply granting licenses make, sell equipment constructed accordance therewith. 1994 Unitrode Corporation. rights reserved. This bulletin, part parts thereof, must reproduced form without permission copyright owner. NOTE: information presented this bulletin believed accurate reliable. However, responsibility assumed Unitrode Corporation use.
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