Preliminary Version Last Updated 1/14/03 LynxEM+ DataBook
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Mobile Computer Display Controller
Preliminary Version
Last Updated 1/14/03
LynxEM+ DataBook
Silicon Motion Inc.
LynxEM+ Databook
Silicon Motion Inc.
LynxEM+ DataBook
Notice Silicon Motion, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice. responsibility assumed Silicon Motion, Inc. this information, infringements patents other rights third parties.
Copyright Notice Copyright 2002, Silicon Motion, Inc. rights reserved. part this publication reproduced, photocopied, transmitted form, without prior written consent Silicon Motion, Inc. Silicon Motion, Inc. reserves right make changes product specification without reservation without notice users
Version Number
Date
9/30/99 11/12/99 12/20/99 02/16/99 05/23/00
Note
registers same LynxEM with exception following: CCR62 7:6, MCR62 Figure Diagram updated Table Description Updated Table SM712 Diagram Package Updated VCLK table register CCR6D Updates Description table Power-on configuration table Change Description Table (VCC Ground Pins) delete reference from FPVDD Delete reference VESA DDC2B Interface Added 4Mbyte internal memory configuration Minor corrections based field input. Change diagram VCC. Changed List Added ordering information table Changed Digital Specification operating power dissipation Revised block diagram Changed Specification MCLK Electrical Specifications Added Sleep Mode Digital Specification table Electrical Specifications
12/07/00 3/31/01 6/27/01 10/18/01
Silicon Motion Inc.
LynxEM+ Databook Date
Version Number
Note
Change Removed panel support 1280x1024 Changed VCCA Delete External SGRAM Configuration figure Minor corrections based field input Changed Digital Specificaitons Changed from MEMINT Clarified definition Interface page Removed references Removed Master Mode with LynxEM+ does support this feature
3/28/02
7/16/02 1/14/03
Silicon Motion®, Inc.
LynxEM+ DataBook
Table Contents
Chapter Overview Functional Block Summary Interface HIF. Memory Controller Drawing Engine Power Down Control Unit Video Processor Video Capture. Backend Controller Popup Icon Core. Module RAMDAC. Chapter Pins LynxEM+ Descriptions LynxEM+ NAND Tree Scan Testing 2-14 General Information 2-14 Chapter Initialization LynxEM+ Power-On Configurations Chapter Interface Configuration Registers Chapter Display Memory Interface Memory Configuration Page Break Look Ahead Memory Timing Control Chapter Video Processor Chapter Drawing Engine Chapter Zoom Video Port Video Capture Unit Zoom Video Port Video Capture Unit. Functional Description Theory Operation Chapter Flat Panel Interface Reduction Circuit LynxEM+ Flat Panel Enhancements LynxEM+ Graphics/Text Expansion Information Introduction. Horizontal Expansion Text Graphics Vertical Expansion Text Graphics Dithering Engine Flat Panel Power ON/OFF Sequencing LVDS Chipset Interface Chapter Miscellaneous Functions 10-1 Video BIOS Interface 10-1 VESA DPMS Interface 10-2 VESA DDC2B Interface 10-2 Chapter Clock Synthesizers 11-1 Chapter Multimedia RAMDAC 12-1
Table Contents
Silicon Motion®, Inc.
LynxEM+ DataBook
Backend (RAM1) 12-1 Chapter Signature Analyzer 13-1 Chapter Power Management 14-1 ACPI 14-1 Adaptive Power Management 14-1 Dynamic Control Functional Blocks 14-1 Dynamic Clock Control Virtual Refresh. 14-2 Standard Power Management 14-2 Standby Mode 14-2 Power Saving Standby Mode. 14-3 Sleep Mode 14-3 Activity Detection 14-4 Power-down Sleep Mode States 14-4 Chapter Configuration Space Registers 15-1 Configuration Space Registers 15-2 Extended Registers. 15-8 Chapter Standard Registers 16-1 Standard Registers 16-4 General Registers 16-4 Sequencer Register. 16-6 CRTC Controller Registers 16-9 Graphics Controller Registers 16-21 Attribute Controller Registers 16-26 RAMDAC Registers 16-30 Chapter Extended Registers 17-1 Extended Registers 17-6 System Control Registers. 17-6 Power Down Control Registers 17-13 Flat Panel Registers 17-18 Memory Control Registers. 17-38 Clock Control Registers 17-40 General Purpose Registers 17-46 Pop-up Icon Registers 17-50 Hardware Cursor Registers 17-52 Extended Control Registers. 17-54 Shadow Registers 17-63 Automatic Lock/Unlock Scheme Shadow Registers 17-64 Chapter Memory Mapped Registers 18-1 Drawing Engine Control Registers 18-4 Video Processor Control Registers 18-20 Capture Processor Control Registers 18-36 Chapter Electrical Specifications 19-1 Absolute Maximum Ratings 19-1 Specifications 19-1 Specifications 19-2 Timing Specifications 19-3 Cycles 19-4 Flat Panel Interface Cycle Timing 19-5 Chapter Mechanical Dimensions 20-1 Chapter Index 21-1
Table Contents
Silicon Motion®, Inc.
LynxEM+ DataBook
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure System Block Diagram LynxEM+ SM712 Diagram Package NAND Tree Connection 2-14 External SGRAM Power-Up Initialization Sequence LynxEM+ BIOS Initialization Flowchart Video Processor Block Diagram Video Encoder Interface Video Port Video Capture Block Diagram Video Capture Data Flow Capture Buffer Structure Interlaced Mode Expansion Algorithm (Single Pixel/Clock) Interface Diagram Panel pixels/clock) Interface Diagram 16-bit DSTN Interface Configuration 24-bit Dual Color Interface Diagram Panel Power Sequencing Timing Diagram Panel Power Sequencing Timing Diagram LVDS Interface with Panel LVDS Interface with DSTN Panel 36-bit (18x2-bit) Interface Diagram 9-10 PanelLink Interface with Panel 9-11 PanelLink Interface with DSTN Panel 9-11 Video BIOS Configuration Interface 10-1 LynxEM+ Protocol Flow Chart 10-3 Clocks Generator Block Diagram 11-1 LynxEM+ RAMDAC Block Diagram 12-1 Signature Analyzer Block Diagram 13-1 Memory Mapped Address Diagram 18-3 Power-on Reset Reset Configuration Timing 19-3 Timing Diagram 19-4 Interface Timing 19-5 DSTN Interface (Clock Data) Timing 19-6 DSTN Interface (Control Clock) Timing 19-6 Mechanical Dimensions 20-1
List Figures
Silicon Motion®, Inc.
LynxEM+ DataBook
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table LynxEM+: Display Support Modes Description SM712 Diagram Package. NAND Tree Scan Test Order 2-14 Power-On Configurations. LynxEM+ Video Port Interface Configurations Setting Summary Video Capture Flat Panel Interface Pins listing color DSTN color LVDS Transmitter Mapping Interface 9-12 LVDS Transmitter Mapping DSTN Interface 9-13 PanelLink Transmitter Mapping Interface 9-14 PanelLink Transmitter Mapping DSTN Interface 9-15 DPMS Summary. 10-2 Recommended Values Common VCLK Settings 11-2 Interface Signals Sleep Mode States 14-4 Configuration Registers Quick Reference. 15-1 Standard Registers Quick Reference 16-1 Configuration Registers Quick Reference. 17-1 Memory Mapped Registers Quick Reference 18-1 Absolute Maximum Ratings. 19-1 Digital Specification 19-1 RAMDAC Characteristics 19-2 RAMDAC/Clock Synthesizer Specifications 19-2 RAMDAC Specifications 19-2 Power-on Reset Configuration Reset Timing 19-3 Timing 19-4 Color Interface Timing. 19-5 Color DSTN Interface Timing 19-6 Ordering Information 20-2
List Tables
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Overview
LynxEM+ combines Silicon Motion's unique multimedia features into solution. LynxEM+ includes video memory within single footprint. This powerful single footprint solution, when combined with SMI's Virtual Refresharchitecture provides complete video subsystem which consumes very little power. LynxEM+ offers enhanced capabilities dual view handling dual applications. Through Virtual Refresh architecture, LynxEM+ simultaneously drive LCD/CRT LCD/TV display combinations. Each display support independent full screen full motion video, well independent graphics refresh rates, resolutions, color depths. LynxEM+ display slides TV/CRT while attached speaker notes available display, invisible audience. dual application experience, spreadsheet displayed LCD, while word processing application browser displayed CRT. Dual view dual application support provided under Windows Windows Windows Windows 2000. LynxEM+ incorporates three separate PLLs allow flexible control functional blocks within device. robust Drawing Engine supports ROPs, BitBLT, transparent BLT, pattern BLT, color expansion, line draw. Host Interface Unit compliant supports mastering. Power Down Control Unit with Dynamic Power Management provides individual block shutdown capability complete Standby Suspend support. Core, Backend Controller RAMDAC incorporated well. LynxEM+'s Concurrent Video Processor Video Capture Unit provide superior video quality real-time video capture playback. LynxEM+'s Video Processor supports multiple independent full screen, full motion video windows with overlay. Each motion video window uses hardware YUV-to-RGB conversion, scaling, color interpolation. When combined with dual view capabilities chip, these independent video streams output separate display devices bilinear scaled support applications such full screen display local remote images video conferencing. LynxEM+ designed with 0.35m, TLM, 3.3V CMOS process technology. hierarchical layout approach provides enhanced internal timing control. addition built-in test modes signature analyzer, LynxEM+ incorporates 20-bit test designated Bus. used simultaneously monitor internal signals from functional blocks through Zoom Video (ZV) Port Interface. capability used increase fault coverage, reduce silicon validation debugging time. LynxEM+ available package.
Overview
Silicon Motion®, Inc.
LynxEM+ DataBook
PCI/AGP PCI/AGP2X Port
Lynx3DM+ LynxEM+ 4/8/16MB
Monitor
Flat Panel
Figure System Block Diagram LynxEM+
Overview
Silicon Motion®, Inc.
LynxEM+ DataBook
Features
Dual Application support under Microsoft Windows Windows Windows with LynxEM+ device Dual Display support under Microsoft Windows Windows Windows Virtual Refresh Architecture
Benefits
applications available same time across display devices. Example: Word LCD, Excel Single chip implementation ideal mobile systems
Portion primary display zoomed display secondary display. Example: Zoom power point slide CRT, slide accompanying speaker notes visible operational power consumption Simultaneous display different resolutions refresh rates Simultaneous display interlaced non-interlaced display
Dynamic power management Individual functional block shut-down Standby, Suspend support Multiple independent hardware video windows YUV-RGB color space conversion Bilinear interpolation
Minimize power dissipation extend battery life
Independent full screen, full motion video separate displays. Complete dual view support video under Windows98 Example: video conferencing Full screen local view LCD, full screen remote view CRT/TV.
Robust, single clock cycle Drawing Engine BitBLT, Transparent BLT, Pattern ROPs Color Expansion Line Draw High performance memory interface internal memory 64-bit memory Mastering
notch graphics performance mobile systems
LynxEM+ provides 400MB/s bandwidth support graphics video. LynxEM4+ provides 688MB/s bandwidth support graphics video. Move graphics data video to/from system memory local graphics memory without impacting performance. Example: Master local videoconferencing image system memory. Supports panel requirements mobile systems Graphics and/or video display
DSTN panel support 1024x768 TVout support Flicker filter Overscan/Underscan support 135MHz 24-bit RAMDAC Zoom Video Port Hardware support landscape/portrait rotation PC99 Compliant, ACPI Compliant support Microsoft Windows Microsoft Windows Microsoft Windows Hardware Video "Bob" Support
Provides PC99 compliant refresh rates Provides support camera tuner input, input Portrait view applications desktop publishing, word processing
Meets WHQL certification requirements Complete support Improves playback quality
Microsoft, Windows, Windows registered trademarks trademarks Microsoft Corporation
Overview
Silicon Motion®, Inc. Functional Block Summary
LynxEM+ DataBook
LynxEM+ consists logic block which interfaces block internal memory. internal memory configuration consists 512Kx32 SGRAM, supports single clock cycle transfers 100MHz. Peak memory bandwidth internal memory over 500MB/s. logic within LynxEM+ consists functional blocks: Interface, Host Interface (HIF), Memory Controller, Drawing Engine, Power Down Control Unit, Video Processor, Video Capture Module, Backend Controller, Core, Module, RAMDAC. summary each functional blocks, along with important features follows: Interface LynxEM+'s Host Interface Unit supports burst read, burst write. Host Interface Unit decodes read, write, memory read, memory write, memory mapped access, Drawing Engine access, access, others. unit also supports Little-Endian Big-Endian format, 8-bit decode board video BIOS ROM. dual aperture feature designed support modes non-VGA modes. addition, special aperture function added allow 64-bit memory access modes. LynxEM+ internal (Host Interface) which designed transfer data between Host Interface Unit other functional blocks. Host Interface Unit controls protocol effectively deliver memory cycles each functional block.
Feature Summary:
Master/Slave interface compliant Dual aperture feature concurrent video/drawing engine access
Memory Controller Memory control provided internal memory. Page Break Look Ahead support assures memory cycle broken there change memory agent within same memory page. Programmable memory arbitration allows memory interface usage fully optimized priority round robin arbitration supported.
Feature Summary:
500MB/s memory bandwidth
Drawing Engine LynxEM+'s Drawing Engine designed accelerate through APIs such Direct Draw. engine pipeline runs single clock cycle speeds 62.5MHz. engine supports functions such operand with raster operations, pattern BLT, color expansion, trapezoid fill, line draw.
Feature Summary:
62.5MHz single clock/cycle engine (EM+) 86MHz single clock/cycle engine (EM4+) Designed accelerate DirectDraw
Power Down Control Unit Power Down Control unit provides Dynamic Power Management functional blocks within LynxEM+. Dynamic Power Management made possible individual clocking control each functional blocks within LynxEM+. Each clock given functional block skew matched maintain synchronization between blocks. functional blocks then turned on/off fly" needed. Power savings under fully operational conditions maximized, process completely transparent user.
Overview
Silicon Motion®, Inc.
LynxEM+ DataBook
Control Virtual Refresh provided through Power Down Control unit well. Through Virtual Refresh, panel timing driven from fully independent PLL. VLCK significantly reduced, while retaining full graphics performance. result significant power savings only configurations. Finally, Power Down Control unit generates power down sequencing Standby Suspend modes. Internal autostandby system standby implementations supported. Under sleep mode, options memory refresh type internal PLL/external clock memory refresh clock provided. Activity detection supported resuming from Standby Suspend modes.
Feature Summary:
Dynamic Power Management Virtual Refresh Standby Suspend model support ACPI, DPMS, compliant
Video Processor Video Processor module manages video playback LCD, CRT, display. Independent video sources scaled displayed full screen different display devices ideal videoconferencing applications. Video Processor module supports, bi-linear scaling, color space conversion, color key, overlay graphics over video. Video Processor module also supports flicker reduction adjustable overscan/underscan display.
Feature Summary:
Multiple video windows Independent video sources different displays Bi-linear scaling Flicker filter underscan display
Video Capture Video Capture module processes incoming video data from Zoom Video Port sends data local video frame buffer. From there, data displayed, well mastered storage hard drive. Incoming data from Zoom Video port interlaced non-interlace format. data cropped, horizontally filtered (2,3,or 4-tap), shrunk size. Single buffer well double buffer capture supported.
Feature Summary:
Support Zoom Video Port interface Crop, filter, shrink support Support implementation when interlaced data captured
Backend Controller Backend Controller module manages data flow generates timing selected display. module provides support 36-bit 24-bit DSTN panels 1024x768 resolution. backend controller contains color encoder, dithering engines DSTN panels, frame accelerator, Virtual Refresh timing generation block. Each blocks within Backend controller module powered down use. addition LynxEM+ integrates innovative circuitry reducing EMI.
Feature Summary:
DSTN support 1024x768 Timing generation Virtual Refresh reduction circuit
Overview
Silicon Motion®, Inc. Popup Icon
LynxEM+ DataBook
LynxEM+ support 64x64 popup icon which zoomed become 128x128 popup icon. popup icon programmed anywhere screen display. addition, popup icon transparency support.
Feature Summary:
Popup icon location flexible Transparency color support
Core LynxEM+ high performance 32-bit core which 100% compatible. addition standard functions, LynxEM+'s core module generates timing, performs screen autocentering expansion, generates timing, provides Hardware Cursor control.
Feature Summary:
100% compatible
Module module provides three separate PLLs MCLK, VCLK, Virtual Refresh clock drive panel timing. 14.318MHz base clock used drive timing. This allows completely independent timing LCD/CRT LCD/TV under dual application dual view. instance, panel driven 60Hz while refresh 85Hz.
Feature Summary:
Separate panel timing
RAMDAC integrated RAMDAC supports pixel clock frequencies 135MHz 3.3V. Anti-sparkle logic provided read/ writes palette. internal band voltage reference saves need external components.
Feature Summary:
135MHz 3.3V
Overview
Silicon Motion®, Inc.
LynxEM+ DataBook
Table LynxEM+: Display Support Modes
Only
Display Resolution Refresh (Hz) 640x480 800x600 1024x768 Color Depth
Simultaneous Mode
Display Resolution 640x480 800x600 1024x768 Refresh (Hz) Color Depth
Dual Display Mode
Display (D1) Display (D2) 640x480 640x480 800x600 1024x768 640x480 800x600 800x600 1024x768 640x480 1024x768 800x600 1024x768 Color Depth (Max Color Depth Display bpp) when (D2) when (D2) when
color depth display 16bpp under dual display
Overview
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Pins
SM712 package. Figure illustrates pinout diagram SM712 package. Figure illustrates mechanical dimensions package.
LynxEM+ Descriptions
following table, Table provides brief description each ball LynxEM+. Signal names with preceding active "LOW" signals, whereas signal names without preceding active "HIGH" signals. Also, following abbreviations used Type. Table outlines numerical SM712 pins.
INPUT SIGNAL Output Signal Input Output Signal
Note: Outputs signals tri-stated. Internal pull-up 100K resistor, with exception CPUCLK, which 200K resistor. Internal pull-down 100K resistor.
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook
Table Description
Signal Name
Host Interface [31:0] multiplexed Address Data Bus. transaction consists address cycle followed more data cycles. Command Byte Enables. These signals carry command during address cycle byte enable during data cycles. Parity. LynxEM+ asserts this signal verify even parity across [31:0] C/~BE [3:0]. Cycle Frame. LynxEM+ asserts this signal indicate beginning duration transaction. deasserted during final data cycle transaction. Target Ready. data cycle completed when both ~IRDY ~TRDY asserted same cycle. Initiator Ready. data cycle completed when both ~IRDY ~TRDY asserted same cycle. Stop. LynxEM+ asserts this signal indicate that current target requesting master stop current transaction. Device Select. LynxEM+ asserts this signal when decodes addresses target current transaction. Select. This input used during configuration read/write cycles. System Clock, MHz. System Reset. LynxEM+ asserts this signal force registers state machines initial default values Request (bus master mode) Grant (bus master mode) Interrupt
Type
Pull-up/ Pull-Down
(mA)
Max. Load (pF)
Description
[3:0] ~FRAME
~TRDY ~IRDY ~STOP
~DEVSEL
IDSEL ~RST ~REQ ~GNT ~INTA
Power Down Interface ~PDOWN ~CLKRUN/ ACTIVITY pull-up pull-up Power down mode enable ~CLKRUN LynxEM+ Memory activity detection depending SCR18 select ~CLKRUN select ACTIVITY
Clock Interface REFCLK CKIN MCKIN/ LVDSCLK pull-up pull-up pull-up refresh clock source power down PALCLK PALTV 14.318 clock (~EXCKEN Video Clock (~EXCKEN Memory Clock (~EXCKEN LVDSCLK (~ESCKEN LVDSCLK free running clock which used drive LVDS transmitter DSTN panels. External Clock Enable. Select external VCLK form CKIN MCLK from MCKIN.
~EXCKEN
pull-up
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Pull-up/ Pull-Down (mA) Max. Load (pF) Description
Signal Name
Type
External Display Memory Interface [9:0] [63:0] ~RAS ~CAS ~CS0 ~DQM [7:0] pull-up pull-up pull-up pull-up pull-up pull-up External Memory Address Bus. video memory column addresses multiplexed these lines. External Memory Data External Memory Write Strobe External Memory SDRAM Address Select External SGRAM Column Address Select External SGRAM Chip Select select within memory, select within memory External SGRAM mask [7:0]. [7:0] byte specific. DQM0 masks [7:0], DQM1 masks DQM7 masks [63:58]. External SGRAM Block write External SGRAM Bank Select. SDRAM dual internal banks. Bank address defines which bank current command being applied. External SGRAM clock. SDCK driven memory clock. SDRAM input signals sampled positive edge SDCK. External SGRAM clock enable. SDCKEN activates (HIGH) deactivates (LOW) SDCLK signal. Deactivating SDCK provides POWER-DOWN SELF-REFRESH mode. Enable
pull-up
SDCK
pull-up
SDCKEN
pull-up
~ROMEN
pull-up
Flat Panel Interface FDATA [23:0] pull-down Flat Panel Data Note: SM712, upper bits [25:24] multiplexed with port, upper bits [23:11] dedicated flat panel data DSTN LCD: Line Pulse LCD: Horizontal Sync DSTN LCD: Frame Pulse LCD: vertical sync M-signal Display Enable. This signal used indicate active horizontal display time. FPR3E used select M-signal Display Enable Flat Panel Shift Clock. This pixel clock Flat Panel Data. Flat Panel Enable. This signal needs become active after panel voltages, clocks, data supplied. This signal also needs become inactive before panel voltages control signals removed. FPEN part VESA FPDI-1B specification. Flat Panel Enable. This signal used control logic power. Flat Panel Voltage Bias Enable. This signal used control Bias power.
LP/FHSYNC FP/FVSYNC
pull-down pull-down pull-down
FPSCLK FPEN
pull-down pull-down
FPVDDEN VBIASEN
pull-down pull-down
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Pull-up/ Pull-Down (mA) Max. Load (pF) Description
Signal Name
Interface GREEN BLUE IREF CRTVSYNCC CRTHSYNC/ CSYNC
Type
pull-up pull-up
Analog Current Output Analog Green Current Output Analog Blue Current Output Current Reference Input Vertical Sync Horizontal Sync Composite Sync depending CCR65 Horizontal Sync Composite Sync
Video Port Interface [15:0] PCLK VREF HREF BLANK/ TVCLK pull-up pull-up pull-up pull-up input/ digital output Pixel Clock VSYNC input from Card video decoder HSYNC input from Card video decoder Blank output TVCLK output depending CCR69 BLANK output TVCLK output TVCLK output used drive external NTSC/PAL encoder. select NTSC please refer CCR65 register
General Purpose Registers USR3 pull-up General Purpose register. recommended USR3 control On/Off. display display General Purpose register. recommended USR2 select NTSC/PAL settings. PALTVCLK NTSCTVCLK REFCLK General Purpose register. USR1/ DDC2/ Data. used select different test modes. General Purpose register. USR0/ DDC2/ Clock. used select different test modes.
USR2
pull-up
USR1 USR0 Test Mode Pins TEST [1:0]
pull-up pull-up
pull-down
Test mode selects
GROUND Pins HVDD MVDD FPVDD VPVDD CVDD AVDD Host Interface Ring, 3.3V Display Memory Interface Ring, 3.3V Flat Panel Interface Ring, 3.3V VPort Interface Ring 3.3V Clock (PLL) Analog Power, 3.3V Analog Power, 3.3V
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Pull-up/ Pull-Down (mA) Max. Load (pF) Description
Filtered Palette Power, 3.3V Analog Ground Analog Ground Analog Ground Filtered Palette Ground Digital 3.3V Core Power Supply Digital 3.3V Internal Memory Power Supply Digital Ground
Signal Name
RVDD CVSS AVSS1 AVSS2 RVSS
Type
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook
MD12
MD31
MD17
MD28
MD20
MD25
MD22
AD12
AD14
~FRAME
~BE2
MD11
~DQM3
MD30
MD18
MD27
MD21
MD24
~BE0
AD10
AD13
~BE1
~TRDY
~STOP
AD16
MD15
MD13
MD10
~DQM2
MD16
MD29
MD19
MD26
MD23
AD11
AD15
~DEVSEL
~IRDY
AD17
AD18
~CS0
~DQM1
MD14
MVDD
MVDD
HVDD
HVDD
HVDD
AD19
AD20
AD21
~DQM0
AD22
AD23
IDSEL
~CAS
~RAS
MVDD
SM712 VIEW
HVDD
~BE3
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
SDCKEN
SDCK
HVDD
~REQ
~GNT
~ROMEN
~RST
~INTA
REFCLK
MD55
MD56
MD54
VSSA
MCKIN
~PDOWN
~CLKRUN
~EXCKEN
MD57
MD53
MD58
PALCLK
VREF
HREF
BLANK
MD52
MD59
MD51
PCLK
MD60
MD50
MD61
MVDD
MD49
MD62
MD48
~DQM7
VPVDD
MD63
~DQM6
MD39
MD40
MD38
MD41
MD43
MVDD
FDA22
FPVDD
FPVDD
FPVDDEN
CVSS
AVSS1
USR0
TEST1
MD37
MD42
MD34
MD33
~DQM5
FPSCLK
FDA23
FDA19
FDA16
FDA13
FDA8
FDA5
FDA2
VBIASEN
CVDD
RVSS
BLUE
USR1
TEST0
MD36
MD46
MD45
MD47
FDA21
FDA18
FDA15
FDA12
FDA9
FDA6
FDA3
FDA0
CRTH SYNC
RVDD
IREF
USR2
MD35
MD44
MD32
~DQM4
FPEN
FDA20
FDA17
FDA14
FDA11
FDA10
FDA7
FDA4
FDA1
CRTV SYNC
CKIN
AVDD
GREEN
AVSS2
USR3
Figure SM712 Diagram Package
Connected compatible with SM810.
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook
Table SM712 Diagram Package
SM712 Name
MD12 MD31 MD17 MD28 MD20 MD25 MD22 AD12 AD14 ~FRAME C/~BE2 MD11 ~DQM3 MD30 MD18 MD27 MD21 MD24 C/~BE0 AD10 AD13 C/~BE1 ~TDRY ~STOP AD16 MD15
{Function1}
{ROM} ROMD4 ROMD5 ROMD7
{Function2}
{Function3}
{Function4}
MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD
ROMD2 ROMD0
MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD MVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD MVDD
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook {Function1}
ROMD1
SM712 Name
MD13 MD10 ~DQM2 MD16 MD29 MD19 MD26 MD23 AD11 AD15 ~DEVSEL ~IDRY AD17 AD18 ~DQM1 MD14 MVDD MVDD HVDD HVDD HVDD AD19 AD20 AD21 ~DQM0
{Function2}
{Function3}
{Function4}
MVDD MVDD MVDD
ROMD6
MVDD MVDD MVDD MVDD MVDD MVDD MVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD MVDD MVDD MVDD
HVDD
HVDD HVDD HVDD MVDD MVDD MVDD
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook {Function1} {Function2} {Function3} {Function4}
SM712 Name
AD22 AD23 IDSEL ~CAS ~RAS MVDD HVDD C/~BE3 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 SDCKEN SDCK HVDD ~REQ ~GNT ~ROMEN
HVDD HVDD HVDD MVDD MVDD MVDD
HVDD HVDD HVDD MVDD MVDD MVDD
HVDD HVDD HVDD MVDD MVDD MVDD MVDD HVDD HVDD HVDD MVDD MVDD MVDD MVDD HVDD HVDD HVDD MVDD MVDD
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook {Function1} {Function2} {Function3} {Function4}
HVDD HVDD MVDD MVDD MVDD MCKIN LVDSCK HVDD HVDD HVDD HVDD MVDD MVDD MVDD
SM712 Name
~RST ~INTA REFCLK MD55 MD56 MD54 MCKIN/LVDSCK ~PDOWN ~CLKRUN ACTIVITY ~EXCKEN MD57 MD53 MD58
VREF HREF BLANK/TVCLK MD52 MD59 MD51 PCLK MD60 MD50 MD61 MVDD MD49 MD62 MD48 PCLK {TFT 18x2} HREF {External encoder} TVCLK
{TESTMODE1} TD19 TD18 TD17
OUT} BLANK VPVDD VPVDD VPVDD MVDD MVDD MVDD
TD16
PCLK
VPVDD VPVDD VPVDD VPVDD MVDD MVDD MVDD
VPVDD VPVDD VPVDD MVDD MVDD MVDD
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook {Function1} {Function2} {Function3} {Function4}
MVDD {ROM} ROMA7 {ROM} ROMA8 ROMA6 ROMA9 ROMA11 {DSTN} UD10 FPVDD TD12 TD10 VPVDD VPVDD VPVDD MVDD MVDD MVDD MVDD VPVDD VPVDD VPVDD MVDD MVDD MVDD
SM712 Name
~DQM7 VPVDD MD63 ~DQM6 MD39 MD40 MD38 MD41 MD43 MVDD FDATA22 FPVDD FPVDD FPVDDEN CVSS AVSS1 USR0/SCL TEST1 MD37 MD42 MD34 MD33 ~DQM5 FPSCLK FDATA23
{I2C/DDC} (Prim) {ROM} ROMA5 ROMA10 ROMA2 ROMA1 {DSTN} UD11
{USR CFG} USR0 TEST1 {TFT18x2} TD13 TD11 VPVDD VPVDD VPVDD VPVDD MVDD MVDD MVDD MVDD MVDD FPVDD FPVDD
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook {Function1}
SM712 Name
FDATA19 FDATA16 FDATA13 FDATA8 FDATA5 FDATA2 VBIASEN CVDD RVSS BLUE USR1/SDA TEST0 MD36 MD46 MD45 MD47 FHSYNC FDATA21 FDATA18 FDATA15 FDATA12 FDATA9 FDATA6 FDATA3 FDATA0
{Function2}
{Function3}
{Function4}
FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD
{I2C/DDC} (Prim) {ROM} ROMA4 ROMA14 ROMA13 ROMA15 {DSTN} M/DE
{USR CFG} USR1 TEST0 TD14 VPVDD VPVDD VPVDD MVDD MVDD MVDD MVDD FHSYNC {External encoder} FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD
CSYNC RVDD IREF USR2 MD35 MD44 {I2C/DDC} {ROM} ROMA3 ROMA12 MVDD MVDD {USR CFG} USR2/NTSCPAL VPVDD TD15 VPVDD CSYNC VPVDD
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook {Function1}
ROMA0 {DSTN} FPEN LD11 LD10 {TFT 18x2} {TFT} FVSYNC FPEN
SM712 Name
MD32 ~DQM4 FVSYNC FPEN FDATD20 FDATA17 FDATA14 FDATA11 FDATA10 FDATA7 FDATA4 FDATA1 CRTVSYNC CKIN AVDD GREEN AVSS2 USR3
{Function2}
{Function3}
{Function4}
MVDD MVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD FPVDD
{I2C/DDC2}
{USR CFG} USR3/ TVONOFF VPVDD
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook
LynxEM+ NAND Tree Scan Testing
LynxEM+ NAND Tree scan test circuit designed verifying device being properly soldered board. detects opened/shorted traces signal with simple test pattern which, this particular case, only ~200 vectors length. NAND Tree scan test circuit uses Combinational logic; therefore, clock pulses required during testing.
General Information
LynxEM+ NAND Tree scan test circuit long chain 2-input NAND gates. first NAND chain input (signal "MCKIN"), last chain output (signal "BLANK"). order setup LynxEM+ NAND Tree scan testing, program USR[3:0] pins 0011h Test[1:0] pins 10h. VDD's, VSS's, Analog pins RED, GREEN, BLUE, IREF, Control pins USR[3:0], Test[1:0] included scan chain.
NAND Tree Pad_output Nandtree_en pad_input pad_input pad_input pad_input
Figure NAND Tree Connection
Table NAND Tree Scan Test Order
Nand Tree Scan Order
Name
MCKIN ~PDOWN ACTIVITY EXCKEN REFCLK ~INTA ~RST ~GNT ~REQ AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24
In/Out
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Name
~CBE3 IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 CBE2 ~FRAME ~IRDY ~TRDY ~DEVSEL ~STOP ~CBE1 AD15 AD14 AD13 AD12 AD11 AD10 ~CBE0 MD23 MD24 MD22 MD25 MD21 MD26
Nand Tree Scan Order
In/Out
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Name
MD20 MD27 MD19 MD28 MD18 MD29 MD17 MD30 MD16 MD31 DQM3 DQM2 MD10 MD11 MD12 MD13 MD14 MD15 DQM1 DQM0 ~RAS ~CAS
Nand Tree Scan Order
In/Out
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Name
SDCK SDCKEN ~ROMEN ~CS0 MD55 MD56 MD54 MD57 MD53 MD58 MD52 MD59 MD51 MD60 MD50 MD61 MD49 MD62 MD48 MD63 DQM7 DQM6 MD39 MD40 MD38 MD41 MD37 MD42 MD36 MD43 MD35 MD44 MD34 MD45 MD33 MD46 MD32
Nand Tree Scan Order
In/Out
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Name
MD47 DQM5 DQM4 FHSYNC FVSYNC FPSCLK FPEN FDATA23 FDATA22 FDATA21 FDATA20 FDATA19 FDATA18 FDATA17 FDATA16 FDATA15 FDATA14 FDATA13 FDATA12 FDATA11 FDATA10 FDATA9 FDATA8 FDATA7 FDATA6 FDATA5 FDATA4 FDATA3 FDATA2 FDATA1 FDATA0 FPVDDEN VBIASEN CRTVSYNC CRTHSYNC
Nand Tree Scan Order
In/Out
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook Name
PCLK VREF HREF BLANK
Nand Tree Scan Order
In/Out
Pins
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Initialization
LynxEM+ generates internal power-on reset during system power-on. After receiving system ~RESET signal, LynxEM+ will release internal power-on reset circuit enter RESET period until host de-asserts ~RESET signal. During RESET period, LynxEM+ resets internal state machines registers power-on default states. During power-on, LynxEM+ configured based configuration lines [22:0]. Table (see this section) provides detailed description each configuration line. (memory data) lines have internal pull-up resistors pads which latched into corresponding register logic rising edge (trailing edge) ~RESET. specific logic during power-on reset, external pull-down resistor must added corresponding line. addition power-on configuration, LynxEM+ performs initialization sequence internal memory. Figure illustrates power-up sequence. SDCKEN signals HIGH, initially tracking VCC. 200ms delay PRECHARGE command banks LOAD MODE REGISTER command AUTO REFRESH cycles
After memory initialization been completed, LynxEM+'s video BIOS ready service system BIOS requests. System BIOS passes pointer LynxEM+ video BIOS start video BIOS initialization sequence.
SDCK
SDCKEN
COMMAND
PRECHARGE
LOAD MODE REGISTER
AUTO REFRESH
AUTO REFRESH
ACTIVE
High-Z
T=200us
BOTH BANKS
CODE
BANK
tMTC
POWER-UP SDCLK stable
PRECHARGE
Program Mode Register
AUTO REFRESH Cycle
AUTO REFRESH Cycle
Figure External SGRAM Power-Up Initialization Sequence
Initialization
Silicon Motion®, Inc.
LynxEM+ DataBook
Figure illustrates LynxEM+ Video BIOS initialization flow. initialization sequence consists following stages: Determine memory size Check display type. (FPR31 [2:0]) only, only, etc. Program appropriate timing registers based display type mode display characters display users read Pass pointer back system BIOS
Start
Turn display 3C5.1=20h
Unlock extended 3C3=40h
CFG_Flag Over-write lines
Panel Write MD[19:16] based Panel
Read settings
Determine memory size
Determine panel size type
initialize panel (load FPR30,32,34-57)
Load table (set MCLK, scratch-bits, etc.)
Initialize
Initialize BIOS data area
mode
Turn display setting FPR31
Display banner
Done
Figure LynxEM+ BIOS Initialization Flowchart
Initialization
Silicon Motion®, Inc.
LynxEM+ DataBook
LynxEM+ Power-On Configurations
(memory data) lines have internal pull-up resistors pads. external pull-down resistor (recommended value ohm) external pull-down resistor
Table Power-On Configurations
Signal Name
[23]
Read/Write
Register Bits
CPR00 [25]
Address
LynxEM+ Description
External memory access only Allows both internal external memory access (default) BIOS size default EBROM Generate EBROM EBROM (default) Expansion Expansion Expansion (default)
[22] [21]
CONFIG ONLY CONFIG ONLY CONFIG ONLY GPR70 [3:0] FPR30 3C5h.70 3C5h.30
[20]
[19:16] MD15
User configuration Bits DSTN Interface Type 16-bit interface 24-bit interface Color Interface Type 9-bit, 3-bit 12-bit, 4-bit 18-bit, 6-bit 24-bit, 8-bit 24-bit, (12+12-bit, pixels/clock) Analog analog interface 36-bit, (18+18-bit, pixels/clock) Display Size 1024 FPCLK Select Normal Inverted Color Type color color Internal Logic Internal logic will running 1/2X MCLK Internal logic will running MCLK Enable Memory Data Enable 32-bit memory data Enable 64-bit memory data External SGRAM Memory Column Address Select 8-bit column address 9-bit column address 10-bit column address Memory Pre-charge Timing Select Reserved
[14:12]
FPR30 [6:4]
3C5h.30
[11:10]
FPR30 [3:2]
3C5h.30
FPR30
3C5h.30
FPR30
3C5h.30
MCR62
3C5h.62
MCR62
3C5h.62
[5:4]
MCR62 [5:4]
3C5h.62
Initialization
Silicon Motion®, Inc.
LynxEM+ DataBook Register Bits
MCR62
Signal Name
Read/Write
Address
3C5h.62
LynxEM+ Description
External Memory Enable Enable external 32-bit memory Disable external 32-bit memory External SGRAM Memory Active-to-Precharge Delay Select MCLK MCLK External SGRAM Memory Refresh Command Delay MCLK MCLK
MCR62
3C5h.62
MCR62
3C5h.62
Initialization
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Interface
LynxEM+ provides glue-less interface system bus, Host Interface Unit supports both slave master mode. maximize performance, Host Interface unit also supports burst write burst read with Read Look Ahead. LynxEM+ fully compliant with Verison 2.1, does have tolerant cell. LynxEM+ with then will need external glue-logic. LynxEM+'s Host Interface Unit manages data transfer between external internal Host Interface (HIF) bus. functional blocks, with exception Drawing Engine, tied through proprietary protocol. Separate decode logic dedicated FIFO used Drawing Engine. addition Configuration Space Registers, Host Interface Unit contains Power Down Control Registers (PDR20-PDR23) System Control Registers (SCR10-SCR1A). These Registers accessed even while internal PLLs turned off.
Configuration Registers
configuration registers designated CSR00 CSR3D. brief description elements register follows: Vendor register (CSR00) hardwired 126Fh identify Silicon Motion, Inc. chip vendor. Device register (CSR02) hardwired 0810h identify LynxEM+ device. ~DEVSEL timing Status register (CSR06) hardwired 01b, which indicates medium speed ~DEVSEL. Class Code register (CSR08) hardwired 030000h specify LynxEM+ compatible device. [7:0] used identify revision LynxEM+. Memory Base Address register (CSR10) specifies configuration space address relocation. After poweron, register defaults 00h, which indicates base register located anywhere 32-bit address space that base register located memory space. Subsystem Vendor Subsystem (addressable CSR2C CSR2E respectively) 32-bit read only registers. These registers used differentiate between multiple graphics adapters within same system.
Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Display Memory Interface
Memory Configuration
LynxEM+ supports Mbytes memory. There three memory configurations: Mbytes internal memory only Mbytes internal memory (there option external memory with this configuration)
internal memory Mbytes 512Kx32 SGRAM. LynxEM+ single cycle interface clocked MHz, which provides over MB/s. LynxEM4+ single cycle interface clocked MHz, which provides over MB/s. LynxEM+ supports total Mbytes external memory composed 256Kx32 SGRAM. Page Break Look Ahead standard architectures, memory controller will break cycle when agent changes. LynxEM+ allow Wait Cycle" during agent changes preceding current agents same page. Both internal memory external memory support this capability.
Memory Timing Control
Memory timing control configurable MD[7:0] during power-on reset. Table Initialization section complete description these memory configuration bits.
Note: lines have internal pull-up resistors pads. default configuration therefore logical during power-on reset. line external pull-down resistor needs added. After power-on initialization, software used overwrite initial setting writing MCR62 bits correspond MD[7:0].
Display Memory Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Video Processor
LynxEM+'s Video Processor manages video data streams, well graphics data streams non-VGA modes. Video Processor process independent video data streams. video windows (primary secondary) displayed screen location with size, overlaid with graphics data. Within Video Processor, Graphics Source Control block, Video Window Control block, Video Window Control block, Pop-up Icon Control block have independent Starting Address Offset Address registers. This means that each control block fetch data from display memory location. Video Window source control block supports double-buffered video capture. Internal logic automatically detects control/status bits capture buffers fetches captured video data from buffer which used. Video Processor supports flicker reduction direct color modes (64K colors colors), well index color modes (256 colors colors). special data path designed feed outputs color palette back Flicker Reduction block. Overscan Underscan Control block used convert lines into visible lines NTSC display. same function also used display. When display enabled, Shadow registers need locked mode PAL).
From Core Pop-Up Icon Control Overscan Underscan Control
Flicker Reduction
Multimedia RAMDAC Block
Graphics Source Control
Display Memory
Video Window Source Control
Color Horizontal Color Interpolation Scaling Vertical Color Interpolation Scaling
Video Window Source Control
Display Control
Figure Video Processor Block Diagram
Video Processor
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Drawing Engine
LynxEM+'s Drawing Engine designed accelerate Microsoft's DirectDraw applications. engine contains 3operand with raster operations, source destination FIFOs, well host data FIFO. drawing engine pipeline allows single cycle operations runs memory clock speed. LynxEM+'s Drawing Engine includes several functions achieve high performance. device supports color expansion with packed mono font, color pattern fill, host BLT, stretch BLT, short stroke, line draw, others. Dedicated pathways designed transfer data between host interface (HIF) Drawing Engine, memory interface (MIF) Drawing Engine. addition, drawing engine supports rotation BIBLT block size, automatic self activate rotation BLIT. This feature allows conversion between landscape portrait display without need special software drivers. LynxEM+ also supports fast BLT, source clear during BLT, transparent BLT, programmable blter stride, page flip, current scan line refresh. LynxEM+'s Drawing Engine also used master captured data hard disk drive system memory during video capture. accomplish this, video capture driver turns Drawing Engine Capture Enable (DPR0E bit4), selects HOST Read command function (DPR0E [3:0]), enables master mode (SCR17 Video Capture Unit loads incoming video stream into Capture Buffer depending which idle (VPR3C indicates idle status). Drawing Engine resets Capture Buffer Capture Buffer control/Status (VPR3C after transfer completed.
Drawing Engine
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Zoom Video Port Video Capture Unit
Zoom Video Port
LynxEM+'s Zoom Video Port Port) designed interface with video solutions implemented PCMCIA CardBus) cards: examples NTSC/PAL decoders, MPEG-2 decoders, JPEG Codecs. Port also directly interface with NTSC/PAL decoder, such Phillips 7111 BT819. Figure illustrates example Phillips video encoder interface Port. Incoming video data from Port interface format. data interlaced noninterlaced. Port configured output video capture function disabled. 18-bit graphics video data format sent when Port configured output mode. Port also configured test port. signals from each logic blocks within LynxEM+ brought internal test Bus) connected Port. System designers silicon validation engineers access these signals setting TEST0, TEST1, USR0, USR1, USR2 pins. This approach bring total internal signals primary pins. test port capability used enhance fault coverage, well reduce silicon validation debugging time. Table lists signal definitions following Port interface configurations: input mode, input mode, graphics/video (output mode).
Philips SAA7110/ SAA7111
[7:0]
LynxEM+
[7:0] UV[7:0] HREF VREF PCLK
Video NTSC/PAL Signal
UV[7:0] HREF
Figure Video Encoder Interface Video Port
Zoom Video Port Video Capture Unit
Silicon Motion®, Inc.
LynxEM+ DataBook
Table LynxEM+ Video Port Interface Configurations
Video Port Interface
VREF HREF BLANK PCLK
Port (Input mode)
HREF (note1) PCLK
NTSC/PAL Decoder (Input mode)
HREF (note1) PCLK
Graphics/Video (Output mode)
BLANK PCLK
Note BLANK used TVCLK output, which independent port. Video Capture Unit Video Capture Unit captures incoming video data from Port then stores data into frame buffer. Video Capture Unit support several features maintain display quality, balance capture rate: 2-tap, 3-tap, 4-tap horizontal filtering reduction horizontal vertical frame size 4:2:2, 4:2:2 with byte swap, 5:5:5, 5:6:5 Multiple frame skipping methods Interlaced data non-interlaced data capture Single buffer double buffer capture Cropping
LynxEM+ uses Video Processor block display captured data LCD, display. captured data displayed through Video Window Video Window stretching, color interpolation, YUV-to-RGB conversion, color functions performed Video Processor. LynxEM+'s Video Processor simultaneously process captured video data perform CD-ROM playback independent video windows. LynxEM+ also supports real-time video capture hard drive system memory through master mode slave mode. master mode, LynxEM+ uses Drawing Engine's Host Host functions maximize performance.
Zoom Video Port Video Capture Unit
Silicon Motion®, Inc. Functional Description
LynxEM+ DataBook
LynxEM+'s Video Capture Unit supports Video Port Extension (VPE) specification video stream processing. This capture unit includes CLIP block, FILTER block, SHRINK block, FIFO control block. Figure Figure illustrate LynxEM+ Video Capture Block Diagram Data Flow. CLIP functional block used select desired rectangles from video stream captured. VPR40 register (Video Source Clipping Control) used define upper left corner rectangle from video source. VPR44 register (Video Source Capture Size Control) used define height width rectangle from video source.
Video Stream from Port Display Memory CLIP Screen Graphics
FILTER Drawing Engine Interface Block
SHRINK
Capture Buffer
VPR1C
Video Window
VPR48 FIFO
Capture Buffer
VPR30
Video Window
VPR4C
Figure Video Capture Block Diagram
FILTER functional block controls horizontal filtering logic. VPR3C (Capture Port Control) used select tap, tap, filtering. SHRINK functional block used only reduce storage area both display memory hard drive, also increase performance video capture video playback. VPR3C used enable vertical reduction, used enable horizontal reduction. With filter shrink functions, LynxEM+ able achieve high video capture performance maintain optimal video playback quality. VPR3C select different frame skipping options event capture rate less than incoming video stream. CPR00 used support interlaced capture double buffer capture. CPR00 used control/status bits Buffer Buffer captured data displayed either Video Window Video Window video capture driver needs program VPR1C VPR30), Video Window Source Start Address, with same address value from Capture Port Buffer Start Address register. VPR00 (Miscellaneous Graphics Video Control) used automatically display capture data Video Window without programming VPR1C register. This feature independent single buffer double buffer mode. double buffer mode Video Window will display buffer which currently used capture data. This feature allows user capture interlaced data together with programming VPR24 [23:16] VPR24 [31:24] will display implementations Video Window
Zoom Video Port Video Capture Unit
Silicon Motion®, Inc.
LynxEM+ DataBook
From
ideo
lier
CPR04 [25:16] CPR08 [10:0]
CPR04 [9:0]
cropping
CPR08 [26:16]
filtering scaling
capture data
capture buffer
Figure Video Capture Data Flow
Theory Operation Initialization Enable Video Capture (CPR00 Preset Buffer Buffer Status/Control bits (CPR00 [2:1] 11b) Enable Drawing Engine (DPR0E Select Host Read Command function (DPR0E [3:0] =9h) Enable master mode (SCR17 Select Field Detection, VREF/HREF polarity, Vertical/Horizontal Reduction, Horizontal Filtering, Video Capture Input Data Format, Frame Skip, Interlaced/non-interlaced other miscellaneous settings (CPR00, Capture Port Control Register)
Zoom Video Port Video Capture Unit
Silicon Motion®, Inc.
LynxEM+ DataBook
Table Setting Summary Video Capture
Continuous Capture Conditional Capture Single Buffer Double Buffer Non-interlaced Mode Interlaced Mode
Buffer Status/Control (CPR00 Buffer Status/Control (CPR00
CPR00bit CPR00 CPR00 CPR00 CPR00 CPR00
Video Capture Unit supports following types capture modes: Single Buffer Mode with Continuous Capture Single Buffer Mode with Conditional Capture Double Buffer Mode with Continuous Capture Double Buffer Mode with Conditional Capture Interlace Non-Interlaced Mode
Summary each video capture modes follows: Single Buffer Mode with Continuous Capture Video Capture Unit (VCU)
Continuously capture incoming video data capture buffer Independent bits
Drawing Engine (DE) recommended Drawing Engine transfer captured data from display memory hard drive system memory this mode. This mode used view captured data only.
Video Processor (VP)
VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window
Single Buffer Mode with Conditional Capture Video Capture Unit (VCU) Drawing Engine (DE) Test will activate transfer captured data from capture buffer hard drive system memory will after completes frame step Video Processor (VP) VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window
monitors start capture will reset after completes frame step
Zoom Video Port Video Capture Unit
Silicon Motion®, Inc. Double Buffer Mode with Continuous Capture Video Capture Unit (VCU) Continuously capture incoming video data into capture buffer buffer Automatically switch from buffer other when completes frame Independent bits Drawing Engine (DE) recommended transfer captured data from display memory hard drive system memory this mode. This mode used view captured data only.
LynxEM+ DataBook
Video Processor (VP) VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window capture buffer used VCU, Video Window will display captured data from capture buffer
Double Buffer Mode with Conditional Capture Video Capture Unit (VCU) Drawing Engine (DE) monitors B2S) will activate transfer captured data from capture buffer 1(or buffer hard drive system memory will B2S) after completes frame will continuously transfer Data from capture buffer step both bits Video Processor (VP) VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window capture buffer used VCU, Video Window will display captured data from capture buffer
monitors bits B2S) start video capture store into capture buffer buffer will reset B2S) after completes frame will continue video capture step both bits
Interlaced Capture
CPR00 bits used select interlaced capture mode. most video capture applications, interlaced video stream will treated non-interlaced video stream dropping even frames (CPR00[13:11] 010b), dropping frames (CPR00[13:11] 011). This approach will reduce artifacts when playing back captured data. However, some video capture applications, de-interlacing needed handle incoming interlaced video stream. de-interlacing case, CPR00 needs enable interlaced capture incoming interlaced video stream. double buffer mode (CPR00 needs turned same time. Capture Buffer Capture Buffer combined together single buffer with line offset. Figure illustrates capture buffer structure. video capture driver will preset bits initialize buffer status/control bits. Video Capture Unit will start video capture After fills capture buffer both bits VCU. video capture driver will activate Drawing Engine transfer captured data capture buffer system memory hard drive when both "0". After completion transfer, Drawing Engine will both "1". Video Capture Unit then continues video capture repeats same protocol. During video playback, captured data displayed either Video Window Video Window recommended display both even frame frame video playback. video captured driver program Video Window Source Start Address Register Video Window Source Width Offset Register such that frame even frame) captured data will dropped during video playback. scaling, color interpolation, YUV-to-RGB conversion functions also enabled same time.
Zoom Video Port Video Capture Unit
Silicon Motion®, Inc.
LynxEM+ DataBook
Even Field From Video Capture Unit Drawing Engine Video Processor
Field
Even Field
Capture Buffer
Capture Buffer
Even Field
Field
Even Field
Figure Capture Buffer Structure Interlaced Mode
Zoom Video Port Video Capture Unit
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Flat Panel Interface
LynxEM+ supports both color dual scan (passive) color (active) panel interface notebook computers. also support color panel with analog interface. color panel, LynxEM+ support single pixel clock 9-bit, 12-bit, 18-bit, 24-bit, double-pixel clock 24-bit, 36-bit interfaces 1024x768 resolution. Table lists complete LynxEM+ panel interface pins both color DSTN LCD. Figure shows singlepixel clock interface, Figure shows double-pixel clock interface, Figure shows 16-bit DSTN interface, Figure shows 24-bit DSTN interface.
Reduction Circuit
LynxEM+ provides reduction circuit flat panel interface. circuit controlled Control Register (Address: 3C5h Index: 58h). reduction control enabled setting logical When circuit turned flat panel interface signals driven independent groups (e.g. 24-bit interface, groups signals each) which delayed small time delta relative another. This approach eliminates noise peaks which occur when significant numbers flat panel interface signals transition same time. spectrum therefore flattened reduced.
LynxEM+ Flat Panel Enhancements
LynxEM+ integrates various flat panel enhancement features such screen auto-centering, screen expansion (including interpolated screen expansion), Virtual Refresh, special dithering engines DSTN flat panels.
LynxEM+ Graphics/Text Expansion Information
Introduction LynxEM+ provides full expansion capability text graphics modes. Text well graphics expansion supported resolution. Expansion supported DSTN panels. detailed description expansion algorithms these devices follows: Horizontal Expansion Text Graphics Horizontal expansion handled pixel pieces whether mode text graphics. There expansion mechanisms: 10-dot expansion 12-dot expansion. 10-dot expansion used expand pixels, 12-dot used expand pixels panel sizes. 10-dot expansion, every pixel duplicated. example, mode3h (80x25 text) mode 12h(640x480 graphics), where pixel pixel p0p1p2p3p3p4p5p6p7p7 pixel (p3) duplicated, well pixel (p7). pattern repeats each pixel piece. 12-dot expansion, every other pixel, beginning with duplicated. example, mode mode p0p1p1p2p3p3p4p5p5p6p7p7. Again, pattern repeats each pixel piece.
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
far, examples assume 8x16 font size. There also 9x16 font size consider this case actual font still 8x16, additional either background color repeat pixel inserted). 9x16 case, pixel duplicated just like 8x16 case. Pixel handled somewhat differently depending whether character text character graphics character text character case, second value becomes background color. graphics case, repeated. Vertical Expansion Text Graphics Vertical expansion text graphics uses Dynamic Duplication Algorithm (DDA) method achieve expansion. same basic methodology used independent resolution. First, initial constant value (for LynxEM+ this 10-bit value) loaded into Vertical Screen Expansion Constant Registers. This value used part logical algorithm determine which lines display duplicate. Figure diagram algorithm.
ADDER
NewSum [10:0]
[10:0]
Figure Expansion Algorithm
each line display, following equation calculated illustrated algorithm: NewSum [10:0] Sum[10:0] [10:0] NewSum [10:0], given line duplicated. text case, logic algorithm will reset each character block, expansion handled terms character rows (e.g. character rows lines each). graphics case, logic algorithm will reset when bottom display reached. constant calculated following equation:
1024 Expanded Resolution Existing Resolution
example, expand line mode 768, equation would
1024
Lines Lines
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
constant then calculated entered into expansion algorithm. DDA[9:0] Dithering Engine LynxEM+ separate dithering engines color DSTN color LCD. DSTN dithering engine includes different dithering patterns which developed with LCD's response time contrast ratio mind. FPR32 used select gray levels gray levels each Red, Green, Blue color. dithering engine includes different dithering patterns which combine frame rate modulation space dithering algorithm. FPR32 used select 4-gray level dithering, 8-gray level dithering, dithering. Flat Panel Power ON/OFF Sequencing LynxEM+ integrates logic panel power ON/OFF sequencing during power down modes display switching. There ways power ON/OFF flat panel: hardware panel power sequencing software panel power sequencing. Hardware panel power sequencing: Hardware panel power sequencing selected when FPR34 Whenever FPR31 toggles, LynxEM+ automatically controls data, controls, FPEN, FPVDD, VBIASEN pins. FPR33 [3:2] determines time period from FPEN VBIASEN, from VBIASEN controls/data, from controls/data FPVDDEN.
FPR33[3:2] Power Sequencing Time Select vertical frame vertical frames vertical frames vertical frames
Figure shows auto panel power sequencing timing relationship. Figure shows auto panel power sequencing timing relationship. flat panels which have non-standard requirements on/off power sequencing, LynxEM+ supports panel power sequencing through software programming. Below examples software programming panel power sequencing: Software panel power sequencing- FPR34 (software panel power sequencing) Setup shadow registers: SVR40 SVR4B FPR31 (enable display) After vertical frames, PDR22 (turn FPVDDEN) After vertical frames, PDR22 (enable controls data) After vertical frame, PDR22 (turn VBIASEN) After vertical frames, PDR22 (turn FPEN)
Note: backlight control independent power sequencing. VBKLGT turned same time FPEN.
Flat Panel Interface
Silicon Motion®, Inc. Software panel power sequencing OFF: FPR34 (software panel power sequencing) Select FPR33 [3:2] panel power on/off timing: PDR22 (turn FPEN) After vertical frames, PDR22 (turn VBIASEN) After vertical frames, PDR22 (enable controls data) After vertical frames, PDR22 (turn FPVDDEN) FPR31 (disable display)
LynxEM+ DataBook
Table Flat Panel Interface Pins listing color DSTN color LynxEM+ Name
LP/FHSYNC FP/FVSYNC FPSCLK FPEN FDA23 FDA22 FDA21 FDA20 FDA19 FDA18 FDA17 FDA16 FDA15 FDA14 FDA13 FDA12 FDA11 FPEN FPEN UD11 UD10 LD11
Color DSTN 16-bit
Color 9-bit
HSYNC VSYNC ENAB FPEN
24-bit
12-bit
HSYNC VSYNC ENAB FPEN
18-bit
HSYNC VSYNC ENAB FPEN
24-bit
HSYNC VSYNC ENAB FPEN
12-bit
HSYNC VSYNC ENAB FPEN RA01 GB01
18-bit
HSYNC VSYNC ENAB FPEN
Name
FDA10 FDA9 FDA8 FDA7 FDA6 FDA5 FDA4 FDA3 FDA2
16-bit
24-bit
LD10
9-bit
12-bit
18-bit
24-bit
12-bit
18-bit
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook Color DSTN Color
LynxEM+
FDA1 FDA0 FPVDDEN VBIASEN
(FDA35)
(FDA34) (FDA33) (FDA32) (FDA31) (FDA30) (FDA29) (FDA28) (FDA27) (FDA26) (FDA25) (FDA24)
denotes first pixel pixels/clk interface. denotes second pixel pixels/clk interface. LynxEM+ SM712 pinout, upper bits panel data multiplexed with port pins P11-P0.
LynxEM+
FPVDDEN VBIASEN panel power control circuitry
pixel/clock
FPEN FHYSNC FVSYNC FPSCLK FDATA [23:0]
FPEN ENAB HSYNC VSYNC (9,12,18,24)
Figure (Single Pixel/Clock) Interface Diagram
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
LynxEM+
FPVDDEN VBIASEN panel power control circuitry
Panel pixels/clock
FPEN FHYSNC FVSYNC FPSCLK
12/18
FPEN ENAB HSYNC VSYNC (12, (first pixel)
12/18
FDATA
(12, (second pixel)
Figure Panel pixels/clock) Interface Diagram
FPVDDEN VBIASEN
panel power control circuitry
FPEN FPSCLK
FPEN
LynxEM+
FDATA19 FDATA18 FDATA17 FDATA16 FDATA15 FDATA14 FDATA13 FDATA12
16-bit Dual Color
FDATA7 FDATA6 FDATA FDATA4 FDATA3 FDATA2 FDATA1 FDATA0
Figure 16-bit DSTN Interface Configuration
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
FPVDDEN VBIASEN
panel power control circuitry
FPEN FPSCLK FDATA FDATA22 FDATA21 FDATA20 FDATA19 FDATA18 FDATA17 FDATA16 FDATA15 FDATA14 FDATA13 FDATA12 FDATA11 FDATA10 FDATA9 FDATA8 FDATA7 FDATA6 FDATA FDATA4 FDATA3 FDATA2 FDATA1 FDATA0
FPEN UD11 UD10 LD11 LD10
LynxEM+
24-bit Dual Color
Figure 24-bit Dual Color Interface Diagram
FPVDDEN Controls/ Data
VBIASEN FPEN
programmed FPR33 [3:2]
Figure Panel Power Sequencing Timing Diagram
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
FPEN
VBIASEN Controls/ Data FPVDDEN
programmed FPR33 [3:2]
Figure Panel Power Sequencing Timing Diagram
FPR33[3:2]
Power On/Off Sequencing Time Select
vertical frame vertical frames vertical frames vertical frames
LVDS Chipset Interface order address cable issues associated with wide, high speed TTL/CMOS panel interface, designers choose LVDS (Low Voltage Differential Signaling) chipset PanelLink chipset (each chipset type includes transmitter receiver). Examples LVDS chipset include National Semiconductor DS90C383/4 (3.3V, MHz) Texas Instruments' SN75LVDS83/2 (3.3V, MHz); copyists from these vendors pin-compatible. PanelLink chipset available from Silicon Image (SiI100). LynxEM+ supports direct interface transmitter either LVDS PanelLink chipset types. Figure Figure illustrate 24-bit interfaces DSTN LVDS panels. Figure Figure illustrate 24-bit interfaces DSTN PanelLink panels. 36-bit LVDS interface channel LVDS), please refer Figure
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
LynxEM+
LVDS Transmitter SN75LVDS83 DS90C383
LVDS Data Pairs
LVDS Receiver SN75LVDS82 DS90C384
Panel
R[7:0] G[7:0] B[7:0] FHYSNC FVSYNC FPSCK
TxIn TxIn TxIn TxIn TxIn TxIn TxCLKIN
TxOut0+ TxOut1+ TxOut2+ TxOut3+ TxCLKOut
LVDS clock
RxIn0+ RxIn1+ RxIn2+ RxIn3+ RxCLKIn
RxOut RxOut RxOut RxOut RxOut RxOut RxCLKOut
R[7:0] G[7:0] B[7:0] HYSNC VSYNC FPSCK
Figure LVDS Interface with Panel
LynxEM+
LVDS Transmitter
LVDS Data
LVDS Receiver
DSTN Panel
UD[11:0] LD[11:0] FPSCK LVDSCLK
TxIn TxIn TxIn TxIn TxIn TxCLKIN
TxOut0+ TxOut1+ TxOut2+ TxOut3+ TxCLKOut
LVDS clock
RxIn0+ RxIn1+ RxIn2+ RxIn3+ RxCLKIn
RxOut RxOut RxOut RxOut RxOut RxCLKOut open
UD[11:0] LD[11:0]
Figure LVDS Interface with DSTN Panel
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
18-bit interface
FDA16 FDA17 FDA18 FDA19 FDA32 FDA33 FDA8 FDA9 FDA10 FDA11 FDA28 FDA29 FDA0 FDA1 FDA2 FDA3 FDA24 FDA25
18-bit LVDS interface Channel
SM712
FDA20 FDA21 FDA22 FDA23 FDA34 FDA35 FDA12 FDA13 FDA14 FDA15 FDA30 FDA31 FDA4 FDA5 FDA6 FDA7 FDA26 FDA27
18-bit interface LVDS Channel
Figure 36-bit (18x2-bit) Interface Diagram
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
LynxEM+
PanelLink Transmitter SiI100
PanelLink Receiver SiI101
Panel
R[7:0] G[7:0] B[7:0] FHYSNC FVSYNC FPSCK
TxIn TxIn TxIn TxIn TxIn TxIn
TxOut0+ TxOut1+ TxOut2+ clock
RxIn0+ RxIn1+ RxIn2+
RxOut RxOut RxOut RxOut RxOut RxOut
R[7:0] G[7:0] B[7:0] HYSNC VSYNC FPSCK
TxCLKOut TxCLKIN
RxCLKIn RxCLKOut
Figure PanelLink Interface with Panel
LynxEM+
PanelLink Transmitter SiI100
PanelLink Receiver SiI101
Panel
U[11:0] L[11:0] FHYSNC FVSYNC LVDSCLK
TxIn TxIn TxIn TxIn TxIn
TxOut0+ TxOut1+ TxOut2+ clock
RxIn0+ RxIn1+ RxIn2+
RxOut RxOut RxOut RxOut RxOut RxOut
R[7:0] G[7:0] B[7:0] HYSNC VSYNC FPSCK
TxCLKIN TxCLKOut
RxCLKIn RxCLKOut
Figure PanelLink Interface with DSTN Panel
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
Table Table list mapping LVDS transmitter with LynxEM+ LVDS DSTN panels. Table Table list mapping PanelLink transmitter with LynxEM+ PanelLink DSTN panels. Please consult your panel manufacturer verify mapping between LVDS receiver panel. mapping from transmitter side must correspond with mapping from receiver side order ensure that panel will function properly.
Table LVDS Transmitter Mapping Interface
LynxEM+ Name
FPDATA16 FPDATA17 FPDATA18 FPDATA19 FPDATA20 FPDATA21 FPDATA22 FPDATA23 FPDATA8 FPDATA9 FPDATA10 FPDATA11 FPDATA12 FPDATA13 FPDATA14 FPDATA15 FPDATA0 FPDATA1 FPDATA2 FPDATA3 FPDATA4 FPDATA5 FPDATA6 FPDATA7 LP/FHSYNC FP/FVSYNC FPSCLK
interface
FHSYNC FVSYNC FPSCLK
LVDS Transmitter
SN75LVDS83/DS90C383
LVDS Transmitter Name
TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN6 TxIN27 TxIN5 TxIN7 TxIN8 TxIN9 TxIN12 TxIN13 TxIN14 TxIN10 TxIN11 TxIN15 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN16 TxIN17 TxIN24 TxIN25 TxIN26 TxIN23 TxCLKIN
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
Table LVDS Transmitter Mapping DSTN Interface
LynxEM+ Name
FPDATA12 FPDATA13 FPDATA14 FPDATA15 FPDATA16 FPDATA17 FPDATA18 FPDATA19 FPDATA20 FPDATA21 FPDATA22 FPDATA23 FPDATA0 FPDATA1 FPDATA2 FPDATA3 FPDATA4 FPDATA5 FPDATA6 FPDATA7 FPDATA8 FPDATA9 FPDATA10 FPDATA11 LP/FHSYNC FP/FVSYNC FPSCLK LVDSCLK
interface
UD10 UD11 LD10 LD11 FPSCLK LVDSCLK
LVDS Transmitter SN75LVDS83/DS90C383
LVDS Transmitter Name
TxIN13 TxIN14 TxIN10 TxIN11 TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN6 TxIN27 TxIN5 TxIN15 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN16 TxIN17 TxIN7 TxIN8 TxIN9 TxIN12 TxIN24 TxIN25 TxIN26 TxIN23 TxCLKIN
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
Table PanelLink Transmitter Mapping Interface
LynxEM+ Name
FPDATA16 FPDATA17 FPDATA18 FPDATA19 FPDATA20 FPDATA21 FPDATA22 FPDATA23 FPDATA8 FPDATA9 FPDATA10 FPDATA11 FPDATA12 FPDATA13 FPDATA14 FPDATA15 FPDATA0 FPDATA1 FPDATA2 FPDATA3 FPDATA4 FPDATA5 FPDATA6 FPDATA7 LP/FHSYNC FP/FVSYNC FPSCLK
interface
FHSYNC FVSYNC FPSCLK
PanelLink Transmitter
SiI100
PanelLink Transmitter Name HSYNC VSYNC IDCK
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
Table PanelLink Transmitter Mapping DSTN Interface
LynxEM+ Name
FPDATA12 FPDATA13 FPDATA14 FPDATA15 FPDATA16 FPDATA17 FPDATA18 FPDATA19 FPDATA20 FPDATA21 FPDATA22 FPDATA23 FPDATA0 FPDATA1 FPDATA2 FPDATA3 FPDATA4 FPDATA5 FPDATA6 FPDATA7 FPDATA8 FPDATA9 FPDATA10 FPDATA11 LP/FHSYNC FP/FVSYNC LVDSCLK
interface
UD10 UD11 LD10 LD11 LVDSCLK
PanelLink Transmitter SiI100
PanelLink Transmitter Name
HSYNC VSYNC IDCK
Flat Panel Interface
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Miscellaneous Functions
This chapter describes functions LynxEM+ such Video BIOS interface, VESA DPMS, VESA DDC2B.
Video BIOS Interface
Video BIOS contains code chip power-on initialization, graphics mode setup, various read/write routines frame buffer. Video BIOS burned LynxEM+ into separate video BIOS EPROM (this typical case add-in cards) integrated into system BIOS (this typical case motherboard graphics implementation). support separate video BIOS access, BIOS address decode must enabled setting CSR30 (Expansion Enable Base Address Register) implementations where video BIOS integrated into system BIOS ROM, BIOS address decode access must disabled clearing CSR30 Figure shows external video BIOS configuration interface LynxEM+. ~ROMEN (ROM Enable) signal from LynxEM+ connects signals BIOS ROM. Since video BIOS address data shared with video memory data (MD) lines, programmers must ensure that memory inactive when reading from Video BIOS ROM. this case, Video BIOS must read shadowed (typically system memory C0000) immediately after reset. Direct physical access Video BIOS must then disabled prevent interference with ensuing graphics operations.
64Kx8 LynxEM+
[7:0] [47:32] ~ROMEN
BIOS
[7:0] [15:0]
Figure Video BIOS Configuration Interface
Miscellaneous Functions
Silicon Motion®, Inc.
LynxEM+ DataBook
VESA DPMS Interface
LynxEM+ supports VESA Display Power Management Signaling (DPMS) direct programming PDR22 (LCD Panel Control Select Register) bits through implementation chip's power down states. Table shows VESA DPMS states methods entering each DPMS states.
Table DPMS Summary
DPMS State
Standby Suspend
HSYNC State
Pulses pulses Pulses pulses
VSYNC State
Pulses Pulses pulses pulses
State
Active Blank Blank Blank
Direct Programming Method
PDR22 [5:4] PDR22 [5:4] PDR22 [5:4] PDR22 [5:4]
Power Down State Method
Automatic Standby DPMS state when enter Standby mode CCR69[2]=0 selects Suspend DPMS state when Sleep mode CCR69[2]=1 selects DPMS state when Sleep mode
VESA DDC2B Interface LynxEM+ provides dual ports I2C-Bus through [3:0] pins various applications such VESA's DDC2B monitor interface. recommended USR1 USR0 primary port signals Bus. USR3 USR2 reserved secondary port. GPR72 (User Defined Register GPR73 (User Defined Register defined support I2C/DDC2 protocol. LynxEM+, master controller only, designed initiate transfer, generate clock signal, terminate transfer slave component. LynxEM+'s I2C-Bus interface designed interface with NTSC/PAL decoders, Proems, audio decoders, others. Each [3:0] pins internal pull-up resistor. enable data (SDA) clock (SCL) from LynxEM+'s primary port, GPR72 (3C5h index 72h) must "11". drive logic line (USR1) line (USR0), program GPR72 "0". read back from GPR72. Figure shows basic I2C-Bus protocol LynxEM+ master transmitter.
Miscellaneous Functions
Silicon Motion®, Inc.
LynxEM+ DataBook
Yes, Check GPR72 [3:2]
Busy?
Initiate Start
Send 7-bit Slave Address with R/~W
Check GPR72[3]
from slave?
Time Out?
optional
Send Byte Slave Address
Abort Transfer
Check GPR72[3]
from slave?
Time Out?
Send Byte Slave Address
Abort Transfer
Check GPR72[3]
from slave?
Time Out?
Last Byte?
Abort Transfer
Stop Transfer
Figure LynxEM+ Protocol Flow Chart
Miscellaneous Functions
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Clock Synthesizers
LynxEM+ integrates three programmable clock synthesizers memory clock (MCLK), Video Clock (VCLK), Video Clock 2(VCLK2). VCLK1 utilized standard only, only, CRT/LCD display modes which refresh rate both devices same. VCLK2 utilized when Virtual Refresh mode implemented this case, VCLK1 utilized panel timing clock panel display block within LynxEM+. VCLK2 utilized clock interface independently LCD/CRT display modes independently clock various functional blocks within device save power under only display mode. Please Virtual Refresh discussion under Power Management section additional details regarding power saving capabilities under Virtual Refresh architecture. Figure illustrates control logic MCLK, VCLK, VCLK2. figure also shows clock generator module WFIFO (WFIFOCLK), RFIFO (RFIFOCLK), (RAMCLK), Video Capture (VCMCLK), Drawing Engine (DPMCLK), Video Processor (VPCLK). TVCLK used external analog encoder (this clock either derived from 14.318MHz base clock NTSC, from separate 17.734480MHz clock source connected input signal PALCLK PAL).
SLEEP STANDBY CCR68_6 CCR68_7 ~EXCKEN PD20_5 VCLK2 CKIN PLL1 1/16 CKIN PLL3 ~EXCKEN 1/16 MCLK VCLK PD20_4 CCR69_0 CCR69_1 FPR31_7
VRCLK
VCLK
VCLK
VCLK2
WFIFOCLK RFIFOCLK RAMCLK
VCLK2
VCLK MCLK PDR21[5:0] STANDBY
MCKIN PLL2
CLOCK GENERATOR
VCMCLK DPMCLK VPCLK TVCLK
1/16 SLEEP AUTO_OFF
MCLK
Figure Clocks Generator Block Diagram
VCLK programmed using VCLK Numerator Register (VNR), CCR6C, VCLK Denominator (VDR) Post Scalar (PS) register, CCR6D. VCLK frequency based following equation:
Clock Synthesizers
Silicon Motion®, Inc.
LynxEM+ DataBook
VCLK 14.31818
post scalar used support VCLK frequencies which need large number. With enabled, number original number. This helps reduce jitter maintain accuracy. VCLK2 programmed using VCLK2 Numerator Register (VCLK2NR), CCR6E, VCLK Denominator (VCLK2DR) register CCR6F. VCLK2 frequency based following equation:
VCLK2NR VCLK2 14.31818 VCLK2DR
Table Recommended Values Common VCLK Settings
Mode
640x480 720x400 (text) 640x480 800x600 -800x600 1024x768 70Hz 85Hz 56Hz -72Hz 75Hz 28.325 31.500 35.484 14.318 49.517 78.750 97h2
Ref. Rate
60Hz
CCR68
CCR68
CCR68
3C2.3
3C2.2
VCLK (MHZ) 25.180
Notes: numbers hard coded modes. Post scalar enabled.
MCLK programmed using MCLK Numerator Register (MNR), CCR6A, MCLK Denominator Register (MDR), CCR6B. MCLK frequency based following equation:
MCLK 14.31818
Clock Synthesizers
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LynxEM+ DataBook
Chapter Multimedia RAMDAC
LynxEM+ contains multimedia RAMDAC, which supports gamma correction with maximum frequency (3.3V power supply). multimedia RAMDAC includes color palette RAMs (RAM0 display, RAM1 display), Sequencer, Hardware Cursor Registers (foreground background), Hardware Pop-up Icon Registers (foreground background), Data Mixer, Power-On Reset, Bias circuit, Monitor Detect circuit, three 8-bit DACs Anti-flicker logic read/writes also built color palette blocks. Figure shows block diagram LynxEM+ Multimedia RAMDAC. LynxEM+ uses internal band voltage reference circuit supply reference voltage. This circuit automatically compensates temperature power supply variation. external portion circuit consists single RSET resistor used full scale voltage output from DAC. RAMDAC supports types modes, color palette index mode direct color mode. color palette index mode, 8-bit input data given pixel goes color palette block through mask register. direct color mode, gamma correction pixel data will bypass color palette RAM. gamma correction pixel data will through color palette which being used gamma correction look activate gamma correction refer CCR65: Encoder Control Registers.
Backend (RAM1)
LynxEM+ includes separate 18-bit bits each RGB) module backend. allows support color palette index modes display. This module written concurrently with RAM0.
RAM1 P[7:0] ~PDOWN RAMCLK Control Unit Hardware Cursor Popup Icon
Color Palette Gamma Correction Look Table MIXER
Video Select
Band-Gap Voltage Reference
BIAS
Monitor Detect
Figure LynxEM+ RAMDAC Block Diagram
Multimedia RAMDAC
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Signature Analyzer
LynxEM+ includes several built-in test features enhance testability fault coverage. LynxEM+'s signature analyzer designed reduce tester time manufacturing test time. This signature analyzer resides within Video Processor block receives 24-bit data from Multimedia RAMDAC block. used test graphics modes, display modes, motion video with single frame data. also used test data combinations such graphics, video video cursor, pop-up icon same time. primary variables signature analyzer length internal shift registers number feedback terms. LynxEM+ implements CRC-CCITT polynomial (X16 16-bit signature shift register. VPR64 (Signature Analyzer Control Status) register used define control operation LynxEM+'s signature analyzer. used Enable/Stop bit. used Reset/Normal bit. used select 8bit Red, Green, Blue data from 24-bit outputs Multimedia RAMDAC. used read back signature from signature analyzer. turn signature analyzer, both must "11". signature shift register will reset initial value. rising edge vertical sync pulse after VPR64 [3:2]=11, state machine will start collecting signature data. automatically reset same time. rising edge next vertical sync pulse, signature analyzer stops automatically reset "0". test software read back 16-bit signature from [31:16] compare golden signature test patterns. Figure block diagram signature analyzer.
VPR64[1:0]
R[7:0]
From Multimedia RAMDAC
G[7:0] B[7:0]
X16+X12+X5+1
Collector
VPR64[31:16]
VSYNC
State Machine
VPR64[3:2]
VSYNC
VPR64{3:2] Enable Reset Signature Analyzer
VPR64{3:2] Start Signature Analyzer
VPR64{3:2] Stop Signature Analyzer
Figure Signature Analyzer Block Diagram
Signature Analyzer
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Power Management
LynxEM+ designed support ACPI requirements defined Management Interface Specification (PPMI v1.0) Display device Class Power Management Specification v1.0a. LynxEM+ also supports variety adaptive power saving clock management methods while full operational mode. Finally, LynxEM+ supports traditional Standby Suspend mode functionality operating systems such Windows which have ACPI support built into summary these capabilities follows.
ACPI
LynxEM+ supports D0-D3 modes operation software programming Power Management Control/Status Register PMSCR[1:0]. required Management Interface Specification, Configuration Space Status Register (offset 06h) indicate capabilities have been defined LynxEM+. offset 34h, Cap_Ptr register stores offset capabilities (this register hardwired 40h). first byte offset value 01h, which indicates Power Management capability (supports states addition required power states). second byte value indicating additional capability features (Note: LynxEM+ does offer support optional ~PME capabilities defined PPMI v1.0). Please refer Power Management Interface Specification Display Device Class Power Management Reference Specification v1.0a additional details. Display driver support ACPI under Windows future versions Windows will provided Silicon Motion accordance with PC97 PC98 requirements.
Adaptive Power Management
LynxEM+ provides intelligent power saving control during graphics/video operation. methods through which power savings achieved Dynamic control functional blocks, dynamic clock control through Silicon Motion's Virtual Refresh architecture. Dynamic Control Functional Blocks major functional blocks within device laid independently. There signal crossover between blocks. Special clock drivers used control each independent functional blocks. clock drivers turned setting Power-Down Registers (PDR20 PDR22), entering internal auto-standby mode (PDR23 Functional blocks therefore turned on/off dynamically response LynxEM+ being utilized. Since blocks shut down unused functional blocks, this power saving feature transparent user. Below some programming recommendations selected display configurations. These auto power saving features implemented through video BIOS system PMI. addition these display configuration recommendations, drawing engine, Port, video processor turned through video driver control.
Power Management
Silicon Motion®, Inc.
only selected display
LynxEM+ DataBook
Disable frame buffer write operation (PDR21 Disable frame buffer read operation DSTN dithering engine (PDR21
Color only selected display with normal refresh
Disable (PDR21 Disable frame buffer write operation (PDR21 Disable frame buffer read operation DSTN dithering engine (PDR21
Color DSTN only selected display with Virtual Refresh
Disable (PDR21 Enable auto shut-down display memory screen refresh cycle frame buffer write cycle (FPR31 VCLK clock rate (reduce clock rate save power)
only selected display
VCLK clock rate 14.1 interlaced mode (CRT30 Disable frame buffer write operation (PDR21 Disable frame buffer read operation DSTN dithering engine (PDR21
Dynamic Clock Control Virtual Refresh Dynamic clock control made possible through Silicon Motion's Virtual Refresh architecture. Virtual Refresh intelligent architecture dynamic clock control only mode, well independent display refresh control when multiple displays enabled (e.g. CRT/LCD, TV/LCD). Virtual Refresh utilizes independent clocks (VCLK, VRCLK): clock, VRCLK drives panel interface maintains proper screen refresh. second clock, VCLK independent panel scaled according user needs (e.g. scaled down power savings, scaled drive higher refresh rate CRT). Virtual Refresh enabled setting FPR31 "1". When display only display viewed user, power saving achieved three functions: Dynamically slows down video clock (VCLK) 25%~50% original clock rate Auto shut-down display memory screen refresh Auto shut-down write frame buffer
These functions automatically implemented when LynxEM+ detects user performed activity selectable number screen refresh cycles. Since significant percentage logic synchronized with VCLK, average power consumption chip will drop dramatically. screen remains with proper screen refresh, power savings transparent user. Note: When multiple displays used, Virtual Refresh architecture also used simultaneously display CRT/TV with different resolutions, independent refresh rates.
Standard Power Management
Standby Mode LynxEM+ supports Standby Mode ways: internal auto-standby system standby from system PMI. internal auto-standby enabled controlled Activity Detection Register (PDR23). When internal timer matches selected condition (PDR23 [2:0]), LynxEM+ immediately enters standby mode Memory access
Power Management
Silicon Motion®, Inc.
LynxEM+ DataBook
LynxEM+ will cause device exit standby mode, reset internal counter timer. system enable system standby mode pulling LynxEM+'s "~PDOWN" signal low. (Note: select standby mode, PDR20 must before pulling ~PDOWN low) LynxEM+ will exit standby mode when "~PDOWN" goes high. When system standby internal auto-standby ignored. Programming sequences internal auto-standby system standby follow.
Start Internal Auto-standby Mode
PDR23 bit[7:6] PDR20 enter standby mode internal timer count matches setting from PDR23 bit[2:0]
Start System Standby Mode
PDR20 enter standby mode "~PDOWN" input driven
Power Saving Standby Mode standby mode designed provide automatic power saving mechanism portable when graphics display sub-system idle short period time. There need BIOS application software program LynxEM+ registers. power saving control done hardware. Both internal auto-standby system standby have same power saving mechanisms listed below. Both memory clock video clock switch lower frequencies which selected [5:4] PDR20 register LynxEM+ will continuously issue DRAM refresh cycles following functional blocks disabled (PDR21 frame buffer write frame buffer read DSTN dithering engine Color Palette Port Drawing engine Video processor auto-power sequence enabled VESA DPMS standby mode enabled
Sleep Mode Sleep mode maximizes power-saving mode while maintaining display memory register integrity. Sleep mode selected when whole system will idle long period time. selected displays will shutdown. PLLs also shutdown external refresh clock selected (CCR69 memory self-refresh mode selected. panel on/off sequence will done simply programming PDR22 register. programming sequence Sleep Mode follows.
Setting Before Entering Sleep Mode
PDR20 enter sleep mode PDR20 select memory refresh type CCR69 select external internal refresh clock
Power Management
Silicon Motion®, Inc.
Enter Sleep Mode (Suspend)
LynxEM+ DataBook
Power panel display enabled. There ways power panel: hardware software (selected FPR34 software approach, system needs program FPR34 PDR22 [3:0] control FPEN, FPVDD, VBIAS,VBKLGT panel interface pins. hardware approach, needs program FPR34 panel ON/OFF timing select FPR33 [3:2], then LynxEM+ will generate proper panel sequencing. "~PDOWN" input driven low. After ~PDOWN been asserted vertical sync cycles, LynxEM+ will automatically shut-down following blocks: frame buffer write frame buffer read DSTN dithering engine Color Palette Port drawing engine Video processor Memory screen refresh Start power-down memory refresh cycle
Exit Sleep Mode (Resume)
Drive "~PDOWN" input high. (200 after PLLs turned After Power panel either hardware software. software panel sequencing, enable display programming PDR22 register. whole system will back original state. hardware panel sequencing, FPR34
Activity Detection activity detection function used monitor LynxEM+ memory activity. System designer select fixed time period programming PDR23 [2:0]. internal timer will count idle period memory operation. idle period matches selected value, LynxEM+ will generate "Low-High" "High-Low" signal system through ACTIVITY output pin. Memory operation reset ACTIVITY signal internal counter. After receiving ACTIVITY signal from LynxEM+, system power management unit start Standby mode Sleep Mode pulling "~PDOWN" signal low. activity detection function also used enable internal autostandby mode setting PDR23 [7:6]. This power saving feature independent software transparent users. Power-down Sleep Mode States
Table Interface Signals Sleep Mode States
Signal Name
Host Interface [31:0] [3:0] ~FRAME ~TRDY tri-state tri-state tri-state tri-state tri-state
Sleep Mode
Power Management
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LynxEM+ DataBook Sleep Mode
tri-state tri-state tri-state tri-state tri-state
Signal Name
~IRDY ~STOP ~DEVSEL IDSEL ~RST ~REQ ~GNT ~INTA Power Down Interface ~PDOWN ~CLKRUN Clock Interface REFCLK/PALCLK CKIN LVDSCLK/MCKIN ~EXCKEN Memory Interface [9:0] [63:0] ~RAS ~CAS [1:0] ~DQM [7:0] SDCKEN ~ROMEN Flat Panel Interface FDATA [23:0] FPSCLK FPEN FPVDDEN VBIASEN LP/FHSYNC
open-collector
tri-state
(note (self-refresh), (CAS-b-RAS) depends
Power Management
Silicon Motion®, Inc.
LynxEM+ DataBook Sleep Mode
Signal Name
FP/FVSYNC Interface CRTVSYNC CRTHSYNC Video Port Interface [15:0] PCLK VREF HREF BLANK/TVCLK General Purpose USR3 USR2 USR1/SDA USR0/SCL Test Mode Pins TEST [1:0] Registers/I2C
Notes: This entry specifies when PDR20 (self-refresh). When PDR20 (CAS before RAS), both ~RAS ~CAS control based refresh clock lines have internal pull-up, therefore, without external pulldown resistors, lines will HIGH. With external pulldown resistors, lines will LOW.
Power Management
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Configuration Space Registers
Table Configuration Registers Quick Reference Summary Registers
CSR00: Vendor CSR02: Device CSR04: Command CSR06: Status CSR08: Revision Class Code CSR0D: Latency Timer CSR10: Memory Base Address Register CSR2C: Configuration Space Subsystem Vendor CSR2E: Configuration Space Subsystem CSR30: Expansion Base Address CSR30: Expansion Base Address CSR34: Power Down Capability Pointer CSR3C: Interrupt Line CSR3D: Interrupt CSR40: Power Down Capability Register CSR44: Power Down Capability Data Extended Registers LOCK: Extended Register Write Protect Control
Page
Configuration Space Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
Configuration Space Registers
specification defines configuration space auto-configuration (plug-and-play), device memory relocation.
CSR00: Vendor
Read Only Address: Power-on Default: 126Fh This register specifies vendor
VENDOR
15:0
Vendor This register hardwired 126Fh identify
CSR02: Device
Read Only Address: Power-on Default: 0712h This register specifies device
DEVICE
15:0
Device This register hardwired 0712h identify device LynxEM+.
CSR04: Command
Read/Write Address: Power-on Default: Note: Reserved bits read only
This register controls which types command cycles supported LynxEM+.
RESERVED
15:6
Reserved Palette Snooping Enable (PSE) Disable Enable
Configuration Space Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
Memory Write Invalidate Enable master (MWR) Disable Enable Reserved Master Enable (PCI) Disable Enable Memory Space Access Enable (MS) (Note: addressing decoding) Disable Enable Space Access Enable (IO) Disable Enable This needs order enable BIOS
CSR06: Status
Read Only Address: Power-on Default: This register controls device select timing status, detect parity status, detects target abort status LynxEM+. order clear this register, must write that particular bit.
RESERVED
RESERVED
14:13 10:9
Detect Parity Error (DPE) Reserved Detect Target Abort Master Mode (DTA) Reserved ~DEVSEL Timing Select (TS) medium speed (hardwired) Reserved
CSR08: Revision Class Code
Read Only Address: Power-on Default: 030000A0h
Configuration Space Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
This register specifies silicon revision Class Code that silicon supports.
BASE CLASS CODE
SUBCLASS CODE
LEVEL PROGRAMMING INTERFACE
REVISION
31:24
Base Class Code Video Controller Subclass Code Register Level Programming Interface hardwired setting Revision example, revision revision
23:16
15:8
CSR0D: Latency Timer
Read Only Address: Power-on Default: This register specifies latency timer that LynxEM+ supports burst master mode.
LATENCY TIMER
Latency Timer burst capable master
CSR10: Memory Base Address Register
Read/Write Address: (Note: Reserved bits read only) Power-on Default: This register specifies configuration space address relocation
RESERVED
LINEAR ADDRESSING MEMORY BASE
RESERVED
31:24
Linear Addressing Memory Base Address. Memory segment allocated within boundary
Configuration Space Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
23:1
Reserved Memory Space Indicator (MSI) (Read only) memory base
CSR2C: Configuration Space Subsystem Vendor
Read/Write Address: Power-on Default: This register specifies Subsystem Vendor
SUBSYSTEM VENDOR
15:0
Subsystem Vendor
CSR2E: Configuration Space Subsystem
Read/Write Address: Power-on Default: 712h This register specifies Subsystem default setting MD[22:20] 111b which configures system BIOS load subsystem information during POST.
SUBSYSTEM
15:0
Subsystem This System written system BIOS during POST
CSR30: Expansion Base Address
Read/Write Address: Power-on Default: This register specifies expansion base address. Note: Reserved bits read only.
RESERVED
BIOS
BASE ADDRESS
31:16
Base Address. Memory segment allocated BIOS 64KB boundary [15:0]
Configuration Space Registers
Silicon Motion®, Inc. 15:1 Reserved
LynxEM+ DataBook
BIOS Address Decode Enable. This valid only memory space access enabled. (CSR04 Disable Enable
CSR34: Power Down Capability Pointer
Read Only Address: Power-on Default: This register contains address where power down management registers located
CAPABILITY POINTER/PCI POWER DOWN MGMT
Capability pointer contains address where Power Down Management Register located.
CSR3C: Interrupt Line
Read/Write Address: Power-on Default: This register specifies Interrupt Line.
INTERRUPT LINE
Interrupt Line
CSR3D: Interrupt
Read Only Address: Power-on Default: This register specifies Interrupt Pin.
RESERVED
Reserved Interrupt (IP) (~INTA)
Configuration Space Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
CSR40: Power Down Capability Register
Read Only Address: Power-on Default: 0601h This register contains address where power down management Capabilities.
POWER DOWN MANAGEMENT CAPABILITY (0601h)
POWER DOWN MGMT CAPABILITY POINT LINK
POWER DOWN MGMT CAPABILITY (01h)
31:16
Power Down Management Capability 0601h Offset Power Down Management Capability Point Link List Offset Power Down Management Capability Offset
15:8
CSR44: Power Down Capability Data
Read/Write Address: Power-on Default: This register contains address where power down management Control, Status Data
DATA
RESERVED
POWER DOWN MGMT CONTROL/STATUS
31:24
Data Read Only. Offset Reserved Offset Power Down Management Control/Status Offset
23:16
15:0
Configuration Space Registers
Silicon Motion®, Inc. Extended Registers
LynxEM+ DataBook
LOCK: Extended Register Write Protect Control
Read/Write Address: 3C3h 3C5h index Power-on Default: This register specifies write protect controls extended registers. extended registers write-protected. order write extended registers, must write [7:5] 010b.
RESERVED
Write Protect Enable (WPE) Extended registers Write-Protected Enable writes Extended registers Others Maintain previous state Reserved
Configuration Space Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
Chapter Standard Registers
Table Standard Registers Quick Reference Summary Registers
General Registers MISC: Miscellaneous Output Register ISR0: Input Status Register ISR1: Input Status Register FCR: Feature Control Register Sequencer Register SEQX: Sequencer Index Register SEQ00: Reset Register SEQ01: Clocking Mode Register SEQ02: Enable Write Plane Register SEQ03: Character Select Register SEQ04: Memory Mode Register CRTC Controller Registers CRTX: CRTC Controller Index Register CRT00: Horizontal Total Register CRT01: Horizontal Display Register CRT02: Horizontal Blank Start Register CRT03: Horizontal Blank Register CRT04: Horizontal Sync Pulse Start Register CRT05: Horizontal Sync Pulse Register CRT06: Vertical Total Register CRT07: Overflow Vertical Register CRT08: Preset Scan Register CRT09: Maximum Scan Line Register CRT0A: Cursor Start Scan Line Register CRT0B: Cursor Scan Line Register CRT0C: Display Start Address High Register CRT0D: Display Start Address Register
Page
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook Page
Summary Registers
CRT0E: Cursor Location High Register CRT0F: Cursor Location Register CRT10: Vertical Sync Pulse Start Register CRT11: Vertical Sync Pulse Register CRT12: Vertical Display Register CRT13: Offset Register CRT14: Underline Location Register CRT15: Vertical Blank Start Register CRT16: Vertical Blank Register CRT17: Mode Control Register CRT18: Line Compare Register CRT22: Graphics Controller Data Latches Readback Register CRT24: Attribute Controller Toggle Readback Register CRT26: Attribute Controller Index Readback Register Graphics Controller Registers GRXX: Graphics Controller Index Register GRX00: Set/Reset Register GRX01: Enable Set/Reset Register GRX02: Color Compare Register GRX03: Data Rotate/ROP Register GRX04: Read Plane Select Register GRX05: Graphics Mode Register GRX06: Graphics Miscellaneous Register GRX07: Color Don't Care Plane Register GRX08: Mask Register Attribute Controller Registers ATRX: Attribute Controller Index Register ATR00-0F: Palette Register ATR10: Attribute Mode Control Register ATR11: Overscan Color Register ATR12: Color Plane Enable Register ATR13: Horizontal Pixel Panning Register ATR14: Color Select Register RAMDAC Registers 3C6: Mask Register 3C7W: Address Read Register 3C7R: Status Register
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook Page
Summary Registers
3C8: Address Write Register 3C9: Data Register
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
Standard Registers
This chapter describes standard registers. following registers description, address stands hexadecimal value either 'D'. Miscellaneous Output Register address based 3Dxh color emulation. Miscellaneous Output Register address based 3Bxh monochrome emulation. General Registers
MISC: Miscellaneous Output Register
Write Only Address: 3C2h Read Only Address: 3CCh Power-on Default:
VIDEO CLOCK
Vertical Sync Polarity Select (VSP) positive vertical sync polarity negative vertical sync polarity Horizontal Sync Polarity Select (HSP) positive horizontal sync polarity negative horizontal sync polarity Odd/Even Memory Page Select (OEM) Select lower page memory Select upper page memory Reserved Video Clock Select Select 25.175MHz dots/line mode Select 28.322MHz dots/line mode Reserved (enable external clock source) Reserved (enable external clock source) Enable Video Access from (EVR) Disable Video access from Enable Video access from Address Select (IO) Select monochrome mode. Address based at3Bxh. Select color mode. Address based 3Dxh
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
ISR0: Input Status Register
Read Only Address: 3C2h Power-on Default: Undefined
RESERVED
RESERVED
Vertical Retrace Interrupt (CRT) Vertical Retrace Interrupt cleared Vertical Retrace Interrupt pending. Reserved Monitor Detect Status (MDS) Monochrome display detected Color display detected Reserved
ISR1: Input Status Register
Read Only Address: 3?Ah Power-on Default: Undefined
RESERVED
COLOR PLANE
DISPLAY ENABLE
Reserved Color Plane Diagnostics These bits return video outputs VID0-VID7, selected Color Plane Enable Register [5:4] Vertical Retrace Status (VRS) display mode vertical retrace mode Reserved Display Enable display mode display mode. either horizontal vertical retrace mode)
FCR: Feature Control Register
Write Only Address: 3?Ah
Standard Registers
Silicon Motion®, Inc. Read Only Address: 3CAh Power-on Default:
RESERVED
LynxEM+ DataBook
RESERVED
Reserved Vertical Sync Control VSYNC output enabled VSYNC output logical 'OR' VSYNC Vertical Display Enable Reserved
Sequencer Register
SEQX: Sequencer Index Register
Read/ Write Address: 3C4h Power-on Default: Undefined
RESERVED
SEQUENCER ADDRESS/INDEX
Reserved Sequencer Address/Index Sequencer address register written with index value sequencer register accessed.
SEQ00: Reset Register
Read/ Write Address: 3C5h, Index: Power-on Default:
RESERVED
Reserved Synchronous Reset (SR) Sequencer cleared halted synchronously Normal operating mode Asynchronous Reset (AR) Sequencer cleared halted asynchronously Normal operating mode
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
SEQ01: Clocking Mode Register
Read/ Write Address: 3C5h, Index: Power-on Default:
RESERVED
Reserved Screen (SO) Normal operating mode Screen turned SYNC signals remain active Video Serial Shift Select (VS) Load video serializer every every other character clock, depending Bit2 this register. Load video serializer every character clock Clock Select (DCS) Normal clock select VCLK input frequency clock divided (320/360 pixel mode) Shift Load (SL) Load video serializer every character clock Load video serializer every other character clock Reserved Clock (DC) wide character clock wide character clock
SEQ02: Enable Write Plane Register
Read/ Write Address: 3C5h, Index: Power-on Default:
RESERVED
ENABLE WRITING
Reserved Enable Writing Memory Maps through (respectively) Disable writing corresponding plane Enable writing corresponding plane
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
SEQ03: Character Select Register
Read/ Write Address: 3C5h, Index: Power-on Default:
SCMB
SCMA
SCMA
SCMB
SCMB
RESERVED
5,3,2
Reserved Select Character (SCMA)
This value select portion plane used generate text character when this register according following table: 5,3,2
Font Table Location
First plane Second plane Third plane Fourth plane Fifth plane Sixth plane Seventh plane Eighth plane
4,1,0
Select Character (SCMB)
This value select portion plane used generate text character when this register according same table character
SEQ04: Memory Mode Register
Read/ Write Address: 3C5h, Index: Power-on Default:
RESERVED
Reserved Chained (CM) Enable odd/even mode Enable Chain mode. Uses lower bits address select plane video memory follows:
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
Plane Selected
Select Sequential Addressing Mode (SSA). This affects only write data accesses into video memory. this register must this effective. Enable odd/even addressing mode. Even addresses access planes addresses access plane Enable system sequential addressing mode Extended Video Memory Enable (EVM) Memory access restricted 16/32K Enable extended video memory access. Allows complete memory access 256K Reserved
CRTC Controller Registers CRTC registers located locations address space. These registers accessed first writing index register (3?4h), then writing data register (3?5h). address either 3Bxh 3Dxh depending Miscellaneous Output Register 3C2h.
CRTX: CRTC Controller Index Register
Read/Write Address: 3?4h Power-on Default: This register loaded with binary value that indexes CRTC controller register where data accessed.
RESERVED
CRTC ADDRESS INDEX
Reserved CRTC Address Index These bits specify CRTC register addressed. value programmed hexadecimal.
CRT00: Horizontal Total Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines number character clocks from HSYNC going active next HSYNC going active.
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
HORIZONTAL TOTAL
Horizontal Total This value (number character clocks scan line)
CRT01: Horizontal Display Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines number character clocks horizontal line active display. This register locked when FPR33 (SC5h, index Please refer FPR33 register.
HORIZONTAL DISPLAY ENABLE
Horizontal Display This value (number character clocks during active display)
CRT02: Horizontal Blank Start Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines number character clocks which horizontal ~Blank asserted.
HORIZONTAL BLANK START
Horizontal Blank Start This value character value which ~Blank signal becomes active.
CRT03: Horizontal Blank Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines display enable skew pulse width ~Blank signal.
DISPLAY ENABLE
HORIZONTAL BLANK
Reserved
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
Display Enable Skew. These bits define display enable signal skew timing relation horizontal synchronization pulses. DESKW1
DESKW0
Character Clock Skew
Horizontal Blank Horizontal Blank 6-bit value. This register contains least significant 5-bits this value. this value CRTC index
CRT04: Horizontal Sync Pulse Start Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register used adjust screen position horizontally specify position which HSYNC active.
HORIZONTAL SYNC PULSE START
Horizontal Sync Pulse Start This value character clock count value which HSYNC becomes active.
CRT05: Horizontal Sync Pulse Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines horizontal sync skew pulse width HSYNC signal.
HORIZONTAL SYNC
Horizontal Blank This Horizontal Blank (HBE) Horizontal Sync Skew. (HSS) These 2-bits define HSYNC signal skew timing relation horizontal synchronization pulses.
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
HSSKW1
HSSKW0
Character Clock Skew
Horizontal Sync Horizontal Sync 5-bit value. This value defines character clock counter value which HSYNC signal becomes inactive.
CRT06: Vertical Total Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines number scan lines from VSYNC going active next VSYNC going active. Vertical total 11-bit value. this value located CRT07 this value located CRT07 this value located CRT30
VERTICAL TOTAL
Vertical Total Vertical Total 11-bit value. This register contains least significant 8-bits this value. This value (number scan lines from VSYNC going active next VSYNC) CRT07 CRT30
CRT07: Overflow Vertical Register
Read/ Write Address: 3?5hIndex: Power-on Default: Undefined This register specifies CRTC vertical overflow registers.
Vertical Sync Start (VSS) Vertical Display Enable This locked when FPR33 (SC5h, index Please refer FPR33 register. (VDE) Vertical Total (VT) Line Compare (LC)
Standard Registers
Silicon Motion®, Inc.
LynxEM+ DataBook
Vertical Blank Start (VBS) Vertical Sync Start (VSS) Vertical Display Enable This locked when FPR33 (SC5h, index (VDE) Vertical Total (VT)
CRT08: Preset Scan Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register used panning text scrolling.
BYTE PLANNING
PRESET SCAN COUNT
Reserved Byte Panning Control. These 2-bits controls number bytes pan. BPC1
BPC0
Operation
Normal Byte left shift Bytes left shift Bytes left shift
Preset Scan Count These bits preset vertical scan counter once after each vertical retrace. This counter automatically incremented after each horizontal sync period. Once maximum scan count reached, this counter cleared. This useful smoothing vertical text scrolling.
CRT09: Maximum Scan Line Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines maximum number scan lines character provides scanning control overflow bits
MAXIMUM SCAN LINE
Enable Double Scan (EDS) Normal Operating
Standard Registers
Silicon Motion®, Inc. Enable Double Scan. scan counter clocked half horizontal scan rate. Line Compare Register (LC) Vertical Blank Start Register (VB) Maximum Scan Line This value equals total number scan lines character
LynxEM+ DataBook
CRT0A: Cursor Start Scan Line Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines scan character line which cursor begins enable/disable cursor.
RESERVED
CURSOR START SCAN LINE
Reserved Enable Cursor (EC) Cursor Cursor Cursor Start Scan Line This value equals starting cursor within character box. this value programmed with value greater than Cursor Scan Line Register (3?5h, index 0Bh), cursor will displayed.
CRT0B: Cursor Scan Line Register
Read/Write Address: 3?5h, Index Power-on Default: Undefined This register defines scan character line which cursor begins enable/disable cursor.
CURSOR SKEW
CURSOR SCAN LINE
Reserved Cursor Skew.
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