Processor Host Support Optimized Intel® mobile Pentium® mobile Celeron
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82443MX100 PCIset
Processor Host Support Optimized Intel® mobile Pentium® mobile Celeronprocessors GTL+ Driver Technology Integrated DRAM Support using 16-Mb, 64-Mb, 128-Mb Technology Standard Registered SDRAM (Synchronous) DRAM Support (x-1-1-1 access MHz) Enhanced Open Page Arbitration SDRAM Paging Scheme Interface Rev. 2.3, 3.3-V, 33-MHz Interface Compliant Integrated Controller Channel Support "Ultra DMA/33" Synchronous Mode System Peripheral Support Enhanced Controller Support Dual Cascaded 82C37 Controllers Interrupt Controller based 82C59 Interrupts System Timer based 82C54 Real Time Clock with 256-Bytes Battery backed X-bus Support SIO, KBCX, Flash Link Controller Audio Modem CODEC Interface Support Port Serial Transfers Mbits/sec Supports UHCI Design Guide SMBus Support Power Management Logic Support Power-On-Suspend, Suspend-To-SDRAM, Suspend-To-Disk Support Thermal Alarm Full Support ACPI Specification Revision GPIO Pins Thermal Design Power 2.1W 1.6W uBGA Package
Intel 82443MX100 PCIset integrates traditional "North Bridge" "South Bridge" into device, which reduces power board space Intel mobile Pentium processor-based designs mobile Celeron processor-based designs. Intel 82443MX100 PCIset contain design defects errors know errata, which cause product deviate from published specifications. Current characterized errata available upon request.
Order Number- 245292-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel retains right make changes specifications product descriptions time, without notice. mobile Celeronprocessor, mobile Pentium® processor, 82443MX100 controller products contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Intel 82443MX100 PCIset Datasheet provided WITH WARRANTIES WHATSOEVER, INCLUDING WARRANTY MERCHANTABILITY, NONINFRINGEMENT, FITNESS PARTICULAR PURPOSE, WARRANTY OTHERWISE ARISING PROPOSAL, SPECIFICATION SAMPLE. Intel disclaims liability, including liability infringement proprietary rights, relating information this specification. license, express implied, estoppel otherwise, intellectual property rights granted herein. two-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol SMBus bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 7641 Prospect 60056-7641 call 1-800-879-4683 *Other brands names property their respective owners. Copyright Intel Corporation, 1999.
Intel® 82443MX100 PCIset
CONTENTS
Introduction References 440MX Feature Summary 440MX Features. Architecture Overview. Signal Description States List. 3.1.1 Signal Description. 3.1.2 Power Ground Pins. GPIO Definition Power Rail Overview Power-up State Initial Value Power-On-Reset Values. Power-up/Reset Strap Options Reset. Power Planes Overview. Power Plane Resume Power Plane. System Address Map. Addressable Memory Support Memory Map. 5.2.1 Compatibility Area 5.2.1.1 Area (00000h-9FFFh; 5.2.1.2 Video Buffer Area (A0000h-BFFFFh; KB). 5.2.1.3 Expansion Area (C0000h-DFFFFh; 5.2.1.4 Extended System BIOS Area (E0000h-EFFFFh; KB). 5.2.1.5 System BIOS Area (F0000h-FFFFFh; 5.2.2 Extended Memory Area 5.2.2.1 Main DRAM Address Range (0010_0000h Main Memory). 5.2.2.2 Extended SMRAM Address Range (Top Main Memory TSEG_SZ Main Memory). 5.2.2.3 Memory Address Range (Top Main Memory 5.2.2.4 High BIOS Area (FFC0_0000h FFFF_FFFFh) System Management Mode (SMM) Memory Range. Memory Shadowing. Decode Rules Cross-Bridge Address Mapping 5.5.1 Interface Memory Decode Rules 5.5.2 Legacy Range Address Space
Intel® 82443MX100 PCIset
5.6.1 Fixed Address Ranges 5.6.2 Variable Decode Ranges. Functional Description Mobile Celeron Processor Mobile Pentium Processor Host Interface 6.1.1 Overview 6.1.2 Host Device Support. 6.1.3 Special Cycles 6.1.4 Symmetric Multiprocessor (SMP) Configuration 6.1.5 In-order Queue Pipelining 6.1.6 Frame Buffer Memory Support (USWC). 6.1.7 Sideband Interface 6.1.7.1 A20M#. 6.1.7.2 FERR#/IGNNE# (Co-processor Error) 6.1.7.3 INIT# 6.1.7.4 Interrupt Signals 6.1.7.5 6.1.7.6 SMI# 6.1.7.7 STPCLK# Memory Interface 6.2.1 DRAM Interface 6.2.1.1 DRAM Interface Overview 6.2.2 DRAM Organization Configuration 6.2.2.1 Configuration Mechanism DIMMs 6.2.2.1.1 Memory Detection Initialization. 6.2.2.1.2 SMBus Configuration 6.2.2.1.3 Accessing Serial Presence Detect Ports. 6.2.2.1.4 DRAM Register Programming. 6.2.3 SDRAM Cycle Encoding 6.2.4 DRAM Address Translation Decoding 6.2.5 SDRAMC Register Programming 6.2.6 SDRAM Paging Policy 6.2.6.1 Overview 6.2.6.2 Open Page Arbitration Policies 6.2.6.3 Selective Auto Precharge Policy 6.2.7 DRAM Power Throttling 6.2.7.1 Overview 6.2.7.2 Conceptual Description Power Throttling. 6.2.7.2.1 During Monitoring Regime 6.2.7.2.2 During Throttling Regime 6.2.7.2.3 Read Write Throttling Regimes. 6.2.7.2.4 Relation Between Read Write Throttling 6.2.7.3 SDRAM Power Throttling Setting Sequence 6.2.8 SDRAM Performance Description 6.2.9 SDRAM Optimizations 6.2.9.1 Dual Quad Bank Support System Memory Management. 6.3.1 SMRAM Range Overview
Intel® 82443MX100 PCIset
6.3.2 Compatible SMRAM (C_SMRAM). 6.3.3 Extended SMRAM (E_SMRAM). Audio Modem Controller. 6.4.1 Audio Controller 6.4.2 Modem Controller. 6.4.3 Overview. 6.4.4 System Initialization 6.4.5 Clocking 6.4.6 Digital Interface. 6.4.6.1 Multi-Point ACLink. 6.4.6.1.1 Primary Codec. 6.4.6.1.2 Secondary Codec 6.4.6.2 AC-link Digital Serial Interface Protocol. Interface. 6.5.1 Interface Overview 6.5.2 North Bridge/Cluster Functionality. 6.5.2.1 North Bridge/Cluster Target. 6.5.2.2 North Bridge/Cluster Initiator 6.5.2.3 Delayed Transactions 6.5.3 South Bridge/Cluster Functionality 6.5.3.1 South Bridge/Cluster Target 6.5.3.2 South Bridge/Cluster Initiator. Controller 6.6.1 Register Description 6.6.2 Functional Description 6.6.2.1 Transfer Modes. 6.6.2.1.1 Single Transfer Mode. 6.6.2.1.2 Block Transfer Mode. 6.6.2.1.3 Demand Transfer Mode 6.6.2.1.4 Cascade Mode. 6.6.2.2 Transfer Types. 6.6.2.2.1 Read Transfers. 6.6.2.2.2 Write Transfers 6.6.2.2.3 Verify Transfer 6.6.2.3 Timings. 6.6.2.3.1 Buffer Bompatible Transfers. 6.6.2.3.2 DREQ DACK# Latency Control. 6.6.2.4 X-bus/DMA Arbitration 6.6.2.4.1 Channel Priority
6.6.2.4.1.1 Fixed Priority 6.6.2.4.1.2 Rotating Priority.87
6.6.2.5
6.6.2.6
6.6.2.4.2 Arbitration During Non-Maskable Interrupts. Register Functionality 6.6.2.5.1 Address Compatibility Mode. 6.6.2.5.2 Summary Transfer Sizes 6.6.2.5.3 Address Shifting When Programmed 16-Bit Count Words 6.6.2.5.4 Autoinitialize Software Commands 6.6.2.6.1 Clear Byte Pointer Flip-Flop Datasheet
Intel® 82443MX100 PCIset
6.10
6.6.2.6.2 Master Clear 6.6.2.6.3 Clear Mask Register 6.6.2.7 Terminal Count Summary. 6.6.2.8 X-bus Refresh Cycles DMA. 6.7.1 Overview 6.7.1.1 PC/PCI 6.7.1.2 Distributed 6.7.2 Configuration 6.7.3 PC/PCI 6.7.3.1 Overview 6.7.3.2 Additional Configuration. 6.7.3.3 PC/PCI Expansion Protocol 6.7.3.4 PC/PCI Expansion Cycles 6.7.4 Distributed 6.7.4.1 Overview 6.7.4.2 Additional Configuration. 6.7.4.3 Read/Write Cycle Protocols 6.7.4.4 Calculating Address 6.7.4.4.1 Single Channel Mask Register 6.7.4.4.2 Clear Mask Register 6.7.4.5 Power Management Implications 6.7.4.6 Other Clarifications Timer 6.8.1 Counter/Timers. 6.8.1.1 Counter System Timer. 6.8.1.2 Counter Refresh Request Signal. 6.8.1.3 Counter Speaker Tone. 6.8.2 Interval Timer Address 6.8.3 Programming Interval Timer. 6.8.3.1 Write Operations. 6.8.3.2 Interval Timer Control Word Format. 6.8.3.2.1 Read Operations. 6.8.3.2.2 Counter Port Read 6.8.3.3 Counter Latch Command. 6.8.3.3.1 Read Back Command. 6.9.1 Overview 6.9.2 Registers 6.9.3 Update Cycle. 6.9.4 Interrupts 6.9.5 Lockable Ranges 6.9.6 External Connections. 6.9.6.1 Crystal. 6.9.6.2 Battery 6.9.7 Century Rollover. Interrupt Controller 6.10.1 Interrupt Controller Functional Description
Intel® 82443MX100 PCIset
6.11 6.12
6.13
Interrupt Sequence Interrupt Acknowledge Cycle Programming Interrupt Controller 6.10.1.3.1 Initialization Command Words (ICWs). 6.10.1.3.2 Operation Command Words (OCWs) 6.10.1.4 End-of-Interrupt Operation 6.10.1.4.1 Interrupt (EOI). 6.10.1.4.2 Automatic Interrupt (AEOI) Mode 6.10.1.4.3 Fully Nested Mode. 6.10.1.4.4 Special Fully Nested Mode. 6.10.1.4.5 Automatic Rotation (Equal Priority Devices) 6.10.1.4.6 Specific Rotation (Specific Priority) 6.10.1.4.7 Poll Command 6.10.1.4.8 Cascade Mode. 6.10.1.4.9 Edge Level Triggered Mode 6.10.1.5 Register Functionality 6.10.1.6 Interrupt Masks. 6.10.1.6.1 Masking Individual Interrupt Request Basis 6.10.1.6.2 Special Mask Mode 6.10.1.7 Reading Interrupt Controller Status 6.10.1.8 Interrupt Steering. 6.10.2 Serial Scheme 6.10.2.1 Overview 6.10.2.2 Protocol. 6.10.2.2.1 Quiet (Active) Mode 6.10.2.2.2 Continuous (Idle) Mode. 6.10.2.2.3 Data Frame 6.10.2.2.4 Stop Frame. 6.10.2.3 SMI# SERIRQ 6.10.2.4 SERIRQ ORing with IRQ. Host Controller. Interface. 6.12.1 Register Block Decode. 6.12.2 Transactions 6.12.3 Timing Modes 6.12.4 Enhanced Timing Modes 6.12.4.1 PIORDY Masking 6.12.4.2 32-Bit Data Port Accesses 6.12.4.3 Data Port Prefetching Posting 6.12.5 Master Function. 6.12.5.1 Physical Region Descriptor Format. 6.12.5.2 Operation 6.12.6 Ultra DMA/33"Synchronous Operation 6.12.6.1 Signal Descriptions. 6.12.6.2 Operation 6.12.6.3 Calculation. 6.12.6.4 Reference X-bus
6.10.1.1 6.10.1.2 6.10.1.3
Intel® 82443MX100 PCIset
6.13.1 Target Interface. 6.13.2 X-bus Clock (SYSCLK) Generation. 6.13.3 Wait State Shortened Cycle Generation 6.13.4 Recovery 6.14 System Management (SMBus) 6.14.1 SMBus Host Interface. 6.14.2 SMBus Slave Interface 6.15 GPIO 6.15.1 Configuration 6.16 System Clocking Pin-out Package Information 440MX Pin-out 440MX Package Dimensions.
Intel® 82443MX100 PCIset
Figures
Figure 440MX Platform Block Diagram.6 Figure Platform Power Rails.23 Figure Memory Address Figure Configuration Space Block Diagram Figure Coprocessor Error Timing Diagram Figure DIMM Configuration with Switches.55 Figure SMRAM Mapping.70 Figure Controller Connection Companion Codec Figure 440MX-based Audio System.72 Figure Standard Bi-directional Audio Frame.76 Figure 440MX Topology Figure Internal Controller.83 Figure X-Bus Arbiter with Fixed Priority (Two-way Rotation).87 Figure X-Bus Arbiter with Rotating Priority Figure Serial Channel Passing Protocol.92 Figure Interrupt Controller Block Diagram. Figure Initialization Sequence 440MX Modes Operation Figure Automatic Rotation Mode Example. Figure Polled Mode. Figure Section Interrupt Steering Logic (Without Serial IRQ). Figure System Conceptual View Figure Enhanced Timing Mode Components Figure Inserting Wait States Deasserting PIORDY. Figure Physical Region Descriptor Table Entry. Figure 8-bit Cycles. Figure 440MX SMBus Interfaces. Figure System Clocking Figure 440MX Pinout (Top Side View). Figure 440MX Pinout (Pin Side View). Figure 440MX Package Dimensions (Top Side View). Figure 440MX Package Dimensions (Bottom View)
Intel® 82443MX100 PCIset
Tables
Table Main Feature Table Host Interface Signal Description.8 Table Memory Signal Description.10 Table Signal Description Table Other System/Test Signal Description Table Signal Description Table Signal Description.13 Table Interrupt Signal Description Table Signal Description Table Clocks, Reset, PLLs, Miscellaneous Signal Description Table Signal Description Table SMBus Signal Description Table Power Management Signal Description Table GPIO Signal Description.16 Table X-bus Signal Description Table Core Power Pins Table Host Power Pins.20 Table Power Pins.20 Table Power Pins.20 Table Resume Power Pins.20 Table VREF Power Pins Table GPIO Pins Programmed Through Config. Dev.7, Table System Resume with GPIO Signals Programmed Functional Pins Table Power-On-Reset Values Signal Group Table DRAM Interface Signals Table Miscellaneous Signals.30 Table Power-up Options During Reset Table Mobile Celeron Processor/Mobile Pentium Processor Frequency Ratios Table Power Planes.33 Table Well Signals Table Resume Well Signals Table Memory Segment Attributes Table Compatibility Memory Area.38 Table Fixed Ranges Decoded 440MX Table Variable Decode Ranges (Available Space KB).46 Table Host Transactions Supported Table Host Responses Supported Table Special Cycle Transactions Table Events Causing INIT# Active Table Sample Possible Options Row/3-DIMM Configurations.54 Table Data Bytes DIMM Used Programming DRAM Registers.57 Table Command Truth Table Table Truth Table Table Operative Command Table.59 Table Muxing DRAM Address Split.63
viii
Intel® 82443MX100 PCIset
Table Programmable SDRAM Timing Parameters.63 Table Available Memory SMRAM when Extended SMRAM Enabled Table Extended SMRAM DRAM Memory Regions Table SMRAM Range Decode Table SMRAM Decode Control Table Audio Description.73 Table Supported Data Streams Table Commands Supported North Bridge/Cluster when Acting Target.77 Table Commands Supported North Bridge/Cluster when Acting Initiator Table Commands Supported South Bridge/Cluster when Acting Target.81 Table Commands Supported South Bridge/Cluster When Acting Initiator Table Rotating Priority Example Table Transfer Size.89 Table Address Shifting 16-bit Transfers.89 Table Terminal Count Summary.90 Table Cycle Address Table Data Port Size Table Cycle Width BE[3:0]#.94 Table 8237 Registers DDMA Function.96 Table Mapping 8237 Register DDMA Peripheral.99 Table Interval Timer Functions Table Interval Timer Counters Address Table Counter Operating Modes Table Interrupt Controller Register Port Address Table Typical Interrupt Functions Table Content Interrupt Vector Byte 80x86 System Mode. Table Suggested Default Values Registers. Table SIRQ Frames Table Legacy Ports: Command Block Registers (CS1x# Chip Select) Table Legacy Port Definition: Control Block Registers (CS3x# Chip Select) Table Command Strobe Width Transaction Types Table IDETIMx Timing Modes Drives Table Ultra DMA/33 Control Signal Redefinition Table System Clocking Table 440MX Package Dimensions. Table Alphabetical List. Table GPIO List
Intel® 82443MX100 PCIset
Revision History
Date October 1999 Revision Detail Initial Release
Intel® 82443MX100 PCIset
Introduction
This document provides specifications Intel 82443MX100 PCIset intended architects, engineers, product planners, marketing groups develop technologies, products, positioning notebook market segment. 440MX single-component mobile chipset that optimized Intel mobile Celeron processors mobile Pentium processors value mini-notebook platforms reduces number mobile chipset components without requiring major programming model changes. accomplishes this integrating 443BX North Bridge chipset (without AGP) PIIX4E South Bridge chipset while adding two-channel, digital link feature. This single-component mobile chipset specifically designed reduce system cost, space, power. 440MX packaged mBGA (the same package 443BX).
References
Intel® 82443MX PCIset Electrical Thermal Specification, Rev. (Order number) GTL+ Specification (Order number) Design Testability 82C54 Datasheet (Order number) Serialized Support Systems, (Order number) Universal Host Controller Interface (UHCI) Design Guide, (Order number 297650-002) Attachment Specification (Order number) Synchronous Transfer Protocol (Proposal), 0.40, Quantum Corp. System Management Specification, Signaling Environment Specifications Specification (draft Rev. 0.96) Local Specification, Revision 2.2.
Intel® 82443MX100 PCIset
440MX Feature Summary
Table summarizes main feature 440MX.
Table Main Feature
Features Processor Interface Processor/Host support mobile Celeron processor/Pentium processor Integrated DRAM Controller Capacity DIMMs Data path size Type supported 8-256 DIMMs rows memory) 64-bit without SDRAM, MHz, Interface Revision Voltage masters interrupts PC-PCI channels Rev. 3.3-V (5.0-V tolerant buffers) Miscellaneous Audio: AC'97 channels channel Components Super (FDC, IR), optional Interface support KBC, Flash, other slow devices External X-bus only) X-bus (8-bit) 440MX
Power Management Functions ACPI compliant power management Legacy Power Management support System Management Support SMBus Wired Management (WFM) Miscellaneous General Purpose Input/Output Programmable Chip Selects GPIOs (muxed w/GPIO) X-bus option ports/1
Intel® 82443MX100 PCIset
440MX Features
Processor/Host support Optimized mobile Celeron processors Pentium processors 100-MHz 66MHz host frequency Supports 32-bit mobile Celeron processor Pentium processor addressing support processor host 36-bit address extension) deep in-order queue; deep request queue Supports uni-processor systems only In-order transaction dynamic deferred transaction support GTL+ driver technology (gated GTL+ receivers reduced power) Integrated DRAM controller using 16-Mb, 64-Mb, 128-Mb generation Supports double-sided DIMMs (four rows memory) 64-bit data interface without 100-MHz 66-MHz memory clock Standard registered SDRAM (Synchronous) DRAM support (x-1-1-1 access) Command issue rate clock Supports ONLY 3.3-V DIMM DRAM configurations Support 16-Mbit, 64-Mbit, 128-Mbit DRAM devices Support symmetrical asymmetrical DRAM addressing Support x16, DRAM device width Refresh mechanism Supports CAS-before-RAS Self Refresh during POS, Suspend mode (STR) Enhanced Open Page Arbitration SDRAM paging scheme Support DIMM serial Presence Detect scheme SMBus interface Support DRAM power throttling interface Rev. 2.2, 3.3-V, 33-MHz interface compliant Asynchronous coupling host bus/core frequency parity generation support CPU-to-PCI write assembly full/partial line writes Combines back-to-back sequential CPU-to-PCI memory writes into burst writes Data streaming support from DRAM (~120 MB/s writes, ~100 MB/s reads) Delayed transaction support reads which cannot serviced immediately Supports concurrent CPU, transactions main memory Integrated arbiter with multi-transaction arbitration mechanism Four masters support combination Graphic, LAN, CardBus, Audio, Modem Overall arbitration scheme concurrency Distributed arbitration model optimum concurrency support Concurrent operations CPU, supported dedicated arbitration data buffering logic arbiter Datasheet
Intel® 82443MX100 PCIset arbiter DRAM arbitration managing multiple request queues Internal DRAM controller arbitration between data requests Refresh requests Overall data buffering Distributed data buffering model optimum concurrency DRAM write buffer with read-around-write capability Dedicated CPU-DRAM, PCI-DRAM read buffers CPU-PCI deferred transaction buffering (bi-directional reads writes) Delayed transaction read buffering path System peripherals Interrupt controller Fifteen interrupts with dual cascaded 8259 Serial interrupt input System timer, speaker tone generator controller supports following: Dual cascaded 8237 DDMA channel PC/PCI Real Time Clock ACPI-compliant one-month alarm 256-byte battery-backed link controller channels) Interface Audio CODEC Interface modem CODEC GPIO pins (31) channel master support ATA33 X-bus support SIO, KBC, Flash X-bus based SMBus Host interface slave interface Power management functions ACPI compliant power management ACPI arbiter disable CLOCKRUN# PME# support Static Clock Gating Processor system power management Stop Grant Halt special cycle translation from host Support system Suspend/Resume SUSCLK/SUS_STAT# (for example, DRAM Power-On-Suspend) SDRAM Self-Refresh power-down support Suspend mode Independent, internal dynamic clock gating reduces 440MX' average power dissipation Static Stop Clock support Power-On-Suspend mode Suspend-To-DRAM
Intel® 82443MX100 PCIset Suspend-To-Disk System management SMI# generation SMRAM space remapping A0000h (128 Optional extended SMRAM space above additional 128K/256K/512K/1 TSEG from Memory, cacheable (cacheability controlled processor) Signals/Packaging/Power signals mBGA 3.3-V core mixed 3.3V with 5.0-V tolerant Buffers 2.1W MHz) 1.6-W MHz) (typical) power dissipation with lowpower features enabled
Intel® 82443MX100 PCIset
Architecture Overview
440MX single-component chipset that integrates North Bridge South Bridge additional digital link channels) into chip. replaces interface with 8-bit X-bus that supports KBC, SIO, Flash memory. Figure illustrates block diagram 440MX platform.
Figure 440MX Platform Block Diagram
Intel Mobile Celeron Processor PentiumII Processor
66/100 MHz, Processor
System Memory (SDRAM) System Memory DIMM#0 (SDRAM) DIMM#1
AC'97 Codec
3.3V, chn.
AC'97 Link chn.)
Central Unit Memory Controller
66/100 3.3V
Panel
Controller
Clock Gen.
(3.3V, bit, MHz)
Graphic Controller
GPIO
GPIO
North Bridge/ Cluster
Controller chn.)
HCI) Power Management Control
CardBus Controller
Drive ports) Power Management
8-bit Flash Keyboard PS/2
Controller chn.)
SMBus
South Bridge/ Cluster
Intel® 82443MX100 PCIset
Signal Description States
List
This section provides detailed description 440MX signals. signals arranged functional groups according their associated interface. Table through Table provide descriptions each signal. state each 440MX signal during Reset provided Section 3.4. Some signals, example HCLKIN Sideband signals, voltage dependent clock interface. mobile Celeron processors, 2.5V. Note that processor address data signals logically inverted. other words, actual values inverted what appears processor bus. processor control signals follow normal convention. indicates active level (low voltage) signal followed symbol indicates active level (high voltage) signal suffix. symbol signal name indicates that active, asserted state occurs when signal voltage level. When does follow signal name signal asserted high voltage level. following notations used describe signal type: I/OD Input Output Open-drain Output pin. This requires pullup processor core. Input Open-drain Output pin. This requires pullup processor core. Bi-directional Input/Output
signal description also includes type buffer used particular signal: GTL+ Open-drain GTL+ interface signal. Refer GTL+ Specification complete details. interface signals. These signals compliant with 5.0-V Signaling Environment Specifications.
CMOS CMOS buffers Voltage compatible signals. These 3.3V only.
Intel® 82443MX100 PCIset
3.1.1
Signal Description
Table Host Interface Signal Description
Signal A20GATE Type Description Address Gate. This input from keyboard controller logically combined with Port which then output A20M# signal. A20GATE saves external gate needed with various other chipsets. Address Mask. A20M# goes active either setting appropriate Port Register, A20GATE input signal. Address Strobe. processor owner asserts ADS# indicate first cycles request phase. Block Next Request. Used block current request owner from issuing request. This signal used dynamically control processor pipeline depth. Priority Agent Request. 440MX only Priority Agent processor bus. 440MX asserts this signal obtain ownership address bus. This signal priority over symmetric requests will cause current symmetric owner stop issuing transactions unless HLOCK# signal asserted. Symmetric Agent Request. BREQ0# asserted during CPURST# configure symmetric agents negated host clocks after CPURST# negated. Reset. CPURST# output from 440MX. 440MX generates this signal based PCIRST# signal (generated internally from South Bridge/Cluster) SUS_STAT# pin. CPURST# allows processor begin execution known state. Data Busy. Used data owner hold data transfers requiring more than cycle. Defer. 440MX generates deferred response defined 440MX' dynamic defer policy. 440MX also uses DEFER# signal indicate processor retry response. Data Ready. Asserted each cycle that data transferred. Numeric Coprocessor Error. This signal tied coprocessor error signal processor. FERR# asserted, 440MX generates internal IRQ13 interrupt controller unit. also used gate IGNNE# signal ensure that IGNNE# asserted processor unless FERR# active. Address Bus. HA[31:3]# connects processor address bus. During processor cycles HA[31:3]# inputs. Note that address inverted processor bus. Host Data. These signals connected processor data bus. Note that data signals inverted processor bus. Hit. Indicates that caching agent holds unmodified version requested line. Also driven conjunction with HITM# target extend snoop window. Modified. Indicates that caching agent holds modified version requested line that this agent assumes responsibility providing line. Also, driven conjunction with HIT# extend snoop window. Host Lock. processor cycles sampled with assertion HLOCK# ADS#, until negation HLOCK#, must atomic. example, snoopable access DRAM allowed when HLOCK# asserted processor. Request Command. Asserted during both clocks request phase. first clock, signals define transaction type level detail that sufficient
A20M# ADS# BNR#
BPRI#
BREQ0#
CPURST#
DBSY# DEFER#
DRDY# FERR#
HA[31:3]#
HD[63:0]# HIT#
HITM#
HLOCK#
HREQ(4:0)#
Intel® 82443MX100 PCIset
Signal
Type
Description begin snoop request. second clock, signals carry additional information define complete transaction type. transactions supported 440MX Host Bridge defined Section 6.1. Host Target Ready. Indicates that target processor transaction ready enter data transfer phase. Ignore Numeric Error. This signal connected ignore error processor. IGNNE# only used 440MX coprocessor error reporting function enabled XBCSA Register (bit 5=1). FERR# active, indicating coprocessor error, write Coprocessor Error Register (F0h) causes IGNNE# asserted. IGNNE# remains asserted until FERR# negated. FERR# asserted when Coprocessor Error Register written, IGNNE# signal asserted. Initialization. INIT# asserted response following conditions: When System Reset Reset Control Register reset Reset toggles from 440MX initiates soft reset asserting INIT#. Shut Down Special cycle decoded Bus. RCIN# signal asserted. write occurs Port 92h,
HTRDY# IGNNE#
INIT#
When asserted, INIT# remains asserted approximately clocks before being negated. Mobile Celeron processor/Pentium Processor: During Reset: High INTR After Reset: High During POS: High
Interrupt. INTR driven 440MX signal that interrupt request pending needs serviced. asynchronous with respect SYSCLK PCICLK always output. interrupt controller must programmed following PCIRST# ensure that INTR known state. During Reset: After Reset: During POS: Non-Maskable Interrupt. used force non-maskable interrupt processor. 440MX generate when either SERR# IOCHK# asserted. processor detects rising edge. reset setting corresponding source enable/disable Status Control Register. Keyboard Controller Reset processor. This from keyboard controller saves external gate needed. This called RESET processor, because uses terminology. However, signal mainly used generate INIT#. Response. Indicates type response according following: RS[2:0] Response Type Idle state Retry response Deferred response Reserved (Not driven 440MX) Hard failure (Not driven 440MX) data response Implicit writeback Normal data response
RCIN#
RS(2:0)#
SMI#
System Management Interrupt. SMI# active output synchronous PCICLK that asserted 440MX response many enabled hardware software events. Note: 440MX allows synchronous events generate SMI# even after STPCLK# occurred.
STPCLK#
Stop Clock Request. STPCLK# active synchronous output synchronous PCICLK that asserted 440MX response many hardware software events. When processor samples STPCLK#
Intel® 82443MX100 PCIset
Signal
Type
Description asserted, responds stopping internal clock.
Table Memory Signal Description
Signal CKE(3:0)# Type Description Clock Enable (SDRAM). Clock Enable used signal self-refresh powerdown command SDRAM array when entering system Suspend. also used dynamically power down inactive SDRAM rows. Chip Select (SDRAM). memory rows configured with SDRAM these pins select particular SDRAM components during active state. Input/Output Data Mask (SDRAM). These pins synchronized output enables during read cycles byte enables during write cycles. read cycles require Tdqz clock latency before functions performed. case write cycles, byte-masking functions performed during same clock when write data driven (for example, 0-clock latency). Memory Address (SDRAM). MA(13,12#:11#,10,(9:0)#) signals provide multiplexed column address DRAM. Each Memory address line programmable buffer strength optimize different signal loading conditions. Memory Data (SDRAM). These signals interface DRAM data bus. SDRAM Column Address Strobe (SDRAM). SCAS# signal generates SDRAM commands encoded SRAS#/SCAS#/WE# signals. SDRAM Address Strobe (SDRAM). SRAS# signal generates SDRAM commands encoded SRAS#/SCAS#/WE# signals. Write Enable Signal (SDRAM). asserted during writes DRAM. lines have programmable buffer strength that optimized different signal loading conditions.
CS(3:0)# DQM(7:0)
MA(13,12#,11# (9:0)#) MD(63:0) SCAS# SRAS#
Intel® 82443MX100 PCIset
Table Signal Description
Signal PDA[2:0] Type Description Device Address. These output signals connected corresponding signals connectors. They used indicate which byte either command block control block being addressed. Device Chip Selects Range. Command Register block. This output signal connected corresponding signal connector. Device Chip Select Range. Control Register block. This output signal connected corresponding signal connector. Device Data. These signals directly drive corresponding signals connector. Device Acknowledge. This signal directly drives DAK# signal connectors. asserted 440MX indicate slave devices that given data transfer cycle (assertion PDIOR# PDIOW#) data transfer cycle. This signal used conjunction with master function associated with AT-compatible channel. Device Request. This input signal directly driven from DREQ signal connector. asserted device request data transfer. This signal used conjunction with master function associated with AT-compatible channel. Disk Read (PIO Non-Ultra33 DMA). This command device that drive data onto lines. Data latched 440MX deassertion edge PDIOR#. device selected either Register file chip selects (PDCS1#, PDCS3#) lines, acknowledge (PDDAK#). Disk Write Strobe (Ultra33 Writes Disk). This data write strobe writes disk. When writing disk, 440MX drives valid data rising falling edges PDWSTB. Disk Ready (Ultra33 Reads from Disk). This ready reads from disk. When reading from disk, 440MX deasserts PRDMARDY# pause burst data transfers. PDIOW# (PDSTOP) Disk Write (PIO Non-Ultra33 DMA). This command device that latch data from lines. device latches data deassertion edge PDIOW#. device selected either Register file chip selects (PDCS1#, PDCS3#) lines, acknowledge (PDDAK#). Disk Stop (Ultra33 DMA). 440MX asserts this signal terminate burst. PIORDY Channel Ready (PIO). This signal keeps strobe active (PDIOR# reads, PDIOW# writes) longer than minimum width. adds wait states transfers. Disk Read Strobe (Ultra33 Reads from Disk). When reading from disk, 440MX latches data rising falling edges this signal. Disk Ready (Ultra33 Writes Disk). When writing disk, this signal deasserted disk pause burst data transfers.
PDCS1# PDCS3# PDD[15:0] PDDAK#
PDDRQ
PDIOR# (PDWSTB PRDMARDY#)
Table Other System/Test Signal Description
Signal SPKR GPIO(14) Type Description Speaker. SPKR signal output counter internally "ANDed" with Port provide Speaker Data Enable. This signal drives external speaker driver device. Upon PCIRST#, output state This signal muxed with GPIO(14). Refer Section count. Intel Reserved signal. This signal must strapped external pull-up resistor.
TEST#
Intel® 82443MX100 PCIset
Table Signal Description
Signal AD[31:0] Type Description Address/Data. AD[31:0] multiplexed address data bus. During first clock transaction, AD[31:0] contain physical byte address bits). During subsequent clocks, AD[31:0] contain data. Command Byte Enables. command byte enable signals multiplexed same pins. During address phase transaction, C/BE[3:0]# define command. During data phase C/BE[3:0]# used Byte Enables. C/BE[3:0]# 0000 0001 0010 0011 0110 0111 1010 1011 1100 1110 1111 Command Type Interrupt Acknowledge Special Cycle Read Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write Invalidate
C/BE[3:0]#
command encodings shown here Reserved. 440MX does reserved values, does respond master generates cycle using reserved values. CLKRUN# DEVSEL# I/OD Clock Run. CLKRUN# uses protocol between 440MX various peripherals dynamic starting stopping clock. Device Select. 440MX asserts DEVSEL# claim transaction. output, 440MX asserts DEVSEL# when claims cycle. input, DEVSEL# indicates response 440MX-initiated transaction bus. DEVSEL# three-stated from leading edge PCIRST# remains three-stated 440MX until driven target. Cycle Frame. FRAME# driven current Initiator indicate beginning duration access. While FRAME# asserted data transfers continue. When FRAME# negated transaction final data phase. FRAME# input 440MX when target. FRAME# output when 440MX initiator remains three-stated 440MX until driven initiator. PC/PCI Acknowledge. Section description. PC/PCI request needed, these used general-purpose inputs. Initiator Ready. IRDY# indicates 440MX's ability, Initiator, complete current data phase transaction. used conjunction with TRDY#. data phase completed clock when both IRDY# TRDY# sampled asserted. During write, IRDY# indicates 440MX valid data present AD[31:0]. During read, indicates 440MX prepared latch data. IRDY# input 440MX when 440MX Target output when 440MX Initiator. IRDY# remains three-stated 440MX until driven initiator. Calculated Parity. "even" parity calculated bits AD[31:0] plus C/BE[3:0]#. "Even" parity means that number "1"s within bits plus counted always even. always calculated bits regardless valid byte enables. generated address data phases only guaranteed valid clock after corresponding address data phase. driven three-stated identically AD[31:0] lines except that delayed exactly clock. output during address phase (delayed clock) 440MX-initiated transactions. also output during data phase (delayed clock) when 440MX Initiator write transaction, when Target read transaction. Reset. 440MX asserts PCIRST# reset devices that reside
FRAME#
GNTA# GPIO(3) IRDY#
PCIRST#
Intel® 82443MX100 PCIset
Signal
Type
Description bus. 440MX asserts PCIRST# during power-up when hard Reset sequence initiated through (CF9h) Register. PCIRST# driven inactive minimum after PWROK driven active. PCIRST# driven minimum when initiated through Register. PCIRST# asserted after PWROK deasserted state. Grants. channels master bus. PGNT[3]# multiplexed with GPIO.
PGNT[3]# GPIO(30) PGNT[2:0]# PIRQ(A-B)#, PIRQ(C-D)# GPIO(22:23)
I/OD
Interrupt Requests. PIRQx# signals routed interrupts described Section 6.10.1.8. Each PIRQx# line separate Route Control Register. PIRQC# PIRQD# multiplexed with GPIO.
PLOCK#
Lock. Indicates exclusive operation require multiple transactions complete. 440MX asserts PLOCK# when doing nonexclusive transactions PCI. PLOCK# ignored when masters granted bus. Power Management Event. Driven peripherals wake system from low-power states S1-S5. included specification. Requests. channels master bus.
PME# GPIO(0) PREQ[3]# GPIO(29) PREQ[2:0]# REQA# GPIO(2) SERR#
PC/PCI Request. Section description. PC/PCI request needed, this signal used GPIO.
I/OD
System Error. SERR# pulsed active device that detects system error condition. Upon sampling SERR# active, 440MX programmed generate NMI, SMI#, interrupt. Some internal conditions also cause 440MX drive SERR# active. Stop. STOP# indicates that 440MX, Target, requesting initiator stop current transaction. Initiator, STOP# causes 440MX stop current transaction. STOP# output when 440MX Target input when 440MX Initiator. STOP# three-stated from leading edge PCIRST#. STOP# remains three-stated until driven 440MX slave. Target Ready. TRDY# indicates 440MX's ability complete current data phase transaction. TRDY# used conjunction with IRDY#. data phase completed when both TRDY# IRDY# sampled asserted. During read, TRDY# indicates that 440MX, Target, placed valid data AD[31:0]. During write, indicates 440MX, Target prepared latch data. TRDY# input 440MX when 440MX Initiator output when 440MX Target. TRDY# three-stated from leading edge PCIRST#. TRDY# remains three-stated 440MX until driven target.
STOP#
TRDY#
Table Signal Description
Signal AC_BIT_CLK AC_RST# AC_SDATA_ IN(0) AC_SDATA_ IN(1) AC_SDATA_ AC_SYNC Type Description Clock. 12.288-MHz serial data clock Reset. Master Reset Serial Data Serial data input Serial Data Serial data input Serial Data Out. Serial data output Sync. 48-KHz fixed rate sample sync
Intel® 82443MX100 PCIset
Table Interrupt Signal Description
Signal IRQ(14) SERIRQ GPIO(7) Type I/OD Description Interrupt Request This interrupt input connected drive. Serial Interrupt Request. This conveys serial interrupt protocol. This signal muxed with GPIO(7).
Table Signal Description
Signal RTCX1 RTCX2 Type Description
Specia 32-KHz crystal. Connected 32.768-KHz crystal. external crystal used, then RTCX1 driven with desired clock rate. Specia 32-KHz crystal. Connected 32.768-KHz crystal. external crystal used, then RTCX2 should remain floating.
Table Clocks, Reset, PLLs, Miscellaneous Signal Description
Signal CLK48 DCLK DCLKO Type Description 48-MHz Clock. This signal runs controller. SDRAM Clock. Feedback reference from external zero-delay SDRAM clock buffer. 440MX uses this clock when accessing SDRAM array. SDRAM Clock Out. 100-MHz 66-MHz SDRAM clock reference generated internally 440MX onboard PLL. feeds external buffer that produces multiple copies DIMMs. Host Clock This receives buffered host clock. This clock used 440MX' logic that resides Host clock domain. This clock used internal generate clock references 100-MHz 66-MHz operations. During POS/STR HCLKIN must low. This same identical clock that goes processor. PCICLK Oscillator Clock. Used 8254 timers. Runs 14.31818 MHz. Clock. This buffered clock reference that synchronously derived external clock synthesizer component from host clock. This clock used 440MX' logic that resides clock domain. During POS/STR PCLKIN must low.
HCLKIN
Table Signal Description
Signal OC[1:0]# USBPRT[0]+, USBPRT[0]USBPRT[1]+, USBPRT[1]Type Description Overcurrent Indicators. These signals corresponding bits controller indicate that overcurrent condition occurred. Universal Serial Port Differential. Data/Address/Command Bus. Universal Serial Port Differential. Data/Address/Command Bus.
Intel® 82443MX100 PCIset
Table SMBus Signal Description
Signal SMBCLK SMBDATA Type I/OD I/OD Description SMBus Clock. SMBus Clock Pin. External pullup required. SMBus Data. SMBus Data Pin. External pullup required.
Table Power Management Signal Description
Signal BATLOW# GPIO(11) CPUSTP# Type Description Battery Low. This signal Resume plane. Battery function needed, then this signal used general-purpose pin. Stop Clock. This signal output external clock generator turn processor memory clocks. This done prior entering state, well states. External System Management Interrupt. EXSMI# falling edge-triggered input 440MX indicating that external device requesting system enter mode. When enabled, falling edge EXSMI# results assertion SMI# processor. EXSMI# asynchronous input 440MX. However, when setup hold times only required asserted PCICLK. Once deasserted must remain deasserted least four PCICLKs allow edge detect logic PCIRST#. external pullup should placed this signal used; otherwise always guaranteed driven. EXSMI# cause SERR# enabled). This signal resides RESUME plane. EXSMI# used, this signal used GPIO. GPIO(10) PCISTP# PWRBTN# Lid. Input from button/switch. This signal used generate wake events interrupts. This signal muxed with GPIO(10). Stop Clock. This signal output external clock generator turn clock. Power Button. This signal causes SMI# request that system enter Sleep state. already Sleep state, causes wake event. PWRBTN# pressed four seconds, causes unconditional transition (power button override) state with only PWRBTN# available wake event. override occurs even system S1-S4 states. Power When asserted, PWROK indication 440MX that (Suspend-to-RAM) power plane PCICLK been stable least PWROK driven asynchronously. When PWROK negated, 440MX asserts PCIRST# RSTDRV. also resets processor. Ring Indicate. When asserted, this signal indicates that telephone ringing signal been received modem that 440MX should wake system accept data from call. This signal muxed with GPIO(12). Resume Well Reset. Used resetting Resume well. using power supply, then external circuit required. Otherwise, delay needed. Suspend Status. This signal asserted 440MX indicate that system will entering low-power state soon. used peripherals indication that they should isolate their outputs that going powered-off planes. Power plane control. Shuts power non-critical systems when (Power-On Suspend) (Power-On-Suspend with full Reset) state. This signal goes turn power. Power plane control. Shuts power non-critical systems when (Suspend-to-RAM) state. This signal goes turn power.
EXSMI# GPIO(24)
PWROK
GPIO(12)
RSMRST# SUS_STAT#
SUSA#
SUSB#
Intel® 82443MX100 PCIset
Signal SUSC#
Type
Description Power plane control. Shuts power non-critical systems when (Suspend-to-Disk) (Soft Off) states. This signal goes turn power. Suspend Clock. 32.768 KHz. This output signal from Real Time Clock generator circuit used Refresh clock 440MX. This signal always running, except Suspend-to-Disk Soft-Off states. During Reset: After Reset: Running Running
SUSCLK
During POS, STR: Running THRM# GPIO(8) Thermal Alarm. Active signal generated external hardware start Hardware clock throttling mode. This signal also generate SMI# SCI. This signal muxed with GPIO(8).
Table GPIO Signal Description
Signal Default Description Type General Purpose I/O. Handled system processor. Some GPIO signals muxed with other functions. (See Section 3.1.2 GPIO definition.) 3.3V only 3.3/5V (3.3V drive with tolerant). Table details.
GPIO[0,1,2,4,5, Input 6,7,8,9,10,11, 12,13,15,17,18, 20,21,22,23,24, 27,29,30] GPIO[3,14,16, 19,25,26,28]
Output General Purpose I/O. Handled system processor. Some GPIO signals muxed with other functions. (See Section 3.1.2 GPIO definition.) 3.3V only 3.3/5.0V (3.3-V drive with 5.0V tolerant). Table details.
NOTE:
This table specifies default direction pins selected GPIOs (GPIO_DIR Register Function Power Management Space).
Intel® 82443MX100 PCIset
Table X-bus Signal Description
Signal BIOSCS# DACK(3)# GPIO(28) Type Description BIOS Chip Select. This chip select driven active during read write accesses enabled BIOS memory ranges. Acknowledge. DACK output lines indicate that request service been granted 440MX. These lines should used decode slave device with IOR# IOW# line indicate selection. Upon PCIRST#, these lines inactive (high). DACK3# muxed with GPIO(28). Acknowledge. DACK output lines indicate that request service been granted 440MX. These lines should used decode slave device with IOR# IOW# line indicate selection. Upon PCIRST#, these lines inactive (high). Request. DREQ lines used request service from 440MX's controller. inactive active edges DREQ assumed asynchronous. request must remain active until appropriate DACKx# signal asserted. DREQ3 muxed with GPIO(27). DREQ(2:0) Request. DREQ lines used request service from 440MX's controller. inactive active edges DREQ assumed asynchronous. request must remain active until appropriate DACKx# signal asserted. Channel Ready. Resources X-bus deassert IOCHRDY indicate that additional time (wait states) required complete cycle. This signal normally high X-bus. Read. IOR# command X-bus slave device that slave drive data X-bus data (SD[15:0]). slave device must hold data valid until after IOR# negated. IOR# driven high upon PCIRST#. During Reset: After Reset: During POS: IOW# High-Z High High
DACK(2:0)#
DREQ(3) GPIO(27)
IOCHRDY
IOR#
Write. IOW# command X-bus slave device that slave latch data from X-bus data (SD[7:0]). IOW# driven high upon PCIRST#. During Reset: After Reset: During POS: High-Z High High
IRQ12 (Mouse IRQ)
Interrupt Request Mouse Interrupt. This provides mouse interrupt function. Config offset :bit X-bus Chip Select Register determines functionality IRQ12. When 4=0, standard interrupt function provided this tied X-bus connector. When 4=1, mouse interrupt function provided this tied IRQ12 output keyboard controller. When mouse interrupt function selected, low-to-high transition this signal latched 440MX generated processor IRQ12. internal IRQ12 interrupt will continue generated until Reset read access address (falling edge IOR#) detected. After Reset, this provides standard IRQ12 function input).
IRQ8# GPIO(6)
IRQ8# always active edge-triggered interrupt input (i.e., this interrupt cannot modified software). Upon PCIRST#, IRQ8# placed active-low edge-sensitive mode. This signal muxed with GPIO(6). During Reset: After Reset: During Power down: High-Z High-Z High-Z
IRQ[3:7]
Interrupt Requests [3:7]. signals provide both system board components X-bus devices with mechanism asynchronously interrupting processor. assertion mode these inputs depends
Intel® 82443MX100 PCIset
Signal
Type
Description programming ELCR Registers. When ELCR programmed low-to-high transition corresponding line recognized interrupt request. This "edge-triggered" mode 440MX default. When ELCR programmed high level corresponding line recognized interrupt request. This mode "level-triggered" mode. Keyboard Interrupt. This interrupt from keyboard controller. internal flip-flop placed between 8259 compatible with keyboard controllers which only pulse IRQ1 signal interrupt. low-to-high transition IRQ1 latched 440MX. Reads port clear internal flip flop, which time flip-flop armed another low-to-high transition. Keyboard Chip Select. KBCCS# asserted during Read Write accesses KBC. This signal muxed with GPIO(26). Microcontroller Chip Select. Dedicated chip select external microcontroller. registers microcontroller hard coded locations 66h. During Reset: After Reset: During POS: High High High
IRQ1 (KBC IRQ)
KBCCS# GPIO(26) MCCS# GPIO(25)
This signal muxed with GPIO(25). MEMR# Memory Read. MEMR# command memory slave that drive data onto X-bus data bus. During Reset: After Reset: During POS: MEMW# High-Z High High
Memory Write. MEMW# command memory slave that latch data from X-bus data bus. During Reset: After Reset: During POS: High-Z High High
PCS(1)# GPIO(16) PCS(0)# GPIO(19) RSTDRV
Programmable Chip Selects. This active chip select asserted cycles that range programmed into Device Monitors[9,10] Function space. assumed that peripheral selected this resides X-bus. NOTE: PCS(1:0)# pins included GPIO section (Section 3.1.2).
Reset Drive. 440MX asserts RSTDRV reset devices that reside Xbus. 440MX asserts this signal during hard Reset during power-up. RSTDRV asserted during power-up deasserted after PWROK driven active. RSTDRV also driven active minimum hard Reset been programmed Register. During Reset: After Reset: During POS: High
SA[18:0]
System Address Bus. These address lines define selection with granularity byte within 512KB section memory. accesses, only SA(15:0) used. 440MX always owns X-bus during slave legacy cycles. SA[18:0] unknown state upon PCIRST#. During cycle, address will driven prevent other devices from falsely decoding cycle. During Reset: After Reset: During POS: High-Z Undefined Last Address
SD[7:0] SYSCLK
System Data Bus. SD[7:0] provide 8-bit data path devices residing X-bus. 440MX three-states SD[7:0] during PCIRST#. X-Bus System Clock. SYSCLK reference clock X-bus. drives
Intel® 82443MX100 PCIset
Signal
Type
Description X-bus directly. SYSCLK generated dividing PCICLK four. During Reset: After Reset: During POS: Running Running
NOTE: This clock needed external Terminal Count. 440MX asserts slaves terminal count indicator. 440MX asserts after address been output, byte count expires with that transfer. When channels use, negated (low). Upon PCIRST#, inactive. During Reset: After Reset: During POS: ZEROWS# High High
Zero Wait States. slave asserts ZEROWS# after address command signals have been decoded indicate that current cycle shortened. 16-bit memory cycle reduced SYSCLKs. 8-bit memory cycle reduced three SYSCLKs. ZEROWS# effect during 16-bit cycles. IOCHRDY negated ZEROWS# asserted during same clock, then ZEROWS# ignored wait states added function IOCHRDY.
NOTES: X-bus signals 5.0V tolerant. Since 440MX does support Secondary Channel, IRQ15 longer available. However, SERIRQ interrupts steered generate Interrupt Interrupt controller.
3.1.2
Power Ground Pins
Table Core Power Pins
Name Description 3.3V Core. This power shut during some low-power states. Core.
Intel® 82443MX100 PCIset
Table Host Power Pins
Name GTLREF VTT[B:A] Description GTL+ Buffer Voltage Reference input mobile Celeron processor Pentium processor I/F. GTL+ termination voltage used early clamps.
Table Power Pins
Name VCCRTC Description Power Well. 2.0V-3.3V. This power expected shut unless battery removed drained, unless external used.
Table Power Pins
Name VCCUSB VSSUSB
NOTE:
Description Power Logic. 3.3V. This power will shut low-power states except Mechanical Off. Ground USB.
VCCSUS VCCUSB should both simultaneously.
Table Resume Power Pins
Name VCCSUS
NOTE:
Description 3.3V Resume Well. This power expected shut unless system unplugged main battery completely drained mobile system.
Note: VCCUSB should both simultaneously.
Table VREF Power Pins
Name REFVCC Description Reference tolerance inputs. This power shut some low-power states.
GPIO Definition
440MX includes GPIOs, twelve which located Resume Well. GPIOs located resume well have their reset control changed from PCIRST# RSMRST#, result retain their programming from S3-S5. They retain their values throughout after Suspend reset their default values. Well column Table lists GPIOs resume well that affected this change.
Intel® 82443MX100 PCIset
Table GPIO Pins Programmed Through Config. Dev.7,
GPIO Pins Well Input Output/OD Device Activity Monitor Default Function, Value PME#, GPIO(1) GPIO(2) GNTA# Resume Generic PIDE1 Resume IRQ8# (See GPIO default priority SERIRQ Core Resume Resume Resume Resume BATLOW# AUDIO SPKR SERIAL PCS1# Resume Resume PCS0# Resume ZEROWS# PIRQC# PIRQD# Resume EXSMI# PIRQC# PIRQD# EXSMI# MCCS# KBCCS# DREQ3 DACK3# PREQ3# PGNT3# SERIAL GENERIC CARDBUS CARDBUS LID, BATLOW#, RI#, AUDIO SPKR, SERIALA PCS1#, GENERIC PCS0#, CARDBUS ZEROWS#, PIRQC#, PIRQD#, EXSMI#, MCCS#, KBCCS#, DREQ3,0 DACK3#, THRM# SERIRQ GPIO(3) Generic PIDE1 GPIO(6)
GPIO(0)* GPIO(1)* GPIO(2) GPIO(3) GPIO(4)* GPIO(5) GPIO(6)
Resume Resume
PME# GPI(1) REQA#
GPIO(7) GPIO(8) GPIO(9)* GPIO(10)* GPIO(11)* GPIO(12)* GPIO(13) GPIO(14) GPIO(15) GPIO(16) GPIO(17)* GPIO(18)* GPIO(19) GPIO(20)* GPIO(21) GPIO(22) GPIO(23) GPIO(24)* GPIO(25) GPIO(26) GPIO(27) GPIO(28) GPIO(29) GPIO(30)
GPIO(7) THRM#,
NOTES: GPIO(x)* capable waking from Sleep states. GPIO[0, capable generating like GPIO(1). These GPIOs generate resume events. following GPIO registers: GPO_REG, GPIO_DIR GPIO_CNTRL (Device Function Space) Resume well reset RSMRST# (unlike those which resume well which reset
Intel® 82443MX100 PCIset
PCIRST#), result retain their programming from S3-S5. They retain their values throughout after Suspend reset their default values.
GPIO default priority follows: GPIO pins controlled GPIO_CNTRL (Muxed GPIO Control Register, Device Function Power Management System space) always default functional pins. These pins used GPIOs corresponding Muxed GPIO Control Register corresponding GPIO_DIR must appropriate value. following four GPIO pins controlled GSCR Register (General Signal Functional Configuration Register Device Function default GPI/GPO: REQA# GNTA# SERIRQ IRQ8# Priority between GPIO Control Registers (for example, Muxed GPIO Control GSCR Registers) GPIO Direction Register (GPIO_DIR Register) defined follows: When functional signal selected these GPIO Control Registers values programmed GPIO_DIR Register ignored. GPIO(14) with three functions (SPKR, Device Monitor, GPIO), priority follows: will used SPKR GPIO_CNTRL Register (Muxed GPIO Control Register, Device Function space) programmed Muxed GPIO Control Register programmed then used Device monitor when GPI_EN_DEV5 (Muxed GPIO Control Register, Device Function set. both Muxed GPIO Control Register GPI_EN_DEV5 then used GPIO (GPIO_DIR Register programs either input output). signals listed Table resume system when used GPIOs. They resume system when programmed functional pins (for example, PME#, LID, BATLOW#, EXSMI#, RI#). GPIO(6)/IRQ8# resume well will wake system from S3/S4/S5 states.
Table System Resume with GPIO Signals Programmed Functional Pins
GPIO GPIO(0) GPIO(10) GPIO(11) GPIO(12) GPIO(24) Functional PME# BATLOW# EXSMI#
Power Rail Overview
Figure illustrates power rails entire 440MX platform.
Intel® 82443MX100 PCIset
Figure Platform Power Rails
Mobile Celeron Processor Pentium Processor
HCLKIN (2.5V) 66/100 MHz, Processor (incl. Reset) Side Band Signals (2.5V)
Clock Gen. CKM66
PCLKIN (3.3V) 3.3V 66/100 MHz, (3.3V)
System Memory (SDRAM) System Memory DIMM#0 (SDRAM) DIMM#1
IOCLK
(3.3V/5V)
Panel
Graphic Controller
3.3V/5V GPIO 3.3/5V X-bus (8-bit) 3.3V
82440MX
3.3V/5V
CardBus Controller
Drive ports)
AC'97 Codec
3.3V
3.3V/5V
Power Management
3.3V
SMBus
Power-up State Initial Value
signal states immediately after Reset (PCIRST#) during POS/STR (Power-On-Suspend Suspend-To-RAM states) defined using following headings:
State during Reset State immediately following Reset (PCIRST#) State during POS/STR Signal isolated during POS/STR
Intel® 82443MX100 PCIset
signal states defined using following nomenclature:
Three-stated Driven Driven High Driven active logic state Undefined
Power-On-Reset Values
Table lists input/output values before after Reset, POS, STR, STD, Mechanical Off. pu/pd column indicates whether internal external pull-up pull-down resistor required. Internal pull-up/pull-down resistors used default strapping values. internal resistors disabled after PCIRST# goes inactive.
Intel® 82443MX100 PCIset
Table Power-On-Reset Values Signal Group
Signal Group
Host
Signal
A20GATE
Power Plane
Main Main
Buffer External During After Type Pu/Pd Reset Reset
3.3/5V Input Note(7) Input Hi-Z
During
Input
During During Mech.
Hi-Z Pwrdn Pwrdn Pwrdn Pwrdn
Interface A20M# Signals(1) ADS# BNR# BPRI# BREQ0# CPURST# DBSY# DEFER# DRDY# FERR# HA[31:3]# HD[63:0]# HITM# HLOCK# (4),(5) HREQ[4:0]# HTRDY# IGNNE# INIT# INTR RCIN# RS[2:0]# SMI# STPCLK# Interface Signals PDA[2:0] PDCS1# PDCS3# PDD[15: PDDAK# PDDRQ PDIOR#/ PDWSTB/ PRDMARDY# PDIOW#/ PDSTOP PIORDY/
Last Hi-Z A20GATE Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Hi-Z High High Hi-Z High Input High Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main
GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ 2.5/3V GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ 3.3/5V GTL+ 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V
Hi-Z Hi-Z Hi-Z HiZ/Low Hi-Z Hi-Z Hi-Z Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note(7) Hi-Z Note(7) Note(7) Input Hi-Z Hi-Z Hi-Z High High Hi-Z High Input High
Hi-Z Hi-Z Hi-Z HiZ/Low Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Hi-Z Hi-Z Undefined High High Input High Input High
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Main Main
3.3/5V 3.3/5V
High Input
High Input
High Input
Hi-Z Hi-Z
Pwrdn Pwrdn
Pwrdn Pwrdn
Intel® 82443MX100 PCIset
Signal Group
Signal
PDRSTB/ PWDMARDY#
Power Plane
Buffer External During After Type Pu/Pd Reset Reset
During
During During Mech.
Test Signals
SPKR GPIO[14] TEST#
Main Resume Main Main Main Main Main Main
3.3V 3.3V 3.3/5V 3.3/5V 3.3V 3.3/5V 3.3/5V 3.3/5V
Input Hi-Z Hi-Z High/ GPIO State Hi-Z Hi-Z
Input Driven Driven Hi-Z Hi-Z High/ GPIO State Hi-Z Driven High High
Last Input Hi-Z Hi-Z High/ GPIO State Hi-Z High Hi-Z
Hi-Z Input Hi-Z Hi-Z Hi-Z
Pwrdn Input Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Interface Signals
AD[31:0] C/BE[3:0]# CLKRUN# DEVSEL# FRAME# GNTA# GPIO(3) IRDY# PCIRST# PGNT[3]# GPIO(30) PGNT[2:0]# PIRQ[A-B]# PIRQ[C-D]# GPIO(22,23) PLOCK# PME# GPIO(0) PREQ[3]# GPIO(29) PREQ[2:0]# REQA# GPIO(2) SERR# STOP# TRDY#
Main Main Main Main
3.3/5V 3.3/5V 3.3/5V 3.3/5V
Hi-Z Hi-Z
Pwrdn Pwrdn Pwrdn Pwrdn
Pwrdn Pwrdn Pwrdn Pwrdn
Main Main
3.3/5V 3.3/5V 3.3/5V
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Driven Hi-Z
Hi-Z Hi-Z Hi-Z Driven Hi-Z
Pwrdn Pwrdn Pwrdn Driven Pwrdn
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Resume Main
3.3V 3.3/5V
Hi-Z
Main Main Main Main Main Resume Resume Main Main Main
3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3/5V
None None None None
Input Hi-Z Hi-Z Hi-Z
Input Hi-Z Hi-Z Hi-Z
Input Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
AC_BIT_CLK Signals AC_RST# AC_SDATA_ IN[1:0] AC_SDATA_ AC_SYNC Interrupt Signal Signals Clocks/ Reset/ PLL/ SERIRQ/ GPIO[7] RTCX[2:1] CLK48
Running Running Input GPIO State Special Input Input Input GPIO State Special Input Input High Driven Hi-Z/ GPIO State Special Input Input
Main Main
3.3V 3.3/5V 3.3/5V
Special
Special Pwrdn Pwrdn
Special Pwrdn Pwrdn
Intel® 82443MX100 PCIset
Signal Group
Misc. Signals Signals
Signal
PCICLK USBPRT0[+:-] USBPRT1[+:-] OC[1:0]#
Power Plane
Main USB/ Resume USB/ Resume Resume Resume Resume Resume
Buffer External During After Type Pu/Pd Reset Reset
3.3/5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V No(10)
During
During During Mech.
Hi-Z Hi-Z Input Hi-Z Hi-Z Input/ GPIO State Input/ GPIO State Input/ GPIO State Input Input Input/ GPIO State Input High Pwrdn Hi-Z Hi-Z Input Hi-Z Hi-Z Input GPIO State Pwrdn Input/ GPIO State Input/ GPIO State Pwrdn Input Input Input/ GPIO State Input Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Running Running Hi-Z Hi-Z Input Hi-Z Hi-Z Input Hi-Z Hi-Z Input Hi-Z Hi-Z Input Hi-Z Hi-Z Input Hi-Z Hi-Z Input/ GPIO State Input/ GPIO State Input/ GPIO State Input Input Input/ GPIO State Input High High
SMBus Signals Power Mgmt Signals
SMBCLK SMBDATA BATLOW# GPIO[11] CPUSTP# EXSMI#/ GPIO[24] GPIO[10] PCISTP# PWRBTN# PWROK GPIO[12] RSMRST# SUS_STAT# SUSA# SUSB# SUSC# SUSCLK THRM# GPIO[8]
Main Resume
3.3/5V 3.3V
No(10)
High Input
High Input
Pwrdn Pwrdn
Resume
3.3V
No(10)
Input
Input
Pwrdn
Main Resume Resume
3.3/5V 3.3V 3.3V 3.3V
No(10)
High Input Input Input
High Input Input Input
Pwrdn Pwrdn Input Pwrdn
Resume Resume Resume Resume Resume Main
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
No(10)
Input High High High
Input High High High High
Input Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Running Running Running Input Input Input/ GPIO State High High
Running Hi-Z Pwrdn
X-bus Signals
BIOSCS# DACK[3]# GPIO(28) DACK[2:0]# DREQ[3] GPIO(27) DREQ[2:0] IOCHRDY IOR# IOW#
Main Main
3.3/5V 3.3/5V
High High
High High
Hi-Z Hi-Z
Pwrdn Pwrdn
Pwrdn Pwrdn
Main
3.3/5V
Input
Input
Input
Hi-Z
Pwrdn
Pwrdn
Main Main Main
3.3/5V 3.3/5V 3.3/5V 3.3/5V
Hi-Z Hi-Z Hi-Z Input
Hi-Z Hi-Z Hi-Z Input
Hi-Z High High Input
Hi-Z Hi-Z Hi-Z Hi-Z
Pwrdn Pwrdn Pwrdn Pwrdn
Pwrdn Pwrdn Pwrdn Pwrdn
IRQ[1] IRQ[3:7] Main IRQ[12] IRQ8#/ GPIO[6] Resume
3.3V
Input
Input/ GPIO
Input/ GPIO
Input/ GPIO
Input/ GPIO
Pwrdn
Intel® 82443MX100 PCIset
Signal Group
Signal
KBCCS# GPIO(26) MCCS# GPIO(25) MEMR# MEMW# PCS[1:0]# GPIO(16,19) RSTDRV SA[18:0] SD[7:0] SYSCLK ZEROWS# GPIO(21)
Power Plane
Main Main Main Main Main Main Main Main Main Main Main Resume Main
Buffer External During After Type Pu/Pd Reset Reset
state 3.3/5V 3.3V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3/5V 3.3V 3.3/5V No(10) No(10) High High Hi-Z Hi-Z High High Undefined Hi-Z High High Hi-Z Hi-Z High Undefined Undefined
During
State High High High High Last Last Last
During During Mech.
state Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z GPIO State Hi-Z state Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn GPIO State Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Running Running High Input Input/ Output Input/ Output Input Input/ Output Input/ Output Input GPIO State GPIO State
General Purpose Input Output Signals
GPIO[1,4,9,17, 18,20] GPIO[2,3,5,7, 13,14,15,16, 19,21,22,23, 25,26,27,28, 29,30]
NOTES: host interface signals have their clamps disabled Suspend, include GTL+ termination, isolated during POS/STR. CPURST# always active when PCIRST# asserted. cold Reset Resume from STR, CPURST# deasserted after PCIRST# deassertion. Resume from which CPURST# option enabled), CPURST# deasserted after SUS_STAT# deassertion. When PCIRST# asserted, enable signal buffer deasserted. Therefore, output floated next clock. HA[7]# HA[15]# buffers enabled when CPURST# active strap values from lines driven out. These signals driven until clocks after CPURST# deassertion. enables these buffers deasserted combinatorially from PCIRST#. Therefore, buffer floated next clock. This signal driven since input only (functionally). BREQ0# driven clocks before CPURST# deassertion remains clocks after CPURST# deassertion. otherwise never driven 440MX. During Suspend, BREQ0#, rest host signals, driven input buffer isolated. During Reset, A20M#, IGNNE#, NMI, INTR values 440MX (for fraction ratio). Upon RSMRST#, Resume Well GPIOs revert back their functional state. Upon PCIRST#, Resume Well GPIOs maintain their previous state. Link signals have internal pullups/pulldowns. unused input should pulled inactive.
Intel® 82443MX100 PCIset
Table DRAM Interface Signals
Name Reset/ Cold Reset After Reset Entering POS/STR State During STD/ Internal POS/STR Mech. pu/pd (optional Reset) Pwrdn Clamp Disabled Suspend clamps Notes
CKE[3:0]
used Self when enter remains during used Self when enter
CS[3:0]#
Undefine
Self
Pwrdn
clamps
DQM[7:0] MA[10]
Pwrdn Pwrdn
clamps clamps Used straps, during Reset Suspend. Used straps, during Reset Suspend. Used straps, during Reset Suspend.
MA[11]#
Pwrdn
clamps
MA[13], MA[12]#, MA[9:0]# MD[63:0]
Pwrdn
clamps
Undefine
Pwrdn
SCAS#
Pwrdn
clamps
SCAS# used Self when enter SRAS# used Self when enter
SRAS#
Pwrdn
clamps
Pwrdn
clamps
Intel® 82443MX100 PCIset
Table Miscellaneous Signals
Name During Cold Reset Pulldown enabled Before After State During Reset Reset POS/STR Isolate Suspend Pu/pd Notes
DCLK (input)
During Suspend: Driven buffer Normal config, this buffer powered down thus resistor disabled. avoid floating, pulldown used. Also connected during cold Reset.
DCLKO (output)
buffer remains powered during Normal config. There buffer config.
HCLKIN Pulldown (input) enabled
100K
Weak pulldown keeps (when synth. powered down) while leaks very little current POS. Resistor disabled Normal operation. Also connected during cold Reset.
PCICLK Pulldown (input) enabled
100K
Weak pulldown keeps (when synth. powered down) while leaks very little current POS. Resistor disabled Normal operation. Also connected during cold Reset.
PCIRST Pulldown enabled
NOTE:
Pulldow nenable
100K
Internal pulldown connected during Suspend cold Reset.
miscellaneous signals CMOS buffers.
5.0-V Tolerance: Although 440MX never drives output above 3.3V, many buffers input buffers tolerate external signals driven 5.0V. following signals must 5.0-V tolerant: inputs I/Os inputs I/Os SERIRQ IRQ14
Signals located Resume well 3.3-V tolerant only.
Power-up/Reset Strap Options
Table lists power-up options that loaded into 440MX during system Reset. 440MX required float signals connected straps during system Reset (PCIRST# active) keep them floated minimum four host clocks after Reset sequence. first column lists signal that sampled obtain strapping option. second column shows register into which strapping option loaded. third column describes functionality that strapping selects. Note that signals used select power-up strap options
Intel® 82443MX100 PCIset
connected either internal pull-down pull-up resistors approximately ohms. That selects default mode signal during Reset. enable different modes, external pullups pulldowns approximately ohms connected particular signals. These pull-up pull-down resistors should connected 3.3-V power supply. GTL+ signals connected through normal pullups. Processor straps controlled 440MX (for example, A15#) driven active least clocks prior active-to-inactive edge CPURST# driven inactive four clocks after active-to-inactive edge CPURST#.
Table Power-up Options During Reset
Signal HA[15]# Register Name/Bit None Description Quick Start Select. value HA[15]# sampled rising edge CPURST# reflects whether Quick Start Stop Clock mode enabled processor. In-order Queue Depth Status. value HA[7]# sampled rising edge CPURST# reflects whether IOQD maximum allowable processor bus. maximum processor In-order Queue depth selected, 440MX will throttle asserting BNR# appropriately processor protocol.
HA[7]#
None
MA12#
NBXCFG[13] Host Frequency Select: MA12# strapped host frequency MHz. MA12# strapped host frequency MHz. MA12# internally pulled-down provide default host frequency MHz. NBXCFG[2] In-Order Queue Depth Enable. MA11# strapped during rising edge PCIRST#, then 440MX will drive HA[7]# during CPURST# deassertion. This forces processor configured non-pipelined operation. MA11# strapped (default), then 440MX does drive HA[7]# during Reset, HA[7]# sampled default non-driven state (for example, pulled GTL+ termination concerned) then maximum allowable queue depth processor protocol selected (for example, Note that this case external logic supplied used drive HA[7]# select proper mode. maximum theoretical queue depth (i.e., selected keeping HA[7]# deasserted during Reset, 440MX uses BNR# mechanism throttle processor maximum four pipelined transactions. MA[11]# IOQD max.
MA11#
MA10
PMCR[3]
Quick Start Select. value this Reset determines which stop clock mode used. MA10 during rising edge PCIRST#, then 440MX drives HA[15]# during CPURST# deassertion. This configures processor Quick Start mode. Note: default mode should active state signal used strapping. This sets processor Quick Start mode 440MX drives HA[15]# during CPURST# deassertion. This signal internally tied 50-Kohm pullup.
MA8#
None
HOST_HFV (High Frequency VCO). internal pulldown minimum used select HOST_HFV default, indicating Host slower speed. external pullup used later decision made select fast Host speed.
Reset
440MX integrates external logic previously required 443BX determining processor fraction frequency multiplier. During Power-On-Reset, pull-up/pull-down Datasheet
Intel® 82443MX100 PCIset
status four pins MA[13], used internally drive A20M#, IGNNE#, NMI, INTR speed strapping processor. After Power-On-Reset, A20M#, IGNNE#, NMI, INTR restored normal functionality. assignment shown follows: MA[13] MA[9]# MA[7]# MA[1]# -INTR -IGNNE# -A20M#
Table shows mobile Celeron processor mobile Pentium processor frequency ratios these assignments.
Table Mobile Celeron Processor/Mobile Pentium Processor Frequency Ratios
Core/Bus Ratio 2/11 (366 MHz) (333 MHz) (300 MHz) (266 MHz) (233 MHz) Safe Ratio (Default)
NOTE:
INTR
IGNNE#
A20M#
MA[13], signals have internal pulldowns select default, safe front-side-bus ratio which processor dependant. 440MX enables these internal pulldowns MA[13], pins only during Reset.
Note:
440MX does drive strapping signals during Reset sequence. Proper strapping must used define logical values these signals. external resistor override default value provided internal pull-up pull-down resistor.
Intel® 82443MX100 PCIset
Power Planes
Overview
Table provides overview four main power planes 440MX.
Table Power Planes
Plane I/O, Core Voltage This plane powered main battery. Assumed 3.3V. When system state, this plane assumed shut. this plane still powered. This plane powered either main battery power. This plane powered battery. When other power available (from main battery), external diode coupling provides power reduce battery drainage. This plane assumed operate from 3.3V down 2.0V.
Resume
Power Plane
Table lists power plane signals. These signals must powered maintain system Soft state.
Table Well Signals
Signal PWROK RSMRST# RTCX1, Usage Input indicates that power plane Used isolate RESUME wells from MAIN well. Input indicates that Resume well should reset that well should isolate from Resume Well. Connections 32.768-KHz Crystal.
Resume Power Plane
Table lists signals that reside Resume well. These signals must powered maintain system states, except Mechanical state.
Intel® 82443MX100 PCIset
Table Resume Well Signals
Signal AC_RST# AC_SDATA_IN (1:0) BATLOW# EXSMI# GPIO[0,1,4,6,9,10, 11,12,17,18,20, IRQ8# OC[1:0]# PME# PWRBTN# SMBCLK SMBDATA SUS_STAT# SUSA# SUSB# SUSC# SUSCLK TEST# USBPRT[1:0]+, USBPRT[1:0]If enabled GPIO(12) PME# enabled GPIO(0) GPIO(6) enabled GPIO(10) BATLOW# enabled GPIO(12) EXSMI# enabled (via Muxed GPIO Register Configuration Device Function Usage
Intel® 82443MX100 PCIset
System Address
Addressable Memory Support
mobile Celeron processor system based 440MX supports addressable memory space 64K+3 bytes addressable space. (The mobile Celeron processor addressability 64K+3 bytes.) programmable memory address space under 1-MB region which divided into regions individually controlled with programmable attributes such Disable, Read/Write, Write Only, Read Only. Attribute programming described Programmable Attribute Registers configuration space. This section focuses memory space partitioned these separate memory regions used. address space explained this section. Although Pentium processor family supports addressing memory ranges larger than assumed that software running 440MX system will never address physical memory above (see Figure
Note:
Memory
internal between North Bridge/Cluster South Bridge/Cluster number cycles from North Bridge/Cluster external that appear internal either positively subtractively decoded South Bridge/Cluster, depending mode selected. cycles from South Bridge/Cluster external that appear internal positively decoded North Bridge/Cluster claimed only there address match. Cycles between North South Bridge/Cluster also broadcast external bus. Thus external bus, which interfaces other devices, logically same internal bus, example Table summarizes memory address space supported. attributes refer Write Enable Read Enable.
Intel® 82443MX100 PCIset
Figure Memory Address
82440MX Memory
Memory Range
0FFFFFh 0F0000h 0EFFFFh 0E0000h 0DFFFFh
Upper BIOS Area (64KB)
Lower BIOS 960KB Arrea (64KB) 896KB
256M (max. TOM)
2xpansion Card BIOS Buffer Area (128KB)
Optional Ext. Mem. Hole
768KB
0C0000h 0BFFFFh Standard Video Memory (SMM Memory) 128KB Optionally Optional Fixed 640KB Memory Hole (128KB) Area (512KB) 512KB
Main DRAM Range 640K 512K
0A0000h 09FFFFh 080000h 07FFFFh 000000h
Compatibility Memory
82440MX Chipset Memory Address
Intel® 82443MX100 PCIset
Table Memory Segment Attributes
Memory Range (Addresses Hex) 00000000 0007FFFF 00080000 0009FFFF 000A0000 000BFFFF Attributes None None None Target Always mapped main memory Configurable external memory main memory Dependency/Comments 512K Region 512K 640K Region
Mapped external memory Video Buffer Normal mode; space mode. Normal mode; mapped main memory mode External memory BIOS add-in card add-on BIOS. WE/RE attributes Registers control whether this range directed Main Memory (only), gets forwarded BIOS. WE/RE attributes Registers control whether this range directed Main Memory (only), gets forwarded BIOS. Registers, maximum
000C0000 000DFFFF 000E0000 000EFFFF
WE/RE WE/RE
000F0000 000FFFFF
WE/RE
BIOS
00100000 (Top Memory) (TOM FEBFFFFF FEC00000 FECFFFFF FED00000 FFBFFFFF FFC00000 FFFEFFFF
None None None WE/RE WE/RE
Main memory External memory Reserved External memory BIOS memory
other systems, this range used APICs.
Destination based enable bits BIOS Decode Enable Register offset E3h, device function Enable this range BIOS Decode Enable Register offset E3h, device function hardwired This range always targeted BIOS.
FFFF0000 FFFFFFFF
WE/RE
BIOS
5.2.1
Compatibility Area
Table shows compatibility memory area from (0000 0000h 0010 0000h) divided into address regions.
Intel® 82443MX100 PCIset
Table Compatibility Memory Area
Address Range 16KB sections (total sections) 16KB sections (total sections) Memory (BIOS Area) Area Area Optional Fixed Memory Hole Video Buffer Area Expansion Area Extended System BIOS Area System BIOS Area Memory Area
There memory segments compatibility area. Thirteen memory ranges enabled disabled independently both read write cycles. segment (512K-640K) mapped either main DRAM PCI. This section describes various memory regions. 5.2.1.1 Area (00000h-9FFFh; area size further divided into parts. 512-KB area 7FFFFh always mapped main memory, while 128-KB address range from 080000 09FFFFh mapped external main DRAM. default this range mapped main memory declared main memory hole (accesses forwarded external PCI) FDHC Configuration Register. 5.2.1.2 Video Buffer Area (A0000h-BFFFFh; 128-Kbyte graphics adapter memory region mapped legacy video device external (typically controller). attribute bits control this area. Processor-initiated cycles this region always forwarded external termination. This region also default region space. SMRAM Control Register controls accesses this space handled. 5.2.1.3 Expansion Area (C0000h-DFFFFh; This 128-Kbyte expansion region divided into eight 16-Kbyte segments. Each segment assigned four Read/Write states main memory: read-only, write-only, read/write, disabled. Typically, these blocks reside external memory therefore given attribute "disabled" main memory. Memory that disabled remapped. 5.2.1.4 Extended System BIOS Area (E0000h-EFFFFh; This 64-Kbyte area divided into four 16-Kbyte segments. Each segment assigned independent read write attributes that reads writes independently mapped main DRAM BIOS. Typically, this area used ROM. Memory segments that disabled remapped elsewhere. 5.2.1.5 System BIOS Area (F0000h-FFFFFh; This area single 64-Kbyte segment. This segment assigned read write attributes. default (after Reset) Read/Write disabled main memory that cycles forwarded
Intel® 82443MX100 PCIset
X-bus (ROM BIOS). manipulating Read/Write attributes, X-bus-based BIOS "shadowed" into main DRAM. When disabled, this segment remapped.
5.2.2
Extended Memory Area
This memory area covers 0010 0000h FFFF FFFFh GB-1) address range divided into following regions: Main DRAM memory from main Memory; maximum 128/256 using 16-Mb, 64-Mb, 128-Mb DRAM technology. memory space from main Memory which includes following specific ranges: High BIOS area from
5.2.2.1
Main DRAM Address Range (0010_0000h Main Memory) address range from main memory mapped main DRAM address range. accesses addresses within this range will forwarded main DRAM memory unless hole this range created using fixed hole controlled FDHC Register. Accesses within this hole forwarded external bus. range physical DRAM memory disabled opening hole remapped Memory.
5.2.2.2
Extended SMRAM Address Range (Top Main Memory TSEG_SZ Main Memory) extended SMRAM space defined address range just below memory. size SMRAM space determined TSEG_SZ value ESMRAMC Register. When extended SMRAM space enabled, non-SMM processor accesses PCI-initiated accesses this range terminated external bus. When enabled amount memory available system equal amount physical DRAM minus value indicated TSEG_SZ bits.
5.2.2.3
Memory Address Range (Top Main Memory address range from main DRAM (top physical memory space) normally mapped external bus, with some exceptions mapped X-bus. sub-ranges within Memory address range defined High BIOS Address Range.
5.2.2.4
High BIOS Area (FFC0_0000h FFFF_FFFFh) Extended Memory Region reserved System BIOS (High BIOS), extended BIOS devices, alias system BIOS. processor begins execution from High BIOS after Reset. Except which always mapped X-bus, this region mapped either X-bus external bus. upper subset this region aliases 256-KB area just below actual address space
Intel® 82443MX100 PCIset
required BIOS less than minimum processor MTRR range this region full must considered.
System Management Mode (SMM) Memory Range
Main memory used System Management (SMRAM) enabling System Management Mode. SMRAM options supported: Compatible SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). System Management (SMRAM) space provides memory area that available handlers code data storage. This memory resource normally hidden from system that processor immediate access this memory space upon entry SMM. Only processor access space. Three options SMRAM locations provided: Below 1-MB option that supports compatible handlers. Above 1-MB option that allows handlers execute with write-back cacheable SMRAM. Optional larger write-back cacheable T_SEG area, from size, above Mbyte. This area located just below main memory. Both above 1-Mbyte solutions require changes compatible SMRAM handler code properly execute above Mbyte.
Memory Shadowing
block memory that designated read-only write-only "shadowed" into main memory. Typically this done allow code execute more rapidly main DRAM. achieve this, designated read-only during copy process while same time DRAM designated write-only. After copying, DRAM designated read-only that shadowed. Processor transactions routed accordingly.
Decode Rules Cross-Bridge Address Mapping
address described above, with exception SMRAM, applies globally accesses arriving either host external bus. Accesses initiated from other peripheral buses other than host external (e.g., USB, IDE) only allowed access main memory, must attempt access other memory space behind 440MX.
5.5.1
Interface Memory Decode Rules
memory read write accesses accepted from external that targeted main DRAM. accesses that fall elsewhere within memory range will claimed. This implies that external devices cannot access BIOS memory X-bus.
5.5.2
Legacy Range
legacy memory range A0000h-BFFFFh always mapped external Normal mode. SMM, mapped main memory.)
Intel® 82443MX100 PCIset
Address Space
processor-initiated accesses, cycles internally terminated, cycles generated internal bus. cycles generated internal types: configuration cycles cycles purpose converting cycles configuration cycles, internal registers used. These registers located processor space, Configuration Address Register (CONFIG_ADDRESS) Configuration Data Register (CONFIG_DATA). These registers used implement configuration space access mechanism described configuration section. Configuration Register accessed space internal 440MX North Bridge/Cluster, cycle will generated internal bus.) Configuration Register accessed internal 440MX North Bridge/Cluster, cycle will generated internal also broadcast external bus. Cycles other than those converted configuration cycles sent internal bus, broadcasted cycles external bus, positively subtractively decoded 440MX South Bridge/Cluster regions residing behind 440MX South Bridge/Cluster. processor allows 64K+3 bytes addressable space addressed. Processor addresses propagated without translation onto destination except I/O-toconfiguration space conversions. This provides addressability 64K+3 byte locations. Note that upper three locations accessed only during address wrap-around when processor A16# address signal asserted. A16# asserted processor whenever access made 4-byte range starting from address 0FFFDh, 0FFFEh, 0FFFFh. A16# also asserted when access made 2-byte range starting from address 0FFFFh. write cycles posted. divided into fixed variable ranges. Fixed ranges cannot moved, some cases disabled. Variable ranges moved also disabled.
5.6.1
Fixed Address Ranges
Table shows Fixed decode ranges positively decoded 440MX South Bridge/Cluster. master targets fixed ranges, they positively decoded Medium speed. Address ranges that listed marked Reserved positively decoded (unless assigned variable ranges) subtractively decoded subtractive decode mode enabled.
Intel® 82443MX100 PCIset
Table Fixed Ranges Decoded 440MX
Address 000h 001h 002h 003h 004h 005h 006h 007h 008h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 020h 010h 011h 012h 013h 014h 015h 016h 017h 018h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh Alias Register Name/Function Master Access CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI Forwarded ISA/EIO? Never Never Never Never Never Never Never Never Never Never Never Never Never Never Never Never Never Never Default Value XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 000000X 000001X 000000X Reg. Type
Base/Current Address (Ch0) Base/Current Byte/Word (Ch0) Base/Current Address (Ch1) Base/Current Byte/Word (Ch1) Base/Current Address (Ch2) Base/Current Byte/Word (Ch2) Base/Current Address (Ch3) Base/Current Byte/Word (Ch3) Command Register 0-3) Status Register 0-3) Request Register 0-3) Mask Register Write Single Mask 0-3) Channel Mode Register 0-3) Clear Byte Pointer 0-3)
Master Clear Register. CPU/PCI Clear Mask Register 0-3) CPU/PCI Write Mask 0-3) CPU/PCI CPU/PCI
024, 028, 02C, INT1 Control Register 030, 034, 038, 025, 029, 02D, INT1 Mask Registers 031, 035, 039, 050h 051h 052h 053h 062h 062h 062h
021h
CPU/PCI
Never
040h 041h 042h 043h 060h 060h 060h 061h 62h, 064h
Timer/Counter Counter Count CPU/PCI Timer/Counter Counter Count CPU/PCI Timer/Counter Counter Count CPU/PCI Timer/Counter Cmnd Mode Input Buffer Output Buffer Reset X-Bus IRQ12 IRQ1 CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI
Never Never Never Never enabled enabled Never Never enabled enabled
063, 065, 067h Status Control Register Microcontroller Chip Select Status Register
Intel® 82443MX100 PCIset
Address 064h 070h
Alias
Register Name/Function
Master Access CPU/PCI CPU/PCI
Forwarded ISA/EIO? enabled disabled disabled disabled enabled enabled Writes forwarded Alias writes forwarded enabled
Default Value
Reg. Type
Command Register
072, 074, 076h Mask (bit
070h
072, 074, 076h Index Register (Not aliased 072h extended enabled) 073, 075, 077h Data Register (Not aliased extended enabled) 090h Extended Index Register Extended Data Register
CPU/PCI
071h
CPU/PCI
072h 073h 080h
CPU/PCI CPU/PCI
DMA1 Page Register (RESERVED) CPU/PCI
081h 082h 083h 084h
091h 093h 094h
DMA1 Memory Page (Ch2) DMA1 Memory Page (Ch3) DMA1 Memory Page (Ch1)
CPU/PCI CPU/PCI CPU/PCI
Never Never Never Writes forwarded Alias writes forwarded enabled
DMA1 Page Register (RESERVED) CPU/PCI
085h
095h
DMA1 Page Register (RESERVED) CPU/PCI
Writes forwarded Alias writes forwarded enabled
086h
096h
DMA1 Page Register (RESERVED) CPU/PCI
Writes forwarded Alias writes forwarded enabled
087h 088h
097h 098h
DMA1 Memory Page Register CPU/PCI (Ch0) DMA1 Page Register (RESERVED) CPU/PCI
Never Writes forwarded Alias writes forwarded enabled
089h 08Ah 08Bh 08Ch
099h 09Ah 09Bh 09Ch
DMA1 Memory Page (Ch6) DMA1 Memory Page (Ch7) DMA1 Memory Page (Ch5)
CPU/PCI CPU/PCI CPU/PCI
Never Never Never Writes forwarded
DMA1 Page Register (RESERVED) CPU/PCI
Intel® 82443MX100 PCIset
Address
Alias
Register Name/Function
Master Access
Forwarded ISA/EIO? Alias writes forwarded enabled
Default Value
Reg. Type
08Dh 08Eh
09Dh 09Eh
DMA1 Page Register (RESERVED) CPU/PCI DMA1 Page Register (RESERVED) CPU/PCI
Writes forwarded Writes forwarded Alias writes forwarded enabled
08Fh 0A0h
09Fh 0A4, 0A8, 0AC, 0B0, 0B4, 0B8, 0BCh 0A5, 0A9, 0AD, 0B1, 0B5, 0B9, 0BDh 0C1h 0C3h 0C5h 0C7h 0C9h 0CBh 0CDh 0CFh 0D1h 0D1h 0D3h 0D5h 0D7h 0D9h 0DBh
DMA1 Page Register Refresh Fast Init Register INT2 Control Register
CPU/PCI CPU/PCI CPU/PCI
Never Never Never
0A1h
INT2 Mask Registers
CPU/PCI
Never
0B2h 0B3h 0C0h 0C2h 0C4h 0C6h 0C8h 0CAh 0CCh 0CEh 0D0h 0D0h 0D2h 0D4h 0D6h 0D8h 0DAh
Advanced Power Management Control Port Advanced Power Management Status Port
CPU/PCI CPU/PCI
Never Never Never Never Never Never Never Never Never Never Never Never Never Never Never Never Never
XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 000000X 000001X 000000X
DMA2 Base/Current Address (Ch4) CPU/PCI DMA2 Base/Current Byte/Word CPU/PCI
DMA2 Base/Current Address (Ch5) CPU/PCI DMA2 Base/Current Byte/Word CPU/PCI
DMA2 Base/Current Address (Ch6) CPU/PCI DMA2 Base/Current Byte/Word DMA2 Base/Current Address DMA2 Base/Current Byte/Word CPU/PCI CPU/PCI CPU/PCI
DMA2 Command Register 4-7) CPU/PCI DMA2 Status Register 4-7) DMA2 Request Register 4-7) DMA2 Write Single Mask 4-7) CPU/PCI CPU/PCI CPU/PCI
DMA2 Channel Mode 4-7) CPU/PCI DMA2 Clear Byte Pointer 4-7) DMA2 Master Clear Reg. 4-7) CPU/PCI CPU/PCI
Intel® 82443MX100 PCIset
Address 0DCh 0DEh 0F0h 170h 177h 1F0h 1F7h 200h207h 279h 376h
Alias
Register Name/Function
Master Access CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI CPU/PCI
Forwarded ISA/EIO? Never Never Always Never Never enabled enabled Never enabled Never Never Never
Default Value
Reg. Type
0DDh 0DFh
DMA2 Clear Mask Register DMA2 Write Mask 4-7) Coprocessor Error Register Secondary Command Block (Note Primary Command Block Game Port Address Secondary Control Block AdLIB Synthesis Primary Control Block Edge/Level Triggered (INT CTRL Edge/Level Triggered (INT CTRL Address Reset Control Register
388-38Bh 3F6h 4D0h 4D1h A79h CF9h
NOTE:
CPU/PCI
enabled Never
Note: 440MX claims secondary addresses even though secondary channel physically available.
5.6.2
Variable Decode Ranges
Table shows Variable Decode Ranges, which using Base Address Registers (BARs) other configuration bits various configuration spaces. software (PCI ACPI) adjust these values. When detected cycle positively decoded, X-bus device response, then cycle forwarded X-bus I/F.
Warning:
Variable Ranges should conflict with Fixed Ranges. Unpredictable results occur configuration software allows range conflicts happen. Hardware checks performed programming conflicts.
Intel® 82443MX100 PCIset
Table Variable Decode Ranges (Available Space
Range Name SMBus Mixer Master (Audio) Master (Modem) Modem GPIO Parallel Port Serial Ports Floppy Disk Controller MIDI SoundBlaster X-bus Programmable Chip Select decode ranges [0:1] Mappable Anywhere Space Anywhere Space Anywhere Space Anywhere Space Anywhere Space Anywhere Space Anywhere Space Anywhere space ranges Space Ranges Space Ranges Space Ranges Space Ranges Space Ranges Space Anywhere Space 1-16 Size (Bytes) Unit Unit SMBus Unit Unit Unit Unit Unit GPIO Unit X-bus Peripheral X-bus Peripheral X-bus Peripheral X-bus Peripheral X-bus Peripheral X-bus Peripheral X-bus Peripheral Target
Figure shows 440MX uses configuration space.
Intel® 82443MX100 PCIset
Figure Configuration Space Block Diagram
Configuration Window
Function AC'97 Audio Host-PCI Bridge, DRAM Control Dev. PCI0 (Physical-
Devices
Devices
Function AC'97 Modem
PCIPeripherals Dev.
Function X-bus Bridge Function Function X-Bus Bridge, ACPI Function
Function
Function Power Management, SMBus
Platform Configuration
Intel® 82443MX100 PCIset
Functional Description
Mobile Celeron Processor Mobile Pentium Processor Host Interface
Overview
host interface optimized support mobile Celeron processor Pentium processor 100-MHz 66-MHz clock frequency. 440MX implements host address, control, data interfaces within single device. Host addresses decoded accesses main memory, memory, I/O, configuration space. Pipelined addressing capability utilized improve overall system performance.
6.1.1
6.1.2
Host Device Support
440MX recognizes supports large subset transaction types that defined mobile Celeron processor/Pentium processor interface. However, each transaction type multitude response types, some which supported this controller. transactions processed order received processor bus. Table summarizes transactions supported.
Table Host Transactions Supported
Transaction Deferred Reply Reserved Interrupt Acknowledge REQa[4:0]# REQb[4:0]# 00000 00001 01000 XXXXX XXXXX 00000 00001 0001x 001xx 00000 00001 0001x 001xx LEN# Support deferred reply initiated previously deferred transaction Reserved Interrupt acknowledge cycles forwarded internal Table Reserved Reserved branch trace message terminated without latching data Reserved Reserved Reserved read cycles forwarded bus. cycles North Bridge/Cluster configuration space forwarded write cycles forwarded bus. cycles North Bridge/Cluster configuration space forwarded Reserved Host initiated memory read cycles forwarded DRAM bus. cycle initiated PCI-initiated
Special Transactions Reserved Reserved Branch Trace Message Reserved Reserved Reserved Read 01000 01000 01001 01001 01001 01001 10000
Write
10001
LEN#
Reserved Memory Read Invalidate
1100x 00010
00xxx LEN#
Intel® 82443MX100 PCIset
Transaction
REQa[4:0]# REQb[4:0]# write cycle DRAM.
Support
Reserved Memory Code Read Memory Data Read
00011 00100 00110
LEN# LEN# LEN#
Reserved Memory code read cycles forwarded DRAM PCI. Host initiated memory read cycles forwarded DRAM bus. memory read cycle initiated PCIinitiated read cycle DRAM. This memory write writeback cycle cannot retried. write forwarded DRAM. standard memory write cycle forwarded DRAM PCI.
Memory Write retry) Memory Write (can retried)
00101 00111
LEN# LEN#
NOTES: Memory cycles, REQa[4:3]# ASZ#. 440MX only supports ASZ# (32-bit address). REQb[4:3]# DSZ#. mobile Celeron processor/Pentium processor, DSZ# (64-bit data size). LEN# data transfer length follows: LEN#Data length bytes (BE[7:0]# specify granularity) Length bytes BE[7:0]# active (not supported) Length bytes BE[7:0]# active Reserved
Table shows supported host responses.
Table Host Responses Supported
RS2# RS1# RS0# Description Idle Retry Response This response generated access made resource that cannot accessed processor that time logic must avoid deadlock. PCI-directed reads, writes, DRAM locked reads retried. 440MX Support
Deferred Response This response returned transactions that executed order." directed reads (memory, Interrupt Acknowledge) writes (I/O only) deferred. Reserved Hard Failure Data Response Reserved supported This response transactions where data been transferred transactions where data transferred. Writes zero length reads receive this response. This response generated transactions that modified cache line. This response transactions where data accompanies response phase. Reads receive this response.
Implicit Writeback Normal Data Response
6.1.3
Special Cycles
special cycle defined when REQa[4:0]=01000 REQb[4:0]=xx001. first address phase, Aa[35:3]# undefined driven value. second address phase, Ab[15:8]# defines type special cycle issued processor. Table specifies cycle type definition, well action 440MX when corresponding cycles identified. Datasheet
Intel® 82443MX100 PCIset
Table Special Cycle Transactions
BE[7:0}# Special Cycle Type This transaction effect. This transaction issued when agent detects severe software error that prevents further processing. This cycle claimed 440MX, which issues shutdown special cycle bus. This cycle retired after terminated master abort mechanism. This transaction issued when agent invalidated internal caches without writing back modified lines. 440MX claims this cycle retires This transaction issued when agent executes instruction stops program execution. This cycle claimed 440MX propagated Special Halt Cycle. This cycle retired after terminated master abort mechanism. This transaction issued when agent written back modified lines invalidated internal caches. 440MX claims this cycle retires Action Taken
0000 0000 0000 0001 Shutdown
0000 0010 Flush
0000 0011 Halt
0000 0100 Sync
0000 0101 Flush This transaction issued when agent completed cache sync flush Acknowledge operation response earlier FLUSH# signal assertion. 440MX claims this cycle retires 0000 0110 Stop Clock This transaction issued when agent enters Stop Clock mode. This cycle Acknowledge claimed 440MX propagated Special Stop Grant cycle. This cycle completed after terminated master abort mechanism. 0000 0111 This transaction first issued when agent enters System Management Mode Acknowledge (SMM). Ab[7]# also this entry point. subsequent transactions from with Ab[7]# treated 440MX accesses space. corresponding cycle propagated PCI. exit SMM, issues another these cycles with Ab[7]# deasserted. space access closed 440MX this point. Others Reserved
6.1.4
Symmetric Multiprocessor (SMP) Configuration
Symmetrical multi-processor configurations supported.
6.1.5
In-order Queue Pipelining
interface includes four deep in-order queue track pipelined transactions. When in-order queue nearly full, asserting halts pipeline#. BNR# asserted until in-order queue begins drain.
6.1.6
Frame Buffer Memory Support (USWC)
allow high-speed write capability graphics, Pentium processor family introduced USWC (uncacheable, speculative, write-combining) memory type. USWC memory type provides write-combining buffering mechanism write operations. high percentage graphics transactions writes memory-mapped graphics region, normally known linear frame buffer. Reads writes USWC non-cached have side effects. case graphics, current 32-bit drivers (without modifications) would Partial Write protocol update frame buffer. highest performance write transaction
Intel® 82443MX100 PCIset
Line Write. combining several back-to-back Partial write transactions (internal CPU) into Line write transaction bus, performance frame buffer accesses would greatly improved. this end, supports USWC memory. Writes USWC memory buffered combined processor's write-combining buffers (WCB). flushed after executing serializing, locked, instruction, when full bytes). extend this capability current drivers, necessary linear frame buffer address range USWC memory type, which done programming MTRR Registers CPU. number bytes less than then series less than equal 8-byte writes performed upon flushing. 440MX further optimizes this providing write combining CPU-to-PCI Write transactions. target write memory, then data combined sent single write burst. USWC DRAMtargeted writes handled regular DRAM writes. Note that application USWC memory attribute limited only frame buffer support. 440MX implements write combining CPU-to-PCI posted write.
6.1.7
Sideband Interface
This section describes each Sideband signals that interface between 440MX processor. 440MX interfaces mobile processor with following seven outputs: A20M# FERR# IGNNE# INIT# INTR SMI# STPCLK#
Outputs Open-drain buffers, which pulled system level voltage. input, FERR#, from special buffer requirements different voltage levels. threshold must compatible with CPUs that drive signal above 1.8V. 6.1.7.1 A20M# A20M# signal active (low) when both following conditions true: ALT_A20_GATE (Bit PORT92 Register) "0." A20GATE input signal "0." external microcontroller (KBC) expected generate A20GATE input signal. 6.1.7.2 FERR#/IGNNE# (Co-processor Error) 440MX supports coprocessor error function with FERR#/IGNNE# pins. function enabled COPROC_ERR_EN (Device 7:Function Offset FERR# tied directly Coprocessor Error signal CPU. shown Figure FERR# driven active CPU, IRQ13 goes active (internally). When detects write COPROC_ERR
Intel® 82443MX100 PCIset
Register, 440MX negates internal IRQ13 drives IGNNE# active. IGNNE# remains active until FERR# driven inactive. IGNNE# never driven active unless FERR# active. COPROC_ERR_EN set, then asserting FERR# does generate internal IRQ13 write does generate IGNNE#.
Figure Coprocessor Error Timing Diagram
FERR#
Internal IRQ13 Write IGNNE#
6.1.7.3
INIT# INIT# signal active (driven low) based several events shown Table When these events occur, INIT# driven clocks then released (and pulled high external pull-up resistor).
Table Events Causing INIT# Active
Event Shutdown special cycle from observed. PORT92 write, where INIT_NOW (bit transitions from PORTCF9 write, where RST_CPU (bit SYS_RST (bit transitions from RCIN# input signal goes low. RCIN# expected driven external microcontroller (KBC). transition RCIN# must occur before 440MX arms INIT# generated again. Comment
6.1.7.4
Interrupt Signals behavior INTR signal described Section 6.10.1 this document.
6.1.7.5
Non-Maskable Interrupts (NMIs) generated when either SERR# IOCHK# asserted.
6.1.7.6
SMI# SMI# active output synchronous PCICLK that asserted 440MX response many enabled hardware software events.
Intel® 82443MX100 PCIset
6.1.7.7
STPCLK# power management controls this active-low, open-drain signal.
6.2.1
6.2.1.1
Memory Interface
DRAM Interface
DRAM Interface Overview 440MX integrates main memory DRAM controller that supports 64-bit SDRAM array. 440MX generates CS#, DQM, SCAS#, SRAS#, SCLK, WE#, CKE, multiplexed addresses MA[13,(12:11)#,10,(9:0)#] DRAM array. CPU/PCI DRAM cycles, address data flows through 440MX. 440MX' DRAM interface operates clock that synchronous CPU' clock MHz. DRAM controller interface fully configurable through control registers. 440MX supports industry-standard, 64-bit wide SDRAM DIMM modules. multiplexed address lines, MA[13:0], allow 440MX support DIMMs. 440MX four lines enabling support four 64-bit rows DRAM DIMM modules. write operations less than Qword size, 440MX performs byte-wide write with DQMs. 440MX targets 100-MHz 66-MHz SDRAM supports both single double-sided DIMMs. 440MX provides refresh functionality with programmable rate (normal DRAM rate refresh/15.6 µs). Additionally, 440MX provides seven-deep refresh queue. 440MX configured Paging Policy Register keep multiple pages open within memory array. Pages kept open rows memory. When 4-bank SDRAM devices (64-Mb technology) used particular row, four pages kept open within that row. When using 2-bank SDRAM devices particular row, pages kept open within that row. 440MX DRAM interface configured SDRAM Control Register, NBXCFG Register bits, four-DRAM Boundary (DRB) Registers. four Registers define size each memory array, enabling 440MX assert proper accesses array.
6.2.2
DRAM Organization Configuration
440MX supports 64-bit DRAM configurations. following discussion, term refers memory devices that simultaneously selected CS#. 440MX supports maximum four rows SDRAM memory. composed discrete DRAM devices, single-sided, double-sided DIMMs. DRAM interface consists following pins: MA[13,(12:11)#,10,(9:0)#] MD[63:0] DQM[7:0] SRAS# SCAS#
Intel® 82443MX100 PCIset CS[3:0]# CKE[3:0] line provided each row. SRAS#, SCAS#, drive four rows SDRAM. Most pins utilize programmable strength output buffers. When contains 16-Mb SDRAMs, MA11# functions Bank Select line. When contains 64-Mb 128-Mb SDRAMs, MA[12:11]# function Bank Addresses (BA[1:0], Bank Selects). DIMMs populated order, example, combination rows populated. Table lists some possible DIMM socket configurations along with their corresponding programming.
Table Sample Possible Options Row/3-DIMM Configurations
Total Memory Size
NOTE:
DIMM0
DIMM1
DRB0
DRB1
DRB2
DRB3
2Mx64/S 1Mx64/S 2Mx64/D 1Mx64/S 4Mx64/S 2Mx64/D 4Mx64/S 1Mx64/S 4Mx64/S 2Mx64/S 2Mx64/D 8Mx64/D 4Mx64/S 8Mx64/D 1Mx64/S 8Mx64/D 2Mx64/S 8Mx64/D 4Mx64/S 8Mx64/D 16Mx64/D
2Mx64/D 1Mx64/S 1Mx64/S 2Mx64/S 4Mx64/S 2Mx64/D 1Mx64/S 4Mx64/S 2Mx64/D 4Mx64/S 4Mx64/S 8Mx64/D 4Mx64/S 1Mx64/S 8Mx64/D 2Mx64/D 8Mx64/D 4Mx64/S 8Mx64/D 8Mx64/D 16Mx64/D
denotes single-sided DIMMs denotes double-sided DIMMs.
Figure depicts 440MX connections two-DIMM SDRAM memory array.
Intel® 82443MX100 PCIset
Figure DIMM Configuration with Switches
DIMM0 CS[3:2]# CS[1:0]# SRAS# SCAS# MA[13,12#, 11#,10,(9:0)#] MD[63:0] DQM[7:0] CKE[3:2]# CKE[1:0]# CLK[7:4] CLK[3:0] SMB_CLK SMB_DATA
DIMM1
6.2.2.1
Configuration Mechanism DIMMs Detection DRAM type installed DIMM supported Serial Presence Detect mechanism defined JEDEC 168-pin DIMM standard. This standard uses (SMB_CLK), (SMB_DATA) SA[2:0] pins DIMMs detect type size installed DIMMs. special programmable modes provided detecting size type memory installed. Type size detection must done serial presence detection pins.
6.2.2.1.1
Memory Detection Initialization
DRAM registers must initialized before cycles memory interface supported. Detection memory size done System Management (SMBus). This two-wire used extract DRAM type size information from serial presence detect port DRAM DIMMs. DRAM DIMMs contain five-pin serial presence detect interface, including (serial clock), (serial data) SA[2:0]. Each device SMBus seven-bit address. DRAM DIMMs, upper four bits fixed 1010. lower three bits strapped SA[2:0] pins. connected directly SMBus. Thus, data read from Serial Presence Detect port DIMMs series SMBus cycles. properly
Intel® 82443MX100 PCIset
configure memory interface, BIOS uses this data determine memory size each four rows.
6.2.2.1.2 SMBus Configuration
Before accessing information from DIMMs, SMBus host interface must initialized. This done registers mapped Configuration Space Device function SMBus accesses done through cycles. desirable make base address programmable avoid conflicts with existing mapped devices system. address programmed through 32-bit SMBus Base Address Register location 90h, Device function Bits 31:16 this register Reserved. Bits 15:4 used select 16-bit base address SMBus host controller. Bits Reserved hard-wired indicating that SMBus host controller always mapped. second register configured SMBus Host Configuration Register located D2h, Device function Bits this register Reserved. Bits used assign interrupt SMBus host controller. IRQ9 SMI# selected. SMBus host interface enabled upon setting this register
6.2.2.1.3 Accessing Serial Presence Detect Ports
Each device SMBus unique seven-bit address. DRAM DIMMs have upper four bits this address hard-wired 1010. remaining three bits strapped each DIMM SA[2:0] pins. example, support DIMMs (four rows memory), SA[2:0] lines strapped 001. Thus, SMBus cycle with target address 1010000 addresses lower order DIMM. Each DIMM contains EEPROM with bytes accessible data. BIOS read this data from Serial Presence Detect Ports determine type, size required attributes each memory. Once SMBus host controller initialized enabled, accessing Serial Presence Detect ports done through sequence reads writes Space Registers defined SMBus base address (see Section 6.2.2.1.2).
6.2.2.1.4 DRAM Register Programming
This section provides overview Serial Presence Detect ports DIMMs obtain required information program DRAM registers. Serial Presence Detect ports used determine Refresh rate, buffer strength, SDRAM timings, sizes, page sizes. Table lists subset data available through on-board Serial Presence Detect each DIMM.
Intel® 82443MX100 PCIset
Table Data Bytes DIMM Used Programming DRAM Registers
Byte 36-41 Memory type SDRAM) addresses, counting bank addresses Column addresses Banks DRAM (single-sided double-sided DIMM) Refresh rate Banks each SDRAM Device Access time from clock CAS# latency through Data width SDRAM components Function
These bytes collectively provide enough data program DRAM registers. example, program (DRAM Boundary) Registers, size each must determined. number addresses (byte plus number column addresses (byte plus number banks each SDRAM device (byte collectively determines total address depth particular SDRAM. Since always data-bits wide, size easily determined programming Registers. Once type DRAM been detected, this information must then programmed into DRAM Boundary Registers. 440MX uses DRAM Type information conjunction with DRAM timings DRAM Timing Register optimally configure DRAM accesses.
6.2.3
SDRAM Cycle Encoding
Table through Table show SDRAM cycle encoding using CS#, SRAS#, SCAS#, WE#, bank select.
Intel® 82443MX100 PCIset
Table Command Truth Table
Function Device deselect Operation Read Read auto precharge Write Write auto precharge Bank Activate Precharge select bank Precharge banks Auto refresh Self refresh entry from IDLE Self refresh exit Power Down entry from IDLE Power Down exit Mode register Symbol DSEL READ READAP WRIT WRITEAP PALL SLFRSH SLFRSHX PWRDN PWRDNX SRAS# SCAS# A9-A0
Table Truth Table
Function Data write/output enable Data mask/output disable Upper byte write enable/lower byte mask Lower byte write enable/high byte mask
NOTE:
High Level, Level, Don' care, Valid data input.
Intel® 82443MX100 PCIset
Table Operative Command Table
Current State SRAS# SCAS# Idle active Read Write Address Command DSEL Action Power Down Power Down ILLEGAL ILLEGAL Active Refresh Self refresh Mode Register access Begin read: Optional Begin write: Optional ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst active Continue burst activ
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