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Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Order Number: 273354-002
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel® products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel® products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® 80310 Processor Chipset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com.
Copyright© Intel Corporation, December Friday, 2000 *Other names brands claimed property others.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Contents
Introduction Intel® 80200 Processor based Intel® XScaleMicroarchitecture Ball Intel® 80312 Companion Chip Ball Routing Guidelines Intel® 80312 Companion Chip Memory Subsystem
5.1.1 5.1.2 5.1.3 5.2.1 5.2.2 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 Layout Guidelines. Intel® 80200 Processor Clocking Layout Guidelines. Layout Guidelines. Wait State Profiles. Layout Guidelines. SDRAM Clocking. SDRAM Power Failure Guidelines System Assumptions External Logic Required Power Failure.29 5.3.5.1 SCKE Logic
10.0
Interrupt Routing Clocking Guidelines Intel® 80200 Processor Signals Requiring Pull-Up/Down Resistors Intel® 80312 Companion Chip Signals Requiring Pull-Up/Down Resistors Intel® 80200 Processor Mixed Voltage Design Considerations
10.1.1 Providing System. 10.2.1 Analog Supply Voltage 10.2.2 Periphery Supply Voltage
11.0 12.0
Intel® 80312 Companion Chip Design Considerations Processor Power Supply Decoupling
12.1.1 Intel® 80312 Companion Chip 12.1.2 Intel® 80200 Processor
13.0 14.0
Intel® 80312 Companion Chip Based Reference Design Debug Connector Recommendations
14.3.1 Intel® 80200 Processor JTAG Emulators 14.3.2 Intel® 80200 Processor Target Debug Interface Connector Multi-ICE Emulator
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
14.3.3 Intel® 80200 Processor Target Debug Interface Connector Windriver Emulator. 14.3.4 JTAG Emulator Reset Circuit 14.3.5 Other Tools
15.0 16.0
Design Manufacturability Thermal Solutions.
16.5.1 16.5.2 16.5.3 16.5.4 16.5.5 Socket Information Socket-Header Vendor. Burn-in Socket Vendor Shipping Tray Vendor JTAG Emulator Vendor
17.0
References Intel® 80312 Companion Chip Schematics Intel® IQ80310 Evaluation Platform Board Bill Materials. Intel® 80312 Companion Chip PBGA Signal Ball Intel® 80200 Processor PBGA Signal Ball
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figures
241L PBGA Diagram (Bottom View) 540L HL-PBGA Diagram (Bottom View) Examples Stubless Short Stub Traces. Intel® 80310 Processor Chipset Interface Signals Intel® 80310 Processor Chipset Clock Signals Mbyte Flash Memory System. Dual-Bank SDRAM Memory Subsystem. Single DIMM Address Control Signals Dual DIMM Address Control Signals. Option Single DIMM Data Signals.21 Option Single DIMM Data Signals.21 Option Dual DIMM Data Signals Option Dual DIMM Data Signals Single DIMM SCE[1:0] Signals. Dual DIMM SCE[1:0] Signals Single DIMM SCKE[1:0] Signals Dual DIMM SCKE[1:0] Signals. Single DIMM SDQM[7:0] Signals Dual DIMM SDQM[7:0] Signals. Discrete SDRAM Address Control Signals. Discrete SDRAM DQM[7:0] Signals Clocking Dual-Bank SDRAM DIMM External Power Failure State Machine External Power Failure Logic System. Logic Generating PWRDELAY SYSTEM_RST#. PWRDELAY Timings. Example Secondary Connector Interrupt Routing Add-in Card Example Configuration. Motherboard Example Configuration. Creating Power "Island". Power Supply Circuit Recommended Power Supply Connection Layout. VCCA Lowpass Filter VCC5REF Current-Limiting Resistor. VCCPLL Lowpass Filter High-Frequency Capacitor Values Layout Intel® 80312 Companion Chip 540L PBGA Header. 540L PBGA Socket Multi-ICE JTAG Emulator Connector (Top View) Windriver JTAG Emulator Connector (Top View). Emulator Reset Circuit Conceptual View Processor with Heat Sink Hole Dimensions Passive Heatsink Board Level Keep Areas. Clearances Board Components Decoupling Schematic. Primary Interface Schematic
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Memory Controller Schematic Flash ROM/Boot Select Schematic UART Schematic LEDs Schematic. Logic Analyzer Schematic. SDRAM 168-Pin DIMM Schematic Secondary PCI/JTAG Schematic Intel® 80200 Processor/Intel® 80312 Companion Chip Schematic. Secondary Schematic 21154 Bridge Schematic Ethernet Controller Schematic SPCI Pull-Ups Schematic Battery/Monitor Schematic SDRAM +3.3 Reference Schematic SCKE Control Schematic Intel® 80200 Processor Core Supply Schematic
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Tables
Intel® 80312 Companion Chip Interface Signals Flash Interface Signals. ROM, SRAM, Flash Wait State Profile Programming SDRAM Interface Signals. Drive Strength Programmability Options Intel® 80312 Companion Chip Interrupt Routing Signals Intel® 80200 Processor Signals Memory Controller, Core JTAG Signals Signals Signals. VDIFF Specification Dual Power Supply Requirements (3.3 Logic Analyzer Header Definitions (Mictor) Intel® 80200 Processor Debug Connector Wiring Multi-ICE Emulator Intel® 80200 Processor Debug Connector Wiring Windriver Emulator. H-PBGA Package Characteristics Heat Sink Vendors Contacts Socket-Header Vendor. Burn-in Socket Vendor Shipping Tray Vendor.59 JTAG Emulator Vendor Related Documentation. Electronic Information.60 Intel® IQ80310 Evaluation Platform Board Bill Materials HL-PBGA Ballpad Order 241L PBGA Ballpad Order
Revision History
Revision -002 -001 Date 12/15/00 09/25/00 Description Revised PWRDELAY information pages Text changes page Original Document.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Introduction
This design guide addresses design considerations designing with Intel® 80310 processor chipset with Intel® XScalemicroarchitecture (ARM* architecture compliant). This chipset consists Intel® 80200 processor based Intel® XScalemicroarchitecture (ARM architecture compliant) Intel® 80312 companion chip.
Intel® 80200 processor able maximum core frequency MHz. Intel® 80200 processor frequency independently controlled maximum
frequency Intel® 80312 companion chip integrates PCI-to-PCI bridge that supports both 64-bit 32-bit modes running MHz. bridge also MHz. Intel® 80312 companion chip also supports memory controller that consists Flash SDRAM interface. memory controller frequency MHz. Intel® 80312 companion chip provides interface that allows direct connection Intel® 80200 processor. This design guide intended provide system designers valuable design information used while designing boards with Intel® 80310 processor chipset with Intel® XScalemicroarchitecture (ARM architecture compliant). Designers should note that this guide focuses upon specific design considerations Intel® 80200 processor Intel® 80312 companion chip intended all-inclusive list good design practices. Intel recommends employing best known design practices with signal integrity testing validation ensure robust design. this guide starting point empirical data optimize your particular design.
Intel® 80200 Processor based Intel® XScaleMicroarchitecture Ball
Intel® 80200 processor signals, design, located PBGA package simplify signal routing system implementation. Figure shows bottom view Intel® 80200 processor. simplify routing minimize number cross traces, keep this layout mind when placing components your system. Individual signals within respective groups have also been laid minimize signal crossings. detailed signal descriptions refer Intel® 80200 Processor based Intel® XScaleMicroarchitecture Datasheet. Contact your Intel sales representative obtain copy document.
Figure
241L PBGA Diagram (Bottom View)
A7816-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Intel® 80312 Companion Chip Ball
Product Name signals, design, located PBGA package simplify signal routing system implementation. Figure shows Intel® 80312 companion chip major signal sections. simplify routing minimize number cross traces, keep this layout mind when placing components your system. Individual signals within respective groups have also been laid minimize signal crossings. detailed signal descriptions refer Intel® 80312 Companion Chip Datasheet document. Contact your Intel sales representative obtain copy document.
Figure
540L HL-PBGA Diagram (Bottom View)
P_PCI
S_PCI
Memory Controller
A8020-01
Intel® 80312 Companion Chip HL-PBGA Signal Ball
Table details ballout Intel® 80312 companion chip processor. Appendix
MISC
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Routing Guidelines
order which signals routed first last varies from designer designer. Some prefer route clock signals first, while others prefer route high speed signals first. Either order used, provided guidelines listed here followed. Route Intel® 80312 companion chip address/data control signals using "daisy chain" topology. This topology assumes that stubs used connect devices net. Figure shows possible techniques achieve stubless trace. When possible apply these techniques congestion, very short stub allowed preferably exceed mils.
Figure
Examples Stubless Short Stub Traces
Stubless
<250 Mils
Short Stub
A7690-01
Trace Length Limits
add-in cards, trace lengths from card edge connector Intel® 80312 companion chip follows:
maximum trace length 32-bit interface signals should exceed inches
32-bit 64-bit cards. This includes signals except those listed `Signal Pins', `Interrupt Pins', `JTAG Pins' Local Specification, Revision 2.2.
trace length additional signals used 64-bit extension limited inches
64-bit cards.
trace length signal inches inch 32-bit 64-bit cards
should routed only single load.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Intel® 80312 Companion Chip Memory Subsystem
Intel® 80312 companion chip integrates memory controller provide direct interface between Intel® 80312 companion chip local memory subsystem. memory controller supports:
Mbytes 8-bit Flash, ROM, SRAM Between Mbytes 64-bit synchronous DRAM (SDRAM) Single-bit error correction, double-bit nibble detection support (ECC)
Flash interface provides 8-bit data bus, 23-bit address bus, control support Mbit Bulk-Erase Boot-Block Flash devices. Flash devices provide storage Intel® 80312 companion chip initialization code. memory controller provides separate SDRAM interface from Flash interface. SDRAM interface consists MHz, 64-bit wide data path support Mbytes/sec throughput. 8-bit Error Correction Code (ECC) across each 64-bit word improves system reliability.
memory controller supports banks SDRAM form single two-bank dual
inline memory module (DIMM) single-bank DIMMs.
memory controller responds internal memory accesses within programmed
address range issues memory request either Flash SDRAM interface. memory controller provides four chip enables memory subsystem. chip enables service SDRAM subsystem (one bank) service Flash devices. Note: design does follow listed guidelines, then very important that design simulated. Even guidelines followed still recommended that design simulated proper signal integrity, flight time, cross talk.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Intel® 80310 Processor Chipset Interface
Intel® 80312 companion chip provides interface that directly connect Intel® 80200 processor external bus. Table defines interface signals. Data between Intel® 80200 processor Intel® 80312 companion chip transferred over Intel® 80312 companion chip SDRAM data bus. Therefore, Intel® 80200 processor data D[63:0] directly connected Intel® 80312 companion chip SDRAM data SDQ[63:0]. Intel® 80200 processor CB[7:0] directly connected Intel® 80312 companion chip SDRAM SCB[7:0]. SDRAM data read transactions transferred directly from SDRAM Intel® 80200 processor whereas write data first transferred into Intel® 80312 companion chip, then later writes data SDRAM. Intel® 80200 processor data that targeted devices other than SDRAM transferred Intel® 80312 companion chip. example, Intel® 80312 companion chip acts slave device taking requests from Intel® 80200 processor. Note: byte enable signals BE[7:0]# from Intel® 80200 processor part interface signals. Intel® 80312 companion chip internally generates byte enable signals from C_LEN[2:0] lower address bits. Refer Intel® 80200 processor Developer's Manual more information. Intel® 80312 Companion Chip Interface Signals
Name C_CLK C_DVALID C_ABORT Description Intel® 80200 processor Output Clock This clock driven Intel® 80200 processor. This clock defines Intel® 80200 processor speed. Intel® 80200 processor Data Valid This signal indicates that cycles later there will valid data cycle data bus. Intel® 80200 processor Abort When this signal asserted with C_DVALID, indicates that next Intel® 80200 processor transaction data been aborted. Intel® 80200 processor Address During first cycle issue phase these signals carry upper bits address. During second cycle issue phase they carry lower bits address. C_ADS#/C_LEN Intel® 80200 processor Address Strobe During first cycle issues phase this signal indicates start request. Intel® 80200 processor Length During second cycle issue phase this signal value which indicates length transaction. Intel® 80200 processor Lock During first cycle issue phase this signal indicates whether current transaction part atomic read-write pair. Intel® 80200 processor Length During second cycle issue phase this signal value which indicates length transaction. Intel® 80200 processor Write/Read During first cycle issue phase this signal write high read low. Intel® 80200 processor Length During second cycle issue phase this signal value which indicates length transaction. Intel® 80200 processor Reset This signal provides reset Intel® 80200 processor. Intel® 80200 processor Interrupt Request This signal provides interrupt request Intel® 80200 processor. Intel® 80200 processor Interrupt Request This signal provide fast interrupt request Intel® 80200 processor.
Table
C_A[15:0]
C_LOCK#/C_LE N[1]
C_W/R#/LEN[0]
C_RESET# C_IRQ# C_FIQ#
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
5.1.1
Layout Guidelines
Figure shows interface signals involved connect Intel® 80200 processor Intel® 80312 companion chip. Intel® 80200 processor data connected Intel® 80312 companion chip SDRAM data bus. example, data between Intel® 80200 processor Intel® 80312 companion chip transferred over Intel® 80312 companion chip SDRAM data bus.
Figure
Intel® 80310 Processor Chipset Interface Signals
Intel® 80200 Processor
A[15:0] ABORT DVALID W_R#/LEN[0] LOCK/LEN[1] ADS#/LEN[2] MCLK IRQ# FIQ# RESET# SCB[7:0] SDQ[63:0] C_A[15:0] C_ABORT C_DVALID
Intel® 80312 Companion Chip
C_W_R#/LEN[0] C_LOCK/LEN[1] C_ADS#/LEN[2] C_CLK C_IRQ# C_FIQ# C_RESET# SCB[7:0] SDQM[7:0] SDQ[63:0]
CB[7:0]
SDQ[63:0]
SDRAM Memory
A7852-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
5.1.2
Intel® 80200 Processor Clocking
Intel® 80200 processor input clocks:
Core Clock Clock MCLK
core clocks independent thus asynchronous clocks. core clock provides reference clock core logic, whereas clock provides reference clock external signals. core clock accepts input clock frequency MHz. This clock supplied using crystal oscillator. Intel® 80200 processor uses internal lock input multiplies frequency variable multiplier produce high-speed core clock (CLK). This multiplier initially configured configuration (PLLCFG) changed anytime later software. Refer Intel® 80200 Processor based Intel® XScaleMicroarchitecture Developer's Manual more details about setting clock frequency. However, ratio MCLK must less. Intel® 80312 companion chip C_CLK that used drive MCLK. used Intel® 80200 processor core, PLLCFG must pulled high order exceed clock ratio requirement. MCLK input driven C_CLK output from Intel® 80312 companion chip. This clock frequency high MHz. Figure Intel® 80310 Processor Chipset Clock Signals
Intel® 80200 Processor
Intel® 80312 Companion Chip C_CLK
MCLK
A7851-01
5.1.3
Layout Guidelines
C_CLK/MCLK uses same guidelines SDRAM DCLKOUT/DCLKIN signals explained Section 5.3.2, "SDRAM Clocking" page Keep request signals trace length between inches.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
ROM, SRAM, Flash Guidelines
Intel® 80312 companion chip memory controller provides interface banks static memory ranging from Kbytes Mbytes. This memory SRAM, ROM, Flash. Optionally, banks dedicated UART device. Table defines Flash interface signals.
Table
Flash Interface Signals
Name Description
RCE[1:0]# Chip Enable Asserted transactions Flash device. RWE# ROE# Write Enable Controls Flash input data buffers. Output Enable Reads asserted, writes deasserted. Controls Flash output data buffers write transactions. Address Latch Enable Indicates transfer physical address. RALE asserted during Flash address cycle deasserted before beginning data cycle.
RAD[16:0] Address/Databus support Mbit Flash (2Mx8). Databus multiplexed RAD[16:9]. RALE
5.2.1
Layout Guidelines
Figure illustrates Flash devices would interface Intel® 80312 companion chip with memory controller. Flash subsystem requires external latch address data demultiplexing RAD[16:3]. data multiplexed RAD[16:9].
Figure
Mbyte Flash Memory System
RAD[2:0] RAD[8:3] A[2:0] A[8:3] A[20:17]
Latch Intel® 80312 Companion Chip
RALE RAD[16:0] ROE# REW# RCE0# RCE1#
Intel® 28F016-70 Mbit Flash
A[20:0]
RAD[16:9]
Latch
A[16:9]
DQ[7:0]
DQ[7:0]
Intel 28F016-70 Mbit Flash
A[20:0]
Interface Signals
DQ[7:0]
Intel® 80200 Processor
A7849-01
Flash signal loading should exceed system conforms I2O* specification, then minimum Mbit Flash (Intel® 28F016SA) suggested. traces between Intel® 80312 companion chip Flash/SRAM should exceed eight inches. Note: boot Flash device must connected chip enable CE1#. This because Intel® 80200 processor boots from address 0x00000000 after reset. Chip enables CE0# CE1# base address registers initialized 0xFE800000 0x00000000 respectively after reset.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
5.2.2
Wait State Profiles
Table summarizes various wait state profiles SRAM writable non-volatile memory devices.
Table
ROM, SRAM, Flash Wait State Profile Programming
Device Speed Address-to-Data Wait States Recovery Wait States
SDRAM Guidelines
memory controller located Intel® 80312 companion chip.The Intel® 80200 processor simply requests memory transactions Intel® 80312 companion chip. Intel® 80312 companion chip memory controller supports banks MHz, 72-bit SDRAM. memory controller supports Mbit, Mbit Mbit SDRAM technology offering Mbytes protected memory. Intel® 80312 companion chip only supports 64-bit wide unbuffered SDRAM with ECC. 32-bit wide SDRAM supported. Table shows SDRAM interface signals.
Table
SDRAM Interface Signals
Name DCLK[3:0] DCLKOUT DCLKIN SCKE[1:0] Description SDRAM Clock These four output clocks driven Unbuffered DIMMs supported Intel® 80312 companion chip. Early SDRAM Clock This clock driven memory subsystem that DCLK[3:0] skewed back accomodate clocks' flight time compatible with 100/133 SDRAM technologies. SDRAM Clock This DCLKOUT clock returning from memory subsystem. Clock enables clock after SCKE[1:0] deasserted, data latched DQ[63:0] SCB[7:0]. burst counters within SDRAM device incremented. Deasserting this signal places SDRAM self-refresh mode. normal operation, SCKE[1:0] must asserted. Data Mask write, these signals disable data byte-by-byte basis, thus preventing certain bytes from being written. read, clocks after asserting SDQM[7:0] output data bytes from SDRAM device disabled. Chip Select Must asserted transactions SDRAM device. bank. Write Enable Controls SDRAM data input buffers. Asserting SWE# causes data DQ[63:0] SCB[7:0] written into SDRAM devices. SDRAM Bank Selects Controls which internal SDRAM banks read write. Mbit devices banks), only SBA[0] used while Mbit devices SBA[1:0]. Address high during read write command, then auto-precharge occurs after command. During row-activate command, this part address. Address bits through Indicates column access depending state SRAS# SCAS#. Address Strobe Indicates that current address SA[13:0] row. Column Address Strobe Indicates that current address SA[13:0] column. Data 64-bit wide data bus. 8-bit error correction code which accompanies data DQ[63:0].
SDQM[7:0] SCE[1:0]# SWE# SBA[1:0] SA[10] SA[13:0] SRAS# SCAS# DQ[63:0] SCB[7:0]
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
5.3.1
Layout Guidelines
SDRAM subsystem implemented with:
banks directly connected printed circuit board bits wide) 168-pin DIMM sockets bits wide)
memory controller supports either dual-bank DIMM single-bank DIMMs. 4-Clock 72-bit Unbuffered SDRAM DIMM Specification requires four clock inputs. Figure illustrates banks SDRAM interfaces with Intel® 80312 companion chip memory controller. clock routing, refer Figure shown Figure SDRAM data (including CB[7:0]) shared Intel® 80200 processor Intel® 80312 companion chip. read transactions, data from SDRAM transferred directly Intel® 80200 processor, whereas write data first transferred into Intel® 80312 companion chip, then later writes data SDRAM. Figure Dual-Bank SDRAM Memory Subsystem
Intel® 80312 Companion Chip
DQ[63:0] SCB[7:0] SRAS# SCAS# SWE# SA[10:0] SBA[1:0]
DQ[63:0] CB[7:0] RAS# CAS# A[10:0] BA[1:0] DQM[7:0] CKE[1:0] CS[3:0]#
SDRAM DIMM
SDQM[7:0] SCKE SCE0 SCE1
Interface Signals
DQ[63:0] CB[7:0] RAS#
SDRAM DIMM
Intel® 80200 Processor
D[63:0]
CAS# A[10:0] CB[7:0] BA[1:0] DQM[7:0] CKE[1:0] CS[3:0]
A7848-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
drive strengths SDRAM signals independently programmable using SDCR register. Table lists some example SDRAM configurations SDCR should programmed. Intel® 80312 companion chip determines SDRAM configuration with Serial Presence Detect EEROM (SPD) located DIMM. interfaces Intel® 80312 companion chip with SPD. Table Drive Strength Programmability Options
Width Form Factor single-sided DIMM single-sided DIMMs double-sided DIMM single-sided DIMM single-sided DIMMs 5[x16] None Bank Bank SDCR[4:3] (DQ) SDCR[6:5] (CE0#, CKE0) SDCR[8:7] (CE1#, CKE1) SDCR[10:9] (DQM) SDCR[12:11] (A[12:0], Controls)
9[x8]
None
9[x8]
9[x8]
9[x8]
9[x8]
5[x16] 5[x16]
double-sided 5[x16] 5[x16] DIMM
NOTES: 8-bit SDRAM available Mbit, Mbit, Mbit SDRAM technologies. 16-bit SDRAM available Mbit Mbit SDRAM technologies.
Specific SDRAM signal topologies have been validated operation. following figures illustrate proven topologies recommended. Proper signal integrity analysis should verify other signal topologies. minimize crosstalk, SDRAM signal routing should minimum mils spacing mils trace width. SDRAM clocks should minimum mils spacing mils trace width.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Single DIMM Address Control Signals
DIMM
Intel® 80312 Companion Chip
5.5"
Address/Control
A7893-01
Figure
Dual DIMM Address Control Signals
Intel® 80312 Companion Chip
5.0"
DIMM0
DIMM1
0.6"
Address/Control
A7894-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Option Single DIMM Data Signals
Intel® 80312 Companion Chip
DIMM
Data
Intel® 80200 Processor
Note: Data includes DQ[63:0] CB[7:0] X+Y: inches inches
A7792-01
Figure
Option Single DIMM Data Signals
Intel® 80312 Companion Chip DIMM
Intel® 80200 Processor
5.5"
3.5"
Note: Data includes DQ[63:0] [7:0]
A8022-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Option Dual DIMM Data Signals
DIMM0 Intel® 80312 Companion Chip
0.6"
DIMM1
Data
Intel® 80200 Processor
Note: Data includes DQ[63:0] CB[7:0] X+Y: inches inches
A7793-01
Figure
Option Dual DIMM Data Signals
Intel® 80312 Companion Chip DIMM0 DIMM1
0.6"
Intel® 80200 Processor
5.5"
3.0"
Note: Data includes DQ[63:0] CB[7:0]
A8028-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Single DIMM SCE[1:0] Signals
DIMM Intel® 80312 Companion Chip
SCE[1:0]
Notes: inches inches
A8029-01
Figure
Dual DIMM SCE[1:0] Signals
DIMM0 Intel® 80312 Companion Chip
0.6"
DIMM1
SCE0
SCE1
Notes: inches inches
inches inches
A8030-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Single DIMM SCKE[1:0] Signals
DIMM Intel® 80312 Companion Chip
5.5"
SCKE(1:0)
A8031-01
Figure
Dual DIMM SCKE[1:0] Signals
DIMM0 Intel® 80312 Companion Chip DIMM1
5.5"
0.6"
SCKE0
5.5"
SCKE1
A8032-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Single DIMM SDQM[7:0] Signals
DIMM Intel® 80312 Companion Chip
4.0"
SDQM[7:0]
A8033-01
Figure
Dual DIMM SDQM[7:0] Signals
DIMM0 Intel® 80312 Companion Chip
0.6"
DIMM1
SDQM[7:0]
A8025-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Discrete SDRAM Address Control Signals
SDRAM SDRAM
Intel® 80312 Companion Chip
SDRAM
SDRAM
Notes: inches inches inches
A8024-01
Example
Discrete SDRAM Data Signals same guidelines shown Section "Option Single DIMM Data Signals" page Section "Option Single DIMM Data Signals" page However, compensate trace length DIMM, inches trace going discrete SDRAMs. Also resistors terminate data signals. Place resistors close SDRAM pins.
Figure
Discrete SDRAM DQM[7:0] Signals
Intel® 80312 Companion Chip
SDRAM
SDRAM
Note: DQM[7:0] signals must between inches.
A8027-01
address control signals SDRAM subsystem include SA[13:0], SCAS#, SCE[1:0]#, SCKE[1:0], SRAS#, SWE#. SDRAM data signals include DQ[63:0], SCB[7:0].
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
5.3.2
SDRAM Clocking
provides five clock signals (DCLKOUT DCLK[3:0]) SDRAM memory subsystem with frequency. 72-bit, 2-bank SDRAM DIMM specification requires four clocks distribute loading across eighteen SDRAM components. Refer Figure clock routing diagram. External resistors capacitors required proper signal integrity clock skew management.
Figure
Clocking Dual-Bank SDRAM DIMM
DIMM(s) (Single Dual)
inches
Intel® 80312 Companion Chip
DCLK0 DCLK1 DCLK2 DCLK3
DCLKOUT DCLKIN
Notes: Single bank DIMM uses only clocks. Therefore, dual DIMM design, each DIMM gets clocks. DCLK[3:0] should equal length. This also applies dual DIMM designs. DCLKIN/DCLKOUT trace length should equal DCLK[3:0] plus inches. load DCLKIN. Keep load within inches from 80312 DCLKIN ball. Ohms series resistors DCLK[3:0] DCLKOUT. Keep series resistors within inches 80312 respective balls.
A8023-01
Note:
single SDRAM bank will clock outputs. Four clock outputs used only when SDRAM banks populated. clock outputs between inches. Each four clock outputs (DCLK[3:0]) must equal length. DCLKIN must inches longer than output clocks requires external capacitor match loading seen other clock outputs. same guidelines apply discrete SDRAMs. Traces from processor capacitor must within inches.
Note:
Unbuffered 168-Pin SDRAM DIMM requires four clock inputs. lumped capacitance value required DCLKIN this reference design.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
5.3.3
SDRAM Power Failure Guidelines
SDRAM technology provides simple enabling data preservation through self-refresh command. When memory controller issues this command, SDRAM refreshes itself autonomously with internal logic timers. SDRAM device remains self-refresh mode long
device continues powered. SCKE held until memory controller ready control SDRAM once again.
board design should ensure power SDRAM subsystem with adequate battery backup reliable method switching between system power battery power. memory controller responsible deasserting SCKE[1:0] when issuing self-refresh command however, while power gradually drops, SCKE[1:0] must remain deasserted regardless state powering Intel® 80312 companion chip.
5.3.4
System Assumptions
Reliable power must present least that Intel® 80312 companion chip memory controller execute power-fail sequence. According specification, P_RST# asserted when power reached volts, which Intel® 80312 companion chip operate. overcome this problem, external voltage detection circuit that will trigger below volts must used. Intel® 80312 companion chip power-fail state machine initialized P_RST# like rest device's state machines since power-fail state machine operational during P_RST# assertion. Intel® 80312 companion chip provides dedicated input pin, PWRDELAY that used initialize memory controller's power-fail state machine when deasserted. This signal must deasserted during assertion P_RST# then gets asserted following deassertion P_RST#. PWRDELAY will deasserted again until power truly failed. Intel® IQ80310 Evaluation Platform Board schematics Appendix provides example circuit generate PWRDELAY.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
5.3.5 5.3.5.1
External Logic Required Power Failure SCKE Logic
Figure shows state machine external logic required control SCKE[1:0] signals. Actual implementations vary.
Figure
External Power Failure State Machine
SCKEOUT
PULLCKE
PULLCKE
P_RST#
A7653-01
Figure
External Power Failure Logic System
Address, Data, Control
Memory Controller
SCKE(0)
SDRAM Subsystem
SYSTEM_RST#
External Logic
PULLCKE
BOARD_PWRDELAY
Note: BOARD_PWRDELAY generated from PWRDELAY.
A7651-01
implementation illustrated Figure requires external logic powered batt. edge detect state machine activates pull-down when deasserts SCKE[1:0]. long Vbatt active, SCKE[1:0] held low. Once memory controller reset, rising edge SYSTEM_RST# deactivates pull-down. memory controller reliably controls SCKE[1:0] this point, driving low. Refer schematics Appendix more details. Note: Figure shows logic SCKE signal. Loading this signal large enough that signals required (one SDRAM bank) above logic should replicated each SCKE[1:0]. Figure shows PWRDELAY SYSTEM_RST# generation. SYSTEM_RST# drives Intel® 80312 companion chip P_RST# signal PWRDELAY drives Intel® 80312 companion chip PWRDELAY signal. SYSTEM_RST# asserted when either PCI_RST# comparator output asserted (low). When SYSTEM_RST# asserted, power-fail state machine Intel® 80312 companion chip triggered. output comparator asserted when drops just below Volts. PWRDELAY logically looks like PCI_RST# shown Figure only PWRDELAY transitions with delay based capacitor (C1). Since PWRDELAY used reset power-fail state machine when low, delay circuit allows ample time power-fail state machine execute power-fail sequence.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Note:
P_RST# signal Intel® 80312 companion chip (driven SYSTEM_RST#) triggers power-fail sequence when transitioning from high low. PWRDELAY resets power-fail state machine. delay circuit (Figure allows power-fail state machine execute power-fail sequence before resetting. Logic Generating PWRDELAY SYSTEM_RST#
PCI_RST# SYSTEM_RST# IOP_P-RST#) Vbatt Vbatt
Figure
150k 0.1% MAX921
HYST
SCKE0
100k 0.1%
REFGND
BRD_PWRDELAY 0.22µF
Vbatt Vbatt
SCKE1
BRD_ DELAY
PWRDELAY PWRDELAY)
A7693-01
Figure
PWRDELAY Timings
PCI_RST# PWRDELAY
BRD_PWRDELAY
A8018-01
addition edge detect state machine described above, second pull-down used force SCKE[1:0] signals during power-up. This necessary Vbatt present during power-up. During power-up Intel® 80312 companion chip erroneously toggle SCKE[1:0] signals during. SCKE[1:0] signals toggle, they cause SDRAM lock Note: PWRDELAY permanently pulled with 1.5K pull-down resistor when battery back-up circuit implemented.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Interrupt Routing
Local Specification, Revision PCI-to-PCI Bridge Architecture Specification, Revision state, interrupt routing system-specific. Generally, BIOS maps device interrupt line Intel® 80312 companion chip secondary INTx line. IDSEL address originates from Intel® 80312 companion chip secondary address connects device IDSEL connector slots. Table provides interrupt routing devices with single interrupt pin. Multifunction devices, which have more than interrupt pin, would follow interrupt routing guidelines shown Figure this case, replace connector with multifunction device.
Table
Intel® 80312 Companion Chip Interrupt Routing Signals
Device's IDSEL Signal S_AD16, S_AD17, S_AD18, S_AD19, Device Interrupt Signal INTA# INTB# INTC# INTD#
Secondary Address lines S_AD[25:16] configured public devices private devices depending Secondary Select Register (SISR). S_AD[31:26] public devices only. When connectors present Intel® 80312 companion chip secondary bus, interrupts rotate subsequent connectors shown Figure
Intel® 80312 Companion Chip MotherBoard Implementation
When implementing Intel® 80312 companion chip onto motherboard, must adhere Device address interrupt routing scheme used primary side which dependent individual motherboard implementation.
Intel® 80312 Companion Chip Add-in Card Implementation
When designing Intel® 80312 companion chip into add-in card, refer Figure Device address interrupt routing.
Figure
Example Secondary Connector Interrupt Routing
S_INTD:A# S_AD31:0 Intel® 80312 Companion Chip SECONDARY CONNECTOR S_INTA# INTA# S_INITB# INTB# S_INTC# INTC# S_INTD# INTD# S_AD16 IDSEL SECONDARY CONNECTOR S_INTB# INTA# S_INTC# INTB# S_INTD# INTC# S_INTA# INTD# S_AD17 IDSEL SECONDARY CONNECTOR S_INTC# INTA# S_INTD# INTB# S_INTA# INTC# S_INTB# INTD# S_AD18 IDSEL SECONDARY CONNECTOR S_INTD# INTA# S_INTA# INTB# S_INTB# INTC# S_INTC# INTD# S_AD19 IDSEL
Note: Secondary Interrupt Signals "Rotate" Subsequent Connectors.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Clocking Guidelines
Intel® 80312 companion chip uses P_CLK (synchronous clock) input clocking. timings primary referenced P_CLK input. Intel® 80312 companion chip provides output clocks (S_CLK[5:0]) devices secondary bus. timings secondary referenced S_CLK[5:0].
Layout Guidelines Add-in Cards
edge connector provides singular clock which must only connected load add-in card. Add-in cards which contain Intel® 80312 companion chip output clocks (S_CLK[5:0]) devices secondary bus. specification allows maximum clock skew between devices connected (allowable clock skew ns). minimize skew primary bus, place Intel® 80312 companion chip close possible edge connector. Trace length from edge connector Intel® 80312 companion chip P_CLK input ("A" Figure must short physically possible (max length inches). secondary bus, allowable skew between device secondary (allowable clock skew ns). Keep these secondary clock routes between inches provide skew less than
Figure
Add-in Card Example Configuration
notes
P_CLK from Edge Connector
Intel® 80312 S_CLK1 Companion Chip
S_CLK5 R_CLKIN R_CLKOUT
S_CLK0
Secondary Device
Secondary Device
Secondary Device
NOTES: Trace length between source component resistor must inch. resistor values Ohms. inches
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Layout Guidelines Motherboards
motherboard implementations, designer much more flexibility with clocking, primarily related controlling central clock resources. Skew requirements motherboard more stringent uncertainty having edge connectors secondary bus. motherboard implementation designs, best choose central clocking resource with enough clock outputs drive devices, including 80312 processor companion chip P_CLK. trace lengths should equalized minimize clock skew. 80312 processor companion chip provides secondary clocks (S_CLK[5:0], R_CLKIN R_CLKOUT) secondary devices connected secondary bus. trace lengths should equalized minimize clock skew. R_CLKIN should directly connected R_CLKOUT trace length should match S_CLK[5:0]. Keep secondary clock routes between inches maintain skew. Refer Figure clock configuration example. minimize skew these designs, following equation trace length (see Figure 29):
Equation Equation Equation Equation
Inches Inches C=E=F S_CLK[5:0] R_CLKOUT should kept within inches. Also, since implementations varied, each design must simulated meet specifications Local Specification, Revision 2.2. minimize skew, clocks connectors should inches shorter than traces routed motherboard devices.
Figure
Motherboard Example Configuration
Central Clock Resource Primary Connector DEVICE
2.5"
Secondary
P_CLK
Device
Intel® 80312 S_CLK1 Companion Chip S_CLK5
R_CLKIN R_CLKOUT
S_CLK0
Secondary Connector
DEVICE
2.5"
P_CLK Secondary Device
NOTES: Trace length between source component resistor must inch. resistor values Ohms. length feedback path
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Intel® 80200 Processor Signals Requiring Pull-Up/Down Resistors
Table identifies signals that require pull-up and/or pull-down resistors recommended resistor values.
Table
Intel® 80200 Processor Signals
Signal HOLD PLLCFG FIQ# IRQ# TRST# Resistor Value Ohms) 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K Pull-up Pull-down pull-down pull-down pull-up pull-up pull-up pull-down Alternatively this signal tied C_RESET#. Unless another master sharing Intel® 80200 processor bus. Comments
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Intel® 80312 Companion Chip Signals Requiring Pull-Up/Down Resistors
Table through Table identify signals that require pull-up and/or pull-down resistors recommended resistor values.
Table
Memory Controller, Core JTAG Signals
Signal Resistor Value Ohms) 1.5K Pull-up Pull-down Comments Dependent which reset mode desired. This signal internal pull-up. Dependent which reset mode desired. This signal internal pull-up. Pull-down special downstream window. This signal internal pull-up. Pull-down 32-bit SPCI protocol. This signal internal pull-up. Alternatively this signal tied P_RST#. These pins have internal pull-ups which default make them input pins after reset. When implementing battery back-up circuit SDRAM, this permanently pulled low. There internal pull-up this pin.
RAD[6]/RST_MODE#
pull-down1
RAD[3]/RETRY
1.5K
pull-down1
RAD[2]/SPMEM#
1.5K
pull-down2
RAD[1]/32BITPCI_EN#
1.5K
pull-down3
TRST#
1.5K
pull-down pull-down4
GPIO[7:0]
1.5K
PWRDELAY
1.5K
pull-down
NOTES: Pull-down only other than default Reset Mode required. Pull-down only special downstream memory window required support external Hot-Plug controller. Pull-down only secondary required function 32-bit bus. Pull-down only required output after reset.
Table
Signals
Signal Resistor value Ohms) 2.7K Pull-up Pull-down Comments This signal must have pull-up allow reading SDRAM size. This signal must have pull-up allow reading SDRAM size.
pull-up
2.7K
pull-up
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
Signals
Signal S_SERR# S_TRDY# S_LOCK# S_PERR# S_DEVSEL# FRAME# STOP# IRDY# INTA# INTB# INTC# INTD# REQ0# REQ1# REQ2# REQ3# REQ4# REQ5# S_AD[63:32] S_C/BE[7:4]# S_PAR64 S_REQ64# S_ACK64# S_M66EN SHOLD# Resistor value Ohms) 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 4.7K 8.2K Pull-up Pull-down pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up1 pull-up Comments Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Bus, pull-up will make secondary operate MHz.
NOTES: Pull-up only secondary operate MHz. pull-down required operation.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
10.0
Intel® 80200 Processor Mixed Voltage Design Considerations
There three different voltage domains Intel® 80200 processor:
Analog Supply Voltage Core Supply Voltage Periphery Supply Voltage
Refer Intel® 80200 Processor based Intel® XScaleMicroarchitecture Datasheet power sequencing requirements.
10.1
10.1.1
Core Supply Voltage
Providing System
most system board designs, system power supply routed board components through dedicated board layer. With requirement supply Intel® 80200 processor, necessary completely power supply layer circuit board. possible create "island" underneath processor existing power supply plane. Figure shows example "island" layout. Other important considerations are:
"island" must large enough include required power supply decoupling
capacitance, necessary connection source.
minimize signal degradation, between island plane should
kept minimum: typical size about 0.02 inches.
Minimize number traces routed across power plane gap, since each crossing
introduces signal degradation impedance discontinuity that occurs gap. traces that must cross gap, route them side board next ground plane reduce eliminate signal degradation caused crossing gap. this possible, then route trace cross right angle degrees).
liberal decoupling capacitance between plane island. Decoupling
island reduces impedance discontinuity.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Creating Power "Island"
island
Plane Connection Point Source
Plane
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
10.2
Choosing Power Source
primary concern that must addressed when selecting power source maximum load current requirement. processor power supply must maintain correct voltage regulation. Refer Intel® 80200 Processor based Intel® XScaleMicroarchitecture Datasheet Intel® 80312 Companion Chip Datasheet power requirements. options supplying processor are:
primary system power supply on-board secondary regulation derive from system power supply
on-board secondary regulation, linear regulator performs adequately most designs shown Figure Figure Power Supply Circuit
Intel® 80200 Processor +3.3V Linear Regulator VOUT
heat power dissipation design goal, then higher complexity cost switching regulator warranted. Switching regulators offer better efficiency, thereby lowering regulator power consumption heat. Figure shows recommended layouts power supply linear regulator connection "island." Figure Recommended Power Supply Connection Layout
Regulator (upright) Heatsink
Supply Using Linear Regulator
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
10.2.1
Analog Supply Voltage
reduce clock skew processor, VCCA Phase Lock Loop (PLL) circuit isolated pinout. lowpass filter, shown Figure reduces noise induced clock jitter effects timing relationships system designs. trace lengths between capacitor, 0.01 capacitor, VCCA must short possible.
Figure
VCCA Lowpass Filter
1/8W
(Board Plane)
4.7µF 0.01µF
VCCA (Processor input pin)
10.2.2
Periphery Supply Voltage
periphery supply voltage directly obtained from power plane system board.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
11.0
Intel® 80312 Companion Chip Design Considerations
VCC5REF Requirement (VDIFF)
mixed voltage systems that drive Intel® 80312 companion chip inputs excess CC5REF must connected system's supply. limit current flow into VCC5REF pin, there limit voltage differential between VCC5REF other pins. voltage differential between VCC5REF pins should never exceed 2.25 Meeting this requirement ensures proper operation guarantees component reliability. This limit applies power-up, power-down, steady-state operation. Table outlines this requirement.
11.1
Table
VDIFF Specification Dual Power Supply Requirements (3.3
Symbol VDIFF Parameter VCC5-VCC Difference 2.25 Units Notes VCC5REF input should exceed more than 2.25 during power-up power-down, during steady-state operation.
voltage difference requirements cannot system design limitations, alternate solution employed. shown Figure series resistor used limit current into VCC5REF pin. This resistor ensures that current drawn VCC5REF does exceed maximum rating this pin. Figure VCC5REF Current-Limiting Resistor
(±0.25V) (±5%, VCC5REF
This resistor necessary systems that guarantee DIFF specification. Also, V-only systems systems that drive pins from logic, connect VCC5REF directly plane. Note: This requirement also applies VREF_P VREF_S pins.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
11.2
VCCPLL Pins Requirement
reduce clock skew processor, Phase Lock Loop (PLL) circuit isolated pinout. lowpass filter, shown Figure reduces noise induced clock jitter effects timing relationships system designs. trace lengths between capacitor, 0.01 capacitor, must short possible. There three pins Intel® 80312 companion chip: VCCPLL1, VCCPLL2 VCCPLL3. Each requires lowpass filter. Providing just lowpass filter tying three inputs recommended.
Figure
VCCPLL Lowpass Filter
1/8W
(Board Plane)
4.7µF 0.01µF
VCCPLL (80312 input pin)
11.3
Pull-ups Pull-down Resistors
Intel® 80312 companion chip inputs which require pull-up should have pullup resistor tied appropriate supply voltage. only design, resistor should tied supply. design where Intel® 80312 companion chip interface components operating resistors tied either supply.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
12.0
Processor Power Supply Decoupling
Processor power supply decoupling critical reliable operation. With ready system, areas concern described Section 12.1:
High frequency decoupling, necessitated processor high speed operation frequency decoupling, necessitated processor power saving features
12.1
12.1.1
High Frequency Decoupling
Intel® 80312 Companion Chip
Decoupling capacitors reduce voltage spikes supplying extra current needed during switching. Decoupling especially critical Intel® 80312 companion chip because internal operation. reliable design will include minimum thirty-two surface mount ceramic chip capacitors between power ground, evenly distributed, around Intel® 80312 companion chip. capacitors must placed close processor possible, attached directly power ground planes, otherwise circuit board inductance will significantly reduce their effectiveness. Figure example place high frequency capacitors back (solder) side motherboard add-in card. package Figure shown reference only; normally visible from back side. When design does permit components back side PCB, place decoupling capacitors around perimeter component side PCB. Inadequate high frequency decoupling results unreliable inconsistent program behavior. These failures often intermittent, difficult diagnose debug.
12.1.2
Intel® 80200 Processor
about twelve surface mount ceramic chip capacitors evenly distributed around Intel® 80200 processor package.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
High-Frequency Capacitor Values Layout Intel® 80312 Companion Chip
Note: 0.1µF Capacitor
A7692-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
13.0
Intel® 80312 Companion Chip Based Reference Design
Appendix schematics Appendix bill material. Schematic files evaluation board available supplied upon request.
14.0
Debug Connector Recommendations
This section describes debug hardware connectors developed Intel® 80312 companion chip. This includes sockets, headers, logic analyzer interposer, Mictor* signal cross reference lists JTAG emulator debug connector/pin assignments.
14.1
PBGA Sockets Headers
Figure Figure illustrate surface mount sockets headers available Intel® 80312 companion chip. Table socket header vendor information.
Figure
540L PBGA Header
.062 inch Chamfer
.060 inch 1.67 inch View Side View
.158 inch
A5858-02
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
540L PBGA Socket
.340 inch inch Chamfer
.125 inch
.812 inch .667 inch .312 inch .062 inch .062 inch 1.674 inch Side View View
A5857-02
.050 inch
.193 inch
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
14.2
Logic Analyzer Connectivity
Mictor connector common connector used Intel® 80312 companion chip logic analysis connectivity. Intel® IQ80310 Evaluation Platform Board developed Intel® 80200 processor, integrates five Mictor connectors route appropriate signals logic analysis probing. Table removable interposer available designs that have available board space Mictor connectors. Figure Figure Figure Refer Table logic analyzer interposer vendor information. Table shows signal cross-references Intel® 80312 companion chip and, associated Mictor connectors Cyclone* board flex tape interposer. Pins1,2,37 used.
Table
Logic Analyzer Header Definitions (Mictor)
Cyclone Interposer DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 Interposer SDQM7 SDQM6 SDQM5 SDQM4 SDQM3 SDQM2 SDQM1 SDQM0 SCB7 SCB6 SCB5 SCB4 SCB3 SCB2 SCB1 SCB0 SA10 SA11 SA12 SRAS# SCAS# SWE# Interposer DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Interposer C_CLK SHOLD# SHOLDA# C_RESETOUT# C_FIQ# C_IRQ# C_RESET# C_ADS# C_LOCK# C_W/R# ABORT DVALID SCE0# SCE1# SBA1 SBA0 CA10 CA11 CA12 CA13 CA14 CA15 MCLK Interposer RAD15 RAD14 RAD13 RAD12 RAD11 RAD10 RAD9 RAD8 RAD7 RAD6 RAD5 RAD4 RAD3 RAD2 RAD1 RAD0 RAD16 RALE RCE0# RCE1# ROE# RWE# I_RST# RALE Cyclone Cyclone Cyclone Cyclone
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
14.3
14.3.1
JTAG Connector Test Interface
Intel® 80200 Processor JTAG Emulators
JTAG emulators Intel® 80200 processor were designed provide convenient non-intrusive means debugging. There JTAG emulators, from Multi-ICE which uses 20-pin connector other from Windriver* which uses 30-pin connector. JTAG emulator provides designer ability download code, read data from registers, single-step processor, insert breakpoints (both hardware software) perform full source level debugging without need intrusive monitor program bulky hardware pod.
14.3.2
Intel® 80200 Processor Target Debug Interface Connector Multi-ICE Emulator
Intel® 80200 processor target should have 20-pin, header connector. BERG* part number 54102-S06-20 equivalent. header made rows pins spacing between adjacent pins between rows 0.100". header assignment illustrated Figure
Figure
Multi-ICE JTAG Emulator Connector (Top View)
0.1"
0.1"
A8016-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table describes interconnections required between target debug interface connector pins/balls Intel® 80200 processor. Table Intel® 80200 Processor Debug Connector Wiring Multi-ICE Emulator
Header Intel® 80200 Processor Ball/Direction Signal Name nTRST RTCK nSRST Connect Recommended Target Resistor
14.3.3
Intel® 80200 Processor Target Debug Interface Connector Windriver Emulator
Intel® 80200 processor target should have 30-pin, header connector. Santec* part number TFM-115-22-S-D-LC equivalent. header made rows pins spacing between adjacent pins between rows 0.100". header assignment illustrated Figure
Figure
Windriver JTAG Emulator Connector (Top View)
0.050" 0.050"
A8015-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table describes interconnections required between target debug interface connector pins/balls Intel® 80200 processor. Table Intel® 80200 Processor Debug Connector Wiring Windriver Emulator
Header NOTES: ICE_RST# generated JTAG debugger. AG32 Intel® 80200 Processor Ball/Direction Intel® 80312 Companion Chip Ball/Direction Signal Name nTRST RWE# ICE_RST#1 RCE0# RAD9 RAD10 RAD11 RAD12 RAD13 RAD14 RAD15 RAD16 RAD6 RAD3 RAD4 ROE# RAD5 Recommended Target Resistor
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
14.3.4
JTAG Emulator Reset Circuit
This section describes nSRST nTRST signals emulator implemented. emulator both drive also able monitor nSRST. driving nSRST emulator issue system reset. monitoring nSRST debugger determine system reset occured. nTRST must designed that both system debugger issue reset JTAG port.
Figure
Emulator Reset Circuit
PCI_RST#
P_RST#
80312)
(to/from JTAG Connector) nSRST
A8021-01
14.3.5
Other Tools
Other tools available that designed complement JTAG emulators. These include full complement boundary-scan hardware software testing Intel® 80200 processor opens, shorts, other manufacturing defects once been installed onto target board.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
15.0
Design Manufacturability
Intel® 80312 companion chip offered high-thermal (HL-PBGA) package. PBGA packaging explained extensively Intel® Packaging Databook (Order Number 240800).
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
16.0
Thermal Solutions
general, three factors affect thermal performance BGA: package board materials, package geometry environment. HL-PBGA package utilizes heat spreader slug across package dissipate heat efficiently. Environmental conditions play critical role thermal performance PBGAs. Ambient conditions, junction case temperatures, device's placement orientation board, conjunction with volume temperature flowing past unit present broad range possible thermal solutions. profiles HL-PBGA package characterized Table
Table
H-PBGA Package Characteristics
Description Junction temperature Case Temperature (optimal) Ambient temperature Airflow motherboard) from system Airflow add-in card) Passive heatsink dimensions Acceptable flange adds side hole direction Maximum heatsink thickness Clip Hole Pattern Heatsink Flatness Criteria (worst case) (worst case) Clip (thickness) Flange type (thickness) with pins. holes (3.175 diameter), 48.4632 34.798 rectangular (see Figure Figure From center heatsink inch directions, mils maximum
16.1
Thermal Recommendations
Based data Intel gathered while performing thermal validation, 80310 processor companion chipset does require heat sink. tests were performed environment with airflow, ambient temperature with processor executing maximum power test. However, case temperature (108 exceeded, passive heat sink used. Information regarding heat sinks provided Section 16.2.
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
16.2
3-Dimensional View: Processor With Heat Sink Attached
assist board designer component placement, hole placement dimensions, Figure Figure detail specifics. Figure details dimensions board designs requiring Passive Heat Sink.
Figure
Conceptual View Processor with Heat Sink
Push Pins Single-fan Active Heatsink
Heatsink Flange
Heat Slug Package
Customer's Board
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
16.3
Figure
Heatsink Hole Dimensions
Hole Dimensions Passive Heatsink
2.98 Holes diameter 3.175 0.0508 48.4632
25.4 Outline Passive Heat Sink Heat Slug Intel® 80312 (over component) 34.798 25.4 Package: 42.5 42.5
5.10
View
Clips
Flange uses pins
Heat Slug Board
Side View
Spring Heat Sink Thermal Interface Material Board Heat Slug Balls
NOTES: sides H-PBGA package electrically conductive; traces edge package. Therefore, materials allowed contact sides this package time, including during shock vibration testing. Heatsink actual dimensions vary depending vendor (see Table 16).
A8306-01
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Figure
Board Level Keep Areas
Trace Keep-Out Areas
Heat Sink Area Keep-Out Area 3.81 (Top Bottom View) Clip Keep-Out Area (Bottom View) Mounting hole diameter 3.175 0.0508
Periphery Components Keep-Out Area [Top View]
Trace Component Keep Area 3.81
Component Keep Area except when component height less than height package Package
A5878-02
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
16.4
Figure
Clearances Board Components
Clearances Board Components
Add-in card Heat sink mounted package Add-in card
Heat sink mounted processor Add-in Card
Maximum allowable component dimension backside Local Specification 2.1)
106.68 height
15.49
6.35
1.57 2.67
Connector
Motherboard
14.48 18.72 total overall dimension
Side View
Note: add-in cards assumed adjacent slots.
A5853-03
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
16.5
Heat Sink Information
Table provides list suggested sources heat sinks. This neither endorsement warranty performance listed products and/or companies.
Table
Heat Sink Vendors Contacts
Heatsink Part Company Factory Phone Passive THERMALLOY, 2021 Valley View Lane Dallas Texas 75234-8993 Email:sales@thermalloyusa.com Outside USA, refer page contact information: http://www.thermalloy.com Attn: Sales (972) 243-4321 (972) 241-4656 21933 thermal grease (uses pins) 21935 with Easy (thermal grease (uses pins)
16.5.1
Socket Information
Table Table provide vendor details socket-headers burn-in sockets Intel® 80312 companion chip. This neither endorsement warranty performance listed products and/or companies.
16.5.2
Table
Socket-Header Vendor
Socket-Header Vendor
Part Company Factory Rep. Phone/Fax 540-Pin Header Adapter Technologies, Inc. 214-218 South Perkasie, 18944 www.adapter-tech.com 540-Pin Socket Carrier
Attn: Sales
215-258-5750/ 215-258-5760
BGAH-540-0-01-3201 -0277-1
BGA-540-0-02-32010275P-130
16.5.3
Table
Burn-in Socket Vendor
Burn-in Socket Vendor
Company Texas Instruments Forbes Blvd. Mansfield, 02048 Factory Representative Attn: Sales Phone Burn-in Socket Part ULGA540-005
508-236-5375
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
16.5.4
Table
Shipping Tray Vendor
Shipping Tray Vendor
Company Factory Attn: Sales Phone 602-465-5381 Shipping Tray Part 7-0000-21001-184-167
16.5.5
Table
JTAG Emulator Vendor
JTAG Emulator Vendor
Company ARM, Ltd. www.arm.com Wind River visionPROBE/visionICE Intel® XScaleMicroarchitecture www.windriver.com Part Multi-ICE* interface Unit KP1-0019A
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
17.0
17.1
References
Related Documents
Intel documentation available from your local Intel Sales Representative Intel Literature Sales. obtain Intel literature write call: Intel Corporation Literature Sales P.O. 5937 Denver, 80217-9808 1-800-548-4725 visit Intel's website http://www.intel.com
Table
Related Documentation
Document Title Intel Order 273411 273414 273410 273425 240800 Special Interest Group 1-800-433-5177 http://developer.intel.com/ technology/memory Special Interest Group 1-800-433-5177
Intel®
80200 Processor based Intel XScale
Microarchitecture Developer's Manual Microarchitecture Datasheet
Intel 80200 Processor based Intel XScale
Intel 80312 Companion Chip Developer's Manual Intel® 80312 Companion Chip Datasheet Intel Packaging Databook Local Specification, Revision 4-Clock 72-bit Unbuffered SDRAM DIMM Specification PCI-to-PCI Bridge Architecture Specification, Revision
17.2
Table
Electronic Information
Electronic Information
Intel's World-Wide (WWW) Location: Customer Support Canada): http://www.intel.com 800-628-8686
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Appendix Intel® 80312 Companion Chip Schematics
following pages (Figure through Figure contain schematics Intel® 80312 Companion Chip.
CAP0805 0.1uF CAP0805 0.1uF
CAP0805 0.1uF
TP10
DECOUPLING
CAP0805 0.1uF C156
Figure
80312/Coyanosa DECOUPLING SPCI DECOUPLING SDRAM DECOUPLING
DECOUPLING
SDRAM3V {8,15,16,17} CAP0805 0.1uF C100 CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF C107 CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF C108 CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF C104 CAP0805 0.1uF C102 CAP0805 0.1uF
CAP0805 0.1uF C117 CAP0805 0.1uF C116 CAP0805 0.1uF C176 CAP0805 0.1uF C123 CAP0805 0.1uF C164 CAP0805 0.1uF C140 CAP0805 0.1uF C163 CAP0805 0.1uF C168 CAP0805 0.1uF C184 CAP0805 0.1uF C155 CAP0805 0.1uF C186 CAP0805 0.1uF C152 CAP0805 0.1uF C174 CAP0805 0.1uF C173 CAP0805 0.1uF C178 CAP0805 0.1uF CAP0805 0.1uF C126 CAP0805 0.1uF C134 CAPT7343 47uF C143 CAP0805 0.1uF C172 CAP0805 0.1uF C185 CAP0805 0.1uF C167
C183
C118
C139
C161
CAP0805 0.01uF CAP0805 0.01uF
Decoupling Schematic
CAPT7343 47uF
CAP0805 0.1uF C154
CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF C146 CAP0805 0.1uF C147
CAP0805 0.1uF
CAP0805 0.1uF C112
CAP0805 0.1uF C128
CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF
CAP0805 0.01uF C101 CAP0805 0.01uF C109 CAP0805 0.01uF
CAP0805 0.1uF C153
CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF C160
C180
CAP0805 0.1uF CAP0805 0.1uF C119 CAPT7343 47uF C188 CAP0805 0.1uF C148 COYANOSA_CORE_VCC {18} CAP0805 0.1uF C149 CAP0805 0.1uF C150 CAP0805 0.1uF C121 CAP0805 0.1uF C110 CAP0805 0.1uF CAP0805 0.1uF C157 CAP0805 0.1uF C165 CAP0805 0.1uF C138 CAP0805 0.1uF C136 CAP0805 0.1uF C177 CAP0805 0.1uF C175 CAP0805 0.1uF CAP0805 0.1uF C137 CAP0805 0.1uF CAP0805 0.1uF C144 CAP0805 0.1uF C127 CAP0805 0.1uF C132 CAP0805 0.1uF C171 CAP0805 0.1uF CAP0805 0.1uF C169 CAP0805 0.1uF C170 CAP0805 0.1uF CAP0805 0.1uF C159 CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF C141 CAP0805 0.1uF C162 CAP0805 0.1uF C181 CAP0805 0.1uF
CAP0805 0.1uF C114
CAP0805 0.1uF C129
CAP0805 0.1uF C135 CAP0805 0.1uF C142 CAP0805 0.1uF C187 CAP0805 0.1uF C182 CAP0805 0.1uF CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF C113
CAP0805 0.01uF C158 CAP0805 0.01uF C133 CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.1uF CAP0805 0.01uF C131 CAP0805 0.01uF C151 CAP0805 0.01uF COYANOSA_CORE_VCC {18}
CAP0805 0.1uF C124
CAP0805 0.1uF C115
CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF C111
CAP0805 0.1uF
CAP0805 0.1uF C120
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
CAP0805 0.1uF C122
CAP0805 0.1uF
CAP0805 0.1uF
CAP0805 0.1uF
Figure
V_IO_A
V_IO_B
V_IO_C
V_IO_D
V_IO_E
V_IO_F
-12V TRST# CONNPCI_B GND1 +5V1 PINTA# +5V2 PINTB# INTB# PINTD# INTD# PRSNT1# V_I/O1 PRSNT2# CONNPCI_B GND1 PC/BE6# PC/BE4# GND4 PRST# V_IO_B V_I/O2 PGNT# GND5 PREQ# REQ# V_IO_B V_I/O PAD31 PAD29 AH20 PPAR64 AD31 AD29 PAD28 GND6 PAD27 AD27 PAD25 AD25 PAD24 +3V1 PC/BE3# C/BE3# PAD23 AD23 PAD22 GND7 312_CLK PAD21 AD21 PAD19 AD19 PAD18 +3V2 AM20 PAD16 CONNPCI_B PFRAME# GND1 PIRDY# IRDY# +3V1 PDEVSEL# DEVSEL# GND2 PLOCK# LOCK# PPERR# PERR# +3V2 PSERR# SERR# +3V3 PC/BE1# PAD14 AD14 GND3 PAD12 PAD10 AD12 AD10 M66EN PAD9 GND4 PAD11 AD11 PAD13 AD13 C/BE1# +3V3 PAD15 AD15 PPAR GND3 SBO# GND8 SDONE +3V2 PSTOP# STOP# GND7 PAD32 GND2 PAD33 AD33 PTRDY# TRDY# PAD35 AD35 PAD34 GND1 V_IO_F V_I/O3 PAD36 AD18 PAD41 AD41 VREF_P PC/BE2# AD17 C/BE2# PAD17 CONNPCI_A PAD39 FRAME# PAD37 AD37 AD39 GND6 PAD38 PAD40 AD16 +3V1 GND5 PAD43 AD43 PAD20 AD20 GND5 PAD42 PAD45 AD45 PAD44 AH17 AD22 +3V2 PAD47 AD47 PIDSEL IDSEL V_IO_E V_I/O2 PAD46 AD24 PAD49 AD49 PAD48 GND4 PAD51 AD51 AD26 GND4 PAD50 PAD26 AD28 PAD53 AD53 PAD52 AD30 +3V1 PAD55 PAD30 PAD57 AD57 GND3 AD55 PAD56 PAD54 GND3 PAD59 AD59 GNT# V_IO_D V_I/O1 PAD58 PAD61 AD61 PAD60 PAD63 RST# PCLK C/BE6# C/BE4# GND2 AD63 V_IO_A +5V2 INTC# PINTC# INTA# +5V1 +12V CONNPCI_A 0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
47uF CAPT7343
PAD63
PAD62
PAD61
PAD60
PAD59
PAD58
PAD57
PAD56
PAD55
PAD54
PAD53
PAD52
PAD51
PAD50
PAD49
PAD48
PAD47
PAD46
PAD45
PAD44
PAD43
PAD42
PAD41
PAD40
PAD39
PAD38
PAD37
PAD36
PAD35
PAD34
PAD33
PAD32
AL22
AJ21
AM23
AH21
AL23
AK22
AM24
AH22
AK24
AJ23
AM25
AJ24
AM26
AH24
AM27
AJ25
AL27
AH25
AM28
AK26
AK28
AH26
AM29
AJ27
AL29
AH27
AM30
AJ28
P_AD63
P_AD62
P_AD61
P_AD60
P_AD59
P_AD58
P_AD57
P_AD56
P_AD55
P_AD54
P_AD53
P_AD52 AH23 AL25
P_AD51
P_AD50
P_AD49
P_AD48
P_AD47
P_AD46
P_AD45
P_AD44
P_AD43
P_AD42
P_AD41
P_AD40
P_AD39
P_AD38
P_AD37
P_AD36
P_AD35
P_AD34
P_AD33 AL30 AH28
P_AD32
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD0
AK10
AM10
AH10 P_AD20 AL10 P_AD19 AJ11 P_AD18 AM11 P_AD17 AH11 P_AD16 AK14 P_AD15 AL15 P_AD14 AH14 P_AD13 AM16 P_AD12 AJ15 P_AD11 AK16 P_AD10 AH15 P_AD9 AL17 P_AD8 AM18 P_AD7 AH16 P_AD6 AL18 P_AD5 AJ17 P_AD4 AM19 P_AD3 AK18 P_AD2 AL19 P_AD1
AH18
PAD9
PAD8
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD31
PAD30
PAD29
PAD28
PAD27
PAD26
PAD25
PAD24
PAD23
PAD22
PAD21
PAD20
PAD19
PAD18
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD0
PPCI +12V N12V GND1 CONNPCI_A PC/BE7# PC/BE5# V_IO_D PPAR64 PAD62 C/BE7# C/BE5# V_I/O1 PAR64 AD62 GND2 AD60 AD58 GND3 AD56 AD54 V_IO_E V_I/O2 AD52 AD50 GND4 AD48 AD46 GND5 AD44 AD42 V_IO_F V_I/O3 AD40 AD38 GND6 AD36 AD34 GND7 AD32 GND8 YAVAPAI PRIMARY SIGNALS PINTA# P_INTA PINTB# P_INTB PINTC# P_INTC PINTD# P_INTD
PPCI
PC/BE0#
AJ16
PC/BE1#
PC/BE2#
PC/BE3#
Primary Interface Schematic
PC/BE4# P_PAR64
PC/BE5#
PC/BE6#
PC/BE7#
P_C/BE0 AM15 P_C/BE1 AL11 P_C/BE2 P_C/BE3 AM22 P_C/BE4 AK20 P_C/BE5 AL21 P_C/BE6 AH19 P_C/BE7
PFRAME#
AJ12
P_FRAME
AL13 PPERR# P_PERR AM14 PSERR# P_SERR AJ19 PREQ64# P_REQ64 AM21PACK64# P_ACK64
PDEVSEL# AK12
PIRDY# P_CLK AM17 P_M66EN
PTRDY#
PSTOP#
PIDSEL
PPAR VREF_P
PREQ#
PGNT#
P_DEVSEL AM12 P_IRDY AH12 P_TRDY AJ13 P_STOP P_IDSEL AH13 P_PAR P_REQ P_GNT
P_RST ZRST# {17} PLOCK# AM13 P_LOCK
CAP0805 0.01uF SWDIP4 P_M66EN 312_CLK PAD3 PAD5 S_M66EN {3,6,9,11,12} PAD7 PAD8
Note: provisional.
P16C2502
FB_IN
FB_OUT
PCLK
+3V4 PAD1 V_IO_C GND4 V_I/O
PC/BE0#
C/BE0# +3V4 PAD6 PAD4 GND5 PAD2 PAD0 V_IO_C V_I/O
CLK_IN
CLK_OUT
1/10W VREF_P
V_IO_C
PACK64#
ACK64# +5V2 +5V3
PREQ64#
REQ64# +5V2 +5V3 PRIMARY INTERFACE
1/2W
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
4.7K 1/10W
R114
RCE0# M4A3-192/96-10VC 1/10W SCB7 SCB6 ROMA SCB5 SCB4 SCB3 SCB2 SCB1 SCB0 SPCI {9,11,12,14} IRQUART1 S_M66EN {2,6,9,11,12} PAL_CLK I_RST# {4,6,7,9} DQ32
R115 PART #101-2911-01
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
SA12 SA12 SA11 YAVAPAI MEMORY CONTROLLER SA10 ROE# RWE# RCE0# RCE1# RALE
DQ33
RAD16 RAD15 RAD14 RAD13 ICE_TRST# RAD12 RAD11 RAD10 RAD9 RAD8 RAD7 RAD6/RST_MODE# RAD5 RAD4/STEST RAD3/RETRY RAD2/SPMEM# RAD1/32BITPCI_EN# RAD0 DCLK0 DCLK1 DCLK2 {7,8} DCLK3 XINT3# RNC4R8P TP11 TP12 TP13 TP14 JUMP1X2 PPCI ICE_RST# 4.7K 1/10W
Memory Controller Schematic
AG32 RCE0 AG31 RCE1 AF32 RALE
IRQUART0 ETHERNET_INT# {13} SWITCH_B SWITCH_A BP_DET# BATT_DISCHRG {15} BATT_CHRG {15} BATT_PRES# {15} ICE_CE#
SBA0 SBA1 SRAS SCAS SCE0 SCE1 SCKE0 SCKE1
SBA0
1/10W
DQ31
DQ30
DQ29
DQ28
C125
DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
20PF CAP1206
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
RAD0 1.5K
MEMORY CONTROLLER
{4,5,6,7} CAP0805 0.1uF RST# {17} SELUART0# SCB7 SCB6 SCB5 SCB4 SCB3 SCB2 SCB1 SCB0 TRST# {10} ROEAG28 AF30 SEL_LED0# IOR# SEL_LED1# RAD15 {4,5,6,7} SDQM7 SDQM6 SDQM5 SDQM4 SDQM3 SDQM2 SDQM1 SDQM0 DCLK0 IOW# RAD16 AC32 AD28 RAD15 AD30 RAD14 AD32 RAD13 AE28 RAD12 AE31 RAD11 AE32 RAD10 AF29 RAD9 RAD8 AA32 RAD7 AB28 RAD6/RST_MODE# AB29 RAD5/ONCE# AB30 RAD4/STEST AB32 RAD3/RETRY AC28 RAD2/SPMEM# AC29 RAD1/32BITPCI_EN# AC31 RAD0 RAD12 ICE_OE# RAD10 SELUART1# RAD11 DCLKIN DCLK1 DCLK2 DCLK3 RWE# ROMA19 ROMA18 ROMA17 ROMA16 RAD16 RAD14 SINTD# I/O0 I/01 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 PRST# I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 RAD13 I/O40 RAD9 I/O41 I/O42 I/O43 CLK0 CLK1 CLK2 CLK3 TMS35 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 I/O87134 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 I/O79 I/O78116 I/O77 I/O76 I/O75 I/O74 I/O73 I/O72 I/O71 I/O70 I/O69102 I/O68 I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 I/O5988 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 I/O51 I/O5076 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 RNC4R8P SWDIP4 RAD6/RST_MODE# RAD3/RETRY RAD2/SPMEM# RAD1/32BITPCI_EN#
Figure
SDRAM {7,8,10}
SA11
SA10
SBA1
SRAS#
SCAS#
SWE#
SCE0#
SCE1#
SCKE0 {8,17}
1/10W
SCKE1 {8,17}
1/10W
R112
DCLKOUT DCLKOUT
1/10W
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
DCLKIN
Figure
RNC4R8P
{3,5,6,7}
2.7K
ROMA
1/10W
RC28F640J3A-120 ROMA20 ROMA22 ROMA19 ROMA21 ROMA18 ROMA20 ROMA17 ROMA19 I_RST# {3,6,7,9} ROMA17 ROMA16 ROMA13 ROMA12 ROMA11 ROE# RWE# RAD10 RAD9 1/10W RAD11 RCE1# RAD12 RAD13 RAD0 RAD14 4.7K 1/10W RAD1/32BITPCI_EN# RAD15 RAD2/SPMEM# RAD16 RAD3/RETRY RAD4/STEST RAD5 RAD6/RST_MODE# ICE_OE# RAD7 RAD8 ROMA9 RAD16 ROMA10 RAD14 ROMA14 ROMA15 ICE_CE# ICE_RST# ROMA18 {10} VPEN BYTE
2.7K 1/10W
R111
RAD6/RST_MODE#
1/10W
R128
RAD7
ROMA21
74LVC573 ROMA16 ROMA15 ROMA14 ROMA13 ROMA12 ROMA11 ROMA10 ROMA9 SWITCH_A SWITCH_B 74LVC573 ROMA22 SWROTHEX-C
RAD16
RAD15
RAD14
RAD13
RAD12
RAD11
RAD10
RAD9
Flash ROM/Boot Select Schematic
RALE
RAD8
HEADER 2X15 SMT/SHR RAD10 RAD12 RAD6/RST_MODE# {10} ICE_TRST# {10} {10} RAD3/RETRY RAD4/STEST RAD5 RAD9 RAD11 RAD13 RAD15 RWE#
RAD5
RAD4/STEST
RAD3/RETRY
RALE
FLASH ROM/BOOT SELECT
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
CONNJ6SMT RAD12 RAD2/SPMEM# RAD0 RXCLK SELUART0# IOR# IOW# DDIS IRQUART0 XTAL1 XTAL2 TXRDY RXRDY BAUDOUT RAD1/32BITPCI_EN# RAD10 RAD9 RAD11 C1RAD14 RAD13 RAD15
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
RAD15 RAD9 RAD2/SPMEM# RAD1/32BITPCI_EN# RAD0 RXCLK BAUDOUT IOR# IOW# DDIS XTAL1 XTAL2 UART1_CLK TXRDY RXRDY SELUART1# RAD11 RAD10 RAD12 RAD13 RAD14
0.1uF CAP0805
0.1uF CAP0805
0.1uF CAP0805
C111
0.1uF CAP0805
OSC1.8432MHZSMT3.3V RNC4R8P UART1_CLK MAX3232E 16C550C {3,4,6,7} RAD16 VR42 UART0_CLK
Figure
UART Schematic
MAX3232E 16C550C {3,4,6,7} RAD16
CONNJ6SMT
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
IRQUART1
UART
Figure
LEDA1
LEDB1
LEDA2
LEDF1
LEDG1
LEDF2
LEDB2
LEDDP2
74LVTH273 RAD9 RAD10 RAD11 RAD12 RAD13 LEDE1 LEDF1 S_M66EN {2,3,9,11,12} LEDG1 LEDDP1 74LVTH273 RAD9 RAD10 LEDC2 RAD12 LEDE2 LEDF2 LEDG2 LEDDP2 RAD14 RAD13 LEDD2 RAD11 LEDB2 LEDA2 HDSP-G211 RAD16 RAD14 RAD15 LEDD1 LEDC1 LEDB1 P_M66EN LEDA1
RNC4R8P
RNC4R8P
RAD15 RAD16 RNC4R8P RNC4R8P
LEDE1
LEDD1
LEDC1
LEDE2
LEDD2
LEDG2
LEDDP1
LEDC2
LEDs Schematic
1/10W 74LVC04 1/10W 74LVC04 GREEN GREEN
{3,4,5,7}
SEL_LED0#
1/10W
GREEN
I_RST# {3,4,7,9}
SEL_LED1#
SPARES
74LVC04 74LVC04
LEDs
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
{3,4,5,6} MICTOR MICTOR C_CLK {10} CLK0 SCB7 SCB6 SCB5 SCB4 SCE0# SCB3 SCE1# SCB2 SCB1 SBA0 SCB0 CLK1 DCLK2 {3,8} DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 GND1 GND2 GND3 GND4 GND5 DQ48 GND5 GND5 DQ49 GND4 GND4 GND5 RAD16 GND5 DQ50 GND3 GND3 GND4 GND4 DQ51 GND2 GND2 GND3 GND3 GND2 RALE GND2 GND1 GND1 GND1 RCE1# GND1 RCE0# ROE# {10} RWE# I_RST# {3,4,6,9} PWRSTATUS0 {10} CA10 SA10 CA11 SA11 CA12 SA12 PLLCFG {10} CA13 SRAS# PWRSTATUS1 {10} CA14 SCAS# CLK1 SWE# MCLK {10} {10} CA15 DQ16 CLK1 RALE CLK1 DQ17 SBA1 DQ18 RAD0 RAD2/SPMEM# RAD1/32BITPCI_EN# DQ19 RAD3/RETRY DQ20 RAD4/STEST DQ21 DVALID {10} RAD5 DQ22 ABORT {10} RAD6/RST_MODE# DQ23 C_W/R# {10} RAD7 DQ24 C_LOCK# {10} RAD8 DQ25 C_ADS# {10} RAD9 DQ26 C_RESET# {10} RAD10 DQ27 C_IRQ# {10} RAD11 DQ28 C_FIQ# {10} RAD12 DQ29 C_RESETOUT# {10} RAD13 DQ30 SHOLDA# RAD14 DQ31 SHOLD# RAD15 CLK0 CLK0 CLK0 MICTOR MICTOR MICTOR
Figure
SDRAM {3,8,10}
CLK0
DQ15
DQ14
DQ13
DQ12
Logic Analyzer Schematic
DQ11
DQ10
CLK1
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
DQ32
LOGIC ANALYZER
Figure
SDRAM3V {1,15,16,17} SDRAM {3,7,10} SDRAM-DIMM168RA GND1 SCE0# DQ33 DQ34 DQ35 VCC1 DQ36 DQ36 DQ37 DQ37 DQ38 SCB2 SCB3 DQ40 GND2 DQ16 DQ41 DQ17 DQ49 DQ50 DQ51 DQ50 DQ18 DQ19 DQ45 DQ45 DQ20 VCC2 DQ46 DQ46 DQ47 DQ47 SCB4 SCKE1 {3,17} SCB5 DQ21 GND3 DQ22 DQ23 VCC3 DQ24 DQ25 DQ26 DQ27 SRAS# DQ28 GND4 DQ29 DQ30 DQ31 DCLK2 {3,7} SBA0 SA11 DCLK1 SA12 VCC8 VCC4 CLK1 GND9 DCLK3 DQ30 DQ29 SA10 SBA1 VCC4 VCC5 CLK0 VCC9 DCLK0 GND4 DQ28 VCC8 SCE1# DQ27 DQ26 SCE0# DQ25 SCAS# DQ24 VCC3 SWE# GND8 DQ23 DQ22 GND3 DQ21 DQ53 DQ54 DQ55 GND7 CKE1 SCB1 DQ15 SCB0 DQ14 DQ15 DQ52 VCC2 DQ20 DQ14 DQ44 DQ43 DQ42 DQ49 DQ48 DQ41 DQ48 GND6 DQ40 SCB7 DQ39 DQ38 DQ39 SCB6 GND2 DQ10 DQ10 DQ11 DQ12 DQ13 DQ13 VCC7 DQ11 DQ12 DQ42 DQ43 DQ44 VCC6 VCC1 DQ35 DQ34 DQ33 SCKE0 {3,17} SCE1# DQ32 DQ32 CKE0 VCC5 CB6136 GND5 GND1 GND5 SDRAM-DIMM168RA
SDRAM 168-Pin DIMM Schematic
GND6 DQ16 DQ17 DQ18 DQ19
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQ51 VCC6 DQ52 NC10 GND7 DQ53 DQ54 DQ55 GND8 DQ56 DQ57 DQ58 DQ59 VCC7 DQ60 DQ61 DQ62 DQ63
DQ31 GND9 CLK2 NC10 NC11
CLK3 NC11 SA2167
SDRAM 168-PIN DIMM
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
SAD63
SAD62
SAD61
SAD60
SAD59
SAD58
SAD57
SAD56
SAD55
SAD54
SAD53
SAD52
SAD51
SAD50
SAD49
SAD48
SAD47
SAD46
SAD45
SAD44
SAD43
SAD42
SAD41
SAD40
SAD39
SAD38
SAD37
SAD36
SAD35
SAD34
SAD33
SAD32
1/10W
S_AD63
S_AD62
S_AD61
S_AD60
S_AD59
S_AD58
S_AD57
S_AD56
S_AD55
S_AD54
S_AD53
S_AD52
S_AD51
S_AD50
S_AD49
S_AD48
S_AD47
S_AD46
S_AD45
S_AD44
S_AD43
S_AD42
S_AD41
S_AD40
S_AD39
S_AD38
S_AD37
S_AD36
S_AD35
S_AD34
S_AD33
S_AD32
4.7K 1/10W
S_AD31
S_AD30
S_AD29
S_AD28
S_AD12
S_AD11
S_AD10
S_AD9
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
P3S_AD8 S_AD7
AC2S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_AD15 S_AD14 S_AD13
S_AD1 S_AD0
PWRDELAY {17} PWRDELAY
SAD9
SAD8
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
SAD31
SAD30
SAD29
SAD28
SAD27
SAD26
SAD25
SAD24
SAD23
SAD22
SAD21
SAD20
SAD19
SAD18
SAD17
SAD16
SAD15
SAD14
SAD13
SAD12
SAD11
SAD10
SAD0
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VCCPLL2 VCCPLL3
1/2W RNC4R8P S_CLK0 S_CLK1 RCLKIN RCLKOUT 1/8W CLKB {11} CLKA {11}
RNC4R8P HEAD2X8
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
0.01uF CAP0805
2.7K 1/10W
RNC4R8P S_CLK3 S_CLK4 E_CLK {12} PAL_CLK
SHOLDA# SHOLD#
1/8W 1/8W
4.7uF CAPT7343
1.5K RNC4R8P
0.01uF CAP0805
HEADER
1.5K 1/10W
4.7uF CAPT7343
0.01uF CAP0805
4.7uF CAPT7343
SPCI {3,11,12,14} RIGHT2X4 BP_DET# S_REQ0 SREQ64# SACK64# S_FRAME YAVAPAI S_REQ4 SECONDARY SIGNALS S_TRDY S_REQ5 SDEVSEL# SRST# SPERR# SLOCK# RNC4R8P R_CLKIN RCLKIN R_CLKOUT RCLKOUT S_HOLD S_HOLDA S_CLK0 S_INTA/XINT0 SINTB# S_INTB/XINT1 S_CLK3 S_INTC/XINT2 S_CLK4 XINT3# S_INTD/XINT3 AJ32 AH32 S_M66EN S_M66EN {2,3,6,11,12} 1/2W AA31 VCC5REF F28VCCPLL1 I_RST I_RST# {3,4,6,7} S_C/BE4 S_C/BE5 VREF_S S_C/BE6 S_C/BE7 AH30 TRST AH31 2.7K SINTC# YAVAPAI INTERRUPT/I2C/JTAG S_CLK1 SINTA# AJ29 AK32 S_PAR S_PAR64 S_C/BE0 S_C/BE1 S_C/BE2 S_C/BE3 RNC4R8P AK31 SINTD# {3,11} SSERR# SSTOP# STRDY# S_IRDY SIRDY# 2.7K R104 S_REQ3 SFRAME# SINTD# S_ACK64 S_REQ2 SINTC# S_REQ64 S_REQ1 SINTB# SINTA# S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_STOP S_DEVSEL S_SERR S_RST S_PERR S_LOCK
Figure
SPCI {3,11,12,14}
SREQ0#
SREQ1#
SREQ2#
SREQ3#
SREQ4#
SREQ5#
SGNT0#
SGNT1#
S_GNT0 S_GNT1
SGNT2#
Secondary PCI/JTAG Schematic
SPAR
SPAR64
SC/BE0#
SC/BE1#
SC/BE2#
S_CLK0 S_CLK1 S_CLK2 S_CLK3 S_CLK4 S_CLK5AH1
SC/BE3#
SC/BE4#
SC/BE5#
SC/BE6#
SC/BE7#
JUMP2X2
1.5K SECONDARY PCI/JTAG
Figure
R108
1/10W
LOCK/LEN1 YAVAPAI COYANOSA REQUEST C_A2 1/10W C_A3 C_A4 C_A5 C_A6 C_A7 C_A8 C_A9 CA10 C_A10 CA11 C_A11 CA12 C_A12 CA13 C_A13 CA14 C_A14 CA15 C_A15 CA15 CA14 CA13 CA12 CA11 CA10 C_A0 C_A1 OSC66.0MHZSMT3.3V R101 C_RESETOUT# PWRSTATUS0 PWRSTATUS1 PLLCFG PLLCFG LOWVPP LOWVCC TRST# TRST PWRSTATUS1 PWRSTATUS0 RESET RESETOUT ADS#/LEN2 C_ADS#/C_LEN2 COYANOSA
C_LOCK/C_LEN1
1/10W
R109
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
1/10W
HOLD MCLK DVALID ABORT SCB0 DCB0 SCB1 DCB1 SCB2 DCB2 SCB3 DCB3 SCB4 DCB4 SCB5 DCB5 SCB6 DCB6 SCB7 DCB7 1/10W 4.7K ABORT DVALID MEMORY MCLK COYANOSA HLDA
T8D28 E1D3
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
INTEL® 80200 /INTEL® 80312
DQ10
C_ADS# C_LOCK# C_W/R# C_RESET# C_FIQ# C_IRQ# C_CLK W/R#/LEN0 C_W/R#/C_LEN0 C_CLK C_IRQ# C_FIQ# C_RESET# C_CLK C_DVALID C_ABORT SDRAM {3,7,8} ODCCTRL0 ODCCTRL1 BYPASS
SWDIP4
RNC4R8P
R100
Intel® 80200 Processor/Intel® 80312 Companion Chip Schematic
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
SAD27 AD27 AD06 SAD4 SAD35 SAD2 SAD0 SAD33 AD05 SAD24 AD03 GND7 GND13 SAD1 AD01 SAD22 +3V10 SAD20 ACK64 REQ64 +5V3 SAD18 +5V4 +12V SAD17 STRST# {14} SC/BE2# C/BE2 SFRAME# GND8 FRAME IRDY STRDY# +3V6 TRDY DEVSEL SINTD# GND9 STOP LOCK SPERR# PERR +3V7 SERR +3V8 SC/BE1# C/BE1 SAD14 AD14 SRST# GND10 SAD12 AD12 SGNT1# AD10 S_M66EN {2,3,6,9,12} SAD30 SAD8 SAD7 C103 GND12 AD08 AD07 +3V9 SAD5 SAD24 SAD17 SAD1 SAD22 SAD20 SACK64# SAD3 AD05 AD03 GND13 AD01 +3V10 ACK64 +5V3 SAD18 +5V4 M66EN GND11 AD09 SAD43 SC/BE0# SAD41 SAD10 GND4 SAD9 SAD45 AD11 SAD47 AD13 SAD11 GND5 GND6 AD31 AD29 SAD28 SAD26 GND7 AD27 AD25 +3V6 C/BE3 AD23 GND8 AD21 AD19 +3V7 AD30 +3V3 SAD13 SAD49 AD15 SAD51 SAD15 GND3 SPAR SAD53 SAD55 SSERR# +3V1 PRSNT2 SDONE +3V2 SAD57 SAD59 SLOCK# GND2 SSTOP# SAD61 SINTB# SDEVSEL# GND1 SAD63 SIRDY# STDI {14} STMS {14} +3V1 SC/BE4# AD17 AD16 SC/BE6# SAD16 CONNPCI_64 3.3V +5V2 +5V1 SACK64# SREQ64# +3V5 AD00 AD02 SAD16 SAD3 AD04 SAD5 AD25 +3V6 C/BE3 AD23 GND8 AD21 AD19 +3V7 CONNPCI_64 3.3V -12V GND4 +5V3 +5V4 INTB INTD PRSNT1 +3V9
SAD26 SAD6 SAD37
0.01uF CAP0805
0.01uF CAP0805
N12V GND9 C/BE7 C/BE6 SC/BE4# C/BE4 +3V1 SPAR64 SAD62 GND10 PAR64 AD63 STRDY# AD61 GND2 SAD60 SINTC# GND9 STOP SAD57 AD57 GND3 GND11 SAD55 AD55 SAD53 AD53 SPAR GND12 SAD15 AD50 SAD49 SAD13 +3V5 SAD11 AD47 SAD45 AD45 SAD9 GND13 SAD43 SAD41 SC/BE0# SAD39 AD37 +3V6 AD35 AD33 GND15 GND8 GND16 CONNPCI_64 3.3V GND1 GND9 C/BE6 C/BE4 GND10 AD63 AD61 +3V4 AD59 AD57 GND11 AD55 AD53 GND12 AD51 AD49 +3V5 AD47 AD45 B82GND13 AD43 AD41 GND14 SAD6 SAD4 SAD39 SAD37 AD39 AD37 +3V6 SAD2 SAD0 SAD35 SAD33 AD35 AD33 GND15 SREQ64# GND8 GND16 SECONDARY GND5 SAD44 SAD42 SAD40 SAD38 AD46 AD48 SAD46 GND4 SAD48 AD50 AD52 SAD50 +3V2 SAD52 AD54 AD56 SAD54 GND3 SAD56 AD58 AD60 SAD58 GND2 SAD60 AD62 PAR64 SAD62 +3V1 SPAR64 C/BE5 C/BE7 SC/BE5# SC/BE7# AD32 GND7 SAD32 AD34 AD36 SAD34 GND6 SAD36 AD39 AD38 GND14 AD07 +3V4 AD40 SAD38 AD43 B84AD41 SAD47 AD51 B78AD49 SAD51 AD15 AD52 SAD50 +3V8 SC/BE1# SAD14 SRST# GND10 SAD12 AD12 SGNT0# AD10 S_M66EN {2,3,6,9,12} SAD30 SAD8 AD08 C/BE0 SAD7 GND11 GND12 M66EN SAD10 GND5 GND6 C/BE1 AD14 +3V2 SAD52 SERR GND3 AD54 +3V7 SSERR# AD56 SAD54 SAD56 PERR +3V1 PRSNT2 SDONE LOCK SPERR# +3V2 SLOCK# AD59 AD58 SSTOP# SAD59 SAD58 +3V4 AD60 DEVSEL GND2 SAD61 +3V6 TRDY SINTA# SDEVSEL# AD62 SAD63 IRDY GND1 SFRAME# GND8 FRAME SIRDY# STDI {14} C/BE2 STMS {14} +3V1 C/BE5 SC/BE5# SAD16 SC/BE6# AD17 SC/BE2# AD16 SC/BE7# CONNPCI_64 3.3V SAD17 STRST# {14} -12V GND4 +5V3 +5V4 INTB INTD PRSNT1 CONNPCI_64 3.3V GND1 CONNPCI_64 3.3V +12V TRST +12V +5V1 INTA INTC +5V2
Figure
SPCI {3,9,12,14}
STCK {14}
SINTB#
SINTD#
C105
CAP0805 0.01uF C106
CAP0805 0.01uF
SPCI CONN
SAD48 SAD46
CLKA
SREQ0#
SAD44 SAD42
+3V2 GND1
SAD31 AD29 SAD28 GND7
+3V5 AD31
+3V3 AD13 AD11 GND4 AD09 GND5 GND6 GND4 AD48 AD46 GND5 AD44 AD42 +3V3
Secondary Schematic
SAD29
SAD40
SAD25
SC/BE3#
SAD23
SAD21
SAD19
AD30A20 +3V3 AD28 AD26 GND2 AD24 IDSEL +3V4 AD22 AD20 GND3 AD18
N12V
STCK {14}
SINTC#
SINTA#
TRST +12V +5V1 INTA INTC +5V2
CAP0805 0.01uF
SPCI CONN
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
CAP0805 0.01uF
CLKB
SREQ1#
+3V5
+3V2 GND1
SAD31
SAD29
SAD27
SAD25
SAD36 SAD34
SC/BE3#
SAD23
SAD32
SAD21
AD44 AD42 +3V3 AD40 AD38 GND6 AD36 AD34 GND7 AD32
SAD19
+3V3 AD28 AD26 GND2 AD24 IDSEL +3V4 AD22 AD20 GND3 AD18
GND5 GND6 C/BE0 +3V4 AD06 AD04 GND7 AD02 AD00 +3V5 REQ64 +5V1 +5V2
SAD31 SAD30 SAD29 SAD28 SAD27 SAD26 SAD25 SAD24 SAD23 SAD22 SAD21 SAD20 SAD19 SAD18 SAD17 SAD16 SAD15 SAD14 SAD13 21154 BRIDGE EAD31 EAD30 EAD29 EAD28 EAD27 EAD26 EAD25 EAD24 EAD23 EAD22 EAD21 EAD20 EAD19 EAD18 EAD17 EAD16 EAD15 EAD14 EAD13 EAD12 EAD11 EAD10 EAD9 EAD8 EAD7 EAD6 EAD5 EAD4 EAD3 EAD2 EAD1 EAD0 SAD12 SAD11 SAD10 SAD9 SAD8 SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0
AA16 P_AD63 AB16 P_AD62 AA17 P_AD61 AB17 P_AD60 P_AD59 AB18 P_AD58 AC18 P_AD57 AA18 P_AD56 AC19 P_AD55 AA19 P_AD54 AB20 P_AD53 P_AD52 AA20 P_AD51 AB21 P_AD50 AC21 P_AD49 AA21 P_AD48 P_AD47 AA23 P_AD46 P_AD45 P_AD44 P_AD43
SAD63 SAD62 SAD61 SAD60 SAD59 SAD58 SAD57 SAD56 SAD55 SAD54 SAD53 SAD52 SAD51 SAD50 SAD49 SAD48 SAD47 SAD46 SAD45 SAD44 SAD43 SAD42 SAD41 SAD40 SAD39 SAD38 SAD37 SAD36 SAD35 SAD34 SAD33 SAD32
P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_AD23 P_AD22 P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 AC10 P_AD10 AA10 P_AD9 P_AD8 AB11 P_AD7 AA11 P_AD6 AA12 P_AD5 AB12 P_AD4 AB13 P_AD3 AA13 P_AD2 P_AD1 AA14 P_AD0
P_AD42 P_AD41 P_AD40 P_AD39 P_AD38 P_AD37 P_AD36 P_AD35 P_AD34 P_AD33 P_AD32
S_AD63 S_AD62 S_AD61 S_AD60 S_AD59 S_AD58 S_AD57 S_AD56 S_AD55 S_AD54 S_AD53 S_AD52 S_AD51 S_AD50 S_AD49 S_AD48 S_AD47 S_AD46 S_AD45 S_AD44 S_AD43 S_AD42 S_AD41 S_AD40 S_AD39 S_AD38 S_AD37 S_AD36 S_AD35 S_AD34 S_AD33 S_AD32
S_VIO
S_PAR
EAD63 EAD62 EAD61 EAD60 EAD59 EAD58 EAD57 EAD56 EAD55 EAD54 EAD53 EAD52 EAD51 EAD50
EAD49 EAD48 EAD47 EAD46 EAD45 EAD44 EAD43 EAD42 EAD41 EAD40 EAD39 EAD38 EAD37 EAD36
EAD35 EAD34 EAD33 EAD32
Figure
21154 Bridge Schematic
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
SAD18 SPAR SSTOP# SGNT2# SREQ2# SC/BE7# SC/BE6# SC/BE5# SC/BE4# SC/BE3# SC/BE2# SC/BE1# SC/BE0# STRDY# SRST# SIRDY# SFRAME# SPCI {3,9,11,14} SDEVSEL# SLOCK# TRST MSK_IN SCLKO_6 SCLKO_5 S_M66ENA S_CFN SCLKO_7 SCLKO_8 SCLKO_9 ETHERNET_CLK {13} SCLKO_4 BPCCE SCLKO_3 SCLKO_2 RNC4R8P SCLKO_1 AC11 P_C/BE0 P_C/BE1 P_C/BE2 P_C/BE3 AC15 P_C/BE4 P_C/BE5 AB15 P_C/BE6 AA15 P_C/BE7 CONFIG66 P_IRDY P_TRDY P_STOP P_IDSEL P_PAR P_REQ P_GNT P_RST P_LOCK GPIO_0 GPIO_1 GPIO_2 GPIO_3 EPAR S_GNT8 SCLK S_GNT4 S_GNT5 S_GNT7 S_GNT6 S_GNT0 S_GNT3 S_GNT2 S_GNT1 S_TRDY S_LOCK S_IRDY S_DEVSEL S_PERR S_SERR S_STOP S_RST ESTOP# ERST# EIRDY# EPERR# ESERR# ETRDY# EDEVSEL# ELOCK# EPAR64 S_PAR64 SCLKO_0 P_FRAME AA6P_DEVSEL P_M66ENA S_M66EN {2,3,6,9,11} P_VIO AB10 21154-BC PCI-TO-PCI BRIDGE PRIMARY SIGNALS P_ACK64 P_PAR64 P_PERR P_SERR P_REQ64AC14 P_CLK E_CLK EGNT0# S_REQ8 SECONDARY SIGNALS S_REQ64 S_FRAME S_ACK64 EACK64# EFRAME# EREQ64# AB14 SACK64# SPAR64 SSERR# EREQ8# S_REQ7 EREQ7# S_REQ6 21154-BC PCI-TO-PCI BRIDGE S_C/BE3 S_C/BE2 S_C/BE1 S_C/BE0 S_C/BE4 S_C/BE5 S_C/BE6 S_C/BE7 EC/BE7# EC/BE6# EC/BE5# EC/BE4# EC/BE3# EC/BE2# EC/BE1# EC/BE0# SPERR# PREQ64# EREQ6# S_REQ5 EREQ5# S_REQ4 EREQ4# S_REQ3 EREQ3# S_REQ2 EREQ2# S_REQ1 EREQ1# S_REQ0 EREQ0# EPCI {13,14}
C130
CAP0805 XXXpF
EAD10 EAD9 RBIAS100 EAD8 RBIAS10 EAD6 EAD5 EAD4 EAD3 EAD2 EAD1 EAD0 I82559ER EAD7 VREF
CAP0805 0.1uF
PERR# SERR# RST# INTA# PME# ISOLATE# ALTRST# CONTROLLER LOCAL MEMORY CLK25/FLA16 EESK/FLA15 EEDO/FLA14 I82559ER CONTROLLER 559VIO CLKRUN# FLD7 TEST TEXEC FLD1 FLD0 FLA0/PCIMODE# SMBD SMBCLK SMBALRT# EECS# FLWE# FLOE# AEN/FLCS# FLA1/AUXPWR FLD2 FLA2 FLD3 FLA3 FLD4 FLA4 FLD5 FLA5 FLD6 FLA6 FLA7/CLKEN IOCHRDY/FLA8 MRST/FLA9 EEDI/FLA13 MCNTSM#/FLA12 MINT/FLA11 MRING#/FLA10
C145
R122
1/10W
R121
1/10W
1/10W
R120
4.7K 1/8W
RNC4R8P
0.1uF CAP0805
R123
R118
1/10W
R117
1/10W 100K
1/10W 2.2K
EC/BE3# EC/BE2# I82559ER EC/BE1# EC/BE0# EAD31 EAD30 EAD29 EAD28 ACTLED# LNKLED# EAD27 EAD26 EAD25 EAD24 R113 1/10W EAD21 EAD20 EAD19 EAD18 EAD17 EAD16 EAD15 R116 EAD13 EAD12 EAD11 1/10W EAD14 EAD23 EAD22 SPEEDLED# LILED# ACTLED# FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL LED2HIGH GREEN BOTTOM CONTROLLER LINE C/BE1# C/BE0# LED2HIGH GREEN CONTROLLER C/BE3# C/BE2# I82559ER CAP0805 18pF CRYSTAL 25.000MHz CAP0805 18pF
Figure
EPCI {12,14}
EFRAME#
ETRDY#
EIRDY#
ESTOP#
EDEVSEL#
EAD16
Ethernet Controller Schematic
EREQ0# REQ# GNT#
EGNT0#
CONN8TJ-XFMR PTC1111-00 NC/SHLD SHLD1 SHLD2 SHLD3 SHLD4
EPAR
EPERR#
ESERR#
ETHERNET_CLK {12}
ERST#
ETHERNET_INT#
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10
93LC46
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
ETHERNET CONTROLLER
R119
1/10W 100K
Figure
EPCI {12,13} RNC4R8P SAD32 SAD33 SAD34 SAD35 SAD55 ESTOP# EAD32 SAD54 EIRDY# EAD34 SAD53 EFRAME# EAD33 SAD52 EREQ0# EAD35 RNC4R8P RNC4R8P RNC4R8P RNC4R8P EAD57 EAD60 EAD54 EAD52 RNC4R8P
SPCI {3,9,11,12}
STDI
STMS
STCK
SPCI Pull-Ups Schematic
STRST#
8.2K RNC4R8P SAD36 SAD37 SAD38 SAD39 SAD59 ESERR# SAD58 ETRDY# SAD57 EDEVSEL# EAD38 EAD37 EAD36 SAD56 EAD39 RNC4R8P RNC4R8P RNC4R8P
8.2K
8.2K
8.2K
8.2K RNC4R8P EC/BE5# EAD61 EAD62 EAD56
8.2K RNC4R8P
SDEVSEL#
STRDY#
SIRDY#
SFRAME#
RNC4R8P SAD40 SAD41 SAD42 SAD43 SAD63 EREQ1# SAD62 EREQ5# SAD61 EREQ8# SAD60 EREQ4# RNC4R8P RNC4R8P RNC4R8P
8.2K
8.2K
8.2K
8.2K
8.2K RNC4R8P EAD42 EAD43 EAD41 EAD40 EAD58 EAD59 EAD55 EAD53
8.2K RNC4R8P
SSERR#
SPERR#
SLOCK#
SSTOP#
8.2K RNC4R8P SAD44 SAD45 SAD46 SAD47 SC/BE7# SC/BE6# SC/BE5# SC/BE4# RNC4R8P RNC4R8P EC/BE6# EREQ64# EAD63 EC/BE7#
8.2K
8.2K
8.2K RNC4R8P EAD50 EAD51 EAD47 EAD44
8.2K RNC4R8P EPERR# ELOCK# EC/BE4# EACK64#
8.2K RNC4R8P
SREQ0#
SREQ1#
SREQ2#
SREQ3#
8.2K RNC4R8P SAD48 SAD49 SAD50 SREQ4# SAD51 1/10W 8.2K 8.2K SREQ5# 8.2K 1/10W 8.2K 8.2K 8.2K 1/10W 8.2K SPAR64 R106 RNC4R8P EREQ6# EREQ2# EREQ3# EREQ7# EAD48 EAD45 EAD46 EAD49 EPAR64 8.2K 8.2K 8.2K RNC4R8P RNC4R8P R107 1/10W 8.2K 8.2K 8.2K
SACK64#
SREQ64#
SPCI PULL-UPS
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
22uF CAPT7343 0.1uF CAP0805 0.1uF CAP0805 1/10W R102 16.5K 1/16W R105
10uF CAPT7343 LM393 MMBT3904 1/16W 1/10W 100K 1/10W LM393 LM393 BATTERY/MONITOR 1/10W BATT_CHRG BATT_PRES# BATT_DISCHRG 1/16W 1/10W
1/16W R103 ISET PROG COMP
1/10W
1.2M 1/16W 1/10W
SI3441DV
COIL-SMT2010 68UH 215K 1/16W 1000pF CAP1206 100K 1/10W 150K 1/16W 1000pF CAP1206 4.7uF CAPT7343 220uF CAPT7343 4.3K 1/16W
4.3K 1/16W MBRS130LT3
V_BATT {16}
53261-0390
+12V SDRAM3V {1,8,16,17}
Figure
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Battery/Monitor Schematic
BATT_REF {16} ADP3801 MBRS130LT3 1/2W CS14 BATA BATB
MK11-2195
BATTERY Li-ion
SPARES
Figure
SI3441DV
1/10W
1/10W
1/16W
R110
SDRAM +3.3 Reference Schematic
MAX6328UR23
RESET
1/16W 4.99K 1/16W 470K
CAP0805 470PF SDRAM3V {1,8,15,17}
100K 1/10W
22uF CAPT7343
LM393
14.7K 1/16W
1/16W
100PF CAP1206
SDRAM3V {1,8,15,17} MAX8863T V_BATT {15} SHDN CAP0805 22PF 1/10W 165K LM385 BATT_REF {15} SDRAM +3.3V REFERENCE
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
1/10W 74LVC08 74LVC32 MMBT3906 SI3441DV SCKE0 {3,8} 74LVC04 MAX921
SCKE Control Schematic
150K 1/16W
HYST
100K 1/10W
1/10W
1/10W
MBRD330
BOARD_PWRDELAY
0.22UF CAPT3216
74LVC08 74LVC14 74LVC14 74LVC14 74LVC08 74LVC32 74LVC14 74LVC08 74LVC32 74LVC08 74LVC14 74LVC08
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
74LVC08 ZRST# SDRAM3V {1,8,15,16} MMBT3906 74LVC08 SCKE1 {3,8} PWRDELAY 74LVC32 MMBT3906 74LVC14 74LVC04
Figure
RST#
SPARES
MMBT3906
SDRAM3V {1,8,15,16}
SCKE CONTROL
Figure
10UH D03316
MAX1644 (1.375V) COYANOSA_CORE_VCC VCC1 VCC2 VCC3 VCC4 PGND2 COMP TOFF R125 10uF CAPT7343 1/16W 49.9K PGND1 SHDN COYANOSA CORE ANALOG SUPPLY C166 FBSEL 2.2uF CAPT3216 470PF CAP0805 R127 R124 220uF CAPT7343 1/2W 1/16W 12.4K
1/2W
R126
0.01uF CAP0805
1/16W 215K
C179 CAPT3216
CAPT7343 4.7uF
Intel® 80200 Processor Core Supply Schematic
CAP0805 0.01uF
VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCCA 1/8W COYANOSA_CORE_VCC INTEL® 80200 CORE SUPPLY
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Appendix Intel® IQ80310 Evaluation Platform Board Bill Materials
This appendix identifies components Intel® IQ80310 Evaluation Platform Board (Table 23). Table Intel® IQ80310 Evaluation Platform Board Bill Materials (Sheet
Item Description IC/SM 74LVC04AD SOIC14 3.3V IC/SM 74LVC08 3.3V TSSOP-14 IC/SM 74LVC14 3.3V TSSOP-14 Manufacturer Texas Instruments Fairchild Semi. Texas Instruments Texas Instruments Philips Fairchild Semi. IC/SM 74LVTH273 TSSOP-20(3.3V) Texas Instruments Fairchild Semi. Texas Instruments U14, IC/SM 74LVC573 SOIC20 Philips Semi Fairchild Semi U20, IC/SM 74C32 TSSOP-14 IC/SM Si3441DV TSOP-6 IC/SM LM393 Power SOIC-8 National Semi. Texas Instruments Motorola National Semi. U2,U10 U11, C125 IC/SM LM385 SOIC-8 IC/SM ADP380 Battery Charger IC/SM MAX6328 SOT23-3 IC/SM MAX1644 SSOP-16 IC/SM MAX921 SOIC-8 IC/SM MAX8863 SOT23-5 M4LV-10VC TQFP VLSI UART 16C550 PLCC 3.3V VLSI 82559ER Enet Cont/Phy VLSI RS232 Transvr 3.3V VLSI Intel 80310 (540BGA) VLSI PCI-PCI 21554-BC PBGA PROCSR Strong BGA241 Flash RC28F640J3A BGA64 MEMORY Serial EPROM 93C46 3.3V 20pf (chip 1206) Texas Instruments Linear Tech. Analog Devices Maxim Maxim Maxim Maxim Lattice Semi Texas Instruments Exar Intel Maxim Intel Intel Intel Intel Microchip Microelectronics LM393M LM393D LM393D LM385M LM385D-1.2 LM385S8-1.2 ADP3801AR MAX6328UR23-T MAX1644EAE MAX921CSA MAX8863TEUK-T M4LV-192/96-10VC TL15C550CFN ST16C550CJ44 82559ER MAX3232ECUP 80310 21154-BC RC28F640J3A-100 93LC46B/SN M93C46-WMN1 Texas Instruments Fairchild Part SN74LVC04D 74LVX04M SN74LVC08APW SN74LVC14APW 74LVC14APWDH 74LCX14MTC SN74LVTH273PW 74LVTH273MTC SN74LVC573ADW 74LVC573AD 74LCX573WM SN74LVC32APW 74LCX32MTC
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
Intel® IQ80310 Evaluation Platform Board Bill Materials (Sheet
Item C45, C40, C57, C58, C68, C188 C32, C47, C52, C54, C10, C44, C31, C48, C59, C62, C75, C85-C87, C92, C94, C95, C101, C103, C105, C106, C109, C131, C133, C151, C158, C179, C180 "C1-C9,C11-C23 C26-C30, C35-C38, C41, C51, C53, C63-C67, C69, C73, C74, C76-C84 C88-C91, C96-C100, C102 C104, C107, C108 C110-C124 C126-C129, C132 C134-C150 C152-C157 C159-C165 C167-C178 C181-C187 C42, C25, C166 "CAPCERM 0.1uf(0805)50V,10% CERM 18pf (0805) CERM 470pf (0805) CERM 22pf (0805) R/SM 1/16W (0603) Murata Phillips Kemet Dale GRM40COG471JAT2A 08055A471JAT2A 0805CG471JOBB2 C0805C220J5GACTU CRCW06031002FT Description CAP., 100pf, 100V, 1206 1000pf (chip 1206) TANT 0.22uf, (1206) TANT 220uf, (7343) TANT 47uf, (7343) TANT 4.7uf, (7343) TANT 22uf, (7343) TANT 1uf, (3216) TANT 10uf (7343) TANT 2.2uf (3216) Manufacturer Sprague Sprague Sprague Part 1206A101JATMA 12061A102JATMA TAJA244M035R TPSE227K010R010 TPSD476K016R015 293D475X9035D2T TAJD475K035R 293D226X9020D2T TAJA105K016R 293D1060025D2T TAJA225K010R
CERM 0.01uf (0805)
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
Intel® IQ80310 Evaluation Platform Board Bill Materials (Sheet
Item R124 R77, R105 R86, R126 R93, R66, R125 R103 R53, R78, R108 R109, R115 R113 R35, R40, R57, R67, R68, R75, R91, R95, R102, R117, R120 R73, R82, R116 R48, R49, R123 R112 R46, R111 R36-R38 R54, R76, R94, R114 R122 R121 R39, R83, R106, R107 R51, R79, R88, "R/SM 1/10W (0805) R/SM 1/10W 100K (0805) R/SM 1/10W (0805) R/SM 1/10W 1.5K (0805) R/SM 1/10W 165K (0805) R/SM 1/10W (0805) R/SM 1/10W 2.2K (0805) R/SM 1/10W (0805) R/SM 1/10W 2.7k (0805) R/SM 1/10W (0805) R/SM 1/10W 4.7K (0805) R/SM 1/10W (0805) R/SM 1/10W (0805) R/SM 1/10W 8.2K (0805) R/SM 1/8W chip 1206 R/SM 1/8W chip 1206 RK73H2A5490FT RK73H2A6190FT Dale CRCW08051653FT RK73H2A1210FT RK73H2A1003FT "R/SM 1/10W (0805) R/SM 1/10W (0805) R/SM 1/10W (0805) R/SM 1/10W (0805) RK73H2A1000FT Description R/SM 1/16W 1.2M (0603) R/SM 1/16W 12.4K (0603) R/SM 1/16W 14.7K (0603) R/SM 1/16W 150K (0603) R/SM 1/16W 16.5K (0603) R/SM 1/16W 215K (0603) R/SM 1/16W (0603) R/SM 1/16W 4.3K (0603) R/SM 1/16W 470K (0603) R/SM 1/16W 4.99K (0603) R/SM 1/16W 49.9K (0603) R/SM 1/16W (0603) R/SM 1/16W (0603) ROHM RK73H1J4991FT MCR03EZHF4992 Dale Dale RK731JT1242F CRCW06031472FT RK73H1J1503FT RK73H1J1652FT CRCW06032153FT Manufacturer Part
R110, R118, R119 R/SM 1/10W 100K (0805)
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
Intel® IQ80310 Evaluation Platform Board Bill Materials (Sheet
Item Description Manufacturer Beckman R50, R98, Resistor/SM 1/2W Dale Res/SM 1/2W 0.5ohm (2010) Dale Beckman R60, R127 R34, R74, R104 R59, R100 R33, R43, R44, R69, R70, R101 R24, R25, R31, Res/SM 1/2W 10ohm (2010) Resistor RNC4R8P 2.7kohm Resistor RNC4R8P 10kohm Resistor RNC4R8P 22ohm Resistor RNC4R8P 4.7kohm Resistor RNC4R8P 1.5Kohm Resistor RNC4R8P Resistor RNC4R8P Resistor RNC4R8P 24ohm Dale Phillips Tech. R1-R23, R26-R30 RNC4R8P 8.2K J11-J15 S2-S4 CONN Male (0.050") CONN SM/TH Mictor Recptcl CONN 64BIT 3.3V/PCB CONN 64BIT 3.3V/PCB RAng CONN DIMM 168P/RAng/Socket/TH CONN/SM (Non-Shielded) CONN 8TJ-SHL-MAG CONN Battery Header RAng Jumper JUMP1X8 Jumper JUMP2X1 Jumper JUMP2X2 Jumper JUMP2X4 (Right Angle) Jumper JUMP2X8 Inductor/SM 10uh Inductor/SM 68uh Switch-Rotary/ comp. coded Switch/SM DIP4 DHS-4S OSC/SM 1.8432 (3.3V) OSC/SM 66.00 (3.3v) Samtec Framatome Meritec Berg Kycon Molex Molex Molex Molex Samtec Molex Coilcraft Coiltronics Morse Ecliptek Connor-Winfield Ecliptek Part CRCW 2010 WSL-2010 LR2010,1%,0.5 BCR1/2100J CRCW2010100J NRC50J100 742083272JTR 742083103JTR 742083220JTR 742083472JTR 742083152JTR 742083300JTR CN1J4T3300J 742083240JTR BCN164ABI822J7 742C083822JTR CN1J4T822J TFM-115-22-S-D-LC 767054-1 145168-4 CEE2X92SC-V33Z14W 981134-184-2MCF 88638-61102 1-390171-6 GM-SMT2-N-66 PTC111-00 53261-0390 22-28-4083 22-28-4023 10-89-6044 BCS-104-LDHE 10-89-6164 D03316P-103 UP1B-680 DRFC16H DHS-4S MI3100HH-1.8432MHz EC2600TS-1.8432M HSM933 1.8432MHz ECS2600TS.66.00M
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
Intel® IQ80310 Evaluation Platform Board Bill Materials (Sheet
Item Description Manufacturer Raltron CR3-CR5 CR7, XTAL 25.000 Pro/TH Green (.125" height) LEDTOWER, High, Green/Green Dual Segment Display Diode/SM Schottky 3A/30V Diode/SM Schottky 1-2A/10V Trnistr/SM General(NPN)(SOT23) Ecliptek Pletronics Hewlett Packard Dailight Hewlett Packard Motorola Motorola Motorola Fairchild Motorola Trnistr/SM General(PNP)(SOT23) Fairchild Semi. Central Semi. Part AS-25.000-20-FUND EC2-20-25.000M LP49-20-25.000MHz HLMP-3507-D00B2 553-0322 HDSP-G211 MBRD330 MBRS130LT3 MMBT3904LT1 MMBT3904 MMBT 3906LT1 MMBT 3906 CMPT 3906
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Appendix Intel® 80312 Companion Chip PBGA Signal Ball
Table details ball Intel® 80312 companion chip. Table HL-PBGA Ballpad Order (Sheet
Ball# Signal DQ31 DQ30 DQ29 DQ27 DQ25 DQ23 DQ22 SCKE1 DQ19 DQ17 SCB3 SDQM3 SBA1 SCE0# SDQM0 SWE# SCB0 DQ14 DQ12 DQ11 DQ63 DQ61 DQ28 Ball# Signal DQ24 DQ21 DQ18 SCB2 SA10 SDQM1 SCB1 DQ13 DQ10 DQ38 DQ37 S_AD33 S_AD35 DQ62 DQ26 DQ54 DQ20 DQ16 Ball# Signal SDQM2 SA11 SRAS# DQ15 DQ46 DQ39 S_AD37 S_AD39 S_AD32 S_AD34 DQ59 DQ56 DQ52 DQ50 DQ48 SA13 SDQM6 SA12
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
HL-PBGA Ballpad Order (Sheet
Ball# Signal SDQM5 SCAS# SCB4 DQ44 DQ42 DQ40 S_AD41 S_AD43 S_AD36 S_AD38 DQ60 DQ58 DQ57 DQ55 DQ53 DQ51 DQ49 SCB7 SCB6 SDQM7 SCKE0 DCLKIN SBA0 SCE1# SDQM4 SCB5 DQ47 DQ45 DQ43 DQ41 DQ34 DQ36 DQ35 Ball# Signal S_AD47 S_AD40 S_AD42 VCCPLL1 DQ33 DCLK1 DCLK0 S_AD49 S_AD51 S_AD44 S_AD46 C_A15 DQ32 DCLK3 DCLK2 S_AD53 S_AD55 S_AD48 S_AD50 DCLKOUT C_DVALID C_CLK S_AD57 S_AD59 S_AD52 S_AD54 C_ABORT C_A14 C_A13 S_AD61 S_AD63 S_AD56 Ball# Signal C_A12 C_A11 PWRDELAY C_A10 S_CBE4# S_CBE6# S_AD60 S_AD62 C_A9 C_A8 C_A7 C_A6 S_ACK64# S_AD1 S_PAR64 S_CBE5# C_A5 C_A4 S_AD3 S_AD5 S_CBE7# S_REQ64# C_A3 C_A2 C_A1 C_A0 S_AD7 S_AD8 VREF_S S_AD0 C_W/R# C_ADS#
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
HL-PBGA Ballpad Order (Sheet
Ball# Signal S_AD45 C_LOCK S_M66EN S_AD10 S_AD2 S_AD4 C_RESET# C_FIQ# C_IRQ# XINT3# S_AD12 S_AD14 S_AD6 S_CBE0# I_RST# XINT2# XINT1# S_CBE1# S_SERR# S_AD9 S_AD11 XINT0# GPIO7 GPIO6 GPIO5 S_PERR# S_LOCK# S_AD13 S_AD15 GPIO4 GPIO3 S_DEVSEL# S_IRDY# Ball# AA28 AA29 AA30 AA31 AA32 AB28 AB29 AB30 AB31 AB32 AC28 Signal S_AD58 S_PAR S_STOP# GPIO2 GPIO1 GPIO0 S_CBE2# S_AD17 S_TRDY# S_FRAME# RAD8 VCCPLL2 S_AD19 S_AD21 S_AD16 S_AD18 VCC5REF RAD7 S_AD23 S_CBE3# S_AD20 S_AD22 RAD6 RAD5 RAD4 RAD3 S_AD25 S_AD27 S_AD24 S_AD26 RAD2 Ball# AC30 AC31 AC32 AD28 AD29 AD30 AD31 AD32 AE28 AE29 AE30 AE31 AE32 AF28 AF29 AF30 AF31 AF32 AG28 AG29 AG30 AG31 AG32 Signal RAD0 RAD16 S_AD29 S_AD31 S_AD28 S_AD30 RAD15 RAD14 RAD13 S_HOLDA# S_GNT0# S_RST# S_HOLD# RAD12 RAD11 RAD10 S_CLK1 S_CLK0 S_CLK2 S_CLK4 RAD9 RWE# RALE S_CLK3 R_CLKOUT S_REQ2# S_GNT1# ROE# RCE1# RCE0#
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
HL-PBGA Ballpad Order (Sheet
Ball# AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AJ10 AJ11 AJ12 Signal R_CLKIN S_GNT2# S_GNT3# S_REQ5# P_AD30 P_AD26 P_IDSEL P_AD20 P_AD16 P_TRDY# P_PAR P_AD13 P_AD9 P_AD6 P_CLK P_AD0 P_CBE7# P_PAR64 P_AD60 P_AD56 P_AD52 P_AD48 P_AD44 P_AD40 P_AD36 P_AD32 TRST# S_REQ1# S_REQ3# S_GNT4# P_GNT# P_AD24 P_AD18 P_FRAME# Ball# AC29 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 Signal RAD1 P_AD11 P_CBE0# P_AD4 P_REQ64# P_AD62 P_AD54 P_AD50 P_AD46 P_AD38 P_AD34 VCCPLL3 S_REQ0# S_REQ4# P_RST# P_AD28 P_AD22 P_DEVSEL# P_AD15 P_AD10 P_AD2 P_CBE5# P_AD58 P_AD55 Ball# AK26 AK27 AK28 AK29 AK30 AK31 AK32 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 Signal S_CLK5 P_AD42 P_AD41 S_GNT5# P_INTA# P_INTC# P_AD27 P_AD23 P_AD19 P_CBE2# P_PERR# P_AD14 P_AD8 P_AD5 P_AD1 P_CBE6# P_AD63 P_AD59 P_AD51 P_AD45 P_AD37 P_AD33 P_INTB# P_INTD#
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
HL-PBGA Ballpad Order (Sheet
Ball# AJ13 AM10 AM11 AM12 AM13 AM14 Signal P_STOP# P_AD31 P_AD29 P_AD25 P_CBE3# P_AD21 P_AD17 P_IRDY# P_LOCK# P_SERR# Ball# AK25 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 Signal P_CBE1# P_AD12 P_M66EN P_AD7 P_AD3 VREF_P P_ACK64# P_CBE4# P_AD61 Ball# AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 Signal P_REQ# P_AD57 P_AD53 P_AD49 P_AD47 P_AD43 P_AD39 P_AD35
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Appendix Intel® 80200 Processor PBGA Signal Ball
Table details ball Intel® 80200 processor. Table 241L PBGA Ballpad Order (Sheet
Ball# Signal VCCP DCB1 DCB2 DCB6 BE0# BE3# BE5# BE6# LOCK RESETOUT# PWRSTATUS0 VCCP VCCP DVALID DCB4 VCCP BE#2 BE#7 VCCP HLDA Ball# Signal VCCP VCCP DCB0 DCB3 DCB7 BE1# BE4# ADS# W_R# ABORT PWRSTATUS1 DCB5 VCCP HOLD Ball# Signal LOWVCC VCCP VCCP VCCP IRQ# FIQ#
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
241L PBGA Ballpad Order (Sheet
Ball# Signal VCCP RESET# VCCP PLLCFG VCCP VCCP VCCP Ball# Signal VCCA MCLK TRST# VCCP VCCP LOWVPP VCCP VCCP VCCP Ball# Signal VCCP VCCP
Intel® 80310 Processor Chipset with Intel® XScaleMicroarchitecture
Table
241L PBGA Ballpad Order (Sheet
Ball# Signal VCCP Ball# Signal VCCP Ball# Signal
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