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Intel® ItaniumProcessor
Hardware Developer's Manual
Document Number: 248701-002
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Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website Intel, Itanium, Pentium, Xeon trademarks registered trademarks Intel Corporation subsidiaries United States other countries. Copyright 2001, Intel Corporation *Other names brands claimed property others.
two-wire communication /protocol developed Phillips. SMBus subset bus/protocol developed Intel. Implementation bus/protocol SMBus bus/protocol require licenses from various entities, including Phillips Electronics, N.V. North American Phillips Corporation.
Intel® ItaniumProcessor Hardware Developer's Manual
Contents
Introduction.1-1 Intel® ItaniumProcessor Cartridge .1-1 Intel® ItaniumProcessor Cartridge .1-2 Intel® ItaniumProcessor System Data Bus.1-2 Processor Abstraction Layer .1-2 Terminology.1-2 References .1-3 1.6.1 Revision History .1-3 Overview .2-1 2.1.1 6-Wide EPIC Core Delivers Level Parallelism .2-1 2.1.2 Processor Pipeline .2-2 2.1.3 Processor Block Diagram.2-3 Instruction Processing .2-4 2.2.1 Instruction Prefetch Fetch .2-4 2.2.2 Branch Prediction .2-5 2.2.3 Dispersal Logic.2-5 Execution.2-5 2.3.1 Floating-point Unit (FPU) .2-6 2.3.2 Integer Logic .2-6 2.3.3 Integer Register File.2-6 2.3.4 Register Stack Engine (RSE).2-7 Control.2-7 Memory Subsystem.2-7 2.5.1 Instruction Cache .2-8 2.5.2 Data Cache .2-8 2.5.3 Unified Cache.2-8 2.5.4 Unified Cache.2-8 2.5.5 Advanced Load Address Table (ALAT).2-9 2.5.6 Translation Lookaside Buffers (TLBs) .2-9 2.5.7 Cache Coherency.2-9 2.5.8 Write Coalescing .2-9 2.5.9 Memory Ordering .2-10 IA-32 Execution .2-10 Signaling ItaniumProcessor System Bus.3-1 3.1.1 Common Clock Signaling .3-1 3.1.2 Source Synchronous Signaling .3-2 Signal Overview .3-3 3.2.1 Control Signals .3-3 3.2.2 Arbitration Signals .3-4 3.2.3 Request Signals .3-5 3.2.4 Snoop Signals .3-5 3.2.5 Response Signals .3-6 3.2.6 Data Signals .3-6 3.2.7 Defer Signals.3-7
Introduction Microarchitecture .2-1
System Overview .3-1
Intel® ItaniumProcessor Hardware Developer's Manual
3.2.8 3.2.9 3.2.10 3.2.11 3.2.12
Error Signals .3-8 Execution Control Signals .3-9 IA-32 Compatibility Signals .3-9 Platform Signals .3-10 Diagnostic Signals.3-10
Data Integrity.4-1 Error Classification .4-1 ItaniumProcessor System Error Detection .4-1 4.2.1 Signals Protected Directly .4-2 4.2.2 Unprotected Signals.4-2 4.2.3 Hard-fail Response .4-2 4.2.4 ItaniumProcessor System Error Code Algorithms .4-3 Configuration Overview.5-1 Configuration Features.5-1 5.2.1 Output Tristate .5-3 5.2.2 Built-in Self Test (BIST).5-3 5.2.3 Data Error Checking .5-3 5.2.4 Response/ID Signal Parity Error Checking .5-3 5.2.5 Address/Request Signal Parity Error Checking.5-3 5.2.6 BERR# Assertion Initiator Errors .5-3 5.2.7 BERR# Assertion Target Errors.5-3 5.2.8 BERR# Sampling .5-4 5.2.9 BINIT# Error Assertion .5-4 5.2.10 BINIT# Error Sampling .5-4 5.2.11 LOCK# Assertion .5-4 5.2.12 In-order Queue Pipelining .5-4 5.2.13 Request Parking Enabled .5-4 5.2.14 Data Transfer Rate.5-4 5.2.15 Symmetric Agent Arbitration ID.5-4 5.2.16 Clock Frequency Ratios .5-6 Initialization Overview .5-6 5.3.1 Initialization with RESET# .5-6 5.3.2 Initialization with INIT# .5-7 Interface .6-1 Accessing Logic .6-2 Registers .6-4 Instructions.6-5 Reset Behavior.6-6 Scan Chain Order .6-6 In-target Probe (ITP) ItaniumProcessor .7-1 7.1.1 Primary Function .7-1 7.1.2 Mechanical Requirements.7-1 7.1.3 Connector Signals .7-3 Logic Analyzer Interface (LAI) ItaniumProcessor .7-4
Configuration Initialization .5-1
Test Access Port (TAP).6-1
Integration Tools .7-1
Intel® ItaniumProcessor Hardware Developer's Manual
Signals Reference Alphabetical Signals Reference A.1.1 A[43:3]# (I/O). A.1.2 A20M# (I). A.1.3 ADS# (I/O). A.1.4 AP[1:0]# (I/O) A.1.5 ASZ[1:0]# (I/O) A.1.6 ATTR[7:0]# (I/O). A.1.7 BCLKP BCLKN A.1.8 BE[7:0]# (I/O) A.1.9 BERR# (I/O) A.1.10 BINIT# (I/O) A.1.11 BNR# (I/O). A.1.12 BPM[5:0]# (I/O) A.1.13 BPRI# (I). A.1.14 BR0# (I/O) BR[3:1]# (I). A.1.15 BREQ[3:0]# (I/O) A.1.16 CPUPRES# (O). A.1.17 D[63:0]# (I/O). A.1.18 D/C# (I/O) A.1.19 DBSY# (I/O) A.1.20 DEFER# (I). A.1.21 DEN# (I/0) A.1.22 DEP[7:0]# (I/O). A.1.23 DHIT# (I). A.1.24 DID[7:0]# (I/O) A.1.25 DPS# (I/O). A.1.26 DRATE# (I). A.1.27 DRDY# (I/O) A.1.28 DSZ[1:0]# (I/O) A.1.29 EXF[4:0]# (I/O) A.1.30 FCL# (I/O) A.1.31 FERR# A.1.32 GSEQ# (I). A.1.33 HIT# (I/O) HITM# (I/O) A.1.34 ID[7:0]# A.1.35 IDS# A.1.36 IGNNE# (I). A.1.37 INIT# A.1.38 (LINTx configured INT). A.1.39 IP[1:0]# (I). A.1.40 LEN[1:0]# (I/O) A.1.41 LINT[1:0] A-10 A.1.42 LOCK# (I/O) A-10 A.1.43 (LINTX configured NMI). A-10 A.1.44 OWN# (I/O) A-11 A.1.45 PMI# (I). A-11 A.1.46 PWRGOOD (I). A-11 A.1.47 REQ[4:0]# (I/O) A-11 A.1.48 RESET# A-12 A.1.49 (I/O) A-12
Intel® ItaniumProcessor Hardware Developer's Manual
A.1.50 RS[2:0]# (I). A-12 A.1.51 RSP# A-12 A.1.52 SBSY# (I/O) A-13 A.1.53 SPLCK# (I/O) A-13 A.1.54 STBN[3:0]# STBP[3:0]# (I/O) A-13 A.1.55 (I). A-13 A.1.56 A-13 A.1.57 A-13 A.1.58 THERMTRIP# A-14 A.1.59 THRMALERT# A-14 A.1.60 A-14 A.1.61 TND# (I/O). A-14 A.1.62 TRDY# A-14 A.1.63 TRISTATE# A-14 A.1.64 TRST# A-14 A.1.65 WSNP# (I/O) A-14 Signal Summaries A-15
Figures
Intel® ItaniumProcessor Cartridge Block Diagram.1-1 Intel® ItaniumProcessor Cartridge Block Diagram.1-2 Examples Illustrating Supported Parallelism .2-2 ItaniumProcessor Core Pipeline .2-3 ItaniumProcessor Block Diagram .2-4 FMAC Units Deliver Flops/Clock.2-6 ItaniumProcessor Memory Subsystem.2-8 IA-32 Compatibility Microarchitecture .2-10 Common Clock Latched Protocol.3-2 Source Synchronous Latched Protocol.3-3 BR[3:0]# Physical Interconnection with Four Symmetric Agents .5-5 Test Access Port Block Diagram.6-2 Controller State Diagram.6-3 Intel® ItaniumProcessor Cartridge Scan Chain Order .6-7 Intel® ItaniumProcessor Cartridge Scan Chain Order .6-7 Front View Mechanical Volume Occupied Hardware .7-2 Side View Mechanical Volume Occupied Hardware.7-2 Debug Port Connector Pinout Bottom View .7-3 Front View Adapter Keepout Volume .7-5 Side View Adapter Keepout Volume.7-5 Bottom View Adapter Keepout Volume .7-6
Intel® ItaniumProcessor Hardware Developer's Manual
Tables
3-10 3-11 3-12 3-13 A-10 A-11 A-12 A-13 A-14 A-15 Control Signals Arbitration Signals Request Signals Snoop Signals Response Signals Data Signals STBP[3:0]# STBN[3:0]# Associations Defer Signals. Error Signals. Execution Control Signals IA-32 Compatibility Signals Platform Signals 3-10 Diagnostic Signals. 3-10 Direct Signal Protection. Processor Power-on Configuration Features ItaniumProcessor BREQ[3:0]# Interconnect (4-Way Processors). Arbitration Configuration ItaniumProcessor System Core Frequency Multiplier Configuration ItaniumProcessor Reset State (after PAL). ItaniumProcessor INIT State. Instructions ItaniumProcessor Controller. Recommended Debug Port Signal Connectivity Address Space Size Effective Memory Type Signal Encoding. Special Transaction Encoding Byte Enables. BR0# (I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect BR[3:0]# Signals Agent IDs. DID[7:0]# Encoding Data Transfer Rates Requesting Agent (DSZ[1:0]#). Extended Function Signals. Length Data Transfer A-10 Transaction Types Defined REQa# REQb# Signals A-11 STBp[3:0]# STBn[3:0]# Associations A-13 Output Signals. A-15 Input Signals. A-15 Input/Output Signals (Single Driver). A-16 Input/Output Signals (Multiple Driver) A-16
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Intel® ItaniumProcessor Hardware Developer's Manual
Introduction
Intel® Itaniumprocessor, first family processors based Itanium architecture, designed address needs high-performance servers workstations. Itanium architecture goes beyond RISC CISC approaches pairing massive processing resources with intelligent compilers that enable parallel execution explicit processor. large internal resources combine with predication speculation enable optimization high performance applications running Windows* Advanced Server Limited Edition, Windows* 64-bit Edition, Linux, HP-UX* v1.5 other Itanium-based operating systems. Itanium processor designed support very large scale systems, including those employing several thousand processors. will provide processing power performance head room backoffice data-intensive servers, internet servers, large data computation intensive applications high-end workstations. SMBus compatibility comprehensive features make Itanium processor ideal applications that demand continuous operation maximum reliability availability. addition, Itanium processor fully compatible, hardware, with IA-32 instruction binaries preserve existing software investments. high performance servers workstations, Itanium processor offers outstanding performance reliability targeted application segments scalability address growing e-business needs tomorrow.
Intel® ItaniumProcessor Cartridge
Itanium processor cartridge contains processor core Level (L3) cache (four Intel Cache SRAMs). high speed cache completely isolated Itanium processor cartridge operates same frequency processor core. Figure shows block diagram Itanium processor cartridge.
Figure 1-1. Intel® ItaniumProcessor Cartridge Block Diagram
CSRAM
CSRAM
CSRAM Address Command Response DATA [0:63] Processor Core
CSRAM
DATA [64:127]
System
000576a
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction
Intel® ItaniumProcessor Cartridge
Itanium processor cartridge contains processor core cache (two Intel Cache SRAMs). high speed cache completely isolated Itanium processor cartridge. Figure shows block diagram Itanium processor cartridge.
Figure 1-2. Intel® ItaniumProcessor Cartridge Block Diagram
CSRAM Address Command Response DATA [0:63] Processor Core
CSRAM
DATA [64:127]
System
000577
Intel® ItaniumProcessor System Data
system signals enhanced version voltage AGTL+ (Advanced Gunning Transceiver Logic) signaling technology used Pentium® Pentium Xeonprocessors. highest performance, system supports source synchronous data transfers. system signals require external termination each signal trace help supply high signal level control reflections transmission line. Maximum system data throughput GB/sec.
Processor Abstraction Layer
Itanium processor cartridge functionality requires Processor Abstraction Layer (PAL) firmware. firmware resides system flash memory part Intel Itanium architecture. This firmware provides abstraction level between processor hardware implementation system platform firmware maintain single software interface multiple implementations processor silicon steppings. firmware encapsulates those processor functions that change from implementation another that System Abstraction Layer (SAL) maintain consistent view processor. System Abstraction Layer (SAL) consists platform dependent firmware. Basic Input/Output System (BIOS) required boot operating system (OS). Intel® ItaniumArchitecture Software Developer's Manual, Vol. System Architecture describes interface detail.
Terminology
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction
example, when RESET# low, processor reset been requested. When high, nonmaskable interrupt occurred. case lines where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', [3:0] `LHLH' also refers High logic level, logic level). term `system bus' refers interface between processor, system core logic other agents. system multiprocessing interface processors, memory I/O. cache does connect system bus, accessible other agents system bus. Cache coherency maintained with other agents system through MESI cache protocol supported HIT# HITM# signals. term "Intel Itanium processor" refers cartridge package which interfaces host system board through PAC418 connector. Intel Itanium processors include processor core, cache, various system management features. Intel Itanium processor includes thermal plate cooling solution attachment.
References
reader this manual should also familiar with material concepts presented following documents tools:
Intel® ItaniumArchitecture Software Developer's Manual, Volume (Document Number:
245317, 245318, 245319, 245320)
Intel® ItaniumProcessor Datasheet (Document Number:
249634)
ItaniumProcessor Family Error Handling Guide (Document Number: 249278) ItaniumProcessor Microarchitecture Reference (Document Number: 245473) IEEE Standard Test Access Port Boundary-Scan Architecture PAC418 VLIF Socket Cartridge Ejector Design Specification PAC418 Cartridge/Power Retention Mechanism Triple Beam Design Guide ItaniumProcessor Heatsink Guidelines
Note: Contact your Intel representative latest revision documents without document numbers.
1.6.1
Revision History
Version Number Description Initial release Intel® ItaniumProcessor Hardware Developer's Manual. Updated Section Introduction. Date 2001
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
This chapter provides introduction Intel Itanium processor microarchitecture. detailed information Itanium architecture, please refer Intel® ItaniumArchitecture Software Developer's Manual. more detailed description Itanium processor microarchitecture, please refer ItaniumProcessor Microarchitecture Reference.
Overview
Intel Itanium processor first implementation Itanium Instruction Architecture (ISA). processor employs EPIC (Explicitly Parallel Instruction Computing) design concepts tighter coupling between hardware software. this design style, interface between hardware software designed enable software exploit available compile-time information, efficiently deliver this information hardware. addresses several fundamental performance bottlenecks modern computers, such memory latency, memory address disambiguation, control flow dependencies. EPIC constructs provide powerful architectural semantics, enable software make global optimizations across large scheduling scope, thereby exposing available Instruction Level Parallelism (ILP) hardware. hardware takes advantage this enhanced ILP, provides abundant execution resources. Additionally, focuses dynamic run-time optimizations enable compiled code schedule flow through high throughput. This strategy increases synergy between hardware software, leads higher overall performance. Itanium processor provides 6-wide 10-stage deep pipeline, running MHz. This provides combination both abundant resources exploit well high frequency minimizing latency each instruction. resources consist integer units, multimedia units, load/store units, branch units, extended-precision floating point units, additional single-precision floating point units. hardware employs dynamic prefetch, branch prediction, register scoreboard, non-blocking caches optimize compile-time nondeterminism. Three levels on-package cache minimize overall memory latency. This includes cache, accessed core speed, providing over 12GB/sec data bandwidth. system designed glueless support 4-processor systems, used effective building block very large systems. advanced delivers over GFLOPS numerics capability GFLOPS single-precision). balanced core memory subsystem provide high performance wide range applications ranging from commercial workloads high performance technical computing.
2.1.1
6-Wide EPIC Core Delivers Level Parallelism
processor provides hardware following execution units integer ALUs, Multimedia ALUs, Extended Precision Units, additional Single Precision Units, load/store units branch units. machine fetch, issue, execute retire instructions each clock. Given powerful semantics Itanium instructions, this expands many more operations being executed each cycle. Figure illustrates examples demonstrating level parallel operation supported various workloads. enterprise commercial codes, MII/MBB template combination bundle pair provides instructions parallel clock load/store, general-purpose ops, post-increment ops, branch instructions). Alternatively, MIB/MIB pair allows
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
same operations, with branch hint branch instead branch ops. scientific code, template each bundle enables parallel clock (loading double-precision operands registers, executing double-precision flops, integer post-increment ops). digital content creation codes that single precision floating point, SIMD features machine effectively provide capability perform parallel clock (loading single precision operands, executing single precision FLOPs, integer ALUs, post-incrementing operations). Figure 2-1. Examples Illustrating Supported Parallelism
Instructions Provide: Parallel Ops/Clock Scientific Computing Parallel Ops/Clock Digital Content Creation
Load Fld-pair (Post incr.)
FLOPS FLOPS)
Instructions Provide: Parallel Ops/Clock Enterprise Internet Applications
Loads (post incr.)
Branch Insts.
Note: SP-Single Precision DP-Double Precision
2.1.2
Processor Pipeline
processor hardware organized into stage core pipeline, shown Figure 2-2, that execute instructions parallel each clock. first three pipeline stages perform instruction fetch deliver instructions into decoupling buffer (instruction rotation) stage that enables front-end machine operate independently from back end. bold line middle core pipeline indicates point decoupling. Dispersal register renaming performed next stages, (expand) (register rename). Operand delivery accomplished across (wordline decode) (register read) stages, where register file accessed data delivered through bypass network after processing predicate control. Finally, last three stages perform wide parallel execution followed exception management retirement. particular, (exception detection) stage accommodates delayed branch execution well memory exception management speculation support.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
Figure 2-2. ItaniumProcessor Core Pipeline
Front-end Pre-fetch/Fetch Instructions/Clock Hierarchy Branch Predictors Decoupling Buffer
Execution Core Single Cycle ALU, Load/Stores Advanced Load Control Predicate Delivery Branch NaT/Exceptions/Retirement
Instruction Delivery Dispersal Instructions onto Issue Ports Register Remapping Register Save Engine
Operand Delivery Register File Read Bypass Register Scoreboard Predicated Dependencies
001097
2.1.3
Processor Block Diagram
Figure shows block diagram Itanium processor. function processor divided into five groups, each summarized below. following sections give high-level description operation each group. Instruction Processing instruction processing group contains logic instruction prefetch fetch, branch prediction, decoupling buffer, register stack engine/remapping. Execution execution group contains logic integer, floating-point (FP), multimedia, branch execution units, integer register files. Control control group contains exception handler pipeline control. Memory Subsystem memory subsystem group contains instruction cache (L1I), data cache (L1D), unified cache, unified cache, Programmable Interrupt Controller (PIC), Advanced Load Address Table (ALAT), system backside logic. IA-32 Execution IA-32 execution group contains hardware handling IA-32 instructions.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
Figure 2-3. ItaniumProcessor Block Diagram
Instruction Cache Fetch/Pre-fetch Engine Decoupling Buffer
Branch Prediction
ITLB
Bundles
IA-32 Decode Control
Register Stack Engine Re-Mapping Cache
Scoreboard, Predicate, NaTs, Exceptions
Integer Registers
Registers
Branch Units
Integer Units
Dual-Port Data Cache DTLB
ALAT
Floating Point Units SIMD FMAC
Controller
001096
2.2.1
Instruction Processing
Instruction Prefetch Fetch
Acting conjunction with sophisticated branch prediction correction hardware, Itanium processor speculatively fetches instructions from moderately sized pipelined instruction cache (L1I) into decoupling buffer. This buffer allows front speculatively fetch ahead hide instruction cache branch prediction latencies. hierarchy branch predictors, aided Branch Hints provided compiler, provides progressively improving instruction pointer resteers. Software-initiated prefetch probes future misses instruction cache then prefetches such target code from cache into streaming buffer eventually into instruction cache. 16KB, 4-way set-associative instruction cache fully pipelined, deliver code (two instruction bundles instructions) every clock. supported single-cycle 64-entry Instruction that fully-associative backed on-chip hardware page walker.
Intel® ItaniumProcessor Hardware Developer's Manual
Cache
Branch Predicate Registers
Introduction Microarchitecture
fetched code into decoupling buffer that hold bundles code. During instruction issue, instructions read from decoupling buffers sent instruction issue rename logic based availability execution resources.
2.2.2
Branch Prediction
processor employs hierarchy branch prediction structures deliver high-accuracy low-penalty predictions across wide spectrum workloads. branch prediction hardware assisted Branch Hint directives provided compiler form explicit instructions, well hint specifiers branch instructions). directives provide branch target addresses, static hints branch direction, well indications when dynamic prediction. These directives programmed into branch prediction structures used conjunction with dynamic prediction schemes. machine provides progressive predictions corrections fetch pointer. These resteers are: Resteer-1: Special single-cycle branch predictor (uses compiler programmed Target Address Registers). Resteer-2: Adaptive Two-level Multi-way Predictor, Return Predictor: Resteers-3,4: Branch Address Calculation Correction (BAC1, BAC2):
2.2.3
Dispersal Logic
processor total issue ports capable issuing memory instructions (ports M1), integer (ports I1), floating-point (ports F1), branch instructions (ports clock. execution units processor through groups issue ports. decoupling buffer feeds dispersal bundle granular fashion bundles instructions cycle), with fresh bundle being presented each time consumed. Dispersal from bundles instruction granular processor disperses many instruction issued left-to-right order. dispersal algorithm fast simple, with instructions being dispersed first available issue port, subject constraints detection instruction independence, detection resource oversubscription.
Execution
Itanium processor following execution units: four integer, four multimedia, extended-precision floating-point additional single-precision floating-point, three branch, load/store units. processor implements integer floating point registers, eight branch registers. integer engines support non-packed integer arithmetic logical operations. multimedia engines treat 64-bit data either 32-bit, 16-bit, 8-bit packed data types. Four integer multimedia operations executed each cycle. floating-point engines support simultaneous multiply-add provide performance scientific computation.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
2.3.1
Floating-point Unit (FPU)
floating-point unit (FPU) delivers Gflops provides full support single, double, extended, mixed mode precision computations. Parallel instructions which operate pairs 32-bit single precision numbers increase single-precision computation throughput. processor also supports multimedia instructions that treat general registers vectors eight 8bit, four 16-bit, 32-bit elements. execution hardware primarily consists latency floating-point multiply-add (FMAC) primitive with high register memory bandwidth, which effective building block scientific computation. peak, instructions, integer instructions, integer loads/stores issued every clock. 128-entry register file with eight read four write ports supporting full bandwidth operation. Figure 2-4. Every cycle, eight read ports feed extendedprecision FMACs (each with three operands) well floating-point stores memory. four write ports accommodate extended-precision results from units results from load instructions each clock. increase effective write bandwidth into from memory, floating-point registers divided into even backs. This enables physical ports dedicated load returns used write four values clock register file (two each bank), using ldf-pair instructions. earliest cache level feed unified cache. latency loads from this cache nine clock cycles. data beyond cache, bandwidth cache double-precision operations clock (one 64-byte line every four clock cycles)
Figure 2-4. FMAC Units Deliver Flops/Clock
bits Stores/Clock
Even Cache Doubleprecision Ops/Clock Cache Doubleprecision Ops/Clock ldf-pair)
Register File (128-entry bits)
bits
001098
2.3.2
Integer Logic
integer execution engine includes four Arithmetic Logic Units (ALUs) memory ports used issue loads stores. common operations fully bypassed.
2.3.3
Integer Register File
integer register file divided into static stacked subsets. static subset visible procedures consists general registers from through GR31. always returns stacked subset local each procedure begins GR32 vary size from zero registers under software control. register stack mechanism implemented renaming register addresses side-effect procedure calls returns. implementation this rename mechanism visible application programs.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
2.3.4
Register Stack Engine (RSE)
Itanium processor eliminates overhead associated with call/return avoiding spilling filling registers procedure interfaces through large register file register stack.When procedure called, frame registers made available called procedure without need explicit save caller's registers. registers remain large physical register file long there enough physical capacity. When number registers needed overflows available physical capacity, Register Stack Engine (RSE) state machine called save registers memory free necessary registers needed upcoming call. call return, processor reversed restore access state prior call. cases where saved some callee's registers, processor stalls return until restore appropriate number callee's registers. Itanium processor implements forced lazy mode RSE.
Control
control group Itanium processor made exception handler pipeline control. exception handler implements exception prioritizing. pipeline control uses scoreboard detect register source dependencies also special support control data speculation well predication. control speculation, hardware manages creation propagation deferred exception tokens (called NaT). data speculation, processor provides Advanced Load Address Table ALAT (see Section 2.5.5). Predication support includes management 1-bit predicate registers well effects predicates instruction execution.
Memory Subsystem
Itanium processor accesses main system memory through system described Chapter "System Overview". memory subsystem group Itanium processor contains instruction cache (L1I), data cache (L1D), unified cache, unified cache, Programmable Interrupt Controller (PIC), Advanced Load Address Table (ALAT), system backside logic (Figure 2-5). cache contains instructions data accessed full clock speed processor. cache handle requests clock banking there conflict conditions. This cache unified, allowing service both instruction data side requests from caches. When request cache causes miss, request automatically forwarded cache. backside logic accesses cache through 128-bit backside operating full clock speed processor. cache misses automatically forwarded main system memory through Itanium processor system bus.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
Figure 2-5. ItaniumProcessor Memory Subsystem
Frontside
Logic
ItaniumProcessor
128b Backside Itanium Processor Cartridge
000675a
2.5.1
Instruction Cache
Itanium processor instruction (L1I) cache size organized 4-way setassociative with line size. fully pipelined deliver line containing instruction bundles (six instructions) every clock. cache physically indexed physically tagged.
2.5.2
Data Cache
Itanium processor data (L1D) cache dual-ported size organized 4-way set-associative (with prediction) with line size two-cycle load latency. support concurrent loads stores. data cache only caches data integer unit, floating-point unit. cache write-through with write allocation. cache physically indexed physically tagged.
2.5.3
Unified Cache
Itanium processor unified cache pseudo-dual-ported supports concurrent accesses banking. cache 6-way set-associative with line size. cache uses write-back with write-allocate policy. cache physically indexed physically tagged.
2.5.4
Unified Cache
Itanium processor unified cache available size organized 4-way set-associative with line size. cache physically indexed physically tagged. cache accessed dedicated 128-bit back-side that runs full processor core speed.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
2.5.5
Advanced Load Address Table (ALAT)
structure called Advanced Load Address Table (ALAT) used enable data speculation Itanium processor. ALAT keeps information speculative data loads issued processor stores that aliased with these loads. Itanium processor ALAT entries 2-way set-associative.
2.5.6
Translation Lookaside Buffers (TLBs)
There three TLBs Itanium processor: first level Data Translation Lookaside Buffer (DTLB1), second level Data Translation Lookaside Buffer (DTLB2), Instruction Translation Lookaside Buffer (ITLB). misses either Data Translation Lookaside Buffers (DTLB1 DTLB2) ITLB serviced hardware page table walker which supports Itanium-defined Virtual Hash Page Table (VHPT) format.
2.5.6.1
Data (DTLB)
DTLB two-level hierarchy (DTLB1 DTLB2 inclusive): DTLB1 entries, fully-associative maintains cached copies main DTLB2. DTLB1 architecturally visible. DTLB2 entries, fully-associative, holds architecturally defined page sizes, data Translation Register (TR) data Translation Cache (TC) entries. There data Itanium processor.
2.5.6.2
Instruction (ITLB)
ITLB single-level: ITLB contains entries fully associative. ITLB holds architecturally defined page sizes, instruction TRs, instruction entries. ITLB only level hierarchy. There eight instruction Itanium processor.
2.5.7
Cache Coherency
three-level cache system requires mechanism data consistency between different caches levels. Every read access memory address must provide most current data that address. Itanium processor implements MESI (Modified, Exclusive, Shared, Invalid) state protocol maintain cache coherency.
2.5.8
Write Coalescing
increased performance uncacheable references frame buffers, Write Coalescing (WC) memory type coalesces streams data writes into single larger write transaction. Itanium processor, loads performed directly from memory from coalescing buffers. Itanium processor, separate two-entry, 64-byte buffer (WCB) used accesses exclusively. processor will evict (flush) each buffer buffer full specific ordering constraints met.
Intel® ItaniumProcessor Hardware Developer's Manual
Introduction Microarchitecture
2.5.9
Memory Ordering
Itanium processor implements relaxed memory ordering model enhance memory system performance. Memory transactions ordered with respect visibility whereby visibility transaction defined point time after which later transactions affect operation. Itanium processor, transaction considered visible when hits instruction serviceable L1D), when reached visibility point system bus.
IA-32 Execution
Itanium processor supports IA-32 instruction binary compatibility hardware (Figure 2-6). This includes support running IA-32 applications Itanium-based applications Itanium-based well IA-32 applications IA-32 both uniprocessor multiprocessor configurations. IA-32 engine designed make registers, caches, execution resources EPIC machine. deliver high performance legacy binaries, IA-32 engine dynamically schedules instructions.
Figure 2-6. IA-32 Compatibility Microarchitecture
IA-32 Instruction Fetch Decode
Shared Instruction Cache
IA-32 Dynamic Scheduler Shared ItaniumProcessor Execution Core IA-32 Retirement Exceptions
001095
2-10
Intel® ItaniumProcessor Hardware Developer's Manual
System Overview
This chapter provides overview Itanium processor system bus, transactions, signals. Itanium processor also supports signals discussed this section. complete signal listing, please refer Intel® ItaniumProcessor Datasheet.
Signaling ItaniumProcessor System
Itanium processor system supports common clock signaling well source synchronous signaling increased performance. Section 3.1.1 Section 3.1.2 describe detail characteristics each type signaling. corresponding timing figures, Figure Figure 3-2, square, triangle, circle symbols indicate point which signals driven, received, sampled, respectively. square indicates that signal driven (asserted deasserted) that clock. triangle indicates that signal received before that point. circle indicates that signal sampled (observed, latched, captured) that clock.
3.1.1
Common Clock Signaling
this mode, system signaling uses synchronous common clock latched protocol. rising edge clock, agents system required drive their active outputs sample required inputs. additional logic located output input paths between buffer latch stage, thus keeping setup hold times constant signals following latched protocol. system requires that every input sampled during valid sampling window rising clock edge effect driven sooner than next rising clock edge. This approach allows full clock communication between system agents least full clock receiver compute response. Figure illustrates latched protocol appears bus. subsequent descriptions, protocol described asserted clock after observed asserted," asserted clocks after asserted." Note that asserted observed asserted until full clock propagate (indicated straight line with arrows) before observed asserted. receiving agent uses determine response asserts That receiving agent full clock cycle from time observes asserted rising edge time computes response (indicated curved line with single arrow) drives this response rising edge Similarly, agent observes asserted rising edge uses full clock compute response (indicated lowermost curved arrow during T2). This response would driven rising edge (not shown Figure 3-1) {internal} signals. Although driven rising edge full clock propagate. observed asserted
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Figure 3-1. Common Clock Latched Protocol
Full clock allowed signal propagation Full clock allowed logic delays
BCLKP
BCLKN
{Internal}
Assert Latch Assert Change internal state Latch
Signals that driven same clock multiple system agents exhibit "wired-OR glitch" electrical electrical high transition. account this situation, these signal state transitions specified have clocks settling time when deasserted before they safely observed, shown with signals that must meet this criterion are: BINIT#, HIT#, HITM#, BNR#, TND#, BERR#.
3.1.2
Source Synchronous Signaling
data also operate source synchronous latched protocol achieve transfer rate. This source synchronous latched protocol accomplished sending latching data with strobes. rest system always uses common clock latched protocol described Section 3.1.1. source synchronous latched protocol operates data twice "frequency" common clock. source synchronous data transfers driven onto time would normally take drive common clock data transfer. both beginning points clock period, drivers send data. both point point clock period, drivers send centered differential strobes. receiver captures data with strobes deterministically. driver pre-drives STBP# before driving data. sends rising falling edge STBP# STBN#, centered with data. driver deasserts strobes after last data sent. receiver captures valid data with difference both strobe signals, asynchronous common clock. signal synchronous common clock (DRDY#) indicates receiver that valid data been sent.
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Figure 3-2. Source Synchronous Latched Protocol
Full clock allowed signal propagation
BCLKP BCLKN DRDY# Data (@driver) STBP# (@driver) STBN# (@driver) Data (@receiver) STBP# (@receiver) STBN# (@receiver)
Drive
Capture Capture Drive Latch D1,D2
Signal Overview
This section describes function various Itanium processor signals. this section, signals grouped according function. complete signal listing, please refer Intel® ItaniumProcessor Datasheet.
3.2.1
Control Signals
control signals, shown Table 3-1, used control basic operations processor.
Table 3-1. Control Signals
Signal Function Positive Phase Clock Negative Phase Clock Reset Processor System Agents Power Good Signal Names BCLKP BCLKN RESET# PWRGOOD
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BCLKP (Positive Phase Clock) input signal positive phase system clock differential pair. also referred some waveforms this overview. specifies frequency clock period used signaling scheme. Each processor derives internal clock from multiplying frequency multiplier determined configuration. Chapter "Configuration Initialization" further details. BCLKN (Negative Phase Clock) input signal negative phase system clock differential pair. RESET# input signal resets system agents known states invalidates their internal caches. Modified dirty cache lines written back. After RESET# deasserted, each processor begins execution power-on reset vector. PWRGOOD (Power Good) input signal must deasserted during power-up asserted after RESET# first asserted system.
3.2.2
Arbitration Signals
arbitration signals, shown Table 3-2, used arbitrate ownership bus, requirement initiating transaction.
Table 3-2. Arbitration Signals
Signal Function Symmetric Agent Request Priority Agent Request Block Next Request Lock Signal Names BREQ[3:0]# BPRI# BNR# LOCK#
BR[3:0]# physical pins processor. processors assert only BR0#. BREQ[3:0]# refers system arbitration signals among four processors. BR0# each four processors connected unique BREQ[3:0]# signal. five agents simultaneously arbitrate request bus, four symmetric agents BREQ[3:0]#) priority agent BPRI#). Processors arbitrate symmetric agents, while priority agent normally arbitrates behalf agents memory agents. Owning request necessary pre-condition initiating transaction. symmetric agents arbitrate based round-robin rotating priority scheme. arbitration fair symmetric. symmetric agent requests asserting BREQn# signal. Based values sampled BREQ[3:0]#, last symmetric owner, agents simultaneously determine next symmetric owner. priority agent asks asserting BPRI#. assertion BPRI# temporarily overrides, does otherwise alter symmetric arbitration scheme. When BPRI# sampled asserted, symmetric agent issues another unlocked transaction until BPRI# sampled deasserted. priority agent always next owner. BNR# asserted agent block further transactions from being issued request bus. typically asserted when system resources, such address data buffers, about become temporarily busy filled cannot accommodate another transaction. After initialization, BNR# asserted delay first transaction until agents initialized. assertion LOCK# signal indicates that symmetric agent executing atomic sequence transactions that must interrupted. locked sequence cannot interrupted another transaction regardless assertion BREQ[3:0]# BPRI#. LOCK# used
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implement memory-based semaphores. LOCK# asserted from start first transaction through last transaction. When locking disabled, LOCK# signal will never asserted.
3.2.3
Request Signals
request signals, shown Table 3-3, used initiate transaction.
Table 3-3. Request Signals
Signal Function Address Strobe Request Address Address Parity Request Parity Signal Names ADS# REQ[4:0]# A[43:3]# AP[1:0]#
assertion ADS# defines beginning transaction. REQ[4:0]#, A[43:3]#, AP[1:0]#, valid clock that ADS# asserted. clock that ADS# asserted, A[43:3]# signals provide active-low address part request. three bits address mapped into byte enable signals byte transfers. AP1# covers address signals A[43:24]#. AP0# covers address signals A[23:3]#. parity signal system correct there even number electrically signals consisting covered signals plus parity signal. Parity computed using voltage levels, regardless whether covered signals active high active low. Request Parity (RP#) signal covers request pins REQ[4:0]# address strobe, ADS#.
3.2.4
Snoop Signals
snoop signals, shown Table 3-4, used provide snoop results transaction control system agents.
Table 3-4. Snoop Signals
Signal Function Purge Global Translation Cache Done Keeping Non-Modified Cache Line Modified Cache Line Defer Transaction Completion Guarantee Sequentiality Signal Names TND# HIT# HITM# DEFER# GSEQ#
TND# signal asserted agent delay completion Purge Global Translation Cache (PTCG) instruction, even after PTCG transaction completes system bus. Software will guarantee that only PTCG instruction being executed system. HIT# HITM# signals used indicate that line valid invalid snooping agent, whether line modified (dirty) state caching agent, whether transaction needs extended. HIT# HITM# signals used maintain cache coherency system level. memory agent observes HITM# active, relinquishes responsibility data return becomes target implicit cache line writeback. memory agent must merge cache
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line being written back with write data update memory. memory agent must also provide implicit writeback response transaction. HIT# HITM# sampled asserted together, means that caching agent ready indicate snoop status, needs extend transaction. DEFER# signal deasserted indicate that transaction guaranteed in-order completion. agent asserting ensures proper removal transaction from In-order Queue generating appropriate response. assertion GSEQ# signal allows requesting agent issue next sequential uncached write even though transaction visible. asserting GSEQ# signal, platform also guarantees retry transaction, accepts responsibility ensuring sequentiality transaction with respect other uncached writes from same agent.
3.2.5
Response Signals
response signals, shown Table 3-5, used provide response information requesting agent.
Table 3-5. Response Signals
Signal Function Response Status Response Parity Target Ready (for writes) Signal Names RS[2:0]# RSP# TRDY#
Requests initiated Request Phase enter In-order Queue, which maintained every agent. responding agent responsible completing transaction In-order Queue. responding agent agent addressed transaction. write transactions, TRDY# asserted responding agent indicate that ready accept write writeback data. write transactions with implicit writeback, TRDY# asserted twice, first write data transfer then implicit writeback data transfer. RSP# signal provides parity RS[2:0]#. parity signal system correct there even number signals consisting covered signals plus parity signal. Parity computed using voltage levels, regardless whether covered signals active high active low.
3.2.6
Data Signals
data response signals, shown Table 3-6, control transfers data provide data path. Data transfers transfer rate, configured reset.
Table 3-6. Data Signals
Signal Function Data Ready Data Busy Strobe Busy Data Data Protection Signal Names DRDY# DBSY# SBSY# D[63:0]# DEP[7:0]#
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Table 3-6. Data Signals (Continued)
Signal Function Positive phase Data Strobe Negative phase Data Strobe Signal Names STBP[3:0]# STBN[3:0]#
DRDY# indicates that valid data must latched. data owner asserts DRDY# each clock which valid data transferred. DRDY# deasserted insert wait states Data Phase. DBSY# holds data before first DRDY# between DRDY# assertions multiple clock data transfer. DBSY# need asserted single clock data transfers. SBSY# holds strobe before first DRDY# between DRDY# assertions multiple clock data transfer. SBSY# must asserted data transfers transfer rate. D[63:0]# signals provide 64-bit data path between agents. partial transfers, byte enable signals BE[7:0]# determine which bytes data will contain valid data. DEP[7:0]# signals provide optional (error correcting code) D[63:0]#. DEP[7:0]# provides valid entire data each clock, regardless which bytes enabled. STBP[3:0]# STBN[3:0]# (and DRDY#) used transfer data transfer rate with source synchronous latched protocol. agent driving data transfer drives strobes with corresponding data signals. agent receiving data transfer uses strobes capture valid data. Each strobe associated with data bits signals shown Table 3-7. Table 3-7. STBP[3:0]# STBN[3:0]# Associations
Strobe Bits STBP3#, STBN3# STBP2#, STBN2# STBP1#, STBN1# STBP0#, STBN0# Data Bits D[63:48]# D[47:32]# D[31:16]# D[15:0]# Bits DEP[7:6]# DEP[5:4]# DEP[3:2]# DEP[1:0]#
3.2.7
Defer Signals
defer signals, shown Table 3-7, used deferring agent complete previously deferred transaction. deferrable transaction (DEN# asserted) deferred response signals, provided requesting agent supports deferred response (DPS# asserted).
Table 3-8. Defer Signals
Signal Function Strobe Transaction IDS# ID[7:0]# Signal Names
IDS# asserted begin deferred response. ID[7:0]# returns deferred transaction that sent DID[7:0]#. Please refer Appendix "Signals Reference" further details.
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3.2.8
Error Signals
Table lists error signals system bus.
Table 3-9. Error Signals
Signal Function Initialization Error Thermal Trip Thermal Alert Signal Names BINIT# BERR# THERMTRIP# THRMALERT#
BINIT# used signal condition that prevents reliable future operation bus. BINIT# assertion enabled disabled part power-on configuration register (see Chapter "Configuration Initialization"). BINIT# assertion disabled, BINIT# never asserted error recovery action taken only processor detecting error. BINIT# sampling enabled disabled power-on reset. BINIT# sampling disabled, BINIT# ignored action taken processor even BINIT# sampled asserted. BINIT# sampling enabled BINIT# sampled asserted, processor state machines reset. agents reset their rotating arbitration, internal state information lost. Cache contents affected. BINIT# sampling assertion must enabled proper processor error recovery. machine-check abort taken each BINIT# assertion, configurable power-on. BERR# used signal error condition caused transaction that will impact reliable operation protocol (for example, memory data error non-modified snoop error). error that causes assertion BERR# detected processor another agent. BERR# assertion enabled disabled power-on reset. BERR# assertion disabled, BERR# never asserted. BERR# assertion enabled, processor supports modes operation, configurable power-on (refer section 5.2.6 5.2.7 further details). BERR# sampling disabled, BERR# assertion ignored action taken processor. BERR# sampling enabled, BERR# sampled asserted, processor core signaled with machine check exception. machine check exception taken each BERR# assertion, configurable power-on. THERMTRIP# Thermal Trip signal. Itanium processor protects itself from catastrophic overheating using internal thermal sensor. This sensor well above normal operating temperature ensure that there false trips. Data will lost processor goes into thermal trip. This signaled system assertion THERMTRIP# pin. Once asserted, signal remains asserted until RESET# asserted platform. There hysteresis built into thermal sensor itself; long temperature drops below trip level, RESET# pulse will reset processor. temperature dropped below trip level, processor will continue assert THERMTRIP# remain stopped. thermal alert open-drain signal, indicated system THRMALERT# pin, brings ALERT# interrupt output from thermal sensor located Itanium processor platform. signal asserted when measured temperature from processor thermal diode equals exceeds temperature threshold data programmed high-temp low-temp registers sensor. This signal used platform implement thermal regulation features such generating external interrupt tell operating system that processor core heating
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3.2.9
Execution Control Signals
execution control signals, shown Table 3-10, contains signals that change execution flow processor.
Table 3-10. Execution Control Signals
Signal Function Initialize Processor Tristate outputs during reset configuration Platform Management Interrupt Programmable Local Interrupts INIT# TRISTATE# PMI# LINT[1:0] Signal Names
INIT# triggers unmaskable interrupt processor. Semantics required platform compatibility supplied firmware interrupt service routine. INIT# usually used break into Hanging Idle Processor states. INIT# another meaning during reset configuration. INIT# sampled asserted asserted deasserted transition RESET#, then processor executes Built-In Self Test (BIST). TRISTATE# sampled asserted asserted deasserted transition RESET#, then processor tristates outputs. This function used during board level testing. PMI# platform management interrupt pin. triggers highest priority interrupt processor. PMI# usually used system trigger system events that will handled platform specific firmware. LINT[1:0] programmable local interrupt pins defined interrupt interface.These pins disabled after RESET#. LINT0 typically software configured INT, 8259-compatible maskable interrupt request signal. LINT1 typically software configured NMI, non-maskable interrupt. LINT[1:0] also used, along with A20M# IGNNE# signals, determine multiplier internal clock frequency described Chapter "Configuration Initialization".
3.2.10
IA-32 Compatibility Signals
compatibility signals, shown Table 3-11, contains signals defined compatibility within Intel Architecture processor family.
Table 3-11. IA-32 Compatibility Signals
Signal Function Floating-Point Error Ignore Numeric Error Address Mask Signal Names FERR# IGNNE# A20M#
Itanium processor asserts FERR# when detects unmasked floating-point error. FERR# included compatibility never asserted Itanium-based system environment. IGNNE# asserted, allows execution floating-point instructions presence prior unmasked floating-point exceptions. IGNNE# deasserted, processor will wait interrupts
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presence unmasked floating-point exceptions. IGNNE# included compatibility never asserted Itanium-based system environment. A20M# asserted, processor interrupted. Semantics required platform compatibility supplied firmware interrupt service routine. A20M# included compatibility never asserted Itanium-based system environment. A20M# IGNNE# also used, along with LINT[1:0] signals, determine multiplier internal clock frequency described Chapter "Configuration Initialization".
3.2.11
Platform Signals
platform signals, shown Table 3-12, provides signals which support platform.
Table 3-12. Platform Signals
Signal Function Processor Present Data Transfer Rate Signal Names CPUPRES# DRATE#
CPUPRES# used detect presence Itanium processor socket. ground (GND) level indicates that part installed while open indicates part installed. DRATE# configures system data transfer rate. asserted, system operates data transfer rate. deasserted, system operates data transfer rate. DRATE# must valid asserted deasserted transition RESET# must change value while RESET# deasserted.
3.2.12
Diagnostic Signals
diagnostic signals, shown Table 3-13, provides signals probing processor, monitoring processor performance, implementing IEEE 1149.1 specification boundary scan.
Table 3-13. Diagnostic Signals
Signal Function Breakpoint Performance Monitor Boundary Scan/Test Access Signal Names BPM[5:0]# TCK, TDI, TDO, TMS, TRST#
BPM[5:0]# Breakpoint Performance Monitor signals. These signals configured outputs from processor that indicate status breakpoints programmable counters monitoring processor events. These signals configured inputs break program execution. used clock activity five-signal Test Access Port (TAP). used transfer serial test data into processor. used transfer serial test data processor. used control sequence controller state changes. TRST# used asynchronously initialize controller.
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Intel® ItaniumProcessor Hardware Developer's Manual
Data Integrity
Itanium processor system incorporates several advanced data integrity features improve error detection correction. system includes parity protection address/request signals, parity protocol protection most control signals Error Correcting Code (ECC) protection data signals. terminology used this chapter listed below:
Machine Check Abort (MCA)
more information Machine Check Architecture, Intel® ItaniumArchitecture Software Developer's Manual, Vol. System Architecture.
Error Classification
Itanium processor classifies errors following categories, listed with increasing severity. implementation always choose report error more severe category simplify logic. Continuable Error: Local MCA: Recoverable Error: error corrected hardware firmware. error cannot corrected, memory image intact. Only agent affected report error machine check handler. error cannot corrected only specific memory range corrupted. agent using data that range affected report error machine check handler. error cannot corrected memory image corrupted. agents affected report error machine check handler. error cannot corrected. agents affected cannot reliably report error exception handler without reset.
Global MCA:
BINIT Global MCA:
ItaniumProcessor System Error Detection
major address data paths Itanium processor system protected check bits that provide either parity ECC. Eight bits protect data bus. Single-bit data errors automatically corrected. two-bit parity code protects address bus. Three control signal groups explicitly protected individual parity bits RP#, RSP#, IP[1:0]#. Errors most remaining signals detected indirectly well-defined protocol specification that enables detection protocol violation errors. Errors signals cannot detected. agent required enable data integrity features since each feature individually enabled through power-on configuration register. Chapter "Configuration Initialization".
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4.2.1
Signals Protected Directly
Most system signals protected either parity ECC. Table shows parity signals signals protected these parity signals.
Table 4-1. Direct Signal Protection
Signal(s) AP0# AP1# RSP# IP0# IP1# DEP[7:0]# Protect(s) ADS#,REQ[4:0]# A[23:3]# A[43:24]# RS[2:0]# IDS#, IDa[7:0]# IDS#, IDb[7:2,0]# D[63:0]#
Address/Request Signals: parity error detected AP[1:0]# reported based
option defined power-on configuration.
Address/Request parity disabled: agent detecting parity error ignores
continues normal operation. This option normally used power-on system initialization system diagnostics.
Response Signals: parity error detected RSP# should reported agent detecting
error protocol error.
Deferred Signals: parity error detected IP[1:0]# should reported agent
detecting error protocol error.
Data Transfer Signals: Itanium processor system configured with either
data error checking ECC. selected, single-bit errors corrected double-bit errors poisoned data detected. Corrected single-bit errors continuable errors. Double-bit errors poisoned data recoverable nonrecoverable. errors read data being returned treated requestor local errors. errors write writeback data treated target recoverable errors.
4.2.2
Unprotected Signals
following Itanium processor system signals protected parity:
execution control signals BCLK, RESET#, INIT# protected. IA-32 compatibility signals FERR#, IGNNE#, A20M# protected. system support signal PMI# protected.
4.2.3
Hard-fail Response
target assert hard-fail response transaction that generated error. central agent also claim responsibility transaction after response time-out expiration terminate transaction with hard-fail response. observing hard-fail response, initiator treat local global machine check.
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4.2.4
4.2.4.1
ItaniumProcessor System Error Code Algorithms
Parity Algorithm
parity signals same algorithm compute correct parity. correct parity signal high covered signals high even number covered signals low. correct parity signal number covered signals low. Parity computed using voltage levels, regardless whether covered signals active-high active-low. Depending number covered signals, parity signal viewed providing "even" "odd" parity; this specification does either term.
4.2.4.2
ItaniumProcessor System Algorithm
Itanium processor system uses code that correct single-bit errors, detect double-bit errors, send poisoned data, detect errors confined nibble. System designers choose detect these errors subset these errors. They also choose same code additional system level caches, main memory arrays, subsystem buffers. more information, Intel® ItaniumArchitecture Software Developer's Manual.
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Configuration Initialization
This chapter describes configuration options initialization details Itanium processor. system contain single multiple Itanium processors with four processors single system bus. processors connected system unless description specifically states otherwise.
Configuration Overview
Itanium processors have some configuration options that determined hardware, some that determined software. Itanium processors sample their hardware configuration asserted-to-deasserted transition RESET#. sampled information configures processor other agents subsequent operation. These configuration options cannot changed except another reset. resets reconfigure agents. Refer Intel® ItaniumProcessor Datasheet further details. Itanium processor also configured with software configuration options. These options changed writing power-on configuration register that agents must implement. These options should changed only after taking into account synchronization between multiple Itanium processor system agents.
Configuration Features
Table lists features provided power-on configuration register signals that reserved during reset configuration. table also includes calls corresponding features that under user control during power-on configuration. details calls, refer Intel® ItaniumArchitecture Software Developer's Manual, Volume agents required maintain some software read/writable bits control some features listed table.
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Table 5-1. Processor Power-on Configuration Features
Feature Data Error Checking Enabled Response/ID Error checking enabled Address/Request Error checking enabled BERR# Assertion Enabled BERR# Sampling Enabled BERR# Assertion Enabled Initiator Internal Errors BINIT# Assertion Enabled Output Tristate Enabled Execute BIST BINIT# Sampling Enabled In-order Queue Depth Reserved1 Select Signals TRISTATE# INIT# A10# A31#, A30#, A14#, A13#, A12#, A11#, A8#, A6#, A43#-A32#, A29#-A16#, A9#, A4#, BR3#-BR0# Call PAL_BUS_SET_FEATURES PAL_BUS_SET_FEATURES PAL_BUS_SET_FEATURES PAL_BUS_SET_FEATURES PAL_BUS_SET_FEATURES PAL_BUS_SET_FEATURES PAL_BUS_SET_FEATURES PAL_BUS_SET_FEATURES PAL_BUS_GET_FEATURES Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Read Read/Write Read Default/Inactive Value Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled i.e. depth
Unused Address bits during reset configuration2 Symmetric Arbitration
PAL_FIXED_ADDR
Read
Based system mapping w.r.t. BREQ0#
Clock Ratios
A20M#, IGNNE#, LINT[1:0] A15# DRATE#
PAL_FREQ_RATIOS
Read
Request Parking Enabled Data Transfer Rate
PAL_BUS_SET_FEATURES PAL_BUS_GET_FEATURES
Read/Write Read
Disabled Disabled i.e. Source Synchronous data transfer rate selected Disabled (dcr.lc=0) i.e. fault lock operations Disabled (default from PAL) i.e. LOCK# assertion enabled
LOCK# Assertion Faulted
DCR.lc
Read/Write
LOCK# Assertion Masked
PAL_BUS_SET_FEATURES
Read/Write
reserved bits must either un-driven driven inactive during reset configuration. These bits used during reset configuration, don't care. This used platforms which support LOCK# have rely DCR.lc cause fault. When locked data reference fault handler installed, this prevent LOCK# from being asserted.
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5.2.1
Output Tristate
Itanium processor tristates tristatable outputs TRISTATE# signal sampled asserted asserted-to-deasserted transition RESET# signal. only exit Output Tristate mode assertion RESET# with TRISTATE# deasserted. Refer Intel® ItaniumProcessor Datasheet further details.
5.2.2
Built-in Self Test (BIST)
Itanium processor executes Built-In Self Test (BIST) INIT# signal sampled asserted asserted-to-deasserted transition RESET# signal. multi-processor cluster-based system architecture, INIT# different processors shared. software control available perform this function.
5.2.3
Data Error Checking
Itanium processor data error checking enabled disabled. After RESET# asserted, data error checking always disabled. Data error checking enabled under software control. more information this feature, please refer Intel® ItaniumArchitecture Software Developer's Manual.
5.2.4
Response/ID Signal Parity Error Checking
Itanium processor system supports parity protection response signals RS[2:0]# transaction signals ID[7:0]#. parity checking these signals enabled disabled. After RESET# asserted, response signal parity checking disabled. enabled under software control.
5.2.5
Address/Request Signal Parity Error Checking
Itanium processor address supports parity protection Request signals, A[43:3]#, ADS#, REQ[4:0]#. parity checking these signals enabled disabled. After RESET# asserted, request signal parity checking disabled. enabled under software control.
5.2.6
BERR# Assertion Initiator Errors
Itanium processor system agent enabled assert BERR# signal detects error. After RESET# asserted, BERR# signal assertion disabled detected errors. enabled under software control.
5.2.7
BERR# Assertion Target Errors
Itanium processor system agent enabled assert BERR# signal addressed (target) agent detects error. After RESET# asserted, BERR# signal assertion disabled target errors. enabled under software control.
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5.2.8
BERR# Sampling
BERR# sampling policy enabled, BERR# input receiver causes global Machine Check Abort (MCA). enabled under software control.
5.2.9
BINIT# Error Assertion
When protocol violated, Itanium processor system agent enabled assert BINIT# signal. After RESET# asserted, BINIT# signal assertion disabled. enabled under software control.
5.2.10
BINIT# Error Sampling
BINIT# input receiver enabled initialization control A10# sampled asserted asserted-to-deasserted transition RESET#.
5.2.11
LOCK# Assertion
requests which require locked sequences, Itanium processors configured lock system bus, fault, complete request non-atomically. enabled under software control.
5.2.12
In-order Queue Pipelining
Itanium processor system agents configured In-order Queue depth sampled asserted asserted deasserted transition RESET#. sampled deasserted asserted deasserted transition RESET#, processors default In-Order Queue depth eight. This function cannot controlled software.
5.2.13
Request Parking Enabled
Itanium processor system agents configured park request when idle. last processor request will park idle request A15# sampled asserted asserted-to-deasserted transition RESET#. processor will park request A15# sampled deasserted asserted-to-deasserted transition RESET#.
5.2.14
Data Transfer Rate
transfer rate Itanium processor system agent configured sampling DRATE# asserted-to-deasserted transition RESET#. DRATE# sampled asserted, data will configured data transfer rate. DRATE# sampled deasserted, data will configured data transfer rate.
5.2.15
Symmetric Agent Arbitration
Itanium processor system supports symmetric distributed arbitration among four agents. Each processor identifies initial position arbitration priority queue based agent supplied configuration. agent Each logical processor particular Itanium processor system must have distinct agent
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BREQ[3:0]# signals connected four symmetric agents rotating manner shown Table Figure 5-1. Every symmetric agent (BR0#) three input only pins (BR1#, BR2#, BR3#). Table 5-2. ItaniumProcessor BREQ[3:0]# Interconnect (4-Way Processors)
Signal BREQ0# BREQ1# BREQ2# BREQ3# Agent Pins BR0# BR1# BR2# BR3# Agent Pins BR3# BR0# BR1# BR2# Agent Pins BR2# BR3# BR0# BR1# Agent Pins BR1# BR2# BR3# BR0#
Figure 5-1. BR[3:0]# Physical Interconnection with Four Symmetric Agents
Priority Agent
BPRI# Agent BR0# BR1# BR2# BR3# BR0# Agent BR1# BR2# BR3# BR0# Agent BR1# BR2# BR3# BR0# Agent BR1# BR2# BR3#
BREQ0# BREQ1# BREQ2# System Interface Logic During Reset BREQ3#
asserted-to-deasserted transition RESET#, system interface logic responsible asserting BREQ0# signal. BREQ[3:1]# signals remain deasserted. processors sample their BR[3:1]# pins asserted-to-deasserted transition RESET# determine their agent from sampled value. Each physical processor logical processor with distinct agent Table 5-3. Arbitration Configuration
BR0#
BR1#
BR2#
BR3#
Arbitration
designate electrical levels.
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5.2.16
Clock Frequency Ratios
following system ratio configurations defined Itanium processor.
Table 5-4. ItaniumProcessor System Core Frequency Multiplier Configuration
Ratio Frequency Core Frequency 2/11 2/12 LINT[1] 0(L) 0(L) LINT[0] 0(L) 1(H) IGNNE# 0(H) 1(L) A20M# 0(H) 1(L)
Initialization Overview
Itanium processor initializes minimum internal states upon RESET#. processor firmware initialize test processor reset.
5.3.1
Initialization with RESET#
Itanium processor begins initialization upon detection RESET# signal active. RESET# signal assertion maskable ignores instruction boundaries including both IA-32 Itanium instructions. Table shows architectural state initialized processor hardware firmware reset. other architectural states undefined hardware reset. Refer Intel® ItaniumArchitecture Software Developer's Manual detailed description registers.
Table 5-5. ItaniumProcessor Reset State (after PAL)
Processor Resource Instruction Pointer Symbol Value Refer ItaniumArchitecture Software Developer's Manual details mode=0 sof=96, sol=0, sor=0, rrbs=0 Description
SALE_RESET entry point Itaniumprocessor.
Register Stack Configuration Register Current Frame Marker
Enforced lazy mode. physical general purpose registers available, register state undefined, locals general register frame, rotation general register frame, rename base registers TLBs cleared. TLBs cleared. caches disabled.
Translation Register Translation Cache Caches
Invalid Invalid Invalid
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5.3.2
Initialization with INIT#
Itanium processor supports INIT interrupt, also referred "warm boot" "soft boot". INIT initiated either asserting INIT# signal INIT interrupt message. INIT cannot masked except when Machine Check (MC) progress. this case, INIT interrupt held pending. INIT recognized instruction boundaries. INIT interrupt does disturb processor architectural states, state caches, model specific registers, integer floating-point states. Table shows processor state modified INIT. Refer Intel® ItaniumArchitecture Software Developer's Manual detailed description registers.
Table 5-6. ItaniumProcessor INIT State
Processor Resource Instruction Pointer Symbol Value Refer ItaniumArchitecture Software Developer's Manual details Original value Original value Description PALE_INIT entry point Itaniumprocessor. Value time INIT. Value time INIT. Invalidate IFS.
Interruption Instruction Bundle Pointer Interruption Processor Status Register Interruption Function State
IPSR
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Configuration Initialization
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Test Access Port (TAP)
This chapter describes implementation Itanium processor Test Access Port (TAP) logic. complies with IEEE 1149.1 (JTAG) Specification. Basic functionality 1149.1compatible test logic described here. details IEEE 1149.1 Specification, reader referred published standard1, many books currently available subject. simplified block diagram shown Figure 6-1. logic consists finite state machine controller, serially-accessible instruction register, instruction decode logic data registers. data registers includes those described 1149.1 standard (the bypass register, device register, BIST result register, boundary scan register). specific boundary scan chain information, please reference Itanium processor BSDL file available developer.intel.com.
Interface
logic accessed serially through dedicated pins processor package: TCK: TMS: TDI: clock signal "Test mode select," which controls finite state machine "Test data input," which inputs test instructions data serially
TRST#:"Test reset," logic reset TDO: "Test data output," through which test output read serially
TMS, operate synchronously with (which independent other processor clock). TRST# asynchronous input signal.
ANSI/IEEE Std. 1149.1-1990 (including IEEE Std. 1149.1a-1993), "IEEE Standard Test Access Port Boundary Scan Architecture," IEEE Press, Piscataway 1993.
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Test Access Port (TAP)
Figure 6-1. Test Access Port Block Diagram
Boundary Scan Test Register
ItaniumProcessor
External Pins Control Cells
Probe Data Register
Probe Instruction Register Control Signals
Device Identification
BYPASS Register
RUNBIST Register
TRST#
Instruction Decode/ Control Logic
Instruction Register Controller
000682
Accessing Logic
accessed through IEEE 1149.1-compliant controller finite state machine. This finite state machine, shown Figure 6-2, contains reset state, run-test/idle state, major branches. These branches allow access either Instruction Register data registers. used controlling input traverse this finite state machine. instructions test data loaded serially Shift-IR Shift-DR states, respectively) using pin. State transitions made rising edge TCK.
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Test Access Port (TAP)
Figure 6-2. Controller State Diagram
Test-LogicReset Run-Test/ Idle SelectDR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR SelectIR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR
000683
following brief description each states controller state machine. Refer IEEE 1149.1 standard detailed descriptions states their operation. Test-Logic-Reset: this state, test logic disabled that processor operates normally. this state, instruction Instruction Register forced IDCODE. Regardless original state Finite State Machine (TAPFSM), always enters Test-Logic-Reset when input held asserted least five clocks. controller also enters this state immediately when TRST# asserted, automatically upon power-up. TAPFSM cannot leave this state long TRST# held asserted. Run-Test/Idle: controller state between scan operations. Once entered controller will remain this state long held low. this state, activity selected test logic occurs only presence certain instructions. instructions that cause functions execute this state, test data registers selected current instructions retain their previous state. Select-IR-Scan: This temporary controller state which test data registers selected current instruction retain their previous state. Capture-IR: this state, shift register contained Instruction Register loads fixed value which least significant bits "01") rising edge TCK. parallel, latched output Instruction Register (current instruction) does change this state.
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Test Access Port (TAP)
Shift-IR: shift register contained Instruction Register connected between shifted stage toward serial output each rising edge TCK. output arrives falling edge TCK. current instruction does change this state. Exit-IR: This temporary state current instruction does change this state. Pause-IR: Allows shifting Instruction Register temporarily halted. current instruction does change this state. Exit2-IR: This temporary state current instruction does change this state. Update-IR: instruction which been shifted into Instruction Register latched into parallel output Instruction Register falling edge TCK. Once instruction been latched, remains current instruction until next Update-IR until TAPFSM reset). Select-DR-Scan: This temporary controller state test data registers selected current instruction retain their previous values. Capture-DR: this state, data parallel-loaded into test data registers selected current instruction rising edge TCK. test data register selected current instruction does have parallel input, capturing required selected test, then register retains previous state. Shift-DR: data register connected between result selection current instruction shifted stage toward serial output each rising edge TCK. output arrives falling edge TCK. data register latched parallel output then latch value does change while data being shifted Exit1-DR: This temporary state data registers selected current instruction retain their previous values. Pause-DR: Allows shifting selected data register temporarily halted without stopping TCK. registers selected current instruction retain their previous values. Exit2-DR: This temporary state registers selected current instruction retain their previous values. Update-DR: Some test data registers provided with latched parallel outputs prevent changes parallel output while data being shifted associated shift register path response certain instructions. Data latched into parallel output these registers from shift-register path falling edge TCK.
Registers
following list test registers which accessed through TAP. Boundary Scan Register Boundary Scan register consists several single-bit shift registers. boundary scan register provides shift register path from input output pins Itanium processor. Data transferred from through boundary scan register.
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Test Access Port (TAP)
Bypass Register bypass register one-bit shift register that provides minimal path length between TDO. bypass register selected when test operation being performed component board. bypass register loads logic zero start scan cycle. Device Identification (ID) Register device register contains manufacturer's identification code, version number, part number. device register fixed length bits, defined IEEE 1149.1 specification. RUNBIST Register runbist register one-bit register that loaded with logic zero when BIST successfully completed. register reports result Itanium processor BIST. Instruction Register instruction register contains four-bit command field indicate following instructions: BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE, RUNBIST, HIGHZ, CLAMP. most significant Instruction register connected least significant connected TDO.
Instructions
Table shows IEEE 1149.1 Standard defined instructions controller. Please note that except BYPASS, which public instructions defined IEEE 1149.1 must have instruction code 0000 xxxx. BYPASS: bypass register contains single shift-register stage used provide minimum length serial path between pins. This bypass enables rapid movement test data from other components system board. EXTEST: This instruction allows data serially loaded into boundary scan chain through TDI, forces output buffers drive data contained boundary scan register. This instruction used conjunction with SAMPLE/PRELOAD test board-level interconnect between components. SAMPLE/PRELOAD: This instruction allows data sampled from input buffers captured boundary scan register serially unloaded from pin. This instruction also allows data pre-loaded into boundary scan chain prior selecting another boundary scan instruction. This instruction used conjunction with EXTEST instruction test board-level interconnect between components. IDCODE: This instruction places device register between allow device identification value shifted TDO. register contains manufacturer's identity, part number, version number. This instruction default instruction after been reset. RUNBIST: This instruction invokes BIST places BIST result register between TDO. BIST result then examined. BIST will continue executing even leaves Run-Test/Idle state. HIGHZ: This instruction places output buffers component inactive drive state. this state, board-level testing performed without incurring risk damage component. During execution HIGHZ instruction, bypass register placed between TDO.
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Test Access Port (TAP)
CLAMP: This instruction selects bypass register while output buffers drive data contained boundary scan chain. This instruction protects receivers from values boundary scan chain while data being shifted out. Table 6-1. Instructions ItaniumProcessor Controller
Format Encoding (Binary) Encoding (Hex)
Public Instructions (IEEE 1149.1 Standard Mandatory) BYPASS EXTEST SAMPLE/PRELOAD Public Instructions (Not Mandatory) IDCODE RUNBIST HIGHZ CLAMP 0000 0010 0000 0111 0000 1000 0000 1011 1111 1111 0000 0000 0000 0001
Reset Behavior
related hardware reset transitioning controller finite state machine into Test-Logic-Reset state. completely disabled upon reset (i.e., resetting TAP, processor will function though exist). Note that there logic which responds normal processor reset signal. transitioned TestLogic-Reset state following three ways: Power processor. This automatically (asynchronously) resets controller. Assert TRST# time. This asynchronously resets controller. Hold high consecutive cycles TCK. This transitions controller Test-Logic-Reset state.
Scan Chain Order
Figure Figure illustrate order scan chain Itanium processor cartridge varying cache sizes.
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Test Access Port (TAP)
Figure 6-3. Intel® ItaniumProcessor Cartridge Scan Chain Order
CSRAM
CSRAM
Processor Core
001054
Figure 6-4. Intel® ItaniumProcessor Cartridge Scan Chain Order
CSRAM
CSRAM
Processor Core
CSRAM
CSRAM
001055
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Test Access Port (TAP)
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Integration Tools
Itanium processor supports In-target Probe (ITP) program execution control, register/ memory/IO access, breakpoint control. This tool provides functionality commonly associated with debuggers emulators. will affect high speed operations processor signals thereby allowing system maintain full operating speed. Itanium processor also supports Logic Analyzer Interface (LAI) module connect logic analyzer signals board. Third party logic analyzer vendors offer variety products with monitoring capability. This chapter describes LAI, well number technical issues that must taken into account when including these tools debug strategy. Please note that simulation your design required ensure that signal integrity issues avoided.
In-target Probe (ITP) ItaniumProcessor
Itanium processor debug port (DP) command control interface debugger. enables run-time control Itanium processors system debug. Support critical requirement effective debug processor board. debug port, which connected system bus, combination system, TAP, execution signals. There certain electrical, functional, mechanical constraints debug port which must followed. electrical constraint requires debug port operate speed Itanium processor system signals high speed. functional constraint requires debug port system handshake multiplexing scheme. mechanical constraint requires associated hardware within specified volume (see Section 7.1.2).
7.1.1
Primary Function
primary function provide control query interface multiple processors. With ITP, control program execution have ability access processor registers, system memory I/O. Thus, start stop program execution using variety breakpoints, single-step program assembly code level, well read write registers, memory I/O. processors controlled from application running Intel processorbased with card slot.
7.1.2
Mechanical Requirements
debug port cable's egress imposes mechanical requirements debug port that must followed. Figure Figure show mechanical volume occupied buffer board hardware when connected connector. dimensions diagrams that follow units inches.
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Figure 7-1. Front View Mechanical Volume Occupied Hardware
Mating plane between connector user's 0.04 dims referenced this plane surface mount version
Figure 7-2. Side View Mechanical Volume Occupied Hardware
Mating plane between connector user's
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7.1.3
Connector Signals
"standard" JTAG IEEE 1149.1 Specification signal levels followed Itanium processor debug port. Additionally, Itanium processor capable much higher speed clock, TCK, than normal 1149.1 Specification environment. highly recommended that system designers conduct platform simulations avoid signal integrity issues. remove possible confusion over connectivity connector pinout shown below Figure along with connectivity table, Table 7-1. recommended connector manufactured Berg* under part number 61641-303, through-hole mount header (pin removed keying). Also available from Berg surface mount version this connector under part number 61698-302TR. through-hole mount version recommended durability reasons. Full specification connectors, including layout guidelines, available from Berg Electronics.
Figure 7-3. Debug Port Connector Pinout Bottom View
BPM5DR# BCLKN BCLKP RESET# BPM[5]# BPM[4]# BPM[3]# BPM[2]# BPM[1]# BPM[0]# DBR# DBA# TRST#
000820
Table 7-1. Recommended Debug Port Signal Connectivity
BCLK(P,N) BPM[5:0]# BPM5DR# DBA# Connection Differential clock driven main system clock driver. Signals require termination. Used force break reset monitor events. Connected Itaniumprocessors chipset. Signals require termination. Signals assertion BPM5# connected that signal on-board isolation. Driven from indicate active access system active event monitoring while running; used left connect.
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Table 7-1. Recommended Debug Port Signal Connectivity (Continued)
DBR# RESET# Connection This signals target initiate reset. open drain should pulled target. Connect system reset (not same RESET#). using additional clock buffer drive TCK, clock source; otherwise connect. This should connected signal Itanium Processor. Depending which topology used, specific connectivity will differ. Ground. Connect 1.5K pull-up VTT. Input from target system port indicating system completely inactive. This connected main reset line shared between processors chipset. Connect devices scan chain debug port connector, unless using clock buffer. using clock buffer, termination resistor required should connect. data Connected first device scan chain. data out. Connected last device scan chain. state management signal. Connected devices scan chain debug port connector. individually buffered from debug port connector. reset signal. Connected devices scan chain debug port connector. individually buffered from debug port connector.
TRST#
past, standard practice cost reduction system platforms first remove debug header improve board throughput, then eventually remove signal traces entirely save board space. This acceptable solution previously since interposer style debug connector could used processor gain access chain. This longer acceptable since, multiprocessor system using Itanium processor with tight timing margins, there capability interposer debug connector. This necessitates, absolute minimum, leaving hardware (without header) debug port system board. Without this, ability debug multiprocessor system through compliant interface very limited.
Logic Analyzer Interface (LAI) ItaniumProcessor
Logic Analyzer Interface (LAI) module provides connect logic analyzer signals board. Third party logic analyzer vendors offer variety products with monitoring capability. Consult vendor specific details product offerings. Itanium processor system monitored with logic analyzer equipment. complexity Itanium multiprocessor systems, critical providing ability probe capture system signals using logic analyzer system debug validation. Therefore, guidelines keepout volume must strictly adhered order logic analyzer interface with target system. probe adapter installed between socket Itanium processor cartridge. adapter pins plug into socket, while Itanium processor cartridge pins plug into socket adapter. Cabling that part probe adapter egresses system allow electrical connection between Itanium processor logic analyzer debug tool.
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Integration Tools
maximum volume occupied adapter, known keep-out volume, well cable egress restrictions, illustrated Figure 7-4, Figure 7-5, Figure 7-6. Please contact logic analyzer vendor actual keep-out volume their respective implementation. Figure 7-4. Front View Adapter Keepout Volume
MATING PLANE
Figure 7-5. Side View Adapter Keepout Volume
ADAPTER PINS MATCHING PAC418 PATTERN SHOWN REFERENCE ONLY
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Integration Tools
Figure 7-6. Bottom View Adapter Keepout Volume
addition system logic analyzer connection, consideration should given other buses system. initial debug boards, logic analyzer connections should provided monitoring critical buses, including buses. slot present, logic analyzer vendors provide plug-in card easy connectivity. Contact logic analyzer vendor connector recommendations part numbers.
Intel® ItaniumProcessor Hardware Developer's Manual
Signals Reference
This appendix provides alphabetical listing Itanium processor system signals. tables this appendix summarize signals direction: output, input, I/O. complete pinout listing including processor specific pins, please refer Intel® ItaniumProcessor Datasheet.
A.1.1
Alphabetical Signals Reference
A[43:3]# (I/O)
A[43:3]# (Address) signals define Byte physical memory address space. When ADS# active, these pins transmit address transaction; when ADS# inactive, these pins transmit transaction type information. These signals must connect appropriate pins agents Itanium processor system bus. A[43:24]# signals parity-protected AP1# parity signal, A[23:3]# signals parity-protected AP0# parity signal. active-to-inactive transition RESET#, processors sample A[43:3]# pins determine their power-on configuration.
A.1.2
A20M#
A20M# (Address-20 Mask) signal asserted intended side effect particular write originating from instruction. platform must guarantee that instruction does complete until this asserted. A20M# ignored Itanium-based system environment.
A.1.3
ADS# (I/O)
ADS# (Address Strobe) signal asserted indicate validity transaction address A[43:3]# pins. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction.
A.1.4
AP[1:0]# (I/O)
AP[1:0]# (Address Parity) signals driven request initiator along with ADS#, A[45:3]#, REQ[4:0]#, RP#. AP1# covers A[43:24]#, AP0# covers A[23:3]#. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high.
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Signals Reference
A.1.5
ASZ[1:0]# (I/O)
ASZ[1:0]# signals memory address-space size signals. They driven request initiator during first Request Phase clock REQa[4:3]# pins. ASZ[1:0]# signals valid only when REQa[1:0]# signals equal 01B, 10B, 11B, indicating memory access transaction. ASZ[1:0]# decode defined Table A-1.
Table A-1. Address Space Size
ASZ[1:0]# 32-bit 36-bit 44-bit Reserved Memory Address Space Memory Access Range Gbyte Gbyte Gbyte Gbyte Tbyte Reserved
observing agents that support GByte (32-bit) address space must respond transaction only when ASZ[1:0]# equals observing agents that support GByte (36-bit) address space must respond transaction when ASZ[1:0]# equals 01B. observing agents that support TByte (44-bit) address space must respond transaction when ASZ[1:0]# equals 00B, 01B, 10B.
A.1.6
ATTR[7:0]# (I/O)
ATTR[7:0]# signals attribute signals. They driven request initiator during second clock Request Phase Ab[31:24]# pins. ATTR[7:0]# signals valid transactions. ATTR[7:3]# reserved undefined. ATTR[2:0]# driven based memory type. Please refer Table A-2.
Table A-2. Effective Memory Type Signal Encoding
ATTR[2:0]# Effective Memory Type Description Uncacheable Write Coalescing Write-Through Write-Protect Writeback
A.1.7
BCLKP BCLKN
BCLKP BCLKN differential clock signals determine frequency. agents drive their outputs latch their inputs differential crossing BCLKP BCLKN when they using common clock latched protocol. BCLKP BCLKN indirectly determine internal clock frequency Itanium processor. Each Itanium processor derives internal clock multiplying BCLKP BCLKN frequency ratio that defined allowed power-on configuration.
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Signals Reference
A.1.8
BE[7:0]# (I/O)
BE[7:0]# signals byte-enable signals partial transactions. They driven request initiator during second Request Phase clock Ab[15:8]# pins. memory transactions (REQa[4:0]# {10000B, 10001B, XX01XB, XX10XB, XX11XB}) byte-enable signals indicate that valid data requested being transferred corresponding byte 64-bit data bus. BE0# indicates D[7:0]# valid, BE1# indicates D[15:8]# valid,., BE7# indicates D[63:56]# valid. Special transactions ((REQa[4:0]# 01000B) (REQb[1:0]# 01B)), BE[7:0]# signals carry special cycle encodings defined Table A-3. other encodings reserved.
Table A-3. Special Transaction Encoding Byte Enables
Special Transaction Shutdown Tristate# Halt Sync (WBINVD) Reserved StopGrant Acknowledge Reserved xTPR Update Byte Enables[7:0]# 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000
Deferred Reply transactions, BE[7:0]# signals reserved. Defer Phase transfer length always same length that specified Request Phase. Invalidate Line (BIL) transaction only exception this rule. Itanium processor, transaction return cache line Bytes); however, length data returned transaction change future Itanium processor family members.
A.1.9
BERR# (I/O)
BERR# (Bus Error) signal asserted indicate unrecoverable error without protocol violation. BERR# assertion conditions configurable system level. Configuration options enable BERR# driven follows:
Asserted requesting agent transaction after observes error Asserted agent when observes error transaction
When agent samples asserted BERR# signal, processor enters Machine Check Handler.
A.1.10
BINIT# (I/O)
BINIT# (Bus Initialization) signal asserted signal condition that prevents reliable future operation enabled during power-on configuration.
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Signals Reference
BINIT# observation enabled during power-on configuration, BINIT# sampled asserted, state machines reset. agents reset their rotating arbitration same state that after reset, internal count information lost. caches affected. BINIT# observation disabled during power-on configuration, BINIT# ignored agents with exception central agent. central agent must handle error manner that appropriate system architecture.
A.1.11
BNR# (I/O)
BNR# (Block Next Request) signal used assert stall agent that unable accept transactions avoid internal transaction queue overflow. During stall, current owner cannot issue transactions. Since multiple agents might need request stall same time, BNR# wire-OR signal. order avoid wire-OR glitches associated with simultaneous edge transitions driven multiple drivers, BNR# asserted sampled specific clock edges.
A.1.12
BPM[5:0]# (I/O)
BPM[5:0]# signals system support signals mainly used inserting breakpoints performance monitoring. They configured outputs from processor that indicate status breakpoints inputs) programmable counters outputs) used monitoring performance.
A.1.13
BPRI#
BPRI# (Bus Priority-agent Request) signal used arbitrate ownership system bus. Observing BPRI# asserted asserted priority agent) causes other agents stop issuing requests, unless such requests part ongoing locked operation.The priority agent keeps BPRI# asserted until requests completed, then releases deasserting BPRI#.
A.1.14
BR0# (I/O) BR[3:1]#
BR[3:0]# physical request pins that drive BREQ[3:0]# signals system. BREQ[3:0]# signals interconnected rotating manner individual processor pins. Table gives rotating interconnection between processor signals.
Table A-4. BR0# (I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect
Signal BREQ0# BREQ1# BREQ2# BREQ3# Agent Pins BR0# BR1# BR2# BR3# Agent Pins BR3# BR0# BR1# BR2# Agent Pins BR2# BR3# BR0# BR1# Agent Pins BR1# BR2# BR3# BR0#
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Signals Reference
During power-up configuration, central agent must assert BR0# signal. symmetric agents sample their BR[3:0]# pins asserted-to-deasserted transition RESET#. which agent samples asserted level determines agent agents then configure their pins match appropriate signal protocol shown Table A-5. Table A-5. BR[3:0]# Signals Agent
Sampled Asserted RESET# BR0# BR3# BR2# BR1# Agent
A.1.15
BREQ[3:0]# (I/O)
BREQ[3:0]# signals Symmetric-agent Arbitration signals (called request). symmetric agent arbitrates asserting BREQn# signal. Agent drives BREQn# output receives remaining BREQ[3:0]# signals inputs. symmetric agents support distributed arbitration based round-robin mechanism. rotating internal state used symmetric agents track agent with lowest priority next arbitration event. power-on, rotating initialized three, allowing agent highest priority symmetric agent. After arbitration event, rotating symmetric agents updated agent symmetric owner. This update gives symmetric owner lowest priority next arbitration event. arbitration event occurs either when symmetric agent asserts BREQn# Idle (all BREQ[3:0]# previously deasserted), current symmetric owner deasserts BREQn# release ownership owner arbitration event, symmetric agents simultaneously determine symmetric owner using BREQ[3:0]# rotating symmetric owner park (hold bus) provided that other symmetric agent requesting use. symmetric owner parks keeping BREQn# signal asserted. sampling BREQn# asserted another symmetric agent, symmetric owner deasserts BREQn# soon possible release bus. symmetric owner stops issuing requests that part existing locked operation observing BPRI# asserted. symmetric agent deassert BREQn# before becomes symmetric owner. symmetric agent reassert BREQn# after keeping deasserted clock.
A.1.16
CPUPRES#
CPUPRES# used detect presence Itanium processor socket. ground indicates that Itanium processor installed, while open indicates that Itanium processor installed.
A.1.17
D[63:0]# (I/O)
D[63:0]# (Data) signals provide 64-bit data path between various system agents. Partial transfers require data transfer clock with valid data byte(s) indicated asserted byte enables BE[7:0]#. Data signals that valid particular transfer must still have correct data selected). BE0# asserted, D[7:0]# transfers least significant byte.
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Signals Reference
BE7# asserted, D[63:56]# transfers most significant byte. data driver asserts DRDY# indicate valid data transfer.
A.1.18
D/C# (I/O)
D/C# (Data/Code) signal used indicate data code (0), only during Memory Read transactions REQa1#.
A.1.19
DBSY# (I/O)
DBSY# (Data Busy) signal asserted agent that responsible driving data system indicate that data use. data released after DBSY# deasserted.
A.1.20
DEFER#
DEFER# signal asserted agent indicate that transaction cannot guaranteed inorder completion. Assertion DEFER# normally responsibility addressed memory agent agent.
A.1.21
DEN# (I/0)
DEN# (Defer Enable) signal driven second clock Request Phase Ab4# pin. DEN# asserted indicate that transaction deferred responding agent.
A.1.22
DEP[7:0]# (I/O)
DEP[7:0]# (Data Protection) signals provide optional protection D[63:0]# (Data Bus). They driven agent responsible driving D[63:0]#. During power-on configuration, DEP[7:0]# signals enabled either checking checking. error correcting code detect correct single-bit errors detect double-bit nibble errors. Chapter "Data Integrity", provides more information about ECC.
A.1.23
DHIT#
DHIT# (Deferred Hit) signal driven during Deferred Phase deferring agent. Read Line (BRL) transactions DHIT# returns final cache status that would have been indicated HIT# transaction which deferred. Itanium processor will ignore DHIT# Read Invalidate Line (BRIL), Read Partial (BRP), Write Partial (BWP) transactions bus.
A.1.24
DID[7:0]# (I/O)
DID[7:0]# Deferred Identifier signals. requesting agent transfers these signals using A[23:16]#. They transferred Ab[23:16]# during second clock Request Phase transactions, Ab[19:16]# only defined deferrable transactions (DEN# asserted).
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Signals Reference
DID[7:0]# also transferred Aa[23:16]# during first clock Request Phase Deferred Reply transactions. deferred identifier defines token supplied requesting agent. DID[7:4]# carry agent identifiers requesting agents (always valid) DID[3:0]# carry transaction identifier associated with request (valid only with DEN# asserted). This configuration limits specification masters with each masters capable making sixteen requests. Table shows encodings. Table A-6. DID[7:0]# Encoding
DID7# Agent Type DID[6]# Reserved DID[5:4]# Agent DID[3:0]# Transaction
DID[7]# indicates agent type. Symmetric agents Priority agents DID[5:4]# indicates agent Symmetric agents their arbitration DID[6]# reserved. DID[3:0]# indicates transaction agent. transaction must unique transactions issued agent which have reported their snoop results. Deferred Reply agent transmits DID[7:0]# (Ab[23:16]#) signals received during original transaction Aa[23:16]# signals during Deferred Reply transaction. This process enables original requesting agent make identifier match wake original request that awaiting completion.
A.1.25
DPS# (I/O)
DPS# (Deferred Phase Enable) signal driven second clock Request Phase Ab3# pin. DPS# asserted requesting agent supports transaction completion using Deferred Phase. requesting agent that supports Deferred Phase will always assert DPS#. requesting agent that does support Deferred Phase will always deassert DPS#.
A.1.26
DRATE#
DRATE# (Data Transfer Rate) signal configures system data transfer rate. DRATE# asserted, system operates data transfer rate. DRATE# deasserted, system operates data transfer rate. DRATE# must valid asserted-todeasserted transition RESET# must change value while RESET# deasserted.
A.1.27
DRDY# (I/O)
DRDY# (Data Ready) signal asserted data driver each data transfer, indicating valid data data bus. multi-cycle data transfer, DRDY# deasserted insert idle clocks.
A.1.28
DSZ[1:0]# (I/O)
DSZ[1:0]# (Data Size) signals transferred REQb[4:3]# signals second clock Request Phase requesting agent. DSZ[1:0]# signals define data transfer capability requesting agent shown Table A-7.
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Signals Reference
Table A-7. Data Transfer Rates Requesting Agent (DSZ[1:0]#)
DSZ[1:0]# Supported Rates Reserved
A.1.29
EXF[4:0]# (I/O)
EXF[4:0]# (Extended Function) signals transferred Ab[7:3]# pins requesting agent during second clock Request Phase. signals specify special functional requirement associated with transaction based requestor mode capability. signals defined Table A-8.
Table A-8. Extended Function Signals
Extended Function Signal EXF4# EXF3# EXF2# EXF1# EXF0# Signal Name Alias Reserved SPLCK#/FCL# OWN# DEN# DPS# Reserved Split Lock Flush Cache Line Modified State Guaranteed Defer Enable Deferred Phase Supported Function
A.1.30
FCL# (I/O)
FCL# (Flush Cache Line) signal driven second clock Request Phase /Ab6# pin. FCL# asserted indicate that memory transaction initiated global Flush Cache (FC) instruction.
A.1.31
FERR#
FERR# (Floating-point Error) signal asserted when Itanium processor detects unmasked floating-point error. FERR# included compatibility never asserted Itanium-based system environment.
A.1.32
GSEQ#
Assertion GSEQ# (Guaranteed Sequentiality) signal implies that platform guarantees completion transaction without retry while maintaining sequentiality.
A.1.33
HIT# (I/O) HITM# (I/O)
HIT# (Snoop Hit) HITM# (Hit Modified) signals convey transaction snoop operation results. agent assert both HIT# HITM# together indicate that requires snoop stall. stall continued reasserting HIT# HITM# together.
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A.1.34
ID[7:0]#
ID[7:0]# (Transaction signals driven deferring agent. signals clocks referenced IDa[7:0]# IDb[7:0]#. During both clocks, ID[7:0]# signals protected IP0# parity signal first clock, IP1# parity signal second clock. IDa[7:0]# returns deferred transaction which sent Ab[23:16]# (DID[7:0]#).
A.1.35
IDS#
IDS# Strobe) signal asserted indicate validity ID[7:0]# that clock validity DHIT# IP[1:0]# next clock.
A.1.36
IGNNE#
IGNNE# (Ignore Numeric Error) signal asserted intended side effect write originating from instruction. platform must guarantee that instruction does complete until this asserted. IGNNE# ignored Itanium-based system environment. During active RESET#, each processor begins sampling A20M#, IGNNE#, LINT[1:0] values determine ratio core-clock frequency bus-clock frequency. active-toinactive transition RESET#, each processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation.
A.1.37
INIT#
INIT# (Initialization) signal triggers unmasked interrupt processor. INIT# usually used break into hanging idle processor states. Semantics required platform compatibility supplied firmware interrupt service routine.
A.1.38
(LINTx configured INT)
8259 Interrupt Request signal which indicates that external interrupt been generated. interrupt maskable. processor vectors interrupt handler after current instruction execution been completed. LINT0 must software configured used either signal another local interrupt.
A.1.39
IP[1:0]#
IP[1:0]# Parity) signals driven second clock Deferred Phase deferring agent. IP0# protects IDa[7:0]# IDS# signals first clock, IP1# protects IDb[7:2, IDS# signals second clock.
A.1.40
LEN[1:0]# (I/O)
LEN[1:0]# (Data Length) signals transmitted using REQb[1:0]# signals requesting agent second clock Request Phase. LEN[1:0]# define length data transfer
Intel® ItaniumProcessor Hardware Developer's Manual
Signals Reference
requested requesting agent shown Table A-9. LEN[1:0]#, HITM#, RS[2:0]# signals together define length actual data transfer. Table A-9. Length Data Transfer
LEN[1:0]# Length bytes bytes Reserved bytes
A.1.41
LINT[1:0]
LINT[1:0] local interrupt signals. These pins disabled after RESET#. LINT0 typically software configured INT, 8259-compatible maskable interrupt request signal. LINT1 typically software configured NMI, non-maskable interrupt. Both signals asynchronous inputs. During active RESET#, each processor begins sampling A20M#, IGNNE#, LINT[1:0] values determine ratio core-clock frequency bus-clock frequency. active-toinactive transition RESET#, each processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation.
A.1.42
LOCK# (I/O)
LOCK# (Bus Lock) signal indicates system that transaction must occur atomically. locked sequence transactions, LOCK# asserted from beginning first transaction through last transaction. locked operation prematurely aborted (and LOCK# deasserted) DEFER# asserted during first transaction sequence. sequence also prematurely aborted hard error (such hard failure response) occurs transactions during locked operation. requests which would lock system bus, Itanium process
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