Cisco Systems Ramesh Iyer, Texas Instruments Digital Signal Proce
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TMS320C54X - TMS320C54X
active noise cancellation for FPGA - active noise cancellation for FPGA
Interface TMS320C54x
Cisco Systems Ramesh Iyer, Texas Instruments
Digital Signal Processing Solutions June 1998
IMPORTANT NOTICE
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Copyright 1998, Texas Instruments Incorporated
TRADEMARKS
trademark Texas Instruments Incorporated. Other brands names property their respective owners.
CONTACT INFORMATION
TMS320 HOTLINE TMS320 TMS320 TMS320 email
(281) 274-2320 (281) 274-2324 (281) 274-2323 dsph@ti.com
Contents
Abstract. Product Support World Wide Web. Email Introduction. C54x Peripherals Designing Interface Requirements Understanding Schematic Practical Usage Appendix Hardware Interconnection Schematics Appendix Timing Diagram FPGA References.
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Added Framing DS-1. Added Word Framing CEPT/PCM-30 Hardware Platform. Buffered Serial Port Receive Mode Timing Diagram System Interconnection Generation BIT6 Signal. Time Slot Selection Latch DSPs Inside Time Slot Selection Latch Slot Inside Time Slot Selection Latch Slot Generation Frame Sync Generation Gated Clock Combining Transmit Data from DSPs Generation Chip Select Signals Timing Diagram FPGA.
Interface TMS320C54x
Abstract
This application report describes hardware logic required interface Texas Instruments (TITM) TMS320C54x digital signal processor (DSP) buffered serial port T1/E1-type serial bus. This interface allows system designer dynamically reconfigure DSPs compress/decompress voice selected time slots.
Interface TMS320C54x
SPRA453
Product Support
World Wide
World Wide site www.ti.com contains most date product information, revisions, additions. Users registering with TI&ME build custom information pages receive product updates automatically email.
technical issues clarification switching products, please send detailed email dsph@ti.com. Questions receive prompt attention usually answered within business day.
Interface TMS320C54x
SPRA453
Introduction
Pulse Code Modulation (PCM) technique digitally transmits analog voice signals. samples original analog signal 8000 quantifies each sample into coded binary digits. Companding technique used quantizer improve signal quantizing noise (SQR) ratio. linear quantizing system, increases with increasing signal amplitudes that large signals have higher than smaller signals. This condition desirable systems using small signals. remedy this, size quantization intervals quantizer adjusted with respect input signal level that intervals smaller small signals larger large signals. This creates non-linear output versus input relationship, results output being compressed with respect input. receiving end, signal must expanded retrieve original signal. This combination compression expansion techniques codec called Compander COMpressor/exPANDER). When companding used, approximately same across range input signal levels. North American Japanese markets 2-255 companding, whereas European networks A-law companding. After input speech been sampled, quantized, encoded digital form, must transmitted final destination. Since every speech channel occupies 64000 bits/second 8000 samples multiplied bits/sample), uneconomical send only encoded voice channel over single transmission channel. multiplexing scheme that multiplexes transmission multiple voice channels over single transmission channel used. Since multiplexing scheme sends information separated time, called Time Division Multiplexing (TDM). identify beginning each frame (that start Channel sending multiplexed stream must framing information. framing information consist single bit, code word same length other channels frame, pre-determined pattern, deletion alteration code word. schemes generally used telephone network either code word bits) data stream identify frame boundaries.
Interface TMS320C54x
SPRA453
uses basic digital multiplexing scheme. also called Primary Rate Carrier system, simply primary rate. line transmit digitized voice channels multiplexed over 4-wire cable wires transmit wires receive). format used frame transmitted data system called DS-1 shown Figure partitions data into bits. first always interpreted framing synchronization bit. remaining bits represent 8-bit words from channels. Since voice channel sampled 8kHz 8-bit sample every microseconds), system must send bits 2seconds, which equivalent 1.544 Mbits/second.
Figure Added Framing DS-1
BITS/FRAME
BITS ENCODED VOICE CHANNELS) ADDED FRAMING
BITS
European system (a.k.a. carries channels encoded voice. format used frame transmitted data system called CEPT (Conference European Postal Telecommunications Administration), PCM-30. This system inserts 8-bit word before channel signify start frame, another 8-bit word between channels signaling information (see Figure This means that length CEPT/PCM-30 frame bits words). Since sampling rate still 8000 2seconds, data rate 256/125 2seconds 2.048Mbps.
Interface TMS320C54x
SPRA453
Figure Added Word Framing CEPT/PCM-30
WORDS (256 BITS/FRAME) BITS ENCODED VOICE CHANNELS
WORD (8-BITS) ADDED FRAMING
WORD SIGNALING INFORMATION
C54x Peripherals
C54x devices support three different types synchronous serial port interfaces:
Standard synchronous serial port Buffered serial port (BSP) Time division multiplexed (TDM) serial port
standard synchronous serial port provides full-duplex communication with serial devices, such codecs converters, sources, such line. features buffering mechanism that greatly reduces overhead handling serial data transfers. Except buffering mechanism, functions similar manner synchronous serial port. Hence, also capable handling data sources. serial port allows device communicate serially with other devices. This port therefore well suited multiprocessor applications. Unfortunately, this port cannot used handle telephony data coming from line.
Interface TMS320C54x
SPRA453
Designing Interface
This interface designed operate multiprocessor environment. target system, used voice-over Frame Relay application, comprises multiple C54x DSPs controlled Motorola host processor, MPC860 (see Figure host processor determines which voice channel will compressed/decompressed using predetermined voice-coding scheme.
Figure Hardware Platform
T1/E1 FRAMER
TMS320C542/8/9
Compressed voice channels
Uncompressed voice channels
FPGA
HOST PROCESSOR
Requirements
following required interface:
Indication start channel Synchronization clock (1.544 MHz) clock (2.044 MHz) means selecting time slot
Interface TMS320C54x
SPRA453
Item achieved connecting frame sync (which indicates start channel interrupt DSP. maintain simplicity, shall refer frame sync system frame sync. Since system capable selectively enabling specific channel/channels under control host processor, system frame sync signal cannot used directly drive serial port frame sync signal. Connecting system frame sync hardware interrupt enables identify beginning (and every) frame. Item achieved clocking serial port correct appropriate) clock rate (1.544 2.044 MHz). Item achieved writing value time slot channel number designated address glue logic circuit. host processor accomplishes this function.
Understanding Schematic
Appendix shows hardware interconnection between C54x, MPC860, FPGA devices. Appendix shows schematic proposed interface implemented using Altera 8000 series FPGA. heart FPGA circuit 8-bit counter. inputs counter system frame sync (FS) 2.048 clock (CLKIN). counter outputs, which through used select time slot channel. These signals labeled TSC0 through TSC4. These five outputs allow user select (=32) channels. Outputs through used generate signal labeled Bit6. Bit6 indicates occurrence sixth clock transition. Referring Figure evident that operation starts when frame sync signal becomes active, this event being sampled falling edge receive clock. clock cycle later, received falling edge receive clock sampling frame sync pulse level. This implies that, start receiving/sending data given channel, frame sync qualified clock cycle earlier. This precisely what signal Bit6 intends achieve.
Interface TMS320C54x
SPRA453
Figure Buffered Serial Port Receive Mode Timing Diagram
CLKR {FO=1} RRDY RINT
loaded from
read
operating environment this application, there C54x66 DSPs board, each capable compressing least time slots.1 FPGA three sets time-slot-selection latch units into which host processor writes necessary time slots. Each latch capable generating necessary signals select time slots DSPs. Data lines D0-D4 address lines A2-A4 brought from host processor. outputs latch-pair labeled P0CHAD0, P0CHAD1, P0CHAD2, P0CHAD3, P0CHAD4 P0CHBD0, P0CHBD1, P0CHBD2, P0CHBD3, P0CHBD4, time slots respectively, first DSP. outputs latch 8-bit counter compared using comparator circuit. result comparison ANDed with BIT6 signal, result which further combined gate with TSE0- generate signal labeled FS0. last operation with TSE0- ensures that time slot zero available selection. Signal FS0, which single pulse clock cycle previous frame, clocked through flip-flop generate FSC0, which used frame sync Buffered Serial Port DSP. Signal also used generate gated clock signal GRCLK0 cascade three flip-flops clocked either with CLK- signals. clock gating control signal spans across clock cycles time slot interest. Frame sync gated clock signals similarly generated other DSPs board, schematics which identical those shown Appendix
capability handle channels speech depends voice coding scheme other system-dependent features such Line Echo Cancellation, Relay etc.
Interface TMS320C54x
SPRA453
HSEL0-, HSEL1-, HSEL2-, HSEL3-, HSEL4-, HSEL5- chip select signals from host processor connect chip select pins each DSPs, respectively.
Practical Usage
While given circuit might seem like overkill most applications, designed based some other needs customer, details which available. Altera FPGA used this circuit costs about $10.00. authors suggest that cheaper FPGAs/PALs available used depending needs individual hardware designers.
Interface TMS320C54x
SPRA453
Appendix Hardware Interconnection Schematics
Figure System Interconnection
HD0-HD7 HBIL HCNTL0 HCNTL1 HR/WHCS-
D0-D7 R/WCSx-
C54x
HDS1HDS2-
MPC860
WE0-
HINTHASVdd
IRQ-
INT3-
HPIENA INT2PCLK ADDR.
BCLKR BCLKX BFSR BFSX
FSCx GRCLKx
HSELPCLK
2.048
FPGA
ADDR.
D0-D4
Interface TMS320C54x
SPRA453
Figure Generation BIT6 Signal
BIT0
DNUP SETN CLRN 2.048 TSC4 TSC3 TSC2 TSC1 TSC0
BIT6
Interface TMS320C54x
SPRA453
Figure Time Slot Selection Latch DSPs
TIME SLOT SELECTION LATCH
From Host processor
FSC0 GRCLK0 Target
CS0CS1WE-
P0TS
FSC1 PCLK Target TSC0 TSC1 TSC2 TSC3 TSC4 P1TS GRCLK1
BIT6
Interface TMS320C54x
SPRA453
Figure Inside Time Slot Selection Latch Slot
P0CHAD0
PCLK
CLRN
P0CHAD1
CLRN
P0CHAD2
CLRN
P0CHAD3
CLRN
P0CHAD4
CLRN
WECS0-
Interface TMS320C54x
SPRA453
Figure Inside Time Slot Selection Latch Slot
PCLK
P0CHBD0
CLRN
P0CHBD1
CLRN
P0CHBD2
CLRN
P0CHBD3
CLRN
P0CHBD4
CLRN
WECS0-
Interface TMS320C54x
SPRA453
Figure Generation Frame Sync
P0CHAD0 TSC0
P0CHAD1 FSC0 TSC1 CLRN
P0CHAD2 TSC2 P0CHAD3 TSC3
P0CHAD4 TSC4
P0CHBD0 TSC0
P0CHBD1 TSC1 BIT6
TSE0-
P0CHBD2 TSC2
P0CHBD3 TSC3
P0CHBD4 TSC4
Interface TMS320C54x
SPRA453
Figure Generation Gated Clock
P0TS
CLK-
FS0D
FS0DD CLK-
BIT6 CLRN CLRN CLRN
FS0D
GRCLK0
TSC0 TSC1 TSC2 TSC3 TSC4 TSE0-
CLK-
Interface TMS320C54x
SPRA453
Figure Combining Transmit Data from DSPs
BDXx (from P0TS
CLRN BDXx (from
P1TS
CLRN BDXx (from
P2TS
CLRN BDXx (from
P3TS
CLRN BDXx (from
P4TS
CLRN BDXx (from
P5TS
CLRN
Interface TMS320C54x
SPRA453
Figure Generation Chip Select Signals
SEL2A10A11 SEL2A5 HSEL1CS1CS0HSEL0-
A11A12 SEL2-
HSEL2CS2-
A10A11A12 SEL2-
HSEL3CS3-
A12SEL2-
HSEL4-
CS4-
A10A11 A12-
HSEL5CS5-
SEL2-
Interface TMS320C54x
SPRA453
Appendix Timing Diagram FPGA
Figure Timing Diagram FPGA
Latch programmed with (Time Slot Time Slot interest
2.048
BIT6 COMPARATOR
BIT6 COMP.O/P
FSC0
FS0D
FS0DD
P0TS
GRCLK0
Interface TMS320C54x
SPRA453
References
TMS320C54x Peripherals User's Guide, Literature number SPRU131D
Stephen Bigelow, Understanding Telephone Electronics, Third Edition
MPC860 PowerQUICC
User's Manual, Motorola Inc., 1996
Altera Flex 8000 Handbook, Altera Inc.
Interface TMS320C54x
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