Gold Code Generators Virtex Devices Author: Maria George, Mujtaba

Datasheets.org.uk - 100 Million Datasheets from 7500 Manufacturers.

Gold Code Generators Virtex Devices Author: Maria George, Mujtaba

Datasheet Thumbnail

Top Searches for this datasheet

vhdl code gold sequence code - vhdl code gold sequence code
vhdl code for gold code - vhdl code for gold code
vhdl code 16 bit LFSR - vhdl code 16 bit LFSR
receiver "positive correlation" frame synchroniza - receiver "positive correlation" frame synchroniza
polynomial* - polynomial*
LFSR - LFSR

Application Note: Virtex Series, Virtex-II Series, Spartan-II family
Gold Code Generators Virtex Devices
Author: Maria George, Mujtaba Hamid, Andy Miller
XAPP217 (v1.1) January 2001
Summary
Gold code generators used extensively Code Division Multiple Access (CDMA) systems generate code sequences with good correlation properties. This application note describes implementation Gold code generators VirtexTM, Virtex-E, Virtex-EM, Virtex-II SpartanTM-II devices. Gold code generators efficiently implemented Linear Feedback Shift Registers (LFSRs) both Virtex/Virtex-II series Spartan-II family using SRL16 macro.
Introduction
multi-user CDMA system several forms "Spread Spectrum" modulation techniques used. most popular Direct Sequence Spread Spectrum (DS-SS). this form modulation each user signal uniquely coded spread across wide band transmission frequencies. Pseudo-random Noise (PN) sequences that orthogonal each other used code user signals. sequences considered orthogonal when their crosscorrelation coefficient zero. These sequences generated using Gold code generators. basic functional blocks Gold code generators LFSRs. SRL16 (Shift Register Look-Up-Table) macro both Virtex/Virtex-II series Spartan-II devices used implement LFSRs thereby reducing FPGA resource utilization. length shift register value from shift register either fixed/static length dynamically adjusted controlling four address inputs A[3:0]. Virtex-II devices, SRLC16 macro cascadable output addition output selected address lines.
Sequences DS-SS Systems
Pseudo-random Noise (PN) sequence/code orthogonal, finite length, binary sequence. Ideally, sequence should orthogonal every time shifted version itself. There three uses sequences DS-SS applications: Spreading bandwidth modulated signal over wide radio spectrum. Uniquely coding different user signals that occupy same transmission bandwidth multi-access system. Synchronization W-CDMA systems where there global timing reference. order achieve these objectives, coding sequences require special correlation properties referred auto correlation, cross correlation.
Auto Correlation
Auto correlation measure well signal differentiate between itself every time-shifted variant itself. Auto correclation finite, discrete signal defined Equation where time delay sequence length.
unnormalized
This equation provides three distinct pieces information. positive correlation indicated when signal difficult impossible distinguish from time-shifted version original signal. negative correlation indicated when signal distinguished from original
2000 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
XAPP217 (v1.1) January 2001
www.xilinx.com 1-800-255-7778
Gold Code Generators Virtex Devices signal. correlation zero indicates signal that orthogonal time-shifted version itself. Consider data word period seven bits time (Table 7-bit code were repeating within discrete system then there only time-shifted replicas word, (shown Table time each original compared with each every time-shifted replica, then there number agreements (A), disagreements (D), that when subtracted provide measure closely words match (correlate). Table sequence "1110010" good auto correlation property provides clear difference correlation value between itself time-shifted variant itself. Table sequence "1111000" same number bits, auto correlation property good there some clear rejections match (correlation value there some "fuzzy" conditions where time-shifted replica almost matches, (correlation value
Table Auto Correlation Example
Sequence 1110010 0111001 1011100 0101110 0010111 1001011 1100101 Time Shift
Table Auto Correlation Example
Sequence 1111000 0111100 0011110 0001111 1000111 1100011 1110001 Time Shift
Cross Correlation
Cross correlation defined correlation between different signals. Cross correlation also calculated subtracting disagreements from agreements, between different sequences opposed time-shifted replicas same signal. Cross correlation finite length descrete signals defined Equation
unnormalized
www.xilinx.com 1-800-255-7778
XAPP217 (v1.1) January 2001
Gold Code Generators Virtex Devices
Non-Interfering Codes User Signals
CDMA system, each multiple user signals receiver assigned unique code that behaves like "key". From examples Table Table evident that some sequences same length have better cross-correlation properties than others these special sequences ones used code user signals system. Ideally, sequences used coding orthogonal each other. Preferred sequences small subset possible approximate (small cross-correlation) m-sequences, Maximal Length Sequences (L). Combining preferred sequences together through gate generates Gold code. important sequences that have small cross correlation between each other order reduce effect called co-channel interference. cross correlation between sequences "keys" small, there possibility that data coded from user incorrectly identified assigned another user because keys reasonable correlation. Research small cross correlation sequences, have been carried many individuals code sets identified Kasami, Gold Walsh used throughout IS-95 UMTS W-CDMA systems. When reviewing technical system specifications that require generators LFSRs, usual find comments such "codes from Kasami Length." "Gold sequences generated with polynomials degree 41", simply "x(n) X7". next section reviews some terminology associated with LFSRs order help match system level definition architectural implementation.
LFSR Terminology
basic functional block Gold code generators LFSRs. LFSRs sequence through states, where number registers LFSR. contents registers shifted right position each clock cycle. feedback from predefined registers taps left most register XOR-ed together. LFSRs have several variables: number stages shift register. number taps feedback path. position each shift register stage. initial starting condition shift register often referred "FILL" state. case LFSRs with feedback, "FILL" value must non-zero value avoid LFSR locking next state.
Shift Register Length This often referred degree, general, longer shift register, longer duration sequence before repeats. shift register fixed length number, duration sequences that generate, determined number, position taps used generate "parity" feedback bit.
LFSR Implementation
There implementation styles LFSRs, Galois implementation Fibonacci implementation. Galois Implementation shown Figure data flow from left right feedback path from right left. polynomial increments from left right with term ("1" polynomial) first term polynomial. This polynomial referred polynomial indicates which taps back from shift register. gate shift register path, therefore, Galois implementation also known in-line, modular type, M-type LFSR.
XAPP217 (v1.1) January 2001
www.xilinx.com 1-800-255-7778
Gold Code Generators Virtex Devices
Count
Data Flow
g(x)
x217_01_060700
Figure Galois Implementation
Fibonacci Implementation Figure data flow from left right feedback path from right left, similar Galois implementation. However, Fibonacci implementation polynomial decrements from left right with last term polynomial. This polynomial referred Reciprocal polynomial feedback taps incrementally annotated from right left along shift register. gate feedback path, therefore, Fibonacci implementation also known Out-of-Line, Simple-Type (S-Type) LFSR.
Count
Data Flow
LFSR polynomial: g(x)
x217_02_060700
Figure Fibonacci Implementation
Shift Register Taps combination taps their location often referred polynomial, expressed P(x) Various conventions used polynomial terms register stages shift register implementation. convention used this application note consistent with convention used CDMA UMTS specification. polynomial P(x) trailing represents which output last stage shift register. output register stage output XOR. couple points note about LFSRs polynomial used describe them are: last shift register leading always used shift register feedback path. length shift register deduced from exponent highest order term polynomial. highest order term polynomial signal connecting final "XOR" output shift register input. does feed back into parity calculation along with other taps identified polynomial.
www.xilinx.com 1-800-255-7778 XAPP217 (v1.1) January 2001
Gold Code Generators Virtex Devices Maximal Length Sequences
maximal length sequence shift register length referred m-sequence, defined e.g., eight stage LFSR will have m-sequences length 255. Correlation Properties There many combinations taps that produce small cross correlation m-sequences. Consequently possible define taps that produce collection small cross correlation m-sequences constant length shift register. Kasami, Walsh, Gold recognized identification small cross correlation maximal length codes. number independent m-sequences (S), given length shift register defined
Gold Code Generators
Gold code generators were initially presented 1967 Gold. suggested that sets small correlation codes could created Modulo addition results LFSRs, primed with factor codes. result codes with correlation properties ideally suited distinguish code from another spectrum full coded signals. These codes known Preferred Pair Gold Codes. They generated XORing outputs samelength LFSRs primed with specific Fill values from factor codes. Figure shows implementation Gold code generator. same-length LFSRs loaded with paired factor codes XOR'd create family codes suited CDMA systems. system level, Gold code generator usually described polynomials indicating LFSR structure implemented.
LFSR
Gold Code
LFSR
x217_03_0060700
Figure Gold Code Generator
Gold Code Generators using LFSRs 16-bit LFSR uses slice Virtex device. Each Virtex series contains four logic cells, organized into slices. logic cell includes 4-input look-up table, carry logic, storage element. Each Virtex-II device four identical slices. Each slice contains 4-input LUTs, registers, carry logic, other dedicated logic. area occupied Gold code generators Virtex devices function number stages taps used LFSR. Figure 8-stage 4-tap Gold code generator implemented slices (3.25 Virtex CLBs). Figure demonstrates 41-stage, 2-tap Gold code generator implemented slices (2.75 Virtex CLBs). Figure demonstrates 41-stage, 2-tap Gold code generator implementation Virtex-II device.
XAPP217 (v1.1) January 2001
www.xilinx.com 1-800-255-7778
Gold Code Generators Virtex Devices
SRL16
SRL16
SRL16
SRL16
SRL16
SRL16
SRL16
SRL16
Slice
Slice
Slice
Slice
Parity Generator FILL DATA FILL ENABLE FILL DATA
LFSR
FILL ENABLE
LFSR
LFSR Polynomial: g(x)1= LFSR Polynomial: g(x)2=
g(x)2 g(x)1
Gold Sequence
Figure 8-Stage, 4-Tap Gold Code Generator
x217 080200
www.xilinx.com 1-800-255-7778
XAPP217 (v1.1) January 2001
Gold Code Generators Virtex Devices
Fill Enable
Fill data
Gold Code Sequence
Slice
Slice
g(X) X41+
Fill Enable
Fill data
SLICE
Slice
Slice
Stage Gold Code Generator UMTS Long Uplink Scrambling Code. Achieved Virtex Slices. Reloadable during clock cycles prior 10ms radio frame. Clocked chip rate.
X217_05_060700
g(X)
Figure 41-Stage, 2-Tap Gold Code Generator
XAPP217 (v1.1) January 2001
www.xilinx.com 1-800-255-7778
Gold Code Generators Virtex Devices
Fill Enable
Fill data
Gold Code Sequence
Slice
Slice
g(X)
Fill Enable Fill data
Slice
Slice
Stage Gold Code Generator UMTS Long Uplink Scrambling Code. Reloadable during clock cycles prior 10ms radio frame. Clocked chip rate.
g(X) X41+
X217_05_010201
Figure 41-Stage, 2-Tap Gold Code Generator
Gold Code Generator Code
Gold code generator reference design written both VHDL Verilog HDL. files available Xilinx site xapp217.zip xapp217.tar.gz. code replicates logic shown Figure output Gold code generator obtained XORing LFSRs. design targeted XCV50-6BG256 device. performance results listed Table code tested work with current versions Express, Exemplar, Synplify. both VHDL Verilog code, design hierarchical levels. This makes code readable produces more efficient debugging verification. reference design, Virtex SRL16E components were inferred achieve most efficient implementation results. SRL16 shift register with four inputs select length output signal. SRL16 component instantiated code doing limits ability quickly modify functionality. ensure that component inferred, follow required syntax. Synthesis tools recognize this syntax infer SRL16 component Virtex FPGAs. reason,
www.xilinx.com 1-800-255-7778 XAPP217 (v1.1) January 2001
Gold Code Generators Virtex Devices
code written differently output netlist (written Synthesis tool) should check verify presence SRL16 components. example syntax correctly infer component available Xilinx website readablility, each LFSR implementation separate block. there problems after following syntax above listed solution, contact Xilinx Technical Support http://support.xilinx.com. code simulated MTI's Modelsim simulator using interface, therefore, testbench used. simulator supporting stimulus using code only, create testbench (HDL) file verify functionality
Table Utilization/Performance XCV50 Speed Grade Device
Design Implementation Utilization Performance SRL16 SRL16 Synopsys FPGA Express v3.3 slices Synplicity Synplify v5.31 slices Exemplar Leonardo v1999.1h slices
example this document creating 41-stage Gold code generator. Each LFSR 41-stage, 2-Tap LFSR implemented using SRL16Es.
Conclusion
Implementing Gold code generators Virtex devices using macro efficient terms FPGA utilization. example, 41-stage Gold code generator realized just Virtex slices.
Revision History
following table shows revision history this document. Date 06/29/00 01/10/01 Version Initial Xilinx release. Updated Virtex-II devices, added Figure Revision
XAPP217 (v1.1) January 2001
www.xilinx.com 1-800-255-7778

Gold Code Generators Virtex Devices Author: Maria George, Mujtaba

Top Searches for this datasheet

Other recent searches