Introduction. Application Specific (ASICs). ASIC CE81 Series Embe
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Master Product Selector Guide
Introduction. Application Specific (ASICs).
ASIC CE81 Series Embedded Array (0.18µm CMOS Technology) Features Description A-Series with 44µm Inline Pitch I-Series with 70µm Inline Pitch S-Series with 66µm Stagger Pitch ASIC Design Support Package Availability CS81 Series Standard Cell (0.18µm CMOS Technology) Features Description ASIC Design Support Package Availability CE71 Series Embedded Array (0.25 CMOS Technology) Features Description J-Series with 66µm Stagger Pitch Wire Bonding K-Series with 88µm Inline Pitch Wire Bonding L-Series with 44µm Inline Pitch Bump T-Series with 88mm Inline Pitch Wire Bonding ASIC Design Support Package Availability CS71 Series Standard Cell (0.25 CMOS Technology) Features Description ASIC Design Support Package Availability CE66 Series Embedded Array (0.35 CMOS Technology) Features Description P-Series with 100µm Inline Pitch. S-Series with 70µm Inline Pitch. ASIC Design Support Package Availability
Master Product Selector Guide
CS66 Series Standard Cell (0.35 CMOS Technology). Features. Description Applications ASIC Design Support. Package Availability CE61 Series Embedded Array (0.28µm Leff) Features. Description E-Series, 70µm Staggered Pitch, Optimized Pad-Limited Designs F-Series, Optimized Core-Limited Designs ASIC Design Support. Package Availability Processor Core Sonet STS-3c/SDH STM-1 Framer Core ARM7TDMIProcessor Core UTOPIA Level Peripheral Core Function Core Host Controller Core ASIC Packaging FC-BGA Packages FBGA Packages Packages FDH-BGA Packages. TAB-BGA Packages. PBGA Packages Packages CPGA Packages ASIC Mixed-Signal Analog Macros Design Support
Microcontrollers
F2MC 16-bit Flexible Microcontrollers F2MC-8L Series Features. F2MC-16L/16LX/16F Series Features F2MC-8L/Low Power/Low Voltage Microcontrollers F2MC-16L High Performance/Low Power/Low Voltage Microcontrollers F2MC-16LX High Performance/Low Power Microcontrollers F2MC-16F High Speed/High Performance Microcontrollers
Series. 32-bit Flexible Microcontrollers Features
Ethernet®.
Ethernet Products Evaluation Kits
AProducts
ADSL
ADSL Products. Development Kits
Application Specific Controllers
IEEE 1394 Controller SCSI Controllers.
Wireless
Filters F5CM (B2) Series (Balanced Filters). F5CE (D2) Series (Dual Mode Filters). F5CH (L2) Series (Ladder Filters) F5CE/F6CE (K2) Series (Ladder Filters). F5CP/F6CP (D2) Series (Dual Mode Filters) F6CE (L2) Series (Ladder Filters) D5CC (D1) Series (Antenna Duplexer) G5CH/G5CN/G6CH/G6CS (L2/D2) Series (Dual Filters) PLLs Single Super PLLs MB15C Series MB15S Series. Dual Super PLLs MB15E Series. MB15U Series MB15F Series. Evaluation Kits. Prescalers Bipolar Prescalers GHz.
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High Performance CMOS Digital Analog Converters MB86060 Interpolating Filters Development Support
High Performance, Leading-Edge Memory
FCRAM. interface FCRAM SRAM interface FCRAM SRAM interface FCRAM with power down mode. Flash Flash Memory Table. 5V-only Flash Memory Devices MBM29F series 3V-only Flash Memory MBM29LV series. Dual-Operation Flash Memory MBM29DL Series Dual-Operation 2.5V Flash Memory (2.3V 2.7V) MBM29DD Series 1.8V-only Flash Memory (1.8V 2.2V) MBM29SL series. Page Mode Devices MBM29PL Series. NAND FLASH MBM30 Series stacked type (Flash RAM) Device MB84VD series 2.5V stacked type (Flash RAM) Device MB84LD series
Color Plasma Displays
Large Screen Color Plasma Components System Integrators 42-inch Wide-VGA Module. 42-inch High Definition Module 37-inch Module. Future Modules. 15-inch Active Matrix TFT-LCD
Advanced Packaging Technology.
Chip Scale Package (CSP) Bump Chip Carrier(BCCTM, BCC++TM) Electrical Characteristics (Self-Inductance). Reliability Criteria Package Family Wafer Bumping Single-Chip Solutions Package FCBGA
Wafer Services
CMOS Technology. Device Characteristics Device Performance Interconnect Characteristics Test Capability.
Representatives Distributors
Master Product Selector Guide
Introduction
Fujitsu Microelectronics, Inc. Your Partner Semiconductors Electronic Devices
Welcome Master Product Selector Guide! Inside these pages, will find comprehensive portfolio advanced semiconductors electronic devices from Fujitsu Microelectronics, Inc. (FMI). product line includes Application Specific Integrated Circuits (ASICs) Application Specific Standard Products (ASSPs) such microcontrollers network/wireless ICs. FMI's memory products include Application Specific Memories (ASMs) such Fast Cycle (FCRAMTM), standard products such flash DRAM. company also markets flat display panels, provides advanced packaging wafer fabrication services. These products services, known their quality reliability, helping Fujitsu customers succeed. This guide help choose from more than 1,000 products available. further information, visit FMI's site http://www.fujitsumicro.com call Customer Response Center (1-800-866-8608). You'll find that innovative solutions help succeed.
Master Product Selector Guide
Capabilities
subsidiary Fujitsu Limited, leading billion Internet-focused, information-solutions provider, utilizes Fujitsu's extensive global resources including indepth engineering support, sub-micron process packaging technologies, world-class manufacturing network. combines these global resources with local capabilities customer partnerships provide end-to-end System solutions. addition quality reliability products, Fujitsu's semiconductor group known ability integrate components provide total solutions. follows systems-level approach. Rather than focusing individual components, looks whole system identifies particular chip needed solve customer's problem. This system-level approach strength only possible because FMI's extensive engineering capabilities. FMI's extensive network design, manufacturing marketing operations throughout U.S. demonstrates Fujitsu's commitment this marketplace. FMI's engineers design centers Jose, Dallas, Raleigh, North Carolina, work with Fujitsu's engineering organizations worldwide. part Fujitsu's worldwide manufacturing network, FMI's expanded wafer fabrication facility Gresham, Oregon, produces leading-edge flash other memory products. Finally, backs development manufacturing efforts with quality support program, giving customers maximum flexibility fit, form, function. FMI's Customer Response Center best industry. Additionally, offers demand-pull programs, Just Time (JIT) deliveries, Electronic Data Interchange (EDI) systems, buffer-inventory, configure-to-order programs.
Application Specific (ASICs)
leading-edge ASIC producer, provides products services that help customers succeed today's market segments. specializes providing cost-effective deep submicron CMOS ASIC solutions performance-driven applications. offers ASIC products ranging from embedded arrays standard cells 0.18µm, 0.25µm 0.35µm CMOS process technologies. FMI's ASIC family series high-performance embedded arrays standard cells, featuring full support mixed-signal macros embedded DRAM, well diffused RAMs, ROMs, wide variety reusable embedded cores supported Fujitsu's IPWareTM. Embedded synchronous DRAMs, 64Mb, available Fujitsu's 0.18µm technology. Three four metal layers standard ASIC process technologies, optional fifth layer available area bump designs 0.18µm process, providing 1,320 signal I/Os. wide range voltage choices core dual power supply option I/Os make ASICs extremely versatile. addition providing high-performance core operation power, FMI's ASIC also capable interfacing with both higher voltage high-speed I/Os.
ASICs System Solutions
0.18-micron (0.13µm Leff) technology production 0.11-micron (0.07µm Leff) technology introduced Multi-million gates logic: gates 0.18-micron Embedded memory blocks:
RAMs, ROMs, Register Files more
Large-capacity Embedded DRAMs: 64Mb chip Library Verified Cores Analog Mixed-signal macros: 10-bit DACs ADCs High Pin-count Flip-chip Ball Grid Array (FC-BGA) packaging
2116 pins FC-BGA package ball pitch
Design Methodology hierarchical timing driven flow Global Support Network Design Customer Response Centers
Master Product Selector Guide
ASIC
Fujitsu fully supports "open" design flow that allows designers tools their choice from mainstream vendors. Three major third party vendors supported Cadence, Synopsys, Mentor Graphics. official signoff simulation tools Cadence Verilog, Synopsys VSS, Model-sim (Verilog/VHDL) from Mentor Graphics. Other popular third party tools supported follows: Synopsys Design Compiler, Movie/Prime Time, Design Power/Power Compiler, TestGen/Test Compiler Cadence NC-Verilog, Leapfrog, Design Planner, CTGen, PBOpt, Wroute/SE, Hyper Extract Dracula
Product CX61 CX66 CX71 CX81 Drawn Geometry (µm) 0.35 0.35 0.25 0.18 Embedded array gates, signal I/Os, gate delay, 0.17µW/gate/MHz Embedded array standard cells 1.1M gates, signal I/Os, gate delay, 0.15µW/gate/MHz Embedded array standard cells 167K gates, signal I/Os, gate delay, 0.06µW/gate/MHz Embedded array standard cells 540K gates, 1320 signal I/Os, gate delay, 0.022µW/gate/MHz
DesignVerifyer from Chrysalis WattWatcher from Sante. Fujitsu's packaging options span wide range-from low-cost plastic QFPs BGAs, high pin-count FBGA FCBGA-so that designers choose optimal package their unique design criteria. Fujitsu recognizes that today's designers need total solutions order successfully implement their ASIC designs. addition Fujitsu's industry-leading silicon process packaging technology, company also offers wide range system-level design support tools, including clock skew measurement, scan insertion, ATPG test support, well compilers. FMI's U.S.-based multidisciplinary engineering support staff ready assist customers.
Descriptions
Application Specific (ASICs)
CE81 Series Embedded Array (0.18µm CMOS Technology)
Features
0.13µm effective channel length layers metal interconnects Very high-density: gates/mm2 million gates Core power supply voltage: 1.8V 1.1V nW/gate/MHz power dissipation 1.1V gate delay 1.8V fan-out Junction temperature range: +125° I/Os: 3.3V, 2.5V, 1.8V, tolerant High-density diffused RAMs ROMs High-speed mixed-signal macros Analog PLLs Wide selection advanced packaging options Proven design methodology tool support
Description
Fujitsu's CE81 series high performance, 0.18µm (0.13µm Leff) CMOS embedded arrays that include full support diffused high-speed RAMs, ROMs, analog, mixed-signal macros, variety embedded functions. CE81 series offers density performance similar those standard-cell implementation, time-to-market advantage gate arrays. CE81 series devices include 44µm, 66µm, 70µm pitch cost-effective solution both pad-limited core-limited designs. inline pads available both 70µm 44µm pitch. 70µm pads wire bonded, whereas 44µm pads used with TAB. 66µm wire-bond stagger pads used optimizing area pad-limited designs. CE81 chip cores operate 1.8V 1.1V. I/Os, operating 1.8V, 2.5V, 3.3V, conveniently interface with various types devices. CE81, which features very power high density, well suited hand-held computing, graphics, communication consumer electronics applications.
A-Series with 44µm Inline Pitch
Frame Total Gates 1,032K 1,370K 1,930K 2,930K 4,137K 5,552K 7,039K 8,394K 9,787K 11,300K 14,045K Total Pads 1,032 1,152
I-Series with 70µm Inline Pitch
Frame Total Gates 527K 791K 1,110K 1,483K 1,689K 2,385K 3,207K Total Pads
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I-Series with 70µm Inline Pitch
Frame Total Gates 4,150K 5,791K 7,249K Total Pads
S-Series with 66µm Stagger Pitch
Frame Total Gates 7,852K 9,203K 10,658K 12,235K 15,085K 19,580K 23,532K Total Pads 1,008
I/Os 1.8V, 2.5V, 3.3V CMOS (2.5V under development) Slew-rate controlled Capable driving large loads: sinking current Transceivers under development: P-CML, LVDS, PCI, SSTL, GTL+ Gbps with clock recovery Serdes (under development) developed: tolerant buffers Cores 32-bit RISC 10/100 64/256 MPEG2 Decoder/Demultiplexer 8VSB Demodulator Dolby Voice Decoder JPEG Encoder Decoder 33/66 MHz, 32/64-bit cores Host Controller/Device (ATA3) Host Controller Smart Card IRDA Interface developed:
7TDMI Hard Macro Hard Macro More being added
Mixed-Signal Macros
Converters
8-bit: MS/s high-speed 3.3V 8-bit: MS/s high-speed 3.3V 8-bit: MS/s 3.3V
Converters
10-bit: MS/s 3.3V 8-bit: MS/s 3.3V 8-bit: MS/s 3.3V Multiplier Compiler Multiplicand (m): Multiplier (n): (even numbers only) Memory Macros SRAM Compiler: single dual port R/W, 1R), bits block High-speed SRAMS, 144K bits block High-density SRAMS (1RW), 512K~ 1.1M bits (under development) Register files: 2R/2W Compiler: 512K bits block Phase-Locked Loops Analog:
ASIC Design Support
Design Verilog Logic Simulators from Cadence, Synopsys, Mentor VHDL/VITAL Logic Simulators from Synopsys, Cadence, Mentor Synthesis, DFT, tools from Synopsys Other Tools Description Verilog-XL, NC-Verilog, VCS, Model-sim (Verilog)
VSS, Model-sim (VHDL), V-System, Leapfrog
Design Compiler, Test Compiler, PrimeTime Chrysalis Design Verifyer Sente Watt Watcher
Application Specific (ASICs)
Package Availability
Pins Frame Size Thin Package (0.5 pitch)
Low-profile Package (0.5 pitch)
Heat-spread Package (0.5 pitch)
Heat-spread Package (0.4 pitch)
Ball Grid Array (0.8 ball pitch)
Ball Grid Array (1.0 ball pitch)
Enhanced Ball Grid Array (1.27 ball pitch)
Fine-pitch Ball Grid Array (0.8 ball pitch)
Fine-pitch Ball Grid Array (0.75 ball pitch)
Fine-pitch Ball Grid Array (0.5 ball pitch)
Master Product Selector Guide
CS81 Series Standard Cell (0.18µm CMOS Technology)
Features
0.13µm effective channel length layers metal interconnects Very high density: 110K gates/mm2 million gates Core power supply voltage: 1.8V 1.1V nW/gate/MHz power dissipation 1.1V gate delay 1.8V fan-out Junction temperature range: +125°C I/Os: 3.3V, 2.5V, 1.8V, tolerant High-density diffused RAMs ROMs High-speed mixed-signal macros Analog PLLs Wide selection advanced packaging options Proven design methodology tool support cell libraries: high-performance high-density
Description
Fujitsu's CS81, 0.18µm (0.13µm Leff) standard-cell product, based Fujitsu's state-of-the-art CMOS process technology, deep sub-micron process designed today's high-density low-power products. cell library, which optimized synthesis-based designs, accurate timing power-characterized data, cell areas, statistical wire-load models. CS81 standard-cell library contains both high-performance highdensity cells, giving designers option combining both types standard cell blocks same chip. CS81 library supports popular third-party tools data-exchange file standards. CS81 chip cores operate 1.8V 1.1V. I/Os, operating 1.8V, 2.5V, 3.3V, tolerance, conveniently interface with various types devices. Interface options include low-swing, high-speed I/Os high-speed interface I/Os. Both inline staggered configurations available. Inline pads available both 70µm 44µm pitch. 70µm pads wire bonded, whereas 44µm pads used with TAB. 66µm wire-bond stagger pads used optimizing area pad-limited designs. addition traditional packages, CS81 family available TAB, EBGA, FBGA, Flip-chip packages. CS81 offers rich ADCs DACs, PLLs, high-speed RAMs ROMs, well variety other embedded functions. following blocks will available near future: Special high-speed I/Os: T-LVTTL, P-CML, LVDS, SSTL, HSTL Special-purpose Interfaces: PCI, AGP, Design Methodology Fujitsu's design methodology ensures first-time silicon success integrating proprietary point tools with popular, sign-off-quality, industry-standard tools such Logic design rule checker Delay calculator Quasi parasitic extraction tool Fujitsu's clock-driven design methodology devised power skew. methodology identifies best-suited clock distribution strategy given design predicts performance advance. Fujitsu supports co-simulation, emulation high-level floor-planning optimize power, timing, size design. This enables designer make effective architecturallevel decisions achieve optimal design solutions.
Application Specific (ASICs)
Fujitsu's design methodology supports cycle-based simulators formal verification, well static timing analysis more conventional VHDL Verilog simulators. Fujitsu's design-fortest strategy includes boundary scan (JTAG) full partial scan, well built-in self-test memory. Applications CS81 offers high-density standard cells very low-power applications. Also provided CS81 high-performance areaoptimized memories, mixed-signal blocks, analog functions, rich Cores Mega Macros, various interfaces. CS81 ASIC design kit, combined with supported tool sets, poised chip developments that require ease-of-tool use, proven design flow quick time market. Mixed-Signal Macros
Converters
I/Os 1.8V, 2.5V, 3.3V CMOS (2.5V under development) Slew-rate controlled Capable driving large loads: sinking current Transceivers under development: P-CML, LVDS, PCI, SSTL, Gbps with clock recovery Serdes (under development) developed: tolerant buffers Cores 32-bit RISC 10/100 64/256 MPEG2 Decoder/Demultiplexer 8VSB Demodulator Dolby Voice Decoder JPEG Encoder Decoder 33/66 MHz, 32/64 cores Host Controller/Device (ATA3) Host Controller Smart Card IRDA Interface developed:
7TDMI Hard Macro Hard Macro More being added
8-bit: MS/s high-speed 3.3V 8-bit: MS/s high-speed 3.3V 8-bit: MS/s 3.3V
Converters
10-bit: MS/s 3.3V 8-bit: MS/s 3.3V 8-bit: MS/s 3.3V Multiplier Compiler Multiplicand (m): Multiplier (n): (even numbers only) Memory Macros SRAM Compiler: single dual port (1RW/1R), bits block High-speed SRAMs, 144K bits High-density SRAMs (1RW) 512K 1.1M bits (under development) Register files: 2R/2W Compiler: 512K bits block Phase-Locked Loops Analog:
ASIC Design Support
Design Verilog Logic Simulators from Cadence, Synopsys, Mentor VHDL/VITAL Logic Simulators from Synopsys,Cadence, Mentor Synthesis, DFT, tools from Synopsys Other Tools Description Verilog-XL, Verilog, VCS, Model-sim (Verilog) VSS, Model-sim (VHDL) V-System, Leapfrog
Design Compiler, Test Compiler, PrimeTime Chrysalis Design Verifyer Cadence
Master Product Selector Guide
Package Availability
Pins/Balls TAB-BGA (Cavity-down) EBGA (Cavity-down) HQFP (Cavity-up) TQFP (Cavity-up) LQFP (Cavity-up) FBGA (Cavity-up) FC-BGA (Cavity-down) 1,089 1,225 1,369 1,681 1,849 2,116 1.27 1.27 1.27 1.00 1.00 1.00 42.4 45.0 47.5 42.5 45.0 47.5 0.80 0.80 0.80 0.80 0.80 0.80 0.50 0.80 0.75 0.50 0.80 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.40 0.50 1.27 1.27 Pin/Ball Pitch Dimensions
Application Specific (ASICs)
CE71 Series Embedded Array (0.25 CMOS Technology)
Features
0.18µm Leff (0.24µm drawn) Propagation delay Separate core supply voltages Mixed-signal macros-A/D converters I/Os: 2.5V, 3.3V tolerant Core power supply voltage: 2.5V, 1.8V, 1.5V Junction temperature: -40°C ~125°C High-performance special I/Os: PCML, LVDS, PCI, SSTL, GTL+, AGP, Analog digital PLLs Packaging options: QFP, HQFP, BGA, TBGA Support major third party tools
Description
Fujitsu's CE71 series high-performance, 0.18µm Leff CMOS embedded arrays that include full support diffused high-speed RAMs, ROMs, mixed-signal macros, variety other embedded functions. CE71 series offers density performance similar those standard cells, provides time-to-market advantage gate arrays. CE71 series devices include 44µm, 66µm, 88µm pitch cost-effective solution both pad-limited corelimited designs. With nominal 1.5V 2.5V core operation with 2.5V 3.3V/5V tolerant I/Os, CE71 series features very low-power consumption 0.06µW/gate/MHz. Potential applications CE71 series include computing, graphics, communications, networking, wireless, consumer designs.
J-Series with 66µm Stagger Pitch Wire Bonding
Frame CE71J1 CE71J2 CE71J3 CE71J4 CE71J5 CE71J6 CE71J7 CE71J8 CE71J9 CE71JA CE71JB CE71JC CE71JD CE71JE CE71JF CE71JG Total Gates 216K 312K 488K 703K 911K 1,098K 1,302K 1,524K 2,020K 2,586K 3,055K 3,564K 4,113K 5,114K 6,698K 8,096K Total Pads 1,008 Signals
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K-Series with 88µm Inline Pitch Wire Bonding
Frame CE71K1 CE71K2 CE71K3 CE71K4 CE71K5 CE71K6 CE71K7 CE71K8 Total Gates 167K 237K 348K 524K 734K 963K 1,110K 1,559K Total Pads Signals
T-Series with 88µm Inline Pitch Wire Bonding
Frame CE71T2 CE71T3 CE71T4 CE71T5 CE71T6 CE71T7 CE71T8 CE71T9 CE71TA CE71TB Total Gates 347K 524K 734K 845K 963K 1,110K 1,407K 1,559K 1.827K 088K 2,398K 3,040K 3,645K 5,152K Total Pads Signals
L-Series with 44µm Inline Pitch Bump
Frame CE71L4 CE71L5 CE71L6 CE71L7 CE71L8 CE71L9 CE71LA CE71LB CE71LC CE71LD CE71LE Total Gates 356K 476K 677K 1,034K 1,469K 1,976K 2,513K 3,001K 3,506K 4,050K 5,043K Total Pads 1,032 1,152 Signals
CE71TC CE71TD CE71TE CE71TG
Application Specific (ASICs)
Mixed-Signal Macros
Converters
10-bit: 1MS/s, 1.5MS/s, MS/s, MS/s MS/s, MS/s 8-bit: KS/s, 1MS/s, MS/s 12-bit: MS/s 10-bit: MS/s, 20MS/s, MS/s 8-bit: 1MS/s, MS/s, MS/s 6-bit: MS/s, MS/s
Converters
Multiplier Compiler Multiplicand (m): Multiplier (n): (even numbers only) Memory Macros SRAM Compiler: single dual port R/W, 1R), bits block, both Partial Write Compiler: 512K bits block High-density single-port 288K bits Register file (2R/W, 2R/2W), 4,608 bits Phase-Locked Loops Analog: (622 under development) I/Os 2.5V, 3.3V tolerant Slew-rate controlled CMOS, TTL, PCML, T-LVTTL, LVDS, PCI, SSTL, GTL+, AGP,
Cores 7TDMI Hard Macro 32-bit RISC 834/836 SPARClite Hard Macros Hard Macro 10/100 64/256 MPEG2 Decoder/Demultiplexer 8VSB Demodulator AC-3 Dolby Voice Decoder JPEG Encoder Decoder PCI-33/66 MHz, 32/64-bit cores Host ControllerDevice (ATA3) Host Controller Smart Card IRDA Interface More being added
ASIC Design Support
Design Verilog Logic Simulators from Cadence, Synopsys Mentor VHDL/VITAL Logic Simulators from Synopsys, Cadence, Mentor Synthesis, power, DFT, tools from Synopsys Other Tools Description Verilog-XL, NC-Verilog, VCS, Model-sim (Verilog)
VSS, Model-sim (VHDL), V-System, Leapfrog
Design Compiler, Design Power, Test Compiler, PrimeTime, MOTIVE, Sunrise TestGen Chrysalis Design Verifyer Sente Watt Watcher
Master Product Selector Guide
Package Availability
Number Pins Frame Size Thin Profile Package (0.4, lead pitch)
Shrink Package (0.5 lead pitch)
Heatspreader Package (0.4, lead pitch)
Ball Grid Array (1.27 ball pitch)
Fine-Pitch Ball Grid Array (0.75, ball pitch)
Ball Grid Array (0.8, ball pitch)
Application Specific (ASICs)
CS71 Series Standard Cell (0.25 CMOS Technology)
Features
0.18µm Leff (0.24µm drawn) million gates 0.05 µW/gate/MHz power dissipation 2.5V, 3.3V, tolerant options Special high-performance I/Os-PCML, LVDS, PCI, SSTL, GLT+, AGP, Core power supply voltage: 2.5V, 1.8V, 1.5V Junction temperature: -40°C~125°C High-performance embedded SRAM DRAM Analog digital PLLs Powerful mixed-signal offering-A/D convertors Advanced packaging Proven design methodology tool support
2.5V Device 2.5V CMOS 2.5V CMOS
CS71
3.3V Device
3.3V CMOS
3.3V Dual Power Supply CMOS (3.3V/2.5V) 5.0V Tolerant
T-LVTTL P-CML LVDS SSTL GTL+ ADC/DAC
High-Speed Interface
High-speed Devices
5.0V Device
5.0V
Analog Interface
Devices
Description
Fujitsu's CS71, 0.25µm (0.18µm Leff) standard cell product, based Fujitsu's state-of-the-art CMOS process technology-a process designed high performance high integration. CS71 family offers million gates, using many five layers metal. CS71 standard cell library most aggressive enhanced library implementing today's deep submicron system-on-silicon designs. cell library optimized synthesis-based designs, designed power. core process operates 1.5V, 1.8V, 2.5V with I/Os operating 2.5V, 3.3V, tolerant conditions. library supports most popular third-party tools data exchange file standards. Both standard staggered configurations available 44µm, 66µm, 88µm pitches. Interface options include low-swing, high-speed I/Os, high-speed interface I/Os. addition traditional packages, CS71 family available Ball Grid Array. CS71 offers rich ADCs DACs, digital analog PLLs, high-speed RAMs, ROMs, DRAMs, well variety other embedded functions. Design Methodology Fujitsu's design methodology ensures first-silicon success integrating proprietary point tools with most popular, sign-off quality, industry-standard tools. Fujitsu's clock-driven design methodology devised power skew. identifies best suited clock distribution strategy given design predicts performance advance. Fujitsu supports co-simulation, emulation, high-level floorplanning ease power, timing, size estimation design. This enables designer make effective architectural- level decisions toward achieving optimal design solutions. Fujitsu's design methodology supports cycle-based simulators formal verification, well static timing analysis more conventional VHDL Verilog simulators. Fujitsu design-fortest strategy includes boundary scan (JTAG), full partial scan, well built-in self-test memory. Applications CS71 offers high integration performance low-power performance low-power consumption. High-performance transmission switching applications, well power-sensitive applications, such mobile computing mobile communications, benefit from this technology.
Master Product Selector Guide
Mixed-Signal Macros
Converters
ASIC Design Support
Design Verilog Logic Simulators from Cadence, Synopsys, Mentor VHDL/VITAL Logic Simulators from Synopsys, Cadence, Mentor Synthesis, power, DFT, tools from Synopsys Other Tools Description Verilog-XL, NC-Verilog, VCS, Model-sim (Verilog)
10-bit: MS/s, MS/s. MS/s, MS/s, MS/s, MS/s 8-bit: KS/s, MS/s, MS/s
Converters
VSS, Model-sim (VHDL), V-System, Leapfrog
12-bit: MS/s 10-bit: MS/s, MS/s, MS/s 8-bit: MS/s, MS/s, MS/s 6-bit: MS/s, MS/s
Design Compiler, Design Power, Test Compiler, PrimeTime, MOTIVE, Sunrise TestGen Chrysalis Design Verifyer Sente Watt Watcher
Memory Macros SRAM Compiler: single dual port R/W, 1R), bits block, both Partial Write Compiler: 512K bits block High-density single-port 288K bits Register file (2R/W, 2R/2W), 4,608 bits Phase-Locked Loops Analog: (622 under development) I/Os 2.5V, 3.3V tolerant Slew-rate controlled CMOS, TTL, PCML, T-LVTTL, LVDS, PCI, SSTL, GTL+, AGP, Cores 7TDMI Hard Macros 32-bit RISC 834/836 SPARClite Hard Macros Hard Macro 10/100 64/256 MPEG2 Decoder/Demultiplexer 8VSB Demodulator AC-3 Dolby Voice Decoder JPEG Encoder Decoder PCI-33/66 MHz, 32/64-bit cores Host Controller Device (ATA3) Host Controller Smart Card IRDA Interface More being added
Application Specific (ASICs)
Package Availability
Pins Frame Size Thin Packages (0.4, lead pitch)
Shrink Package (0.5 lead pitch)
Heatspreader Package (0.4, lead pitch)
Ball Grid Array (1.27 ball pitch)
Fine-Pitch Ball Grid Array (0.75, ball pitch)
Ball Grid Array (0.8, ball pitch)
Master Product Selector Guide
CE66 Series Embedded Array (0.35 CMOS Technology)
Features
0.28µm Leff (0.34µm drawn) Propagation delay Mixed signal macros: converters High-density diffused RAMs ROMs Separate core supply voltages I/Os: 3.3V tolerant Core power supply voltage: 3.3V, 2.5V ~2.0V Junction temperature: -40°C ~125°C Special I/Os: PCI, I2C, Analog digital PLLs Packaging options: QFP, HQFP, LQFP, TQFP, PBGA, FBGA Support major third party tools
Fixed Layout Soft Macro
Embedded Hard Macro
Clock Tree
Fixed Layout Soft Macro
PCML
Description
Fujitsu's CE66 series high-performance, CMOS embedded arrays featuring mixed-signal macros, diffused high-speed RAMs, ROMs, variety other embedded functions. CE66 series combines density performance standard cells with time-to-market advantage gate arrays. addition, I/Os, operating 3.3V tolerant conditions, designed
P-Series with 100µm Inline Pitch
Frame CE66P1 CE66P2 CE66P3 CE66P4 CE66P5 CE66P6 CE66P7 CE66P8 CE66P9 CE66PA CE66PB CE66PC CE66PD CE66PE CE66PF Total Gates 188K 233K 283K 337K 396K 427K 460K 528K 602K 680K 761K 847K 940K 1037K 1138K Total Pads Signals
provide cost-effective solutions core-limited pad-limited designs. CE66 series features very power consumption 0.29µW/gate/MHz 3.3V. Potential applications CE66 series include consumer market, communications, networking designs.
S-Series with 70µm Inline Pitch
Frame CE66S1 CE66S2 CE66S3 CE66S4 CE66S5 CE66S6 CE66S7 CE66S8 CE66S9 CE66SA Total Gates 113K 137K 164K 207K 256K 311K 391K 481k 580K Total Pads Signals
Application Specific (ASICs)
Mixed-Signal Macros
Converters
More being added
ASIC Design Support
Design Verilog Logic Simulators from Cadence, Synopsys Mentor VHDL/VITAL Logic Simulators from Synopsys, Cadence Mentor Synthesis, DET, tools from Synopsys Other Tools Design Compiler, Test Compiler, PrimeTime, MOTIVE, Sunrise TestGen Chrysalis Design Verifyer Description Verilog-XL, NC-Verilog, VCS, Model-sim (Verilog) VSS, Model-sim (VHDL), V-System, Leapfrog
8-bit: (video) 8-bit: (video) 8-bit: (general purpose) 10-bit: (general purpose) 10-bit: (general purpose) 6-bit: (disk) 8-bit: (video) 10-bit: (general purpose) 10-bit: (general purpose)
Converters
Package Availability
Pins TQFP LQFP Frame Size
Multiplier Compiler Multiplicand (m): Multiplier (n): (even numbers only) Memory Macros SRAM Compiler: single dual port R/W, 1R), bits block, partial write option Compiler: 512K bits block Delay line: bits Phase-Locked Loops Analog: Digital: 180-360 (Preliminary) I/Os 3.3V, tolerant Slew-rate controlled CMOS, TTL, LVTTL, T-LVTTL, SDRAM I/F, PCI, I2C, Cores 32-bit RISC 832/833/835 SPARClite Hard Macros Hard Macro 10/100 64/256 MPEG2 Decoder/Demultiplexer 8VSB Demodulator AC-3 Dolby Voice Decoder JPEG Encoder Decoder PCI-33/66 MHZ, 32/64-bit cores Host Controller/Device (ATA3) Host Controller Smart Card IRDA Interface
HQFP PBGA FBGA
Master Product Selector Guide
CS66 Series Standard Cell (0.35 CMOS Technology)
Features
0.28µm Leff (0.34µm drawn) Propagation delay 0.3µW/gate/MHz power dissipation 3.3V Mixed-signal macros: converters High-density diffused RAMs ROMs Separate core supply voltages I/Os: 3.3V tolerant Core power supply voltage: 3.3V, 2.5V ~2.0V 100µm inline pitch core-limited designs Special I/Os: PCI, I2C, Analog digital PLLs Packaging options: QFP, HQFP, LQFP, TQFP, PBGA, FBGA Support major third party tools High-performance SRAM DRAM
3.3V Device 3.3V CMOS 3.3V CMOS
CS66
Dual Power Supply
5.0V Device
5.0V
5.0V Tolerant
(5.0V/3.3V)
T-LVTTL P-CML LVDS SDRAM SSTL ADC/DAC Devices
High-Speed Interface
High-Speed Devices
Analog Interface
Description
Fujitsu's CS66, 0.35µm (0.28µm Leff) standard cell product based state-of-the-art Fujitsu CMOS process technology-a process designed high integration cost effective solutions. cell-based design enables realization "system-on-silicon" applications that include following: User-defined logic Sophisticated analog functions High-density memory Intelligent peripherals Cores traditional packages, CS66 family available Ball Grid Array. CS66 also offers rich ADCs DACs, analog digital PLLs, high-speed RAMs, ROMs, DRAMs, along with variety other embedded functions. Design Methodology Fujitsu's design methodology ensures first-silicon success integrating proprietary point tools with most popular sign-off quality, industry-standard tools. Fujitsu's clock-driven design methodology offers power skew. identifies best-suited clock distribution strategy given design predicts performance advance. Fujitsu supports co-simulation, emulation, high-level floorplanning ease power, timing, size estimation design. This enables designer make effective architectural-level decisions achieve optimal design solutions. Fujitsu's design methodology supports cycle-based simulators formal verification, well static timing analysis more conventional VHDL Verilog simulators. Fujitsu's design-fortest strategy includes boundary scan (JTAG), full partial scan, well built-in self-test memory.
CS66 technology based enhanced 3.3V process that provides fast performance along with 3.3V power savings. CS66 standard cell library aggressive optimal library implementing today's high-performance deep submicron systemson-silicon. CS66 supports dense, high-clock frequency, system-level designs that meet performance, integration, power management requirements networking, telecommunication, electronic data processing, digital video applications. library also supports most popular third- party tools data exchange file standards. core operates 3.3V 2.5V with I/Os operating 3.3V, tolerant, combination these. addition
Application Specific (ASICs)
Applications
High-performance transmission switching applications power-sensitive applications, such mobile computing mobile communications, benefit from this technology. Mixed-Signal Macros
Converters
8-bit: (video) 8-bit: (video) 8-bit: (general purpose) 10-bit: (general purpose) 10-bit: (general purpose) 6-bit: (disk) 8-bit: (video) 10-bit: (general purpose) 10-bit: (general purpose)
Converters
Cores 32-bit RISC 832/833/835 SPARClite Hard Macros Hard Macro 10/100 64/256 MPEG2 Decoder/Demultiplexer 8VSB Demodulator AC-3 Dolby Voice Decoder JPEG Encoder Decoder PCI-33/66 MHZ, 32/64-bit cores Host Controller/Device (ATA3) Host Controller Smart Card IRDA Interface More being added
Multiplier Compiler Multiplicand (m): Multiplier (n): (even numbers only) Memory Macros SRAM Compiler: single dual port R/W, 1R), bits block, partial write option Compiler: 512K bits block Delay line: bits Phase-Locked Loops Analog: Digital: 180-360 (Preliminary) I/Os 3.3V, tolerant Slew-rate controlled CMOS, TTL, LVTTL, T-LVTTL, SDRAM I/F, PCI, I2C,
ASIC Design Support
Verilog Logic Simulators from Cadence, Synopsys Mentor VHDL/VITAL Logic Simulators from Synopsys, Cadence Mentor Synthesis, power, DFT, tools from Synopsys Other Tools Design Compiler, Design Power, Test Compiler, PrimeTime, MOTIVE, Sunrise TestGen Chrysalis Design Verifyer Verilog-XL, NC-Verilog, VCS, Model-sim (Verilog) VSS, Model-sim (VHDL), V-System, Leapfrog
Master Product Selector Guide
Package Availability
Pins TQFP LQFP HQFP PBGA FBGA P2,P3, Frame Size
Application Specific (ASICs)
CE61 Series Embedded Array (0.28µm Leff
Features
0.28µm Leff (0.35µm drawn) Propagation delay Mixed-signal macros: converters High-density diffused RAMs ROMs Separate core supply voltages I/Os: 3.3V tolerant 70µm staggered pitch pad-limited designs High-performance special I/Os: PCML, LVDS, PCI, SSTL Analog digital PLLs Packaging options: QFP, HQFP, Support major third party tools
PCML
Fixed Layout Soft Macro
Embedded Hard Macro
Clock Tree
Fixed Layout Soft Macro
Description
Fujitsu's CE61 series high-performance, CMOS embedded arrays, featuring full support mixed-signal macros, well diffused high-speed RAMs, ROMs, variety other embedded functions. CE61 series offers density performance approaching standard cells, provides time-to-market advantage gate arrays. E-series optimized pad-limited designs, F-series offers cost-effective solution corelimited designs. fifth metal layer option also available area bump designs, providing over 1,000 pads. Featuring true 3.3V internal operation, with 3.3V, tolerant I/Os, CE61 series features very low-power consumption 0.32µW/gate/MHz. Potential applications CE61 series include computing, graphics, communications, networking, wireless, consumer designs.
E-Series, 70µm Staggered Pitch, Optimized Pad-Limited Designs
Frame CE61E71 CE61E59 CE61E45 CE61E35 CE61E25 CE61E19 CE61E15 CE61E09 CE61E08 CE61E07 Total Gates 1,584K 1,149K 784K 602K 403K 280K 193K 120K Total Pads
F-Series, Optimized Core-Limited Designs
Frame CE61F80 CE61F70 CE61F60 CE61F50 CE61F40 CE61F30 CE61F20 CE61F10 Total Gates 2,026K 1,508K 1,182K 913K 664K 476K 303K 132K Total Pads
Master Product Selector Guide
Mixed-Signal Macros Converters 8-bit, (video) 8-bit, (video) 8-bit, (video) 10-bit, (general purpose) 8-bit, (general purpose) Converters 8-bit, (video) 6-bit, (disk drive) 10-bit (digital communications) 8-bit, (general purpose) 10-bit, (general purpose) Multiplier Compiler Multiplicand (m): Multiplier (n): (even number only) Memory Macros SRAM Compiler: single dual port R/W, 1R), bits block Compiler: 512K bits block Phase-Locked Loops Digital: Analog: I/Os 3.3V, tolerant Slew-rate controlled CMOS, TTL, PCML/PECL, LVDS, PCI, SSTL, 1284, GTL+ Mega Macros achieve highest level integration customers, Fujitsu offers rich intellectual properties (IPs), developed either internally acquired through strategic relationships with providers. Interface Functions ARC: 32-bit embedded core OakDSPCore®: 16-bit fixed point core core 10/100 Ethernet P1394 High-Performance Functions MPEG2 (Q1'99) 16/64/256 (Q1'99) QPSK (Q1'99)
ASIC Design Support
Design Verifire (VCS, Cadence Tools, Synopsys, Synthesis) Description Verilog-XL Sign-off Simulation Veritime Verifault Design Compiler (Synopsys) Vhdlfire Vital compliance tools Sign-off Simulation Design Time Design Compiler Other Tools Motive, Sunrise, HLD, DesignPower
Package Availability
Number Pins Frame Size Quad Flat Packages (1.0, 0.8, 0.65 pitch) F10, E7/8/9/15/19/25/35/45 E7/8/9/15/19/25/35/45/59, F20/30/40/50/60/70/80
Shrink Quad Flat Packages (0.5 pitch) (0.4 E7/8/9, E7/8/9, E9/15, E7/8/9/15/19/25/35/45, E7/8/9/15/19/25/35/45, F20/30/40/50 E8/9/15/19/25/35/45, F20/30/40/50 E9/15/19/25/35/45/59, F20/30/40/50/60/70/80 E15/19/25/35/45/59, F30/40/50/60/70 F40/50/60/70/80 F50/60/70/80 E19/25/35/45/59
Heatspreader Quad Flat Packages (0.5 pitch) (0.4 E9/15/19/25/35/45/59/71, F20/30/40/50/60/70/80 E15/19/25/35/45/58/71, F30/40/50/60/70/80 F40/50/60/70/80 E35/45/59/71, F50/60/70/80 E19/25/35/45/59/71
Ball Grid Array (1.27 pitch) E15/19, F40/50 E25/35, F60/70 E35/45, F60/70 E45/59
Application Specific (ASICs)
Processor Core
Features
Application-specific custom core instruction Eliminates need separate processor Supports operation (typical) 2.5V Single hardware software development environment Small size Embedded on-chip debug logic instructions. processor separate instruction data buses, number external interrupt signals. offers separate instructions; first instructions pre-defined base case provide arithmetic logical instructions well load/store branch/jump instructions. remaining instructions available customer application-specific extensions; these instructions from library ones that have been developed customer. Extension instructions single multi-cycle built with instruction-specific local memory that separate from other memory systems. development environment provides seamless simulation testing environment, essentially providing many levels code simulation testing. High software development toolchain directly linked into flow providing detailed information about each step design flow. This core ideally suited variety applications consumer space Global Positioning Systems (GPS), handheld devices, digital cameras, cordless phones, well networking space router applications.
Benefits
reduction power dissipation High performance demanding applications Cost effective ASIC integration Embedded system ready fast time-to-market
Description
comprised Base RISC Engine, Extension Library, Architect, integrated test suites, multi-interface architecture, Co-design toolset, complete software development toolchain, both hardware software emulators. Provided synthesizable "soft macro" with configuration controlled user through Architect test suite, architecture configured meet specific performance cost targets enabling customers effectively manage their design process system level. 4-stage pipeline processor incorporating full 32-bit instructions, data addressing. instruction orthogonal with addressing modes implemented arithmetic logical instructions, well optional conditional execution
Deliverables
Fujitsu application engineer works with customer determine process technology best suited customer's specific need. After technology selected, following deliverables supplied customer: source codes written VHDL VHDL Test Bench functional verification
Master Product Selector Guide
Sonet STS-3c/SDH STM-1 Framer Core
Features
Compliant with ITU-T I.432, ANSI Bellcore compliant System interface Utopia Level Simple byte format line interface Processes following overhead bytes:
Section (OOF, LOF, alarms, access) Line (L-AIS, L-RDI alarms, BIP, access APS, (L-FECV) Path (P-AIS, P-RDI, P-LOP, P-PLM, P-UNEQ alarms, BIP, access, processing Apayload hex), (P-FECV))
Description
Sonet Framer macro implements transmission convergence sublayer required Sonet STS-3c STM1 Adata transport. macro been designed with hierarchy that contains framing functions, cell handling functions configuration/register access handling separate submodules. transmit Acell stream mapped into Sonet/SDH Mbps framing structure, inserting required framing overhead bytes. This data output byte format across simple interface, where passed Sonet/SDH transceiver. receive path takes byte stream from Sonet/SDH Mbps transceiver, extracting processing framing overhead bytes passing Astream Framer configuration overhead byte access will handled across common slave only interface. framer power-up already configured basic operation. This core ideally suited variety applications wide area networking space, including, Aswitches, routers, switches, more emerging equipment optical transport arena.
Cell handling includes: Cell delineation using HEC/HEC calculation insertion Cell header error detection/correction Cell payload scrambling/de-scrambling Idle cell unassigned cell handling Statistics event triggering Interfaces directly Cell Buffer macro
Benefits
Rich features compatible with industry standards Industry standard Utopia Level interface Easy interface SONET/SDH transceiver
Deliverables
Fujitsu's application engineers work with customers help them select process technology that will suit customer's specific need. After technology selected, following supplied customer: Encrypted source codes written Verilog representing entire hierarchical OC-3 Framer core design. Encrypted Verilog Test Bench functional verification. hierarchical gate level netlist framer core.
Application Specific (ASICs)
ARM7TDMIProcessor Core
Features
32-bit addressing Thumb® 16-bit instruction extension Supports operation (typical) 2.5V Static design low-power dissipation mW/MHz Small size Embedded on-chip debug logic Well-supported hardware software environment slow. core will consume MHz(average) 2.5V, which makes ideal power applications market. core area just mm2, making very cost competitive ASIC integration. Fujitsu's core supported MicroPakperipherals provided ARM, including Advance Peripheral (timer, interrupt controller, remap, pause controller), Advanced System (external memory interface, test interface controller, decoder, arbiter, reset controller). Fujitsu developing additional peripherals such cache controller embedded DRAM controller assist customers with complex system-ona-chip designs.
Benefits
linear address space removes need segmented, banked, overlaid memory 32-bit performance 16-bit system cost High performance demanding applications Ideal low-power applications, such cellular phones hand-held devices Embedded system ready fast time market
Deliverables
Fujitsu value-added ARM7TDMI Processor Core enables customers design variety complex system-on-a-chip ASIC designs resulting fast time-to-market. Fujitsu application engineer works with customer identify customers' specific requirements. Fujitsu will provide customer with following information support ARM7TDMI core: Verilog Model Front-end simulation model with Verilog wrapper Design Compiler Model Timing analysis Library Exchange Format (LEF) Floorplanning Place Route
Description
ARM7TDMI embedded core part Fujitsu's IPWareLibrary. Fujitsu ARM7TDMI processor core, developed ARM, implemented Fujitsu's 0.25µm process technology. This core contains ARM7TDMI processor features, including 32-bit RISC engine, Thumb instruction (smaller code size), debug functions, multiplier, embedded support logic. ARM7TDMI processor supported multiple hardware software vendors through wide array development tools RTOS created ARM. ARM7TDMI processor supports speeds (typical case) 2.5V (worst case) 2.3V, 125C, process
Master Product Selector Guide
UTOPIA Level
Features
layer Alayer operation Level Level support Cell octet-level handshake support Level Supports 16-bit Utopia Interface; simple interface cell buffer macro Basic polling interfaces allowing user defined polling schemes Supports range cell sizes from bytes Support flexible, user-configurable polling schemes simple synchronous interfaces Operates
Description
Utopia Level interface provides standard interface between single Alayer device multiple layer devices. macro also configured Utopia Level interface, which used provide standard interface between single Alayer device single layer device. macro used either ALayer Layer mode. Eight 16-bit Utopia data supported. macro also performs data flow control between layers: parity checking port address/poll address routing. routing (0-15 bytes long) added each Acell, which treated extension cell. Likewise, Acell include field. Corresponding UDF1 UDF2 bytes included cell, depending whether 16-bit mode selected. This core ideally suited variety applications local area networking (LAN) space switches Aaccess switches. also employed wide area networking (WAN) space switches, routers, well applications Central Office (CO) Consumer Premise Equipment (CPE) equipment.
Benefits
Support AForum specification Level Simple synchronous interface cell buffer macro Allows target device address decoding polling schemes attached externally
Deliverables
Fujitsu application engineer works with customer help them select process technology that best suits customer's specific need. After technology selected, following deliverables supplied customer: Encrypted source codes written Verilog HDL, representing entire hierarchical Utopia II/I core design Encrypted Verilog Test Bench functional verification hierarchical gate-level netlist framer core
Application Specific (ASICs)
10/100 Mbps Ethernet Core
Features
Independent Interface (DII) generic interface System 10/100 Mbps Media Independent Interface (MII) connecting various types Physical Layers Optional 7-wire interface connecting legacy Mbps Physical Layer Full IEEE 802.3/802.3u compliant Address Recognition Logic (ARL) destination address lookup filtering Optional external CAM, ROM, EEPROM interface PAUSE Flow Control operation full-duplex link (802.3x) Parallel generation Command Status Registers (CSR) that provide various softprogrammable features minimize connection wires
Description
10/100 core part Fujitsu IPWareLibrary. 10/100 core PAUSE Flow Control Ethernet Media Access Controller (MAC) capable both Mbps data operation. fully compliant with IEEE 802.3 802.3u Specifications that employ Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. PAUSE Flow control provides hardware support full-duplex flow control. standard connecting Mbps MII-supported PHY, such 100Base-T4, 100Base-FX, 10Base-T, 10Base-F optional 7-wire interface chosen, provide connection legacy Mbps Physical Layer, namely 10Base-T, 10Base-2, 10Base-5, even 10Base-F independent interface (DII) generic interface that uses simple handshake protocol. connected number standard interfaces system buses, such PCI, ISA, EISA, 680x0, nuBus, etc. ASIC core provides various soft-programmable features. These on-board registers also minimize number connection wires between Interface Unit ASIC core. registers programmed handle nonstandard packet sizes such Long Packets Short Packets. Short Packets very useful fast testing.
Benefits
Soft core that implemented technology University Hampshire (UNH) compliant core IEEE 802.3/802.3u compliant core with PAUSE capability Optional serial interface external ROM/EEPROM Synchronous Clock design Internal Scan JTAG Boundary Scan that inserted customer before netlist handoff Fujitsu after design handoff
Deliverables
Fujitsu's application engineer works with customers helps them select process technology that will suit customer's specific need. After technology selected, following supplied customer: Encrypted source codes written Verilog rep-resenting entire hierarchical core design Encrypted Verilog Test Bench standalone cores functional verification hierarchical gate level netlist core
Master Product Selector Guide
Peripheral Core
Features
V2.1 compliant 32-bit 64-bit 32-bit 64-bit Application Datapath Speed Options Fast back-to-back Master Cycles Support Full Bandwidth Burst Support Read-only Configuration Register optionally downloaded from EEPROM system start-up Memory Write Invalidate Support Dual Address Cycles Support Fujitsu Core family architected performance, verified through combination logic synthesis, floorplanning, place route, post layout timing verification with deep-submicron libraries. Cores offer synchronous asynchronous application interfaces. Asynchronous Cores synchronize control data signals between clock application clock, which operate different frequency. synchronous Cores assume that signals from application synchronized clock. read-only register within configuration space optionally downloaded from EEPROM system startup. Information such vendor which typically hard-coded into chip incorporating core, loaded system start. This allows same chip used more than system.
Benefits
Soft core that implemented technology Rigorous testing performed ensure compliance functional correctness wide range operations Synchronous asynchronous application interfaces Internal scan JTAG boundary scan inserted customer before netlist handoff Fujitsu after handoff
Deliverables
Fujitsu family application-optimized synthesizable cores become facto standard designers need high performance, off-the-shelf availability, fast incorporation into ASIC designs. Fujitsu's application engineer works with customers helps them select process technology that will suit customer's specific need. After technology selected, following supplied customer: Encrypted source codes written Verilog representing entire hierarchical core design hierarchical gate level netlist core
Description
Synthesizable Core part Fujitsu IPWareLibrary. Fujitsu Cores synthesizable modules that provide interface between application bus. protocol timing requirements handled core, which controlled through simple application interface. Fujitsu Cores available 32-bit 64-bit paths either application interface. FIFO configured different depths. Also, Fujitsu provide these cores without FIFOs.
Application Specific (ASICs)
Function Core
Features
USBV1.0 compliant Mb/s Mb/s data transfer rate Scalable physical parameters Selectable synchronous/asynchronous reset mode Suspend/resume logic provided Programmable number end-points bit-level protocol. module transmits receives packets, handles parallel-to-serial serial-to-parallel data conversion, NRZI encoding/decoding, surfing/stripping, checking generation. also monitors handles reset, suspend, resume signaling. Device Configuration module contains device request control, configuration scan, endpoint information register modules. device request control module receives handles device requests, either processing them passing them application processing. configuration scan module accesses device, configuration, interface, end-point descriptors. core expects descriptors stored another addressable element within application logic. endpoint information register module holds current configuration, interface, end-point information device. Function Core ideally suited variety applications including, limited pointing devices, scanners, cameras, machines, printers, joysticks, keyboards.
Benefits
Soft core that implemented technology Silicon-proven decrease time-to-market Provides longer battery life portable devices Scalability meet different application speeds Supports wide range function device classes (low cost, medium speed)
Description
Function Core synthesizable core part Fujitsu IPWare Library. This core fully compliant with revision specification. This core includes main modules: Serial Interface Engine (SIE) Device Configuration module shown block diagram. module contains receiver, transmitter, control, function control, control, clock recovery, power management/timing control modules. Together these modules manage
Deliverables
Fujitsu Microelectronics, Inc. application engineer works with customer select process technology best suited meet customer's specific needs. After technology selected, following information supplied customer: Encrypted Verilog source code hierarchical gate level netlist
Master Product Selector Guide
Host Controller Core
Features
USBV1.0 compliant Open HCIV1.0 compliant PCIV2.1 compliant Mb/s Mb/s data transfer rate Integrated root
Description
Host Controller synthesizable core part Fujitsu IPWare Library. core complete interface. fully compliant with specification Open specification authored Microsoft, Compaq, National Semiconductor. side, compliant with V2.1. core used motherboard with stand-alone PCI-based ASSP. interface contains primary modules. serial interface engine (SEI), responsible protocol, other root hub, used expand number ports. Host Controller incorporates much intelligence required processing incoming outgoing data, well legacy keyboard support PS/2 keyboards con-nected PS/2 keyboard controllers through Port 60/64. This core ideally suited variety applications ranging from palmtop computing, mobile computing, other consumerrelated applications such medical monitoring devices.
Benefits
Soft core that implemented technology Silicon-proven reduce time-to-market Legacy keyboard mouse support Supports control, bulk, isochronous, interrupt data transfer types support various applications
Deliverables
Fujitsu Microelectronics, Inc. application engineer works with customer select process technology best suited meet customer's specific needs. After technology selected, following information supplied customer: Encrypted Verilog source code hierarchical gate level netlist core
Application Specific (ASICs)
ASIC Packaging
Fujitsu, world leader packaging interconnect technology, offers extensive range packages from industry-standard Quad Flat Pack (QFP) wide variety Ball Grid Array (BGA) configurations. Fujitsu owns operates several ISO-level package manufacturing assembly facilities Japan, shipping millions packages month meet needs customers. ASIC customers, Fujitsu offers "one-stop shopping" their packaging needs. addition robust "off-the-shelf" standard packages, Fujitsu offers ASIC customers capability complete in-house turnkey package design, well assembly test services. range ASIC packaging solutions Fujitsu provides includes lead insertion matrix-type PGAs surface mount Flat Quad Lead, type QFP, LQFP, TQFP, HQFP, Matrix type BGAs LGAs. Fujitsu's packages ideally suited communication computation ASIC applications offered following categories: Flip-chip Ball Grid Arrays (FC-BGA) Providing range packaging solutions Tape-automated-bonding Ball Grid Arrays (TAB-BGA) Providing thermal-enhanced packaging solutions Enhanced Ball Grid Arrays (EBGA) Providing Electrical thermal-enhanced packaging solutions Fine-pitch Ball Grid Arrays (FBGA) Providing Chip-Scale Packaging (CSP) solutions Face-down Heat-enhanced Ball Grid Arrays (FDH-BGA) line offered cost-effective thermal enhanced packaging solution
FC-BGA Packages
Encapsulation Adhesive Themal Compound Chip Capacitor Area Bump
Glass Ceramic (thick-film)
Solder Ball
Traditional packaging, with perimeter wire-bonded dies, longer meets requirements today's high pin-count chips, such those required GHz-range sustained frequencies. result, more sophisticated, bumped-area flip-chip interconnect technology preferred, excellent thermal dissipation capability which inherent structure. Inside Flip-chip packages, Fujitsu's unique wiring strip interconnect technology further enhanced thermal electrical characteristics these packages. features Fujitsu's FC-BGA technology are: High pin-count 2116 1.00mm ball-pitch, small sizes lighter weights Some offerings FC-BGAs 1.27mm ball pitch Excellent electrical properties dielectric constant inductance multi-layer layers) build-up substrate technology Superb power dissipation further augmented thermal vias, thermal compounds, heat spreaders heat sinks profile JEDEC-standard packages easily surface mountable conventional standard boards Fujitsu's FC-BGAs especially suited high integration computing communication applications Ultra thin profile, including heat spreaders (2.5mm -3mm) Moisture resistant (JDEC Level
Master Product Selector Guide
FBGA Packages
Fine-pitch (FBGA) technology, Fujitsu's Chip Scale Packaging (CSP) solutions, provides benefits reduced package space weight. Utilizing polyamide tape substrate, FBGAs available rectangular square body size packages.
Packages
Enhanced (EBGA) packages offer cost-effective electrical thermal solutions mid-range pin-count chips. multi-layer substrate provides excellent electrical performance. Fujitsu's EBGAs have built-in ultra-thin heat spreaders improved characteristics superb thermal dissipation. EBGA packages available styles: 1-Tier Type
Wire
Encapsulant
layers lamination 200-300 performance 2-Tier Type
Solder Polyimide Substrate Attach
layers lamination High performance
Heat Spreader Thermal Compound
Features Fine-pitch packages are: count packages some pins JEDEC-approved fine Ball pitch with lowest pitch just 0.5mm highest 0.8mm Small-outline Low-profile package Provides cost-effective packaging density Good replacement candidate QFP/Shrink-QFP technology
Solder Ball
Sealing Resin
Wire
Standard Features Cavity down with various types thermal-efficient heat-spreaders high-power design applications Square outline 1.27mm ball pitch Ultra-thin profile Surface mountable JEDEC compliant Wire (Au-wire) bonding Sealed resin cavity high reliability
Application Specific (ASICs)
FDH-BGA Packages
Soon added Fujitsu's packaging family Faced-down Heat-spreader BGA, which cost-effective Thermal-enhanced packaging solution. main features FDH-GBA are: Printed circuit board: FR-4 (High type) Heat spreader: Copper with plating Adhesive: Silver epoxy paste Wire bonding: wire Mold resin: Epoxy type
Anchor holes (filled resin) Adhesive Heat Spreader
TAB-BGA Packages
Heat Spreader Stiffener
Tape
Encapsulation Solder Ball
Mold Resin
Pattern (Cu)
Solder Resist
Wire
FR-4 High Solder Ball
Tape Automated Bonding (TAB-BGA) packages, leads connect package lead-frame directly Au-bumps, thereby eliminating bond wires conventional maximum bond-wire length constraint. conventional wire-bond technology maximum bond wire length angle constraints sometimes prevents small into large cavity package. However, TAB-BGAs, package lead-frame custom designed each based size pin-count. result, both lengths angles leads optimized that particular application. Consequently, this method facilitates reduction pitch much possible. Padlimited designs decrease/optimize size through reduced pitch. Fujjitsu's TAB-BGA packages with metal heat spreaders excellent high-power chips requiring high-thermal dissipation. Additional features TAB-BGA package follows: Supports high pin-counts: 272-720 pins Provides Flexibility assignment Square body 0.8mm 1.00mm ball pitch Excellent heat dissipation with heat spreader profile package Cost-effective packaging high pin-count designs
Master Product Selector Guide
PBGA Packages
Plastic Over Molded Array Carrier (OMPAC) style package designed low-cost applications. This utilizes four-layer printed circuit board substrate that provides high level electrical performance. PBGA packages provide good thermal performance with moderate power dissipation. Thermal performance further enhanced through additional thermal vias balls placed directly under mounting area. Epoxy-filled through holes substrate ensure high level reliability. very cost-sensitive designs, lower performance, two-layer low-cost printed circuit board version PBGA also available.
Mold Resin
Packages
Fujitsu offers both plastic ceramic packages 1.00, 0.80, 0.65, 0.50 0.40 lead pitches. leads this package extend from four sides package. leads either gullwing (L-shaped) straight. These packages conform industry standards with counts ranging from pins. Lead frames constructed with either iron/nickel alloy copper alloy that offers good thermal electrical performance. Shrink-QFP (SQFP) uses lead pitch lead counts ranging from 304. example, regular 144-pin package 28x28 0.65mm lead pitch. Whereas, same 144-pin shrink version SQFP just 20x20 0.5mm lead pitch. Heat spread-QFP (HQFP) package uses heat-spreader that attached bottom then attached leadframe with adhesive tape. HQFP offers better thermal performance than traditional packages. ASIC applications, additional types packages, Low-profile (LQFP) Thin (TQFP), available. Mounting height TQFP packages thinnest with maximum height only 1.27mm. LQFP packages have smaller body size than regular QFP. lead pitch both LQFP TQFP packages 0.40 0.50
Board
Chip
Solder Ball
Features include: 1.27mm ball pitch Square body Pin-count: 256-480 pins
Application Specific (ASICs)
CPGA Packages
Ceramic (laminated)
(ceramic, metal) Seal (Low melting point braze metal) Metalize (tungusten) Laminated ceramic (alumina) (Kovar)
Although Ceramic Grid Array packages (CPGA) less popular today cost lower value compared QFPs BGAs, some low-end Fujitsu ASIC series still being offered CPGA packages. CPGA packages have 2.54mm leadpitch they available 321, counts. leads this package extend straight down from bottom package grid arrangement.
Master Product Selector Guide
ASIC Mixed-Signal Analog Macros
Capacitor Resistor Analog P-well Deep N-well Analog Circuit N-well Digital VSS/Gnd Digital Circuit P-Sub P-well N-well
Features
Leading-edge 0.35, 0.25, 0.18-micron technologies, with choice standard twin-well high performance triple-well design Well-adapted Standard Cells Embedded Arrays, including Embedded DRAM ASIC products converters: 6-bit 10-bit, 1MS/s MS/s converters: 8-bit 10-bit, MS/s MS/s Analog PLLs other analog functions power consumption Disable reducing power consumption IDDQ test Precision resistors capacitors analog designs (see illustration above)
from Fujitsu's IPWareare provided enable customers implement system-level solutions single chip. Triple-Well CMOS Process Fujitsu's triple-well process allows P-well placed inside N-well, resulting three types well structures, shown illustration above. This third type well useful isolating circuitry within from other sections chip reverse bias between N-well P-substrate. mixed-signal designs, where noise injection problem, analog sections completely isolated from digital section using this third type well structure. There resistive path between analog digital circuit, since P-well connected analog isolated from digital VSS/ground reverse biased N-well. triple-well also significantly reduces capacitive coupling between analog digital VSS/ground. Consequently, high degree isolation achieved sensitive analog circuits from detrimental digital noise sources. Triple-well enables Fujitsu design high-precision analog macros, such 10-bit DAC, mixed-signal ASICs. With triplewell, sensitive analog circuits mixed-signal ASICs protected from noise sources high-speed digital logic blocks. This isolation technique facilitates positioning digital mixed-signal blocks closest proximity possible, thereby reducing overall size.
Description
Technology Overview achieve highest level system integration, Fujitsu offers variety analog mixed-signal macros customer conjunction with Embedded Arrays Standard Cell libraries. Data communications, networking, graphics, digital audio/video among applications that take advantage these mixed-signal analog macros. Additionally, embedded RAMs, ROMs, phase-locked loops (PLLs), other cores
Application Specific (ASICs)
Design Support
IEEE involved ongoing process define standardize common analog behavioral modeling language, called VHDL-A. Fujitsu will support VHDL-A when ratified. Currently, Fujitsu supports following mixed-signal simulation tools: Behavioral/Gate Level Simulation Verilog Digital gate level libraries Analog macro functional models VHDL Digital gate level VITAL compliant libraries Analog macro functional models Interface Timing Models Synopsys Design Compiler Prime Time Transistor-Level Simulation Hspice Spice netlist Level BSIM-3 models 0.35µm Macro Library Converters 10-bit: MS/s (general-purpose) bit: MS/s (general-purpose) 8-bit: MS/s, 3.3V 8-bit: MS/s, 3.3V 8-bit: kS/s (general-purpose) Phase-Locked Loops (PLLs) Analog: 50-200 Digital: 180-360 0.25µm Macro Library Converters 10-bit: MS/s, 2.5V 10-bit: MS/s, 2.5V 10-bit: MS/s, 2.5V 10-bit: MS/s, 3.3V 10-bit: MS/s, 3.3V 8-bit: MS/s, 3.3V 8-bit: MS/s, 2.5V 8-bit: kS/s, 2.5V 8-bit: MS/s, 3.3V 8-bit: kS/s, 3.3V Converters 10-bit: MS/s, 2.5V 10-bit: MS/s, 2.5V 10-bit: MS/s, 2.5V 10-bit: MS/s, 3.3V 8-bit: MS/s, 2.5V 8-bit: MS/s, 2.5V 8-bit: MS/s, 2.5V 8-bit: MS/s, 3.3V 8-bit: MS/s, 3.3V 6-bit: MS/s, 2.5V Converters 10-bit: MS/s, 3.3V 10-bit: MS/s, 3.3V 8-bit: MS/s, 3.3V 6-bit: kS/s, 3.3V
Phase-Locked Loops (PLLs) Analog: (622 under development) 0.18µm Macro Library Converters 10-bit: MS/s, 3.3V 10-bit: MS/s, 3.3V 10-bit: MS/s, 3.3V 8-bit: MS/s, 3.3V 8-bit: MS/s, 3.3V Converters 10-bit: MS/s, 2.5V 10-bit: MS/s, 3.3V 10-bit: MS/s, 3.3V 8-bit: kS/s, 3.3V 8-bit: MS/s, highspeed 3.3V 8-bit: MS/s, highspeed 3.3V 8-bit: MS/s, 3.3V 6-bit: MS/s
Phase-Locked Loops (PLLs) Analog: Other Analog Macros ASIC Op-amps: General-purpose, noise, high speed, unity-gain buffer, speaker amplifier Various kinds, including high stability bandgap reference General-purpose, 1-ch, 1-ch inv, 2-ch 20-400 High-speed general purpose Detectors bias circuits
Bias Vref Circuits:
Analog Switches: Delay Locked Loops (DLLs): Comparators: Fuses:
Master Product Selector Guide
Microcontrollers
Fujitsu offers broad spectrum 16-, 32-bit microcontrollers, covering general purpose application-specific types, with rich variety features, including latest technologies, such on-chip Flash ROM. supported quality software hardware development tools, making Fujitsu ideal one-stop-shop those seeking make their products benefit from microcontroller revolution.
Master Product Selector Guide
F2MC
16-bit Flexible Microcontrollers
F2MC, which stands Fujitsu Flexible Microcontrollers, includes Fujitsu's original general-purpose applicationspecific microcomputers. F2MC line includes F2MC-8L series with 8-bit architecture F2MC-16L/16LX/16F series with 16-bit architecture. F2MC provides efficient development system that supports flexible range needs. Fujitsu also provides software support packages backup endusers, such powerful emulator that supports debugging realtime processing application software development, macro assembler compiler that support large-scale software development.
F2MC-16L/16LX/16F Series Features
Memory Space: maximum Reinforced 32-bit operation using 32-bit accumulator/register: 32-bits 32-bits 16-bits 16-bits 32-bits 16-bits Multiple interrupts based eight priority levels F2MC-16L Minimum instruction cycle: 62.5 ns/16 Operating voltage range: 2.7V 5.5V Pipeline processing using four-byte queue Built-in clock multiplier that Expanded power management modes: operation, Stop, Sleep, Watch, Intermittent operation Number instructions: F2MC-16LX Minimum instruction cycle: 62.5 ns/16 Operating voltage range: 3.0V 5.5V avoidance program patch processing Expansion from F2MC-16L functions plus signed multiplication/division instructions F2MC-16F Enhanced high-speed signed operation Enhanced real-time instructions Pipeline processing using eight-byte queue high-speed operation with Harvard architecture External access cycle equivalent internal access cycle (two cycles) Number instructions:
MC-8L Series Features
Operating voltage: 2.2V 6.0V
Minimum instruction cycle: 0.32µs/12.5 Data retention voltage: 1.5V minimum Clock gear function: Four-stage software selectable instruction cycles Memory space: maximum Memory-mapped 8-bit general-purpose register registers/banks, banks) Enhanced multiple interrupt handling Powerful arithmetic operation transfer functions: Multiplication/division instructions 8-bit 8-bit 16-bit, 16-bit/8-bit 8-bit 16-bit data transfer Number instructions:
Microcontrollers
F2MC-8L/Low Power/Low Voltage Microcontrollers
Features Series MB89xxx 120/A Part MB89121 MB89123A MB89125A MB89131 MB89P131 MB89133A MB89P133A MB89135L MB89P135A MB89144A MB89144 MB89145 MB89146 MB89P147 MB89143A ROM/ Byte 1024 Clock (kHz) (32) (32) Ports Ext. Inter. Timer Timer Timer/ Counter UART Serial Conv. Contr. Buzzer Special Features (A-Version with on-chip Remote Control (A-Version with on-chip Remote Control) PowerSaving Modes SLEEP STOP CLOCK SLEEP STOP CLOCK Count
130/A
(32)
Driver outputs) Programmable Pulse Generator Driver outputs) Remote Control, (A-Version with on-chip voltage booster) Remote Control, (A-Version with on-chip voltage booster) DTMF Generator
SLEEP STOP CLOCK
(32) (32)
8bit
SLEEP STOP CLOCK SLEEP STOP CLOCK
150/A
MB89151/A MB89152/A MB89153/A MB89154/A MB89155/A MB89P155/A MB89161/A MB89163/A MB89165/A MB89P165/A MB89173 MB89P173 MB89174A MB89P175A MB89173L MB89174L MB89181 MB89182 MB89183 MB89184 MB89185 MB89P185 MB89191 MB89191A MB89191AH MB89193 MB89193A MB89193AH MB89195 MB89P195 MB89195A MB89P195A MB89537/C/H/HC MB89538/C/H/HC MB89P538
1024 2048 2048
160/A
(32)
SLEEP STOP CLOCK
170/A
3.58 (32) 7.16 (32) 3.58 (32) (32)
SLEEP STOP CLOCK SLEEP STOP CLOCK SLEEP STOP CLOCK
170L
Remote Control
190/A/AH
Remote Control, High Current Outputs version)
SLEEP STOP
530/C/H/HC
12.5 (32)
I2C-Interface versions) 5V(H) mask versions Converter, Programmable Pulse Generator Dual power supply 3V-5V needed I2C-Interface versions) 5V(H) mask versions DAC:
SLEEP STOP CLOCK
550A
MB89557A MB89558A MB89P558A
1024 2048 2048
12.5 (32)
SLEEP STOP CLOCK
560/C/H/HC
MB89567/C/H/HC MB89P568
1024 1024
(32)
SLEEP STOP CLOCK
MB89577 MB89P579[4]
3072 3072
(32)
SLEEP STOP CLOCK SLEEP STOP SLEEP STOP
MB89583[4] MB89585[4] MB89P585 MB89593[4] MB89595[4] MB89P595
1024 1024 1024 1024
0.33
Function
0.33
Function
Master Product Selector Guide
F2MC-8L/Low Power/Low Voltage Microcontrollers (continued)
Features Series MB89xxx Part MB89601 MB89P601 MB89603 MB89613R MB89615R MB89623R MB89625R MB89P625 MB89626R MB89627R MB89P627 MB89628R MB89629R MB89P629 MB89T623 MB89T625 MB89T627 MB89635R MB89636R MB89637R MB89P637 MB89T635R MB89T637R MB89643 MB89645 MB89646 MB89647 MB89P647 MB89653AR MB89655AR MB89656AR MB89657AR MB89P657A MB89663R MB89665R MB89P665 MB89673R MB89673AR MB89675R MB89675AR MB89677A/AR MB89P677A MB89689 MB89P689 ROM/ Byte 1024 1024 3072 3072 4096 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 2048 2048 Clock (kHz) Ports Ext. Inter. Timer Timer Timer/ Counter UART Serial Conv. Contr. Buzzer Special Features PowerSaving Modes SLEEP STOP SLEEP STOP SLEEP STOP Count
External Interface External Interface
(32)
External
SLEEP STOP CLOCK
(32)
External Interface conv.
SLEEP STOP CLOCK
650A
(32)
SLEEP STOP CLOCK
Input Capture Output Compare External Up/Down Counter
SLEEP STOP HWSTB SLEEP STOP
670A
(32)
Modem Signal Output
SLEEP STOP CLOCK SLEEP STOP CLOCK SLEEP STOP SLEEP STOP
810A
MB89816A MB89P817A MB89821 MB89823 MB89P825 MB89855R MB89857 MB89P857 MB89T855 MB89865 MB89867 MB89P867 MB89875 MB89P875 MB89898 MB89899 MB89P899 MB89913 MB89915 MB89P915 MB89923 MB89925 MB89P928
2048 2048 1024 1024 1024 1024 1536 2048 2048 1024
(32)
External Interface Motor External Interface Motor
(32) (32) (32)
SLEEP STOP
SLEEP STOP CLOCK SLEEP STOP CLOCK SLEEP STOP CLOCK SLEEP STOP
Modem Signal Output, DTMF Generator Driver, outputs) Voltage Detection Reset Voltage Detection, Timer, Input Capture, Output Compare
Microcontrollers
F2MC-8L/Low Power/Low Voltage Microcontrollers (continued)
Features Series MB89xxx Part MB89935 MB89P35 ROM/ Byte Clock (kHz) Ports Ext. Inter. Timer Timer Timer/ Counter UART Serial Conv. Contr. Buzzer Special Features Input Capture Programmable Pulse Generator Stepper Motor Driver 5.5V Operation, Voltage Reset, External Voltage Monitor Interrupt PowerSaving Modes SLEEP STOP Count
MB89943 MB89P945
SLEEP STOP
MB89951 MB89953 MB89P955 MB89965C MB89P965A MB89983[4] MB89P985[4]
SLEEP STOP SLEEP STOP CLOCK SLEEP STOP CLOCK SLEEP STOP
(32) (32)
I2C-Interface, 5.5V Operation
MB89997
Remote Control
series feature built-in Watchdog Timer series available Package many SH-DIP MB89Pxxx signifies device Under development
F2MC-16L High Performance/Low Power/Low Voltage Microcontrollers
Series MB90xxx 610A 620A Part MB90611A MB90613A MB90622A MB90623A MB90P623A MB90632A MB90634A MB90P634A MB90641A MB90P641A MB90652A MB90653A MB90P653A MB90654A MB90F654A MB90662A MB90663A MB90P663A MB90671 MB90672 MB90673 MB90P673 MB90T673 MB90676 MB90677 MB90678 MB90P678 MB90T678 Under development ROM/ Byte 1024 3072 1664 2048 2048 1024 2048 3072 2048 2048 3072 5120 5120 8192 8192 1664 2048 2048 1664 2048 2048 2048 1644 2048 3072 3072 2048 Clock (kHz) (PLL ext. MHz) (PLL ext. MHz) kHz) (PLL ext. MHz) Ports ICU/OCU Timer/ Counter UART Serial Conv. External Interface Prog. Pulse Gen. Special Features Chip Select Outputs Controller Converter, Down Counter Chip Select Outputs Converter, Down Counter, I2C- Interface PowerSaving Modes SLEEP STOP, SLEEP STOP, SLEEP STOP SLEEP STOP, SLEEP STOP,. Count
630A
ch/4
640A 650A
(PLL ext. MHz) (PLL ext. MHz) kHz)
ch/4
660A
(PLL ext. MHz)
Inverter Motor, (Multi Function Timer)
SLEEP STOP, SLEEP STOP,
(PLL ext. MHz)
ch/8 bit)
(PLL ext. MHz)
ch/8 bit)
I2C-Interface
SLEEP STOP,
Master Product Selector Guide
F2MC-16LX High Performance/Low Power Microcontrollers
Series MB90xxx Part MB90427A MB90428A MB90F428A MB90473, MB90474, MB90F474 MB90F476 MB90497 MB90F497 MB90522A MB90F523A MB90523A MB90543 MB90F543 MB90549 MB90F549 MB90552A MB90553A MB90F553A MB90561 MB90562 MB90F562 MB90567 MB90568 MB90F568 MB90573 MB90574A MB90F574A ROM/ Flash Byte 4096 6144 6144 10240 16384 16384 4096 2048 3072 4096 4096 6144 6144 4096 4096 2048 4096 4096 1024 2048 2048 3072 4096 4096 5120 10240 10240 Clock (kHz) (PLL ext. MHz) kHz) (PLL ext. kHz) (PLL ext. kHz) (PLL ext. kHz) (PLL ext. MHz) kHz) (PLL ext. MHz) kHz) (PLL ext. Mhz) kHz) (PLL ext. MHz) Ports ICU/OCU Timer/ Counter UART Serial Conv. External Interface Prog. Pulse Gen. Special Features WDT, sound generator, SMC, controller WDT, I2C, PWC, controller, WDT, I2C, controller, CAN, WDT, Controller Converter, Down Counter 2.0B Interface 2.0B Interface PowerSaving Modes SLEEP STOP, Supply Volts Count
SLEEP STOP, SLEEP STOP, SLEEP STOP, SLEEP STOP,
3.6,
ch/8
ch/2 ch/4 ch/2 ch/4 ch/4
SLEEP STOP, SLEEP STOP, SLEEP STOP,
550A
I2C-Interface, Clock Monitor Output
(PLL ext. MHz)
ch/4
motor control Wave Generator
SLEEP STOP,
(PLL ext. MHz) (PLL ext. MHz) kHz)
ch/4
SLEEP STOP, SLEEP STOP,
ch/4
Converter Down Counter C-Interface Chip Select Outputs Converter, PWC, Clock Monitor Output, Controller 2.0B Interface Stepper Motor Driver, Sound Generator WDT, 2.0B Interface Stepper Motor Driver
MB90583 MB90F583B MB90587 MB90594 MB90F594A MB90F591 MB90591
6144 6144 4096 6144 6144 8192 8192
ext. MHz) kHz) (PLL ext. MHz)
ch/2
SLEEP STOP,
ch/6
SLEEP STOP,
MB90598 MB90F598
4096 4096
(PLL ext. MHz)
ch/4ch
SLEEP STOP,
Under development
Microcontrollers
F2MC-16F High Speed/High Performance Microcontrollers
Series MB90xxx ROM/ Flash ext. Byte 3072 4096 3072 4608 4608 2048 3072 3072 1024 1024 1152 2048 1536 4096 Clock Timer/ Counter External Interface Prog. Pulse Gen. PowerSaving Modes SLEEP STOP, SLEEP STOP, SLEEP STOP, SLEEP STOP, Count
Part MB90214 MB90P214B MB90223 MB90224 MB90P224A/B MB90233 MB90234 MB90P234 MB90F243 MB90F243H MB90F244 MB90242A MB90F245 MB90246A
Ports
ICU/OCU ch/8
UART
Serial
Conv.
Special Features Write inhibit RAM, Gear Function Write Inhibit RAM, Gear Function Converter, S-EEPROM Interface, Level Comparator, Product Unit
ch/6
246A
Product Unit, Converter,
SLEEP STOP,
MB90Pxxx signifies device MB90Fxxx signifies Flash device
Master Product Selector Guide
Series
32-bit Flexible Microcontrollers
which stands Fujitsu RISC, latest generation Fujitsu general-purpose application-specific microcomputers. provides efficient development system that supports flexible range needs. Fujitsu also provides software support packages backup endusers, such powerful emulator that supports debugging realtime processing application software development, macro assembler compiler that support large-scale software development.
Features
RISC core with 5-stage pipeline harvard architecture Operating 16-bit fixes length commands double word transfers that increase performance Instruction cache buffer frequently used instructions, increased performance Internal Internal nonvolatile memory (Flash ROM) DRAM controllers Standard peripherals (UART, timers, counters, PWM, A/D) Power down modes Number instructions:
External Interface PowerSaving Modes
Series MB91xxx 101A
Part MB91101A
ROM/ Flash
Byte 2048
Clock
Ports
ICU/OCU
Timer/ Counter
UART
Serial
Conv.
Prog. Pulse Gen.
Special Features Instruction cache, DRAM controller controller, PWM, search module DRAM controller controller, PWM, search module DRAM controller controller, PWM, search module instruction RAM, internal instruction cache, DRAM controller controller, search module instruction RAM,
Count
MB91106
2048
MB91F109
4096
MB91110
(but instruction RAM)
5120
MB91F133
6144
MB90Pxxx signifies device
Ethernet
1983, introduced first commercially available Ethernet controller Manchester encoder/decoder chip-set. Today, with close decades experience, continues bring customers easy-to-use products variety networking applications. FMI's current portfolio includes, amongst others, 10/100 MAC, Mbps full duplex MAC, BaseT high-speed xDSL Ethernet Bridge controller. products targeted applications like, xDSL modems, set-top-boxes, home networks, routers switches. Each device supported development that allows designer write sample test codes device before prototyping design. Fujitsu MB86961A full duplex 10Mbps Ethernet Transceiver (PHY) that provides direct interface 10Base-T outputs. ideal twisted-pair Ethernet applications provides universal ability interface with most popular controllers. Functions like pulse shaping filtering eliminates need external filtering components, thus reducing overall system cost. MB86961A provides outputs receive, transmit, collision link-test LEDs, compatible with both shielded unshielded twisted-pair cables. MB86961A offers unique feature reducing power consumption automatically shutting down unused ports. available both 44-pin PLCC 48-pin PQFP packages. Typical applications include set-top-box, xDSL home gateways. Fujitsu MB86967 cost, single-chip Mbps Ethernet controller that includes JEIDA4.2 standard Card interface, interface generic interface. buffer manager functions arbitration management external memory these substantially reduce software overhead. These functions provide simultaneous access from host data link controller concurrent updating transmit receive buffer pointers. System interface configuration includes memory mapping, access combination these. MB86967 supports both burst well single transfer operations. With Mbps bandwidth, interface allows full architecture's throughput capability. MB86967 contains 64-bit hash table multicast address filter capable removing receiving long packets. device comes 100-pin LQFP package. MB86967 ideal 10Mbps full-duplex Ethernet solutions. Typical applications include printers, plotters, POS, internet applications, ovens, dishwashers, microwaves like.
Master Product Selector Guide
Fujitsu MB86976 xDSL Ethernet Bridge Controller CMOS VLSI device designed LAN-WAN bridging applications. MB86976 offers high level integration provide flexibility seamless integration 10Mbps Ethernet over xDSL Small Office Home Office (SOHO) access. controller accepts packets directly through on-chip 10Mbps Ethernet Media Access Controller (MAC) accepts serial stream (PPP, PPP-LEX HDLC) with maximum rate Mbps. also provides LAN-to-WAN WAN-to-LAN translation between packets serial stream. MB86976 includes hardware-based, advanced address filter with programmable features that accept reject packets, thus enhancing complex bridging, routing firewall capabilities. highly integrated MB86976 device also supports system designs with standard interfaces. processor interface supports 8-bit 16-bit, multiplexed non-multiplexed microcontrollers from Intel, Philips Siemens. MB86976 also interfaces standard 70ns fast page mode 256KX16 DRAMs (such Fujitsu's MB814260-70), standard Mbps Ethernet Transceiver (such Fujitsu's MB86961A) standard Discrete Multitone (DMT) Carrierless Amplitude Phase (CAP) xDSL modem
Ethernet Products
chipsets. device comes 144-pin PQFP package. ideal building xDSL ready Ethernet remote routers modern equipment. Fujitsu MB86974 PAUSE Flow control Ethernet controller that operates either 100Mbps 10Mbps. half-duplex mode, controller implements IEEE 802.3 Carrier Sense Multiple Access with Collision Detect (CSMA/CD) protocol. full duplex mode, controller implements IEEE 802.3 control layer. controller offers direct interface with burst mode, burst size control support little endian modes. device features large arbitration FIFO buffers, on-chip EEPROM support. Because on-chip memory buffering capability, controller does require external local buffer memory. MB86974 comes 144-pin LQFP package. Typical applications include set-top-box, xDSL, cable modem home gateways. Information FMI's current products included this section. additional products development, including several that intended Fast Ethernet remote access applications.
Functions Part Number MB86967 MB86961A MB86964 MB86960 MB86965B MB86974 MB86976 Device Description Controller with generic PC-card interface Twisted Pair Transceiver Controller with generic interface Controller with generic interface Controller with generic interface Controller LAN-WAN Bridge Controller Encoder/Decoder 10-BASE-T Transceiver On-Chip Filters Package 100-pin LQFP 44-pin PLCC, 48-pin PQFP 100-pin SQFP 100-pin PQFP 160-pin PQFP LQFP 144-pin PQFP
Ethernet®
Evaluation Kits
Evaluation DK86964 DK86965B DK86967 DK86967 DK86967 DK86974 DK86976 Product MB86964 MB86965B MB86967 MB86960 MB86961A MB86974 MB86976 Includes OrCAD schematics, PADS database, Gerber files, User guide, drivers Novell, Windows 95/98 DOS, data sheet application notes. OrCAD schematics, database, Gerber files, drivers Novell Windows 95/98, data sheet, application notes user guide. OrCAD schematics, database, Gerber files, drivers Novell Windows 95/98, data sheet, application notes user guide. OrCAD schematics, PADS database, Gerber files, User guide/ programmer's manual, drivers Novell, Windows 95/98 DOS, data sheet application notes. OrCAD schematics, PADS database, Gerber files, User guide/ programmer's manual, drivers Novell, Windows 95/98 DOS, data sheet application notes. OrCAD schematics, PADS database, Gerber files, User guide/programmer's manual, drivers Novell, Windows 95/98 OS/2, data sheet application notes. OrCAD schematics, PADS database, Gerber files, User guide/ programmer's manual, Host code including license agreement source code, data sheet application notes.
Master Product Selector Guide
AFujitsu early innovator field Aand primary member AForum, group established investigate Awithin private networks. Fujitsu MB86680 self-routing switch element (SRE) Aswitch fabrics. ideally suited applications variety customer-premises equipment, such Ahubs network access controllers. device organized switch with separate input output ports matrix expansion. Fujitsu MB86681 self-routing switch element similar MB86680 described above with additional features. Fujitsu MB86687A Aprotocol controller which autonomously terminates AAdaptation Layer Standards Type Type device ideally suited applications variety customer-premises equipment, such Aworkstation adapter cards Ahubs. device supports simultaneous segmentation reassemble 1024 virtual circuits (VCs). MB86687A supports peak segmentation rates with leaky bucket averaging basis, with optional bucket fill before segmentation continues. Fujitsu MB86688A FireBurst25 A25.6 Mbps Multi-PHY device highly integrated, multiple-port interface between magnetics AAdaptation Layer Asystem. Implementing ports single device significantly reduces cost port. Each ports provides framing transceiver functions according AForum 25.6 Mbps Physical Layer Specification. device 16bit UTOPIA Level 2-compliant Acell interface that operate MHz. 25.6 Mbps cell streams concentrated onto single Multi-PHY UTOPIA interface under control ALayer device. Mixed-signal technology used implement Physical Layer circuitry each port. Physical Media Dependent (PMD) functions, including line drivers, equalization, clock recovery included each transceiver block. Transmission Convergence (TC) functions performed each 25.6 Mbps framer block. FireBurst25 designed UTOPIA Level 2-based system, including Mbps switches stand-alone concentrators.
Master Product Selector Guide
Fujitsu MB86689 Address Translation Controller provides autonomous high-speed translation function Acell header information real time Mbps. translation supports replacement Avirtual path (VPI) virtual channel (VCI) identifiers also allows 24-bit routing appended. device designed interface directly with MB86683 Network Termination Controller (NTC) described above, which will located Aswitch input/output ports. MB86689 also incorporates 8-bit parallel cell stream interface which facilitates autonomous in-line address translation. MB582/3 transceivers designed 155.52 Mbps serial data transmission ATM, SDH, SONET applications. MB582 transmitter provides parallel-to-serial conversion 8-bit parallel input signal, while MB583 receiver converts received serial signal 8-bit parallel output signal also performs clock recovery function. FireStreamTM155 (MB86697) high performance Aprotocol controller which autonomously terminates AAdaptation Layer standard Type (AAL5). Acells received through UTOPIA v2.01 compliant interface. Simultaneous segAProducts
Part Number MB86680 MB86681 MB86687A MB86689 MB582/3 MB86688 MB86697 MB86698 Device Description Self-routing Aswitch element (SRE) Enhanced Aswitch element (SRE-L) 32-bit ASAR with generic (ALC) Aaddress translation controller (ATC) SONET transmitter/receiver pair (Txcrv) FireBurst25 Multi-Phy Aframer (FB25) FireStream155 with (FS155)
mentation reassembly achieved average rate excess 155Mbps. FireStreamTM155G (MB86698) high performance Aprotocol controller which autonomously terminates AAdaptation Layer standard Type (AAL5). Acells passed UTOPIA v2.01 compliant interface. Access system memory through 50MHz generic interface achieve simultaneous segmentation reassembly average rate excess 155Mbps. AForum traffic classes (ABR, VBR, CBR, UBR) supported with traffic management AForum TM4.0 specification 65536 virtual circuits (VCs). FireStream devices ideally suited many Aapplications including Aswitches, access units, adapter cards multiprotocol hubs, bridges routers. devices have operating voltage volts, fabricated Fujitsu's high-speed bipolar technology, have wide temperature operating range +85°C. Both packaged 48pin plastic quad flat packages.
Speed Mbps Mbps Mbps Mbps Mbps 25.6 Mbps Mbps Mbps
Package 176-pin SQFP 208-pin SQFP 208-pin SQFP 80-pin 48-pin SQFP 208-pin HQFP 240-pin HQFP 240-pin HQFP
FireStream155G with generic processor (FS155G)
ADSL
Fujitsu Microelectronics, Inc. (FMI) offers industry's most highly integrated ATMbased Asymmetric Digital Subscriber Line (ADSL) modem. fully featured Discrete Multi Tone (DMT) modem capable echo-cancelled operation over POTS ISDN. product integrates dedicated power-optimizing digital processing hardware with very low-noise, high-resolution analog front (AFE). integrated offers lowest noise receive paths available ADSL that, together with world-class 15-bit A-to-D D-to-A converters, provides superior performance over varied loop conditions. Aexpertise from Fujitsu completes collaborative design with UTOPIA cell interface allowing simple interoperation with Fujitsu's family Adevices. Additionally, serial data interfaces provide seamless connection Fujitsu's MB86976 Ethernet bridge controller packet-mode applications. MB86670 (KeyWave device) uses Kbytes external interleave RAM. hostprocessor running software supplied Fujitsu, configures controls modem's operation. This software configurability allows KeyWave offer ANSI T1.413 Category G.dmt G.lite modes operation both central office (CO) remote-terminal (ATU-R) applications. external line driver, transformer passive hybrid components complete analog line interface. high integration modem ability single host control multiple modems allow high packing densities achieved well ATU-R side. modem's single 3.3-volt supply simplifies ATU-R designs. MB86670 KeyWave been designed 0.35-micron CMOS technology using Fujitsu's triple-well process provide necessary analog/digital isolation required low-noise performance.
Master Product Selector Guide
Fujitsu MB86626 (KeyWaveAFE device) complete analog front ADSL modems. device integrates high resolution analog digital converters (ADC) digital analog converters (DAC), combined with active filtering significantly reduces requirements placed external components. architecture
ADSL Products
Part MB86670 MB86626 Device Name KeyWave KeyWave Description
supports both analog digital echo cancellation (EC). MB86626 KeyWaveAFE ideal cost sensitive Customer Premise Equipment (CPE) power sensitive Central Office (CO) equipment.
Typical Applications DSLAM equipment. DSLAM equipment.
Package 240-pin HQFP 80-pin LQFP
Single-chip ADSL device Remote Terminal (RT) Central Office (CO) applications 15-bit Analog Front (ADC
Development Kits
Part DK86670-C DK86670-R DK86626-2 KeyWave application) KeyWave (CPE applications) KeyWave Includes ADSL modem board, supporting software, user guide, schematics, data sheet applications notes. ADSL modem board, supporting software, user guide, schematics, data sheet applications notes. AFE, transmit Amplifier, Hybrid interface, supporting software, user guide, schematics, data sheet application notes. Available
Application Specific Controllers
Since 1985, empowered customers general-purpose, high-performance SCSI market with superior performance applications including large disk array controllers, workstations, high-end PCs, more. Fujitsu's ongoing commitment this industry continues produce exciting breakthroughs enhanced integration, well reduced size, cost power consumption. Fujitsu's rapid adoption IEEE 1394 standard, example, already showing returns upcoming 400-megabit serial controller gigabit solutions development.
Master Product Selector Guide
IEEE 1394 Controller
Fujitsu's 1394 integrated circuit design philosophy based principle that 1394 will universal interface broad variety applications that will cross over traditional boundary between computer consumer markets. this vision become reality, cost implementing 1394 must driven down level comparable application-specific interfaces that 1394 designed replace. same time 1394 must maintain interoperability compliance with standards that still evolving today. root cost model silicon controller software that links level world 1394 logic with systems that expected seamlessly create high speed personal network. Fujitsu Microelectronics understands these challenges from bottom developing silicon meet disparate needs increasingly diverse 1394 application base. approach been target specific application segments identify unique requirements integrate highest level functionality without restricting user from implementing unique features. trade-off between over integration under integration always challenge. Over integration results excessive costs, reduced flexibility, increased power consumption above. little integration application cost impacted through higher chip count, increased board space, most importantly, forcing more control processing function into software stack where execution less than optimal. Fujitsu's first 1394 implementations, MB86611 MB86612 were developed primarily Japanese consumer products marketplace were designed 1394 1995 specification S100 data rates. cornerstone Fujitsu's 1394 design methodology been integration complete PHY, including transceivers, PLL, node arbitration logic, with upper level LINK functions into single 3.3-volt integrated circuit. addition LINK logic, these devices were equipped with additional hardware designed perform higher level functions (above LINK layer) such time stamp processing frame pulse regeneration both (MPEG) protocols. This actually application layer function that normally would executed more slowly software.
Description
Fujitsu developing products designed European markets that have been designed 1394a, OHCI specifications. Supporting S400 data rates, these products target both host motherboards add-in cards) peripheral applications including, printers, scanners, video conference cameras, boxes storage subsystems. MB86613 complete OHCI chip that features support independent contact programs including support isochronous channels. large byte FIFO designed buffer speed variations reduce risk FIFO overrun condition. MB86613 includes many latest OHCI 1394a features including Fairness Control, Physical Upper Bound registers, Fly-By Arbitration, Suspend/Resume, Ping Packet Second Cycle Limit. MB886613 supports line power with remote power with Link capability through three 1394 ports. Fujitsu recently introduced low-cost version MB86613, MB86613L. single-port version housed 100pin package. (The non-"L" version uses 144-pin package.) Other than reduced port count, version identical MB86613. MB86614 S400 device that supports 1394a features listed above, supplied simple two-port device. MB86614 also sheds PCI/OHCI interface generic 16-bit interface features hardware support SBP-2 chain readand-write commands, which significantly reduces control overhead. device intended applications such printers, scanners cameras. MB86614 comes configurations: common DMA/CPU interface separate DMA/CPU interface channels.
Application Specific Controllers
Part Number MB86611 MB86612 MB86613 MB86613L MB86614 MB86615 MB86616 MB86617 MB86618 MB866YY
Device Description application (DVC Support) MPEG support applications PCI/OHCI Host Controller cost OHCI application SBP-2 support 1394 peripherals cost application SCSI 1394 Tailgate copy protection version MB86616 Mbit (only)
Ports
Speed (Mbps)
Availability Immediate Immediate Immediate Immediate Immediate Immediate
high level development effort required these produces, minimum volume requirement will apply. Contact sales office specifics.
Master Product Selector Guide
SCSI Controllers
Fujitsu's current product offering includes parallel implementations with Fast-10, Fast-20, wide options (see table). block diagram MB86600 Series architecture shown below. Fujitsu taken core architecture approach with MB86600 Series family, making easier migrate designs within product line. On-chip features have been carefully chosen provide maximum benefit greatest number designers. internal processor executes SCSI operations user-definable strings, thus increasing design flexibility reducing system overhead. User program memory stores custom SCSI operations on-chip, further reducing need access external system components. Additional features serve further enhance performance simplify design-in: Support Fast-10, Fast-20, wide (ultra SCSI) options Support command queuing Single-ended drivers (support external differential drivers) Programmable interrupt system Separate send receive buffers commands, status, messages Terabyte transfer counter Auto selection/reselection mode Diagnostic mode
Interface MB86604 16-bit General Purpose Interface MB86606 32-Bit Interface (including Controller) Interface Controller
Main Register
User Memory MB86604: 256-Byte MB86606: 2K-Byte
Timer
32-Byte Receive Buffer (MSG, CMD, Status)
Data FIFO MB86604: 32-Byte MB86606: 512-Byte
32-Byte Send Buffer (MSG, CMD, Status)
Internal Processor
Phase CNTL
Transfer CNTL
SCSI Interface
MB86600 Series Core Block Diagram
Part Number MB86604 MB86606
SCSI Width 8-bit 16-bit
User 256-Byte 2K-Byte
Data FIFO 32-Byte 512-Byte
Package (Pin/Type) 100/QFP 144/SQFP
Features Fast, SCSI general purpose interface Fast-20 SCSI
Wireless
Fujitsu leading worldwide supplier filters. Approximately half cellular phones currently worldwide utilize Fujitsu's technology. most recent filters meet stringent size weight requirements personal communications systems. Fujitsu offers industry's largest selections single dual Super PLLs wide range Prescaler devices. series Super PLLs, based Fujitsu's fourthgeneration technology, exhibits power consumption excellent noise characteristics demanded digital cellular products. FMI's customers have advantage advanced packaging technologies, area which Fujitsu acknowledged world leader. example, Fujitsu's frequency synthesizers produced using surface-mount packaging technology. low-cost space-efficient packages dramatically reduce size mounting area, providing size weight advantages without sacrificing flexibility.
Master Product Selector Guide
Filters
Fujitsu's extensive range filters portable, mobile, fixed communications most advanced world. These filters fabricated using Fujitsu's proprietary quartz lithium tantalate (LiTaO3). This technology allows manufacture filters with wide bandwidth, insertion loss, high stop-band attenuation. product range constantly expanding meet challenges both analog digital communications systems. example, advanced packaging technology development low-loss antenna filters high-performance duplexer filters. 881/836 duplexer leading-edge product 1900 filters make possible design smaller lighter subscriber equipment. applying multichip technology, Fujitsu offers range dual filters RF/Mixer applications.
Wireless
F5CM (B2) Series (Balanced Filters)
F5CM series filters designed interstage applications featuring balanced/unbalanced ports.
Bandwidth (MHz)
85°C Small inband ripple
Description Input Output
Part Number F5CM-902M50-B263 F5CM-902M50-B264 F5CM-902M50-B265 F5CM-947M50-B260 F5CM-947M50-B261 F5CM-947M50-B262 F5CM-836M50-B268 F5CM-881M50-B266 F5CM-897M50-B271 F5CM-942M50-B270
Application (Tx) (Tx) (Tx) (Rx) (Rx) (Rx) Amps/CDMA (Tx) Amps/CDMA (Rx) EGSM (Tx) EGSM (Rx)
Center Frequency (MHz) 902.5 902.5 902.5 947.5 947.5 947.5 836.5 881.5 897.5 942.5
Insertion Loss (dB)
balanced balanced balanced unbalanced unbalanced unbalanced balanced unbalanced balanced unbalanced
unbalanced unbalanced unbalanced balanced balanced balanced unbalanced balanced unbalanced balanced
F5CM
Master Product Selector Guide
F5CE (D2) Series (Dual Mode Filters)
F5CE (D2) filters have high stop-band attenuation excellent pass-band flatness. 85°C 50-ohm impedance
Part Number F5CE-950M00-D230 F5CE-895M50-D243S F5CE-820M00-D231 F5CE-836M50-D232 F5CE-881M50-D233 F5CE-902M50-D234 F5CE-947M50-D235 F5CE-915M00-D238 F5CE-897M50-D241 F5CE-942M50-D240
Application (Tx) (Tx) (Rx) AMPS (Tx) AMPS (Rx) (Tx) (Rx) (Tx) EGSM (Tx) EGSM (Rx)
Center Frequency (MHz) 950.0 895.5 820.0 836.5 881.5 902.5 947.5 915.0 897.5 942.5
Bandwidth (MHz)
Insertion Loss (dB)
F5CE
Wireless
F5CH (L2) Series (Ladder Filters)
F5CH family LiTaO3 bandpass filters have been designed filter applications 1000 frequency range. 85°C 50-ohm impedance
Bandwidth (MHz) Insertion Loss (dB) High Atten High rejection High rejection High rejection High rejection High rejection High rejection High rejection High rejection High rejection High rejection
Part Number F5CH-836M50-L2AL F5CH-836M50-L2AW F5CH-881M50-L2AM F5CH-881M50-L2AV F5CH-888M50-L2CL F5CH-888M50-L2CW F5CH-933M50-L2CM F5CH-911M50-L2DL F5CH-856M50-L2DM F5CH-902M50-L2EL F5CH-902M50-L2EW F5CH-947M50-L2EM F5CH-947M50-L2EV F5CH-897M50-L2KL F5CH-942M50-L2KM F5CH-942M50-L2KV F5CH-950M00-L2FW F5CH-820M00-L2FM F5CH-820M00-L2FV F5CH-940M50-L2MD F5CH-915M00-L2JW F5CH-906M00-L2PA F5CH-906M00-L2PZ F5CH-851M00-L2PB F5CH-935M00-L2LD
Application AMPS/CDMA (Tx) AMPS/CDMA (Tx) AMPS/CDMA (Rx) AMPS/CDMA (Rx) ETACS (Tx) ETACS (Tx) ETACS (Rx) NTACS (Tx) NTACS (Rx) (Tx) (Tx) (Rx) (Rx) EGSM (Tx) EGSM (Rx) EGSM (Rx) PDC800 (Tx) PDC800 (Rx) PDC800 (Rx) Dual-PDC800 (Tx) ISM900 J-CDMA (Tx) J-CDMA (Tx) J-CDMA (Rx) PAGER
Center Frequency (MHz) 836.5 836.5 881.5 881.5 888.5 888.5 933.5 911.5 856.5 902.5 902.5 947.5 947.5 897.5 942.5 942.5 950.0 820.0 820.0 940.5 915.0 906.0 906.0 851.0 935.0
Comments
F5CH
Master Product Selector Guide
F5CE/F6CE (K2) Series (Ladder Filters)
F5/F6CE (K2) series LiTaO3 ladder filters used interstage filter applications 1700 range. 85°C 50-ohm impedance
Bandwidth (MHz) High Atten loss High rejection loss High rejection Insertion Loss (dB) High rejection
Part Number F5CE-836M50-K205 F5CE-836M50-K225 F5CE-836M50-K230 F5CE-881M50-K206 F5CE-881M50-K287 F5CE-881M50-K210 F5CE-897M50-K226 F5CE-897M50-K231 F5CE-942M50-K216 F5C3-942M50-K288 F5CE-950M00-K201 F5CE-941M50-K208 F5CE-942M50-K209 F5CE-820M00-K202 F5CE-820M00-K204 F5CE-906M00-K211 F5CE-906M00-K215 F5CE-851M00-K212 F5CE-902M50-K213 F5CE-947M50-K214 F5CE-947M50-K228 F6CE-1G4410-K220 F6CE-1G4890-K221 F6CE-1G6190-K222
Application AMPS (Tx) AMPS (Tx) AMPS (Tx) AMPS (Rx) AMPS (Rx) AMPS (Rx) EGSM (Tx) EGSM (Tx) EGSM (Rx) EGSM (Rx) PDC800 (Tx) PDC800 (Tx) PDC800 (Tx) PDC800 (Rx) PDC800 (Rx) JCDMA (Tx) JCDMA (Tx) JCDMA (Rx) (Tx) (Rx) (Rx) 1.5G (Tx) 1.5G (Rx) 1.5G (Lo)
Center Frequency (MHz) 836.5 836.5 836.5 881.5 881.5 881.5 897.5 897.50 942.5 942.5 950.0 941.5 942.5 820.0 820.0 906.0 906.0 851.0 902.5 947.5 947.5 1441.0 1489.0 1619.0
Comments High rejection loss High Atten loss
F5CE/F6CE
Wireless
F5CP/F6CP (D2) Series (Dual Mode Filters)
F5/F6CE (D2) series LiTaO3 filters used interstage filter applications 1700 range. 85°C 50-ohm impedance 2.5x2.0x
Center Frequency (MHz) 942.5 950.0 820.O 836.5 881.5 902.5 947.5 1441.0 1489.0 Bandwidth (MHz)
Part Number F5CP-942M50-D201 F5CP-950M00-D209 F5CP-820M00-D202 F5CP-836M50-D203 F5CP-881M50-D204 F5CP-902M50-D205 F5CP-947M50-D206 F6CP-1G4410-D207 F6CP-1G4890-D208
Application EGSM (Rx) PDC800 (Tx) PDC800 (Rx) AMPS (Tx) AMPS (Rx) (Tx) (Rx) PDC1.5G (Tx) PDC1.5G (Rx)
0.10 0.10
0.88 0.10
0.10
0.63 0.10 min.
030) INDEX
R0.18 min.
F5CP/F6CP
Master Product Selector Guide
F6CE (L2) Series (Ladder Filters)
F6CE series LiTaO3 ladder bandpass filters have been designed applications 1000 2500 range offer superior stability over wide range operating temperatures. 85°C insertion loss 50-ohm impedance
Bandwidth (MHz) 83.5 22.80 83.5 Insertion Loss (dB) High rejection High rejection High rejection High rejection High rejection High rejection High rejection High rejection High rejection High rejection High rejection
Part Number F6CE-1G5754-L2UA F6CE-1G7475-L2YA F6CE-1G8425-L2YE F6CE-1G8425-L2YB F6CE-1G8800-L2XA F6CE-1G8800-L2XZ F6CE-1G8800-L2XJ F6CE-1G8650-L2XDX F6CE-1G8950-L2XEX F6CE-1G9600-L2XB F6CE-1G9600-L2XK F6CE-1G9600-L2XY F6CE-1G9450-L2XF F6CE-1G9750-L2XG F6CE-1G7300-L2TC F6CE-1G7475-L2YAC F6CE-1G7650-L2TA F6CE-1G8200-L2TD F6CE-1G8425-L2YBC F6CE-1G8550-L2TB F6CE-2G4485-L2RA F6CE-2G4418-L2RB F6CE-1G9065-L2UD F6CE-2G4500-L2WA F6CE-2G4840-L2WC F6CE-2G4418-L2WD F6CE-1G9500-L2ZP F6CE-2G1400-L2ZQ
Application (Tx) (Rx) (Rx) US-PCS (Tx) US-PCS (Tx) US-PCS (Tx) US-PCS (Tx) US-PCS (Tx) US-PCS (Rx) US-PCS (Rx) US-PCS (Rx) US-PCS (Rx) US-PCS (Rx) Korea-PCS (Tx) Korea-PCS (Tx) Korea-PCS (Tx) Korea-PCS (Rx) Korea-PCS (Rx) Korea-PCS (Rx) Bluetooth Bluetooth Wireless Wireless Wireless W-CDMA (Tx) W-CDMA (Rx)
Center Frequency (MHz) 1575.42 1747.5 1842.5 1842.5 1880.0 1880.0 1880.0 1865.0 1895.0 1960.0 1960.0 1960.0 1945.0 1975.0 1730.0 1747.5 1765.0 1820.0 1842.5 1855.0 2448.5 2441.75 1906.55 2450.0 2484.0 2441.75 1950.0 2140.0
Comments
F6CH
F6CE
Wireless
D5CC (D1) Series (Antenna Duplexer)
D5CC series LiTaO3 ladder antenna duplexers frequency range 1000 MHz. D5CC series transmitter filter, receiver filter, matching circuit, housed small package. High power, 1.2W maximum 50-ohm impedance
Part Number D5CC-881M50-D1C5 D5CC-881M50-D1C6 D5CC-881M50-D1C7 D5CC-881M50-D1C8
Application AMPS (Tx) AMPS (Rx) AMPS (Tx) AMPS (Rx) AMPS (Tx) AMPS (Rx) AMPS (Tx) AMPS (Rx)
Center Frequency (MHz) 836.5 881.5 836.5 881.5 836.5 881.5 836.5 881.5
Bandwidth (MHz)
D5CC
Master Product Selector Guide
G5CH/G5CN/G6CH/G6CS (L2/D2) Series (Dual Filters)
This series dual filters make possible shrink size portable wireless communications equipment offering dual filters with internal matching single package. 50-ohm impedance insertion loss
Bandwidth (MHz) Insertion Loss (dB) in/2 in/2 in/2 in/2 in/2 in/2 in/2 in/2 in/2 in/2 in/2 in/2 in/2 High rejection in/2 Internal Connection in/2
Part Number G5CN-942M50-D291 G5CH-942M50-D294 G5CN-877M50-D292 G5CH-865M00-L212 G6CH-1G8800-L214 G6CH-1G9600-L215 G6CH-1G7475-L216 G6CH-1G8425-L217 G6CH-1G8425-L224 G6CH-1G8425-L218 G6CH-1G8950-L210D G6CN-1G8950-L231 G6CH-1G9750-L230 G6CH-1G9600-L219 G6CH-1G9600-L226
Application PDC800 (Tx) PDC800 (Tx) PDC800 (Rx) J-CDMA (Rx) AMPS (Tx) AMPS (Rx) (Tx) (Rx) EGSM (Rx) EGSM (Rx) Half Band Half Band Half Band PCN+PCS EGSM+PCS
Filter
Center Frequency (MHz) 893.5 942.5 895.5 942.5 826.5 877.5 839.0 865.0 836.5 1880.0 881.5 1960.0 902.5 1747.5 947.5 1842.5 942.5 1842.5 942.5 1842.5 1865.0 1895.0 1865.0 1895.0 1945.0 1975.0 1842.5 1960.0 942.5 1960.0
Comment
Wireless
in/2 type
G5CN
G5CH
in/2 type
Master Product Selector Guide
PLLs
With introduction MB1501 Super PLL, high frequency with integral prescaler, Fujitsu established first industry standard. Today, company offers industry's largest selections frequency synthesizers anywhere world. continuing technical leadership position through constant development Super PLLs. These being designed into hundreds applications used around world, including CATV, set-top boxes, pagers, digital cellular radios, cordless telephone systems. example, submi-cron CMOS MB15C03 developed pager market consumes only microwatts power while achieving high level performance. Using Fujitsu's advanced BiCMOS process, MB15E03SL Super consumes only milliwatts power while meeting stringent requirements digital com-munications, including GSM, PCS, PHS, DECT, PDC. Fujitsu prepar
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