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bq4016 - bq4016
bq4016Y - bq4016Y
1024Kx8 Nonvolatile SRAM
Data retention absence power Automatic write-protection during power-up/power-down cycles Conventional SRAM operation; unlimited write cycles 10-year minimum data retention absence power Battery internally isolated until power applied
CMOS bq4016 nonvolatile 8,388,608-bit static organized 1,048,576 words bits. integral control circuitry lithium energy source provide reliable nonvolatility coupled with unlimited write cycles standard SRAM. control circuitry constantly monitors single supply out-of-tolerance condition. When falls tolerance, SRAM unconditionally write-protected prevent inadver tent rite operation.
this time integral energy source switched sustain memory until after returns valid. bq4016 uses extremely standby current CMOS SRAMs, coupled with small lithium coin cell provide nonvolatility without long write-cycle times writecycle limitations associated with EEPROM. bq4016 same interface industry-standard SRAMs requires external circuitry.
A0-A19 DQ0-DQ7 Address inputs Data input/output Chip enable input Output enable input Write enable input volt supply input Ground connect
Part Number bq4016MC
Maximum Access Time (ns)
Negative Supply Tolerance
Part Number bq4016YMC
Maximum Access Time (ns)
Negative Supply Tolerance -10%
bq4016/bq4016Y Functional Description
When power valid, bq4016 operates standard CMOS SRAM. During power-down power-up cycles, bq4016 acts nonvolatile memory, automatically protecting preserving memory contents. Power-down/power-up control circuitry constantly monitors supply power-fail-detect threshold VPFD. bq4016 monitors VPFD 4.62V typical systems with supply tolerance. bq4016Y monitors VPFD 4.37V typical systems with supply tolerance. When falls below VPFD threshold, SRAM automatically write-protects data. outputs become high impedance, inputs treated "don't care." valid access process time power-fail detection, memory cycle continues completion. memory cycle fails terminate within time tWPT, write-protection takes place. falls past VPFD approaches control circuitry switches internal lithium backup supply, which provides data retention until valid applied. When returns level above internal backup cell voltage, supply switched back VCC. After ramps above VPFD threshold, write-protection continues time tCER (120ms maximum) allow processor stabilization. Normal memory operation resume after this time. internal coin cells used bq4016 have extremely long shelf life. bq4016 provides data retention more than years absence system power. shipped from Benchmarq, integral lithium cells electrically isolated from memory. (Self-discharge this condition approximately 0.5% year.) Following first application VCC, this isolation broken, lithium backup provides data retention subsequent power-downs.
Mode selected Output disable Read Write Operation High High DOUT Power Standby Active Active Active
Absolute Maximum Ratings
Symbol TOPR TSTG TBIAS TSOLDER Note: Parameter voltage applied relative voltage applied excluding relative Operating temperature Storage temperature Temperature under bias Soldering temperature Value -0.3 -0.3 +260 Unit seconds Conditions
Permanent device damage occur Absolute Maximum Ratings exceeded. Functional operation should limited Recommended Operating Conditions detailed this data sheet. Exposure conditions beyond operational limits extended periods time affect device reliability.
Recommended Operating Conditions 70°C)
Symbol Note: Parameter Supply voltage Supply voltage Input voltage Input high voltage Minimum 4.75 -0.3 Typical Maximum Unit Notes bq4016Y bq4016
Typical values indicate operation 25°C.
Electrical Characteristics 70°C, VCCmin
Symbol Parameter Input leakage current Minimum Typical
VCCmax) Maximum Unit Conditions/Notes -1.0 0.2V, 0.2V, Min. cycle, duty 100%, ,II/O 0mA, VIH, bq4016 bq4016Y
Output leakage current Output high voltage Output voltage Standby supply current Standby supply current
Operating supply current
Power-fail-detect voltage Supply switch-over voltage
Typical values indicate operation 25°C,
Capacitance 25°C, 1MHz, 5.0V)
Symbol CI/O Note: Parameter Input/output capacitance Input capacitance Minimum Typical Maximum Unit Conditions Output voltage Input voltage
These parameters sampled 100% tested.
Parameter Input pulse levels Input rise fall times Input output timing reference levels Test Conditions 3.0V (unless otherwise specified)
Figure Output Load Read Cycle
Symbol tACE tCLZ tOLZ tCHZ tOHZ Read cycle time Address access time Chip enable access time Output enable output valid Chip enable output Output enable output Chip disable output high Output disable output high Output hold from address change 70°C, VCCmin VCCmax) Parameter Min.
Figure Output Load
Conditions Output load Output load Output load Output load Output load Output load Output load Output load
Read Cycle (Address Access)
Read Cycle Access) 1,3,4
Read Cycle Access)
held high read cycle. Device continuously selected: VIL. Address valid prior coincident with transition low. VIL. Device continuously selected: VIL.
70°C, VCCmin VCCmax) Symbol tWR1 tWR2 tDH1 tDH2 Notes: Parameter Write cycle time Chip enable write Address valid write Address setup time Write pulse width Write recovery time (write cycle Write recovery time (write cycle Data valid write Data hold time (write cycle Data hold time (write cycle Write enabled output high Output active from write Min. Max. Units Measured from address valid beginning write. Measured from beginning write write. Measured from going high write cycle. Measured from going high write cycle. Measured first low-to-high transition either Measured from going high write cycle. Measured from going high write cycle. pins output state. pins output state. Conditions/Notes
write ends earlier transition going high going high. write occurs during overlap write begins later transition going going low. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met. goes simultaneously with going after going low, outputs remain high-impedance state.
Write Cycle (WE-Controlled) 1,2,3
Write Cycle (CE-Controlled) 1,2,3,4,5
must high during address transition. Because active low) during this period, data input signals opposite polarity outputs must applied. high, pins remain state high impedance. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met.
Power-Down/Power-Up Cycle 70°C)
Symbol Parameter slew, 4.75 4.25 slew, 4.25 slew, VPFD (max.) Minimum Typical Maximum Unit Time during which SRAM write-protected after passes VFPD power-up. 25°C. Delay after slews down past VPFD before SRAM write-protected. Conditions
Chip enable recovery time
Data-retention time absence Write-protect time
Typical values indicate operation 25°C, Batteries disconnected from circuit until after applied first time. accumulated time absence power beginning when power first applied device.
Caution: Negative undershoots below absolute maximum rating -0.3V battery-backup mode affect data integrity.
Data Sheet Revision History
Change Notes: Page Description Changed from "Preliminary" "Final" data sheet
Change Sept 1996 changes from June 1995.
36-Pin C-Type Module
36-Pin (C-Type Module)
Dimension Minimum 0.365 0.015 0.017 0.008 2.070 0.710 0.590 0.090 Maximum 0.375 0.023 0.013 2.100 0.740 0.630 0.110 0.150 0.210
0.120 0.175 dimensions inches.
blank Commercial +70°C)
mark negative supply tolerance negative supply tolerance
bq4016 1024K NVSRAM
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Copyright 1999, Texas Instruments Incorporated
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