Z86E61 E63

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Z86E61 - Z86E61

WITH
Z86E61/E63 16K/32K EPROM
RELIMINAR
RODUCT PECIFICA
TION
Z86E61/E63
CMOS 16K/32K EPROM MICROCONTROLLER
FEATURES
8-Bit CMOS Microcontroller 40-Pin DIP, 44-Pin PLCC Style Packages 4.5V 5.5V Operating Range Clock Speeds:
High Voltage Protection High Voltage Inputs EPROM Protect EPROM: Kbytes Z86E61 Kbytes Z86E63 Bytes Register File Bytes General-Purpose Bytes Control Status Registers Bytes Ports Programmable 8-Bit Counter/Timers Each with 6-Bit Programmable Prescaler Vectored, Priority Interrupts from Eight Different Sources On-Chip Oscillator that Accepts Crystal, Ceramic Resonator, External Clock Drive
Power Consumption: (max) Fast Instruction Pointer: Standby Modes: STOP HALT Input/Output Lines
Full-Duplex UART Digital Inputs Levels Auto Latches
GENERAL DESCRIPTION
Z86E61/E63 microcontrollers members single-chip microcontroller family with 16K/32 Kbytes EPROM bytes general-purpose RAM. Offered 40-pin 44-pin PLCC package styles, these devices pin-compatible EPROM versions Z86C61/ ROMless option available 44-pin versions only. With Kbytes bytes general-purpose RAM, Z86E61/E63 offers fast execution, efficient memory, sophisticated interrupts, input/output manipulation capabilities, easy hardware/software system expansion. applications demanding powerful capabilities, Z86E61/E63 offers pins dedicated input output. These lines grouped into four ports. Each port consists eight lines, configurable under software control provide timing, status signals, serial parallel with without handshake, address/data interfacing external memory. Z86E61/E63 address both external memory preprogrammed ROM, making well suited highvolume applications where code flexibility required.
WITH 16K/32K
Z86E61/E63 EPROM
GENERAL DESCRIPTION (Continued)
There three basic address spaces available support this configuration: Program Memory, Data Memory, general-purpose registers. unburden system from coping with real-time tasks such counting/timing serial data communication, Z86E61/E63 offers on-chip counter/timers with large number user selectable modes (Figure
Notes: Signals with preceding front slash, "/", active Low, e.g., B//W (WORD active Low); /B/W (BYTE active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit Device
Output Input
XTAL R//W /RESET
Port
Machine Timing Instruction Control
UART
Counter/ Timers
FLAGS Prg. Memory 16K/32K Register Pointer Register File 8-Bit Program Counter
Interrupt Control
Port
Port
Port
(Bit Programmable)
Address/Data (Byte Programmable)
Address (Nibble Programmable)
Figure Z86E61/E63 Functional Block Diagram
WITH
Z86E61/E63 16K/32K EPROM
DESCRIPTION Standard Mode
Table 40-Pin Identification
XTAL2 XTAL1 /RESET R//W
Standard Mode Symbol 13-20 21-28 31-38 XTAL2 XTAL1 /RESET R//W P07-P00 P17-P10 P27-P20
Function Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port Port Reset Read/Write Data Strobe Address Strobe Port
Direction Input Output Input Output Input Input Output Output Output Output
Z86E61 /E63
Ground Input Port Input Port Pins 0,1,2,3,4,5,6,7 In/Output Port Pins 0,1,2,3,4,5,6,7 In/Output Port Output Port Input Port Pins 0,1,2,3,4,5,6,7 In/Output Port Input Port Output
Figure 40-Pin Configuration
WITH 16K/32K
Z86E61/E63 EPROM
DESCRIPTION (Continued) Standard Mode
XTAL1 XTAL2
/RESET R//W R//RL
Z86E61/E63 PLCC
Figure 44-Pin PLCC Configuration
Table 44-Pin PLCC Identification Standard Mode Symbol XTAL2 XTAL1 /RESET R//W Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Port Port Connected Reset Read/Write Data Strobe Address Strobe Port Ground Port Direction Input Output Input Output Input Input Input Output Output Output Output Input Input Standard Mode Symbol 14-16 18-22 23-27 29-31 34-38 40-42 P02-P00 R//RL P07-P03 P10-P14 P17-P15 P24-P20 P27-P25 Function Port Pins 0,1,2 ROM/ROMless control Port Pins 3,4,5,6,7 Port Pins 0,1,2,3,4 Connected Port Pins 5,6,7 Port Port Port Pins 0,1,2,3,4 Connected Port Pins 5,6,7 Port Port Direction In/Output Input In/Output In/Output Input In/Output Output Input In/Output Input In/Output Input Output
WITH
Z86E61/E63 16K/32K EPROM
DESCRIPTION EPROM Mode
XTAL2 XTAL1 /RESET
Table 40-Pin Identification
/PGM
EPROM Mode Symbol 7-10 13-20 21-28 31-37 XTAL2 XTAL1 /RESET A7-A0 D7-D0 A14-A8 /PGM
Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Connected Chip Enable Reset Connected Ground EPROM Prog Mode Address 0,1,2,3,4,5,6,7 Data 0,1,2,3,4,5,6,7 Connected Prog Voltage Address 8,9,10,11,12,13,14 Prog Mode Output Enable Connected
Direction Input Output Input Input Input Input Input Input Input Input In/Output Input Input Input Input Input Input
Z86E61 /E63
Figure 40-Pin Configuration
WITH 16K/32K
Z86E61/E63 EPROM
DESCRIPTION (Continued) EPROM Mode
XTAL2 XTAL1 /PGM
/RESET
Z86E61/E63 PLCC
Figure 44-Pin PLCC Configuration
Table 44-Pin PLCC Identification EPROM Mode Symbol 8-11 14-16 XTAL2 XTAL1 /RESET A0-A2 Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Connected Chip Enable Connected Reset Connected Ground EPROM Prog Mode Address 0,1,2 Connected Direction Input Input Input Input Input Input Input Input Input Input Input Input EPROM Mode Symbol 18-22 23-27 29-31 34-38 40-41 A7-A3 D4-D0 D7-D5 A12-A8 A13-A14 /PGM Function Address 3,4,5,6,7 Data 0,1,2,3,4 Connected Data 5,6,7 Connected Prog Voltage Address 8,9,10,11,12 Connected Address Prog Mode Output Enable Connected Direction Input In/Output Input In/Output Input Input Input Input Input Input Input Input
WITH
Z86E61/E63 16K/32K EPROM
FUNCTIONS
ROMless (input, active Low). Connecting this disables internal forces device function Z86C91 ROMless (see Z86C91 product specification more information). When left unconnected pulled High VCC, device functions normal Z86E61/E63 EPROM version. Note: This only available 44-pin versions Z86E61/E63. (output, active Low). Data Strobe activated once each external memory transfer. READ operation, data must available prior trailing edge /DS. WRITE operations, falling edge indicates that output data valid. (output, active Low). Address Strobe pulsed once beginning each machine cycle. Address output through Port external programs. Memory address transfers valid trailing edge /AS. Under program control, placed highimpedance state along with Ports Data Strobe, Read/Write. XTAL2, XTAL1 Crystal Crystal (time-based input output, respectively). These pins connect parallelresonant crystal, ceramic resonator, external single-phase clock on-chip oscillator buffer. R//W (output, write Low). Read/Write signal when writing external program data memory. /RESET (input, active Low). avoid asynchronous noisy reset problems, Z86E61/E63 equipped with reset filter four external clocks (4TpC). external /RESET signal less than 4TpC duration, reset occurs. fifth clock after /RESET detected, internal signal latched held internal register count external clocks, duration external /RESET, whichever longer. During reset cycle, held active while cycles rate TpC/2. When /RESET deactivated, program execution begins location 000C (HEX). Power-up reset time must held until stable, whichever longer. Port (P07-P00). Port 8-bit, nibble programmable, bidirectional, compatible port. These eight lines configured under software control nibble port, address port interfacing external memory. When used port, Port placed under handshake control. this configuration, Port lines used handshake control /DAV0 RDY0 (Data Available Ready). Handshake signal assignment dictated direction upper nibble P07-P04. lower nibble must have same direction upper nibble under handshake control. external memory references, Port provide address bits A11-A8 (lower nibble) A15-A8 (lower upper nibbles) depending required address space. address range requires bits less, upper nibble Port programmed independently while lower nibble used addressing. both nibbles needed operation, they must configured writing Port Mode register. ROMless mode, after hardware reset, Port lines defined address lines A15-A8, extended timing accommodate slow memory access. initialization routine include reconfiguration eliminate this extended timing mode (Figure Port (P17-P10). Port 8-bit, byte programmable, bidirectional, compatible port. multiplexed Address (A7-A0) Data (D7-D0) ports. Z86E61/E63, these eight lines programmed input output lines configured under software control address/data port interfacing external memory. When used port, Port placed under handshake control. this configuration, Port lines, P34, used handshake controls RDY1 /DAV1. Memory locations greater than 16384 (E61) 32768 (E63) referenced through Port interface external memory, Port must programmed multiplexed Address/ Data mode. more than external locations required, Port must output additional lines. Port placed high-impedance state along with Port /AS, /DS, R//W, allowing share common resources multiprocessor applications. Data transfers controlled assigning Acknowledge input, Request output (Figure
WITH 16K/32K
Z86E61/E63 EPROM
FUNCTIONS (Continued)
Port (I/O) Z86E61 /E63
Handshake Controls /DAV0 RDY0 (P32 P35)
Level Shifter
Auto Latch
Figure Port Configuration
WITH
Z86E61/E63 16K/32K EPROM
Z86E61 /E63
Port (AD7-AD0)
Handshake Controls /DAV1 RDY1 (P33 P34)
Level Shifter
Auto Latch
Figure Port Configuration
WITH 16K/32K
Z86E61/E63 EPROM
FUNCTIONS (Continued)
Port (P27-P20). Port 8-bit, programmable, bidirectional, CMOS compatible port. Each these eight lines independently programmed input output, globally open-drain output. Port always available operation. When used port, Port placed under handshake control. this configuration, Port lines used handshake control lines /DAV2 RDY2. handshake signal assignment Port lines, P36, dictated direction (input output) assigned (Figure Table
Z86E61 /E63
Port (I/O)
Handshake Controls /DAV2 RDY2 (P31 P36)
Open-Drain
Level Shifter
Auto Latch
Figure Port Configuration
Port (P37-P30). Port 8-bit, CMOS compatible fourfixed input four-fixed output port. These eight lines have four-fixed (P33-P30) input four-fixed (P37-P34)
WITH
Z86E61/E63 16K/32K EPROM
output ports. Port when used serial I/O, programmed serial serial out, respectively (Figure
Z86E61 /E63
Port (I/O Control)
Figure Port Configuration
Port configured under software control provide following control functions: handshake Ports (/DAV RDY); four external interrupt request signals
(IRQ3-IRQ0); timer input output signals (TIN TOUT), Data Memory Select (/DM) EPROM control signals (P30 /CE, /OE,
Table Port Assignments CTC1 Int. IRQ3 IRQ2 IRQ0 IRQ1 TOUT IRQ4 IRQ5 Serial UART Serial EPROM
Notes: Handshake Signals Data Available Ready
WITH 16K/32K
Z86E61/E63 EPROM
UART OPERATION
Port lines, P30, programmed serial lines full-duplex serial asynchronous receiver/transmitter operation. rate controlled Counter/ Timer0. Z86E61/E63 automatically adds start stop bits transmitted data (Figure 10). parity also available option. Eight data bits always transmitted, regardless parity selection. parity enabled, eighth parity bit. interrupt request (IRQ4) generated transmitted characters. Received data must have start bit, eight data bits, least stop bit. parity received data replaced parity error flag. Received characters generate IRQ3 interrupt request.
Transmitted Data Parity) Start Eight Data Bits Stop Bits
Received Data Parity) Start Eight Data Bits Stop
Transmitted Data (With Parity) Start Seven Data Bits Parity Stop Bits
Received Data (With Parity) Start Seven Data Bits Parity Error Flag Stop
Figure Serial Data Formats
Auto Latch. Auto Latch puts valid CMOS levels CMOS inputs that externally driven. This reduces excessive supply current flow input buffer when driven source.
Note: P33-P30 inputs differ from Z86C61/C63 that there clamping diode because EPROM high voltage detection circuits. Exceeding maximum specification during standard operating mode cause device enter EPROM mode
ADDRESS SPACE
Program Memory. Z86E61/E63 address Kbytes (E61) Kbytes (E63) external program memory (Figure 11). first bytes program memory reserved interrupt vectors. These locations contain 16-bit vectors that correspond available interrupts. EPROM mode, byte byte 16383 (E61) 32767 (E63) consists on-chip EPROM. addresses 16384 (E61) 32768 (E63) above, Z86E61/E63 executes external program memory fetches. ROMless mode, Z86E61/E63 address Kbytes program memory. Program execution begins external location 000C (HEX) after reset.
65535 16384 (E61) 32768 (E63) 16383 (E61) 32767 (E63) External
WITH
Z86E61/E63 16K/32K EPROM
On-Chip PROM
access registers directly indirectly through 8-bit address field. Z86E61/E63 also allows short 4-bit register addressing using Register Pointer (Figure 14). 4-bit mode, Register File divided into working register groups, each occupying continuous locations. Register Pointer addresses starting location active working register group. Stack. Z86E61/E63 16-bit Stack Pointer (R255R254) used external stacks that reside anywhere data memory ROMless mode, only from 16384 (E61) 32768 (E63) 65535 EPROM mode. 8-bit Stack Pointer (R255) used internal stack that resides within general-purpose registers (R239R4). high byte Stack Pointer (SPH Bits 15-8) general purpose register when using internal stack only.
65535
Location First Byte Instruction Executed After RESET
IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Interrupt Vector (Lower Byte)
Interrupt Vector (Upper Byte)
Figure Program Memory Configuration
External Data Memory
Data Memory (/DM). EPROM version address Kbytes (E61) Kbytes (E63) external data memory space beginning location 16384 (E61) 32768 (E63). ROMless version address Kbytes external data memory. External data memory included with, separated from, external program memory space. /DM, optional function that programmed appear P34, used distinguish between data program memory space (Figure 12). state signal controlled type instruction being executed. opcode references PROGRAM (/DM inactive) memory, instruction references DATA (/DM active Low) memory. Register File. register file consists four port registers, general-purpose registers, control status registers (Figure 13). instructions
32768 (E63) 16384 (E61) 16383 (E61) 32767 (E63) Addressable
Figure Data Memory Configuration
WITH 16K/32K
Z86E61/E63 EPROM
ADDRESS SPACE (Continued)
LOCATION R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 R239 General-Purpose Registers
IDENTIFIERS Stack Pointer (Bits 7-0) Stack Pointer (Bits 15-8) Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports Mode Port Mode Port Mode Prescaler Timer/Counter0 Prescaler Timer/Counter1 Timer Mode Serial FLAGS
R253 (Register Pointer)
upper nibble register file address provided register pointer specifies active working-register group.
Register Group
P01M PRE0 PRE1
Specified Working Register Group
lower nibble register file address provided instruction points specified register.
Register Group
Register Group Ports
Port Port Port Port
Figure Register Pointer
Figure Register File
WITH
Z86E61/E63 16K/32K EPROM
FUNCTIONAL DESCRIPTION
Counter/Timers. There 8-bit programmable counter/timers (T0-T1), each driven 6-bit programmable prescaler. prescaler driven internal external clock sources; however, prescaler driven internal clock only (Figure 15). 6-bit prescalers divide input frequency clock source integer number from Each prescaler drives counter, which decrements value 256) that been loaded into counter. When both counters prescalers reach count, timer interrupt request, IRQ4 (T0) IRQ5 (T1), generated. counter programmed start, stop, restart continue, restart from initial value. counters also programmed stop upon reaching zero (single pass mode) automatically reload initial value continue counting (modulo-n continuous mode). counter, prescalers, read time without disturbing their value count mode. clock source user-definable either internal microprocessor clock divided-by-four, external signal input through Port Timer Mode register configures external timer input (P31) external clock, trigger input that retriggerable non-retriggerable, gate input internal clock. Port line also serves timer output (TOUT) through which internal clock output. counter/timers cascaded connecting output input
Internal Data Write PRE0 Initial Value Register Write Initial Value Register Read Current Value Register
6-Bit Down Counter 8-bit Down Counter
Internal Clock
IRQ4 Serial Clock TOUT
External Clock Clock Logic 6-Bit Down Counter 8-Bit Down Counter
IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write Write
Initial Value Register Read
Current Value Register
Internal Data
Figure Counter/Timers Block Diagram
WITH 16K/32K
Z86E61/E63 EPROM
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. Z86E61/E63 different interrupts from eight different sources. interrupts maskable prioritized. eight sources divided follows: four sources claimed Port lines P33-P30, Serial Out, Serial counter/timers (Figure 16). Interrupt Mask Register globally individually enables disables interrupt requests. When more than interrupt pending, priorities resolved programmable priority encoder that controlled Interrupt Priority register (refer Table Z86E61/E63 interrupts vectored through locations program memory. When interrupt machine cycle activated, interrupt request granted. Thus, this disables subsequent interrupts, saves Program Counter Status Flags, then branches program memory vector location reserved that interrupt. This memory location next byte contain 16-bit address interrupt service routine that particular interrupt request. accommodate polled interrupt systems, interrupt inputs masked Interrupt Request register polled determine which interrupt requests need service. Software initialized interrupts supported setting appropriate Interrupt Request Register (IRQ). Internal interrupt requests sampled falling edge last cycle every instruction, interrupt request must valid 5TpC before falling edge last clock cycle currently executing instruction. ROMless mode, when device samples valid interrupt request, next (external) clock cycles used prioritize interrupt, push bytes FLAG register stack. following nine cycles used fetch interrupt vector from external memory. first byte interrupt service routine fetched beginning 58th cycle following internal sample point, which corresponds 63rd cycle following external interrupt sample point.
IRQ0 IRQ5
Global Interrupt Enable
Interrupt Request
PRIORITY LOGIC
Vector Select
Figure Interrupt Block Diagram
Clock. Z86E61/E63 on-chip oscillator high gain, parallel resonant amplifier connection crystal, ceramic resonator, suitable external clock source (XTAL1 Input, XTAL2 Output). crystal should cut, max; series resistance
WITH
Z86E61/E63 16K/32K EPROM
(RS) less than equal Ohms. crystal should connected across XTAL1 XTAL2 using recommended capacitors from each ground (Figure 17). Note: Actual capacitor value specified crystal manufacturer.
XTAL1 XTAL2 Ceramic Resonator Crystal Clock
XTAL1
XTAL1
XTAL2
XTAL2
External Clock
Figure Oscillator Configuration
HALT. Turns internal clock XTAL oscillation. counter/timers external interrupts IRQ0, IRQ1, IRQ2, IRQ3 remain active. devices recovered interrupts, either externally internally generated. interrupt request must executed (enabled) exit HALT mode. After interrupt service routine, program continues from instruction after HALT. STOP. This instruction turns internal clock external crystal oscillation, reduces standby current (typical) less. STOP mode terminated reset, which causes processor restart application program address 000C (HEX).
order enter STOP HALT) mode, necessary first flush instruction pipeline avoid suspending execution mid-instruction. this, user must execute (opcode OFFH) immediately before appropriate SLEEP instruction. i.e., STOP HALT clear pipeline enter STOP mode clear pipeline enter HALT mode
PROGRAMMING Z86E61/E63 User Modes
Z86E61/E63 uses separate timing cycles different User Modes available. Table shows Z86E61/ User Modes. Table shows timing programming waveforms. User MODE EPROM Read Z86E61/E63 EPROM read cycle provided that user read Z86E61/E63 standard 27128 (E61) 27256 (E63) EPROM. This accomplished driving /EPM (P32) activating /OE. /PGM remains inactive. This mode valid after execution EPROM protect cycle. Timing EPROM read cycle shown Figure User MODE EPROM Program Z86E61/E63 Program function conforms Intelligent programming algorithm. device programmed with 6.0V 12.5V. Programming pulses applied increments maximum pulses before proper verification. After verification, programming pulse three times duration cycles necessary program device issued ensure proper programming. After addresses programmed, final data comparison executed programming cycle complete. Timing Z86E61/E63 programming cycle shown Figure
WITH 16K/32K
Z86E61/E63 EPROM
PROGRAMMING (Continued)
User Mode PROM Verify Program Verify cycle used part intelligent programming algorithm insure data integrity under worst-case conditions. differs from EPROM Read cycle that active must driven 6.0V. Timing shown Figure User Modes EPROM Protect extend program security, EPROM protect cycles provided Z86E61/E63. Execution EPROM protect cycle prohibits proper execution EPROM Read, EPROM Verify, EPROM programming cycles. Execution protect cycle disables accesses upper bytes register memory (excluding mode configuration registers), first user's program must (R251). Timing shown Figures User Modes. Table shows programming voltage each mode Z86E61/E63.
Table Programming Table User/Test Mode Device User Modes EPROM Read Program Program Verify EPROM Protect Protect Device Pins /PGM Port CNFG Data
ADDR Addr Addr Addr
5.0V 6.0V 6.0V 6.0V 6.0V
Notes: 12.0V 0.5V 12.0V 0.5V Irrelevant during programming maximum. during programming, verify, read maximum.
Z86E63 Signal Description EPROM Program/Read
following signals required correctly program read Z86E63 device. ADDR. address must remain stable throughout program read cycle. DATA. data must stable during programming (/OE High, /PGM Low, High). During read data outputs data. XCLK. clock required clock /RESET signal into registers before programming. constant clock applied, XCLK input toggled minimum cycles before programming verify function begins. maximum clock frequency applied when EPROM mode MHz. /RESET. reset input held constant High value throughout normal programming. must held High program EPROM protect option bit. Also, time /RESET input changes state XCLK must clocked minimum times clock /RESET through reset filter. /OE. When device placed EPROM mode, input also serves precharge sense amp. precharge signal should first half stable address High second half. PRECHG signal inverted from signal should High first half second half, stable address. EPROM output data should sampled during second half stable address. access time EPROM defined later sections. This part calculation access time required because this precharged sense with precharge clock.
Table Timing Programming Waveforms Parameters Name Address Setup Time Data Setup Time Setup Setup Time Chip Enable Setup Time Program Pulse Width Data Hold Time Setup Time Data Access Time Data Output Float Time Overprogram Pulse Width Setup Time /PGM Setup Time Address Setup Time Option Program Pulse Width 0.95 2.85
WITH
Z86E61/E63 16K/32K EPROM
Units
Address Data
Address Stable
Address Stable
Invalid
Valid
Invalid
Valid
5.5V
4.5V
/PGM
Figure EPROM Read
WITH 16K/32K
Z86E61/E63 EPROM
PROGRAMMING (Continued)
Address Data
Address Stable
Data Stable
Data Valid
4.5V
/PGM
Program Cycle Verify Cycle
Figure EPROM Program Verify
WITH
Z86E61/E63 16K/32K EPROM
Address Data
Address
4.5V
/PGM
Protect Programming
Protect Programming
Figure Programming EPROM, Protect Size Selection
WITH 16K/32K
Z86E61/E63 EPROM
PROGRAMMING (Continued)
Address Data
Address
4.5V
/PGM
Protect Programming
Protect Programming
Figure Programming EPROM, Protect Size Selection
WITH
Z86E61/E63 16K/32K EPROM
Start
Addr First Location
6.0V 12.5V
Program Pulse
Increment
Fail Verify Byte Pass Prog. Pulse Duration Fail
Verify Byte Pass
Increment Address
Last Addr 4.5V
Verify Bytes Pass 5.5V
Fail
Device Failed
Verify Bytes Pass Device Passed
Fail
Figure Intelligent Programming Flowchart
WITH 16K/32K
Z86E61/E63 EPROM
ABSOLUTE MAXIMUM RATINGS
Symbol TSTG Description Supply Voltage* Storage Temp Oper Ambient Temp -0.3 -65° 7.0° +150° Units Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; operation device condition above those indicated operational sections these specifications implied. Exposure absolute maximum rating conditions extended period affect device reliability.
Notes: Voltages pins with respect GND. Ordering Information
STANDARD TEST CONDITIONS
characteristics listed below apply standard test conditions noted. voltages referenced GND. Positive current flows into referenced (Figure 23).
From Output Under
Figure Test Load Diagram
WITH
Z86E61/E63 16K/32K EPROM
CHARACTERISTICS
+70°C VCC+ VCC+ -0.3 VCC+ Typical 25°C
Parameter Input Voltage Input Voltage Clock Input High Voltage Clock Input Voltage Input High Voltage Input Voltage Output High Voltage Output Voltage Reset Input High Voltage Reset Input Voltage Input Leakage Output Leakage Reset Input Current Supply Current Standby Current Standby Current
Units
Conditions P33-P30 Only Driven External Clock Generator Driven External Clock Generator
ICC1 ICC2
-0.3 -0.3
-2.0 +2.0
5.25V 5.25V 5.25V, HALT Mode HALT Mode STOP Mode STOP Mode
Notes: requires loading (%F1H) with value prior STOP execution. this sequence: TMR,#00 STOP
WITH 16K/32K
Z86E61/E63 EPROM
CHARACTERISTICS External Memory Read Write Timing Diagram
R//W
Port
Port
(Read)
Port
(Write)
Figure External Memory Read/Write Timing
WITH
Z86E61/E63 16K/32K EPROM
CHARACTERISTICS External Memory Read Write Timing Table
+70°C
Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS)
Parameter Address Valid Rise Delay Rise Address Float Delay Rise Read Data Req'd Valid Width Address Float Fall (Read) Width (Write) Width Fall Read Data Req'd Valid Read Data Rise Hold Time Rise Address Active Delay Rise Fall Delay R//W Valid Rise Delay Rise R//W Valid Write Data Valid Fall (Write) Delay Rise Write Data Valid Delay Address Valid Read Data Req'd Valid Rise Fall Delay Valid Fall Delay
Units
Notes [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [2,3]
Notes: When using extended memory timing TpC. Timing numbers given minimum TpC. clock cycle dependent characteristics table. Standard Test Load timing references logic logic
Clock Dependent Formulas Number Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW TdDSR(DR) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Equation 0.40 0.32 0.59 3.25 2.83 6.14 0.66 1.65 2.33 10.56 1.27 1.67 1.97 42.5 0.59 3.14 sTpC 0.88 0.91 10.7 26.3
WITH 16K/32K
Z86E61/E63 EPROM
CHARACTERISTICS Additional Timing Diagram
Clock
IRQN
Figure Additional Timing
CHARACTERISTICS Additional Timing Table
+70°C 62.5 5TpC 8TpC 5TpC 5TpC 1000 5TpC 8TpC 5TpC 5TpC 1000
Symbol TrC,TfC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH
Parameter Input Clock Period Clock Input Rise Fall Times Input Clock Width Timer Input Width Timer Input High Width Timer Input Period Timer Input Rise Fall Times Interrupt Request Input Times Interrupt Request Input Times Interrupt Request Input High Times
Units
Notes [2,4] [2,5] [2,3]
Notes: Clock timing references 3.8V logic 0.8V logic Timing references 2.0V logic 0.8V logic Interrupt references request through Port Interrupt request through Port (P33-P31). Interrupt request through Port
WITH
Z86E61/E63 16K/32K EPROM
CHARACTERISTICS Handshake Timing Diagrams
Data
Data Valid
Next Data Valid
/DAV (Input)
Delayed
(Output)
Delayed
Figure Input Handshake Timing
Data
Data Valid
Next Data Valid
/DAV (Output)
Delayed
(Input)
Delayed
Figure Output Handshake Timing
WITH 16K/32K
Z86E61/E63 EPROM
CHARACTERISTICS Handshake Timing Table
+70°C
Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY0(DAV) TdD0(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV)
Parameter Data Setup Time Data Hold Time Data Available Width Fall Fall Delay Rise Rise Delay Rise Fall Delay Data Fall Delay Fall Fall Delay Fall Rise Delay Width Rise Fall Delay
Data Direction
WITH
Z86E61/E63 16K/32K EPROM
CONTROL REGISTER DIAGRAMS
R240
R243 PRE1
Serial Data LSB)
Count Mode Single Pass Modulo Clock Source Internal External Timing Input (TIN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure Serial Register (F0H: Read/Write)
R241
Function Load Disable Count Enable Count Function Load Disable Count Enable Count
Figure Prescaler Register (F3H: Write Only)
R244
Modes External Clock Input Gate Input Trigger Input (Non-retriggerable) Trigger Input (Retriggerable) TOUT Modes Used Internal Clock
Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) Current Value (When Read)
Figure Counter/Timer Register (F4H: Read/Write)
R245 PRE0
Figure Timer Mode Register (F1H: Read/Write)
R242
Count Mode Single Pass Modulo Reserved (Must Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) Current Value (When Read)
Figure Prescaler Register (F5H: Write Only)
Figure Counter/Timer Register (F2H: Read/Write)
WITH 16K/32K
Z86E61/E63 EPROM
CONTROL REGISTER DIAGRAMS (Continued)
R246
R248 P01M
Definition Defines Output Defines Input
Mode Output Input Stack Selection External Internal Mode Byte Output Byte Input High-Impedance DA0, /AS, /DS, /R//W, A12, Selected Reserved (Must
Figure Port Mode Register (F6H: Write Only)
R247
Port Pull-Ups Open Drain Port Pull-Ups Active Reserved (Must Input Output /DAV0/RDY0 RDY0//DAV0 Input Output Input /DAV1/RDY1 RDY1//DAV1
R249
Mode Output Input
Figure Port Mode Register (F8H: Write Only)
Input (TIN) Output (TOUT) /DAV2/RDY2 RDY2//DAV2 Input Output Serial Serial
Parity Parity
Interrupt Group Priority Reserved Reserved IRQ1, IRQ4 Priority (Group IRQ1 IRQ4 IRQ4 IRQ1 IRQ0, IRQ2 Priority (Group IRQ2 IRQ0 IRQ0 IRQ2 IRQ3, IRQ5 Priority (Group IRQ5 IRQ3 IRQ3 IRQ5 Reserved (Must
Figure Port Mode Register (F7H: Write Only)
Figure Interrupt Priority Register (F9H: Write Only)
R250
R253
WITH
Z86E61/E63 16K/32K EPROM
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
Input IRQ0) Input Input Input, Serial Input Serial Output
Reserved (Must Register Pointer
Reserved (Must
Figure Interrupt Request Register Read/Write)
Figure Register Pointer Register (FDH Read/Write)
R251
R254
Enables IRQ5-IRQ0 IRQ0) Enables Protect Enables Interrupts
Stack Pointer Upper Byte (SP15 SP8)
Figure Interrupt Mask Register Read/Write)
R255
R252 FLAGS
Figure Stack Pointer Register Read/Write)
User Flag User Flag Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Stack Pointer Lower Byte (SP7 SP0)
Figure Stack Pointer Register (FFH Read/Write)
Figure Flag Register Read/Write)
WITH 16K/32K
Z86E61/E63 EPROM
CHARACTERISTICS Supply Current
(mA)
Frequency (MHz)
Legend: 5.6V 5.0V 4.4V
Figure Typical Frequency
WITH
Z86E61/E63 16K/32K EPROM
CHARACTERISTICS Standby Current
(mA)
Frequency (MHz)
Legend: 5.6V 5.0V 4.4V
Figure Typical ICC1 Frequency
WITH 16K/32K
Z86E61/E63 EPROM
INSTRUCTION NOTATION
Addressing Modes. following notation used describe addressing modes instruction operations shown instruction summary. Symbol Meaning Indirect register pair indirect working register pair address Indirect working register pair only Indexed address Direct address Relative address Immediate Register working register address Working register address only Indirect register indirect working register address Indirect working register address only Register pair working register pair address Flags. Control register (R252) contains following flags: Symbol Meaning Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag
Affected flags indicated Clear zero clear according operation Unaffected Undefined
Symbols. following symbols used describing instruction set. Symbol FLAGS Meaning Destination location contents Source location contents Condition Code Indirect address prefix Stack Pointer Program Counter Flag Register (Control Register 252) Register Pointer (R253) Interrupt Mask Register (R251)
WITH
Z86E61/E63 16K/32K EPROM
CONDITION CODES
Value 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 0001 1010 0010 1111 0111 1011 0011 0000 Mnemonic Meaning Always True Carry Carry Zero Zero Plus Minus Overflow Overflow Equal Equal Greater Than Equal Less than Greater Than Less Than Equal Unsigned Greater Than Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than Equal Never True (Always False) Flags
WITH 16K/32K
Z86E61/E63 EPROM
INSTRUCTION FORMATS
CCF, IRET, NOP, RCF, RET,
One-Byte Instructions
MODE 1110 dst/src
dst/src
CLR, CPL, DEC, DECW, INC, INCW, POP, PUSH, RLC, RRC, SRA, SWAP CALL (Indirect)
MODE 1110 1110
ADC, ADD, AND, SBC, SUB, TCM,
1110
MODE 1110
ADC, ADD, AND, SBC, SUB, TCM,
VALUE
VALUE
MODE MODE ADC, ADD, AND, SBC, SUB, TCM, LDE, LDEI, LDC, LDCI MODE dst/src
1110 1110
MODE dst/src
src/dst
ADDRESS dst/src 1110
src/dst
VALUE dst/CC DJNZ, CALL
STOP/HALT
Two-Byte Instructions
Three-Byte Instructions
INSTRUCTION SUMMARY
Note: Assignment value indicated symbol example: indicates that source data added destination data result stored destination location. notation "addr (n)" used refer given operand location. example: refers destination operand.
WITH
Z86E61/E63 16K/32K EPROM
INSTRUCTION SUMMARY
Address Opcode Mode Byte (Hex) Address Opcode Mode Byte (Hex) INCW dstdst IRET FLAGS@SP; SPSP PC@SP; SPSP IMR(7)1 true, PCdst true, PCPC Range: +127, -128 dst, dstsrc r=0-F
Instruction Operation dst, dstdst dst, dstdst dst, dstdst CALL SPSP @SPPC, PCdst CNOT dst0 dstNOT dst, dstDA dstdst DECW dstdst IMR(7)0 DJNZr, PCPC Range: +127, -128 IMR(7)1 HALT
Flags Affected
Instruction Operation dstdst
Flags Affected
r=0-F
c=0-F c=0-F
r=0-F
dst, dstsrc LDCI dst, dstsrc rrrr
WITH 16K/32K
Z86E61/E63 EPROM
INSTRUCTION SUMMARY (Continued)
Address Opcode Mode Byte (Hex) Address Mode Opcode Byte (Hex)
Instruction Operation dst, dstdst dst@SP; SPSP PUSH SPSP @SPsrc PC@SP; SPSP
Flags Affected
Instruction Operation STOP dst, dstdstsrc SWAP
Flags Affected
dst, (NOT dst) dst, dst, dstdst
These instructions have identical addressing modes, which encoded brevity. first opcode nibble found instruction table above. second nibble expressed symbolically this table, value found following table left applicable addressing mode pair. example, opcode instruction using addressing modes (destination) (source)
Address Mode
Lower Opcode Nibble
dst, dstdstsrcC
RPsrc
WITH
Z86E61/E63 16K/32K EPROM
OPCODE
Lower Nibble (Hex)
IRR1 10.5 10/12.1 PUSH 10.5 DECW 10.5 INCW SWAP 10.5 12/14.1 PUSH 10.5 DECW 10.5 INCW SWAP 12.0 Irr2 12.0 Irr1 12.0 Irr2 12.0 Irr2 18.0 LDEI Ir1, Irr2 18.0 LDEI Ir2, Irr1 18.0 LDCI Ir1, Irr2 18.0 LDCI Ir1, Irr2 Ir1, 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 IR2, 10.5 IR2, 10.5 IR2, 10.5 IR2, 10.5 IR2, 10.5 IR2, 10.5 IR2, 10.5 IR2, 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 12.10.0
Upper Nibble (Hex)
10.5 IR1, 10.5 IR1, 10.5 IR1, 10.5 IR1, 10.5 IR1, 10.5 IR1, 10.5 IR1, 10.5 IR1,
12/10.5 12/10.0 DJNZ
STOP HALT
10.5 10.5 10.5 10.5 IR2, IR1, 10.5 10.5 10.5 10.5 IR2, IR1, 10.5 r1,x,R2 10.5 20.0 20.0 CALL CALL* r2,x,R1 IRR1 10.5 10.5 10.5 10.5 IR2, IR1, 10.5
14.0 16.0 IRET
Bytes Instruction Lower Opcode Nibble Pipeline Cycles
Execution Cycles Upper Opcode Nibble
Legend: 8-bit Address 4-bit Address Address Address Sequence: Opcode, First Operand, Second Operand Note: Blank areas defined. *2-byte instruction appears 3-byte instruction
10.5
Mnemonic
First Operand
Second Operand
WITH 16K/32K
Z86E61/E63 EPROM
PACKAGE INFORMATION
40-Pin Package Diagram
44-Pin PLCC Package Diagram
WITH
Z86E61/E63 16K/32K EPROM
44-Pin Package Diagram
WITH 16K/32K
Z86E61/E63 EPROM
ORDERING INFORMATION Z86E61
40-Pin Z86E6116PSC 44-Pin Z86E6116FEC 44-Pin PLCC Z86E6116VSC
40-Pin Z86E6120PSC 44-Pin PLCC Z86E6120VSC
Z86E63
40-Pin Z86E6316PSC 44-Pin PLCC Z86E6316VSC
40-Pin Z86E6320PSC 44-Pin PLCC Z86E6320VSC
fast results, contact your local Zilog sales office assistance ordering part desired.
CODES Preferred Package
Plastic Plastic Chip Carrier
Temperature
+70°C
Speeds
Environmental
Plastic Standard
Example:
86E61 Z86E61, MHz, +70°C, Plastic Standard Flow Environmental Flow emperature Package Speed Product Number Zilog Prefix

Z86E61 E63

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