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Z16C30 USC® USER'S MANUAL
USER's MANUAL
CHAPTER
INTERRUPTS
INTRODUCTION
interrupt subsystem derives from Zilog's long experience providing most advanced interrupt capabilities microprocessor field. These capabilities used their best advantage system including Zilog processor other Zilog peripherals, it's easy interface interrupt other processors well. This chapter describes USC's interrupt capabilities them various system applications. dedicates eight pins interrupts. Each channel interrupt request output (/INTA /INTB). /SITACK /PITACK inputs signal that processor acknowledging interrupt, different ways with different kinds host microprocessors. applications which interrupt acknowledge cycles cannot easily detected USC, software simulate such cycle. Each channel Interrupt Enable (IEIA, IEIB) (IEOA, IEOB) pins. These signals allow systems including several Zilog-compatible peripherals Interrupt Acknowledge Daisy Chain select multiple interrupting devices should serviced. This eliminate need separate interrupt controller. other hand, because provides separate Interrupt Request outputs Interrupt Enable inputs each channel, external interrupt control logic process interrupt requests round-robin dynamic-priority fashion among channels more USCs and/or other peripheral devices.
INTERRUPT ACKNOWLEDGE DAISY-CHAINS
Figure shows interrupt acknowledge daisy-chain. highest-priority daisy-chainable device that request interrupt tied High. Because this, always request interrupt, "has first claim providing interrupt vector answer interrupt acknowledge cycle. highest-priority device connected next-higher-priority device. This "daisy chaining" outputs inputs continues until lowest-priority daisy-chainable device that request interrupt, which left unconnected. With with Zilog-compatible devices except Z80® family members, IACK daisy chain serves separate functions. During interrupt acknowledge cycle, daisy chain acts select highest-priority requesting device return interrupt vector. After that, until resulting interrupt service routine over, daisy chain serves block interrupt requests from devices having lower priority than that currently being serviced, while allowing them from higher-priority devices. This daisy-chain structure allows nesting interrupt service routines. Nesting greatly improve worst-case interrupt response times critical real-time applications well I/O-intensive computing systems. Whether host software uses nested interrupts, USC's interrupt subsystem provides most efficient interrupt handling possible.
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INTERRUPT ACKNOWLEDGE DAISY-CHAINS (Continued)
Host
/IACK /IRQ Peripheral
/SITACK /INTA /PITACK IEIA IEIB
/INTB IEOB IEOA /IACK /IRQ Peripheral (NC)
Figure 7-1. Interrupt Daisy Chain
EXTERNAL INTERRUPT CONTROL LOGIC
There valid reasons system designer might choose interrupt acknowledge daisy chain (plus less valid being familiar with them). First, system that includes many channels having similar baud rates serial traffic, strict priority among channels that's inherent daisy chain, might endanger proper interrupt servicing channel(s) low-priority chain. such cases, interrupt service requirements more easily guaranteed using central interrupt controller that distributes interrupt acknowledgments among channels round-robin (rotating-priority) basis. Such schemes target "fairness" rather than priority interrupt servicing among channels. second reason simple/wired interrupt daisy chain would system which data rates vary over considerable range among several channels, determined dynamically rather than being known system being designed. channel's interrupt servicing requirements typically vary directly with serial data rate.) such system, external interrupt logic distribute interrupt acknowledge cycles using dynamic priority determined each channel's data rate. Both rotating-priority dynamic-priority systems arranged shown Figure 7-2. interrupt control logic maintains inputs channels high most time, that channels assert their /INT outputs. logic simply /INT outputs various channels make interrupt request processor. Alternatively, dynamic-priority system with processor that supports multiple levels interrupts, control logic assign different channels different processor levels. Regardless interrupt control logic derives processor request, when processor does interrupt acknowledge cycle, logic must select particular device from among those requesting interrupt, "receive" cycle. control logic implement this choice ways. First, negate inputs device, then wait specified setup time before presenting cycle devices, using /PITACK /SITACK signal possible other control signals. simply present cycle only selected channel, typically using single pulse /PITACK.
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Processor
Interrupt Control Logic
/INT, /INTB IUSC
IEIA, IEIB
/SITACK /PITACK Other Devices
Figure 7-2. External Interrupt Control
USING /RXREQ /TXREQ INTERRUPT REQUESTS
When external controller isn't used handle Receive Transmit data channel, corresponding isn't used output transfer request. this case software still program "DMA request" output, system designer output signal another interrupt request instead. will see, software program "interrupt request levels" determine when FIFO asserts /INT pin. These request levels similar those discussed Chapter FIFO controls pin. system designer /TxREQA, /TxREQB, /RxREQA, /RxREQB another interrupt request line. This particularly advantageous system which host processor multiple interrupt request levels, software allows/uses nested interrupts. such system, pin(s) connected different request level than /INT pin, that data interrupts have different priority than other kinds interrupts. 'DMA Requests Receiver Transmitter' section Chapter describes channel asserts until software completely filled TxFIFO emptied RxFIFO, until message/ frame, whichever comes first. This differs from channel asserts /INT output, means that interrupt service routine must take provide data until FIFO full empty until frame message, order avoid immediate re-interruption.
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INTERRUPT TYPES SOURCES
Internally, uses daisy-chaining scheme much like that described earlier. Each channel includes interrupt "types", that arranged fixed priority order. Four types include several independent interrupt stimuli "sources". Figure shows interrupt types sources channel USC, arranged with highest priority type top. relative priority channels determined external wiring among pins, external interrupt controller.
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Sources
Exited Hunt Idle Received Break/Abort Boundary Abort/Parity Error Overrun Preamble Sent Idle Abort Sent EOF/EOM Sent Sent Underrun /RxC Fall /RxC Rise /TxC Fall /TxC Rise /RxREQ Fall /RxREQ Rise /TxREQ Fall TxCREQ Rise /DCD Fall /DCD Rise /CTS Fall /CTS Rise Underflow DPLL Desync BRG1 Zero BRG0 Zero Miscellaneous Pins TxFIFO Fill Level Threshold Data Status RxFIFO Fill Level Threshold Data Status
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Channel
Types
Highest Priority
Internal Daisy Chain
Channel Interrupts Vector
Lowest Priority
Figure 7-3. Interrupt Types Sources
Internal Daisy Chain
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INTERNAL INTERRUPT OPERATION
Figure presents model typical internal structure interrupt subsystem, source that type "t". Note that Figure represents model USC's interrupt logic rather than exact logic; it's included only understanding interrupt subsystem. Each individual source associated register that we'll call Interrupt bit. (Previous Zilog documents called this Interrupt Enable bit, also used same term another that applies entire type. distinguish between these kinds register bits, this description will call that applies individual sources "IA".) bits fully under software control. When associated source cause interrupt. sources typically readable register bits themselves, derived from various kinds logic, such logic that compares fullness FIFO with threshold level which interrupt, logic that detects transitions another register bit. Each source logically ANDed. rising edge logical these terms, sources type, sets "Interrupt Pending" (IP) type. family members, bits independently state associated bits, cleared only software Reset). close examination Figure will show that setting delayed "armed" source comes true during interrupt acknowledge cycle, that's particularly important understanding USC's interrupt subsystem. second register associated with each type Interrupt Enable bit. This under full software control. When interrupt requested when type's Note that while associated software then sets before clears associated bit, immediate interrupt result. There more register each type, called Interrupt Under Service bit. interrupt logic sets type during interrupt acknowledge cycle, daisy chain shows that highest-priority type that's currently requesting interrupt. (This includes types higher-priority devices higher-priority types within channel.) Aside from hardware software Reset, only reset software. This typically done near interrupt service routine that type. During execution interrupt service routine given type, type's blocks interrupt requests from lower-priority types. gate near Figure shows actual conditions type request interrupt. type's bits must both must incoming "IEI" signal must true. true indicates that higher-priority type (on-chip external) set. Finally, Master Interrupt Enable (MIE) register channel must
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From pin, Next-Higher-Priority Type From Other Types ADnb
From Other Megacell(s)
/INT
/tIUS WRREGb Reset Source ADna From Other Sources WRREGa Reset Reset Logic1
/IACKcy Reset
/tIUS
Iack Read Next-Lower-Priority Type Drive Vector
Figure 7-4. Model Interrupt Logic Source Type
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DETAILS MODEL
bits appear near left side Figure 7-4, D-type flip-flops that capture state line when software writes specific register. appears D-type flip-flop latch that hardware" described above; software clear latch. signal labelled /IACKcy duration interrupt acknowledge sequence. appears D-type flip-flop that clock inputs acknowledge cycle; again, software clear IUS. various signals named that clear IUS, represent software operations. These reflect writing certain register position, represent writing encoded command register. Since software always clear during interrupt service routine, typically also clear IUS, there often several ways clear these bits, shown multiple signals these functions Figure. thing shown Figure typical command "Reset Highest IUS" implemented including this function would have considerably increased complexity logic, which already complex enough! downward-pointing gates Figure form type's "IEO" output. They assert this output only type's incoming High There register "Disable Lower Chain" (DLC) each channel; if/when channel's forced false/low. downward-pointing gate reflects functional shift daisy-chain during interrupt-acknowledge cycles. output High except during IACK cycles, which time allows asserted High only this type requesting interrupt. Finally, signal labelled "Drive Vector" controls when channel places interrupt vector data during interrupt acknowledge cycle. There register Vector (NV) each channel; NV=1 prevents driving vector. interface logic derives signal "IACK Read" from /RD, /PITACK combination R//W high. most cases IACK Read true during latter part time that /IACKcy true. channel provides vector AD7-0 while IACK Read true, types channel highest priority interrupting type. keep complexity reasonable, Figure doesn't include mechanism which content returned interrupt vector reflect identity channel's highest-priority interrupting type.
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INTERRUPT OPTION
Configuration Register (BCR) affects interrupt subsystem. This information also presented Chapter Interfacing. 2PulseIACK (Double-Pulse Interrupt Acknowledge; BCR1): software should program this /PITACK isn't used carries single pulse when host processor acknowledges interrupt, /PITACK carries pulses when host processor acknowledges interrupt. latter mode compatible with certain Intel processors.
INTERRUPT ACKNOWLEDGE CYCLES
doesn't require Interrupt Acknowledge cycles. system designer simply pull /SITACK /PITACK pins, software read Interrupt Pending (IP) bits Daisy Chain Control Register (DCCR), which described later sections. Even host processor does Interrupt Acknowledge cycles, doesn't have provide vector. high channel's Interrupt Control Register (ICR) channel sets highest priority interrupt then pending, does return interrupt vector. But, since most microprocessors today perform interrupt acknowledge cycles obtain 8-bit interrupt vector, rest this section will assume vectored interrupts. Figure shows interrupt acknowledge cycle that's signalled /SITACK, with multiplexed addresses data. (Actually there subcases this kind cycle, depending whether host processor uses signalling. Since timing same either strobe, Figure simply shows trace labelled "/DS /RD".) channel samples /SITACK rising edge /AS, "freezes" internal interrupt state; requesting interrupt forces output regardless state IEI, starts resolving internal interrupt priorities. pins part interrupt acknowledge daisy chain with other interrupting devices, this resolution occurs concert with interrupt logic other devices. must valid specified setup time before goes low. host CPU's strobe must delayed needed guarantee this. high channel requesting interrupt, responds setting highest requesting type interrupt, driving vector onto AD7-0 pins, driving /WAIT//RDY appropriately signal when vector valid. leading/falling edge /RD, and/or channel requesting interrupt, doesn't respond cycle.
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INTERRUPT ACKNOWLEDGE CYCLES (Continued)
AD15-AD0
(not used)
vector
/SITACK
/WAIT//RDY Wait) /WAIT//RDY Ack)
/INT
Figure 7-5. Interrupt Acknowledge Cycle signalled /SITACK, Multiplexed
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ZILOG Figure shows interrupt acknowledge cycle that's signalled /SITACK, with separate address data lines. before there subcases this kind cycle, depending whether host processor uses signalling. Since timing identical either strobe, Figure simply shows trace labelled "/DS /RD".) Here channel freezes internal interrupt state response falling edge /SITACK; again, requesting interrupt forces output regardless state IEI, starts resolving internal interrupt priorities.
Z16C30 USC® USER'S MANUAL this mode /SITACK must stay until after goes low, must valid specified setup time before goes low. (The falling edge have delayed guarantee this.) high channel requesting interrupt, responds setting highest priority requesting type interrupt, driving vector onto AD7-0 pins, driving /WAIT//RDY appropriately signal when vector valid. leading/falling edge /RD, and/or channel requesting interrupt, doesn't respond cycle.
AD15-AD0
vector
/SITACK
/WAIT//RDY Wait)
/WAIT//RDY Ack)
/INT
Figure 7-6. Interrupt Acknowledge Cycle signalled /SITACK, Non-Multiplexed
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INTERRUPT ACKNOWLEDGE CYCLES (Continued)
Figure shows kind interrupt acknowledge cycle that expects when /PITACK goes 2PulseIACK (BCR1) Here single pulse /PITACK substitutes pulse previous cases; latter signals must remain high throughout cycle. this case, operation nonmultiplexed identical with that multiplexed once strobe over. only distinction that multiplexed must meet minimum times between pulse /PITACK preceding following pulses /AS. These minima similar those required register read write cycles. this mode, interrupt acknowledge daisy chain IEI/IEO cannot used select whether channel another device should respond each interrupt acknowledge cycle. Instead, external logic like that shown Figure must decide which requesting device/channel respond interrupt acknowledge cycle, such cycle occurs when more than requesting interrupt. external logic would typically consider state individual devices'/channels' interrupt request lines making this decision. (The lines cannot OR-tied this case.) this "single-pulse" mode, must hold around leading/falling edge /PITACK. high channel requesting interrupt that point, responds /PITACK driving vector onto AD7-0 pins driving /WAIT//RDY appropriately signal when vector valid. leading/falling edge /PITACK, and/or channel requesting interrupt that point, doesn't respond cycle.
AD15-AD0
vector
/PITACK /WAIT//RDY Wait) /WAIT//RDY Ack) /INT
Figure 7-7. /PITACK Interrupt Acknowledge Cycle with 2PulseIACK=0
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ZILOG Figure shows kind interrupt acknowledge cycle that expects when /PITACK goes 2PulseIACK (BCR1) Here, consecutive pulses /PITACK constitute complete interrupt acknowledge cycle, should both stay high throughout cycle. This mode compatible with several microprocessors made Intel Corp. other companies. preceding case, operation similar whether multiplexed non-multiplexed. multiplexed must meet minimum times between pulses pulses /PITACK. These minima similar those between register read cycles. "double pulse mode" channel keeps internal state that distinguishes /PITACK pulses each pair. channel freezes internal interrupt state response first falling edge /PITACK. requesting
Z16C30 USC® USER'S MANUAL interrupt forces output regardless state IEI, starts resolving internal interrupt priorities, channel does otherwise respond first cycle. this mode must valid specified setup time before /PITACK goes second pulse. high this point channel requesting interrupt, responds second /PITACK pulse setting highest-priority requesting type interrupt, driving vector onto AD7-0 pins, driving /WAIT//RDY appropriately signal when vector valid. leading edge /PITACK, and/or channel requesting interrupt, doesn't respond cycle.
AD15-AD0
vector
/PITACK /WAIT//RDY Wait) /WAIT//RDY Ack) /INT
Figure 7-8. /PITACK Interrupt Acknowledge Cycle with 2PulseIACK=1
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7.10 INTERRUPT ACKNOWLEDGE READ CYCLES
Interrupt Acknowledge cycles similar cycles that occur when host processor reads register, which discussed Chapter However, user should note following ways which interrupt acknowledge cycles differ from read cycles:
When /WAIT//RDY carries Wait function, channel asserts during interrupt acknowledge cycles, never does during register Read Write cycles. When /WAIT//RDY carries Acknowledge function, channel asserts later Interrupt Acknowledge cycles than Reads. However, relationship between falling edge /WAIT //RDY validity data lines similar both kinds cycles.
multiplexed bus, /SITACK acts like address line. When samples /SITACK rising edge /AS, ignores address lines. non-multiplexed bus, each leading edge captures state /SITACK. With signalling, state R//W doesn't matter cycle which samples /SITACK low. other cycles R//W differentiates Read cycles from Writes.)
7.11 INTERRUPT TYPES
Each channel includes types interrupts, arranged internal interrupt daisy chain following priority order: Receive Status (highest priority) Receive Data Transmit Status Transmit Data Miscellaneous (lowest priority) IdleRcved when this (RCSR6) goes from because receiver seen consecutive bits. asynchronous modes with clocking, receiver sets RCSR6 after time less, this source's shouldn't such modes. when this (RCSR5) goes from because Receiver detected Break condition asynchronous mode Abort condition HDLC/SDLC mode. this source interrupt logic sets when software Receive channel reads character from RxFIFO that's marked with RxBound status. Such marking reflects address character Nine-Bit mode, negation /DCD during character external sync mode, last character frame HDLC/SDLC 802.3 modes, five block terminating characters Transparent Bisync mode.
Break/Abort
Each these types each bit, described earlier section this chapter.
7.11.1 Receive Status Interrupt Sources Bits
interrupt sources channel's Receive Status bit. Software read status each source LSByte Receive Command/Status Register (RCSR), which shown Figure 7-9. following descriptions RCSR status bits similar those 'Detailed Status RCSR' section Chapter ExitedHunt when this (RCSR7) goes from because receiver detected Sync Flag sequence synchronous mode.
RxBound
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ZILOG Abort/PE this source interrupt logic sets when software Receive channel reads character from RxFIFO that failed parity checking, HDLC/SDLC mode with QAbort (RMR8) set, character that followed Abort sequence. RxOver
Z16C30 USC® USER'S MANUAL this source interrupt logic sets when software Receive channel reads character from RxFIFO that's marked with Overrun status. character marked first that arrived while FIFO full. indeterminate number characters after have been lost. `Handling Overruns Underruns' Chapter more information.
RCmd(WO) 2ndBE 1stBE RxResidue
ShortF/ Exited CVType Hunt
Idle Rcved
Break /Abort
Bound
CRCE
Abort
Over
Avail
Figure 7-9. Receive Command/Status Register (RCSR)
"RxFIFO fill level" last RCSR 15-12 command level" last RCSR 15-12 command level" last RCSR 15-12 command
Idle Exited Rcved Hunt
Break /Abort
Bound
Word Status
Abort
RXOver TCOR
Figure 7-10. Receive Interrupt Control Register (RICR)
described Chapter once Interrupt-Armed RCSR been set, must "unlatched" writing that position RCSR. Exited Hunt, Abort HDLC mode), RxBound, Abort/PE, RxOver, this action also clears RCSR bit. IdleRcved Break/Abort async modes) bits RCSR don't become until software unlatched line condition ended. Each these sources separate Interrupt (IA) LSByte Receive Interrupt Control Register (RICR). Figure 7-10 shows RICR. interrupt logic Receive Status described above. corresponding RCSR effect thus will cause interrupts. setting bits ExitedHunt, IdleRcved, Break/Abort conditions effect bits RCSR, while bits RxBound, Abort/ Overrun conditions affect corresponding RCSR bits operate, described Chapter order ensure that future interrupts requested properly when more than Receive Status condition Armed RICR, Receive Status interrupt service routine must clear bits RICR then desired ones again, after cleared RCSR bits that serviced.
When software wants change bits RICR after register first initialized, should write only byte register rather than bits, avoid inadvertently changing threshold setting byte.
7.11.2 Receive Data Interrupts
This interrupt type only source, there's interrupt logic sets when character received number previously-received characters RxFIFO equal number programmed "Receive Data Interrupt Request Level". That character that makes number characters RxFIFO exceed programmed value. also number characters less than programmed threshold level, receiver places character marked with RxBound status RxFIFO. received data handled either software polling external Receive channel, disable Receive Data interrupt leaving later section discusses bits.)
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7.11.2 Receive Data Interrupts (Continued)
program Receive Data Interrupt Request Level, first write "Select RICRHi=/INT Level" command RCmd field Receive Command/Status Register (RCSR15-12). Then write number received characters which channel should start requesting Receive Data interrupt, minus one, MSByte Receive Interrupt Control Register (RICR). example, channel should request Receive Data interrupt when 32-byte RxFIFO becomes full, write RCSR158, then write decimal (hex RICR15-8. good programming practice follow these steps with writing "Select RICRHi=FIFO Status" command RCSR, protect Request Level from inadvertent modification when other parts software change bits RICR. Code that writes reads Receive Data Interrupt Request threshold must ensure that interrupts will occur between time writes "Select RICRHi=/INT Level" command RCSR, when writes reads value RICR, such interrupts lead other code writing different Select command (for FIFO Fill level request threshold) RCSR. Figure 7-11 shows sample service routine Receive Data interrupts. While it's particularly fancy efficient, does illustrate several important points: reads FIFO fill level determine many characters read. fact, that reception RxBound character (i.e., last character frame, message, Receive Data bit, means that Receive Data interrupt service routine can't blindly read number characters implied Interrupt Request Level. explicitly clears Receive Data bits writing Daisy Chain Control Register (DCCR) described later section. Neither affected reading data from RxFIFO. re-reads FIFO fill level after clearing bit, processes characters that have been received while processing earlier characters. This procedure guards against losing interrupt associated with late-arriving Frame (RxBound) character. reads status from RCSR "before" reading each character, reads RCSR extra time after reading Frame (RxBound) character, clear latching status that occurs when RxBound character read out. (This only handle RxBound checking. Another enable Receive Status interrupt when Receive Data interrupt service routine reads RxBound character RxFIFO, check RxBound status this routine all. Software that uses this method must ensure that Receive Status interrupt interrupt Receive Data "nested" fashion.)
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Start: Interrupt with Vector Data"
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NECESSARY, write 0101 RCmd (RCSR15-12)
Read FIFO count RICR15-8
CT=0?
Clear (write 9016 DCCR7-0)
Read FIFO count RICR15-8
Read Status from RCSR. Handle bits other than RxBound required.
CT=0?
Read store last byte/word from RDR. Decrement accordingly
Frame? RxBound (RCSR4) Read store byte word from RDR. Decrement accordingly
Clear (write 9016 DCCR15-8)
Read RCSR15-8 RCSR15-0, clear latched status
Return from Interrupt
Perform Frame processing (switch buffers etc.)
Figure 7-11. Sample Service Routine Receive Data Interrupts
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7.11.2 Receive Data Interrupts (Continued)
Sent Idle Sent Abort Sent EOF/ Sent Sent Sent Under Empty
TCmd
Rsrvd
Txidle
Figure 7-12. Transmit Command/Status Register (TCSR)
Idle Sent Abort Sent Sent Under
"TxFIFOStatus" last TCSR 15-12 command level" last RCSR 15-12 command level" last TCSR 15-12 command
Sent
EOF/ Sent
Wait2 Send
TC1R
Figure 7-13. Transmit Interrupt Control Register (TICR)
7.11.3 Transmit Status Interrupt Sources Bits
interrupt logic Transmit Status response interrupt sources. Software read status each source LSByte Transmit Command/Status Register (TCSR), which shown Figure 7-12. following descriptions TCSR bits similar those 'Detailed Status TCSR' section Chapter PreSent interrupt logic when this (TCSR7) goes from because transmitter finished sending "Preamble" selected Channel Control Register (CCR11-8) synchronous mode. interrupt logic when this (TCSR6) goes from because transmitter sent idle line state selected TxIdle field (TCSR10-8). TxIdle TxMode specify condition Flags Syncs, this each sent. Otherwise, bit-oriented Idle conditions, it's only after first sent. interrupt logic HDLC/SDLC mode, when this (TCSR5) goes from because transmitter sent Abort character.
EOF/EOM Sent
interrupt logic synchronous mode, when this (TCSR4) goes from because transmitter sent closing Flag Sync character message frame. interrupt logic sync mode, when this (TCSR3) goes from because transmitter sent sequence just before message frame. interrupt logic when this (TCSR1) goes from because transmitter needed character from TxFIFO empty.
CRCSent
TxUnder
IdleSent
Once these TCSR bits must cleared writing that position TCSR. order ensure that future interrupts requested properly when more than Transmit Status condition Armed TICR, Transmit Status interrupt service routine must clear bits TICR then desired ones again, after cleared TCSR bits that serviced. Each these sources separate Interrupt (IA) LSByte Transmit Interrupt Control Register (TICR). Figure 7-13 shows TICR. interrupt logic sets Transmit Status when
AbortSent
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ZILOG corresponding Transmit Command/Status Register (TCSR) goes from corresponding TCSR effect thus will cause interrupts. setting bits TICR direct effect TCSR bits. When software wants change bits TICR after register first initialized, should write only byte register rather than bits, avoid inadvertently changing threshold setting byte.
Z16C30 USC® USER'S MANUAL good programming practice follow these steps with writing "Select TICRHi=FIFO Status" command TCSR, protect Request Level from inadvertent modification when other parts software change bits TICR. Code that writes reads Transmit Data Interrupt Request threshold must ensure that interrupt will occur between time writes "Select TICRHi=/INT Level" command TCSR, when writes reads value TICR, such interrupts lead other code writing different Select command (for FIFO Fill level request threshold) TCSR. Note that Purge FIFO Purge FIFO) command will typically make channel immediately Transmit Data bit. This will, turn, make channel start requesting interrupt /INT
7.11.4 Transmit Data Interrupts
This interrupt type only source, there's need interrupt logic sets Transmit Data whenever number empty character positions TxFIFO greater than number programmed "Transmit Data Interrupt Request Level". transmitted data handled external Transmit channel, disable this interrupt leaving later section discusses bits.) program Transmit Data Interrupt Request Level, first write "Select TICRHi=/INT Level" command 0110) TCmd field Transmit Command Status Register (TCSR15-12). Then write number empty character positions which channel should start requesting Transmit Data interrupt, minus one, MSByte Transmit Interrupt Control Register (TICR). example, channel should request Transmit Data interrupt when 32-byte TxFIFO only four characters left write TCSR15-8, then write decimal (hex TICRI5-8.
hadn't been doing channel's high, bits higher-priority bits
with interrupts, Transmit Data interrupt service routine must explicitly clear Transmit Data bits writing Daisy Chain Control Register (DCCR) described later; bits aren't cleared simply writing data into TxFIFO.
RxCDn RxCUp TxCDn TxCUp RxRDn RxRUp TxRDn TxRUp DCDDn DCDUp CTSDn CTSUp Under
DPLL DSync
BRG1
BRG0
Figure 7-14. Status Interrupt Control Register (SICR)
RxCL/U
/RxC
TxCL/U
/TxC
RxRL/U /RxREQ TxRL/U /TxREQ DCDL/U
/DCD
CTSL/U
/CTS
Under
DPLL DSync
BRG1
BRG0
Figure 7-15. Miscellaneous Interrupt Status Register (MISR)
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7.11.5 Interrupt Sources Bits
interrupt logic response rising and/or falling edges pins each channel, namely /RxC, /TxC, /RxREQ, /TxREQ, /DCD, /CTS. following description similar that 'Edge Detection Interrupts' section Chapter Software program channel detect rising and/or falling edges /CTS, /DCD, /TxC, /RxC, /TxREQ, /RxREQ pins, interrupt when such events occur. Figure 7-14 shows that Status Interrupt Control Register (SICR) includes separate Interrupt (IA) bits rising falling edges each these pins. these bits makes channel detect that kind edge, while makes ignore such edges. This edge detection interrupt mechanism operates without regard whether various pins programmed inputs outputs Control Register (IOCR). When channel detects edge that's enabled SICR, records event internal latch that's directly accessible USC's register map. Instead, shown Figure 7-15, Miscellaneous Interrupt Status Register (MISR) includes bits each these pins, called "Latched/Unlatch" bit, other being "data bit" that same name itself. hardware software Reset sequence clears bits zero. While associated data reports tracks state "transparent" fashion, with indicating indicating high. Whenever pin's internal edgedetecting latch set, channel sets clears detection latch, sets bit. read cleared (and necessary set) Daisy Chain Control Register (DCCR1). While state associated data frozen (latched). These bits remain this state, regardless further transitions pin, until software writes bit. This clears "opens" data once again report track state pin, least "instant". more enabled transitions occurred while set, then again right after software writes Writing effect; doesn't matter what value software writes "data" bits.
7.11.6 Miscellaneous Interrupt Sources Bits
interrupt logic Miscellaneous response four interrupt sources. Software read status these sources LSByte Miscellaneous Interrupt Status Register (MISR), which shown Figure 7-15. following descriptions repeat some information that presented Chapters RCCUnder RCCUnder channel sets this (MISR3) Misc receiver decremented Receive Character Counter (RCC) zero then receives another character same frame/message). DPLLDSync channel sets this (MISR2) Misc software Digital Phase Locked Loop circuit Biphase encoding DPLL detects consecutive missing clocks, indicating loss synchronization. BRG1 channel sets this (MISR1) Misc when Baud Rate Generator counts down zero. BRG0 channel sets this (MISR0) Misc when Baud Rate Generator counts down zero.
DPLLDSync
BRG1
BRG0
Once these bits software must write that position "unlatch" Writing MISR3-0 clears "read-side" unless setting event recurred while latched, which case again immediately. Each these four sources separate Interrupt (IA) LSByte Status Interrupt Control Register (SICR). Figure 7-14 shows SICR. interrupt logic sets corresponding MISR, Miscellaneous bit, when indicated condition occurs. logic won't corresponding MISR thus associated condition can't cause interrupts. Clearing does clear corresponding MISR.
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7.12 INTERRUPT PENDING UNDER SERVICE BITS
Software read, set, clear Interrupt Pending (IP) Interrupt Under Service (IUS) bits, interrupt types channel, Daisy-Chain Control Register (DCCR). Figure 7-16 shows DCCR. MSByte deals only with bits, while LSByte deals with bits used clear bits step. Software read bits from DCCR13-8 bits from DCCR5-0. MSBits each byte always read When software writes DCCR, MSBits each byte represent command that applied type(s) selected ones written LSBits that byte. DCCR15-14 field that channel interprets follows: Operation operation Clear bit(s) type(s) selected DCCR13-8 bit(s) type(s) selected DCCR13-8 "clear both" option seems efficient, general useful only during initialization sequences. later section "Software Requirements" describes interrupt service routine should clear before examining device status, should delay clearing until (nearly) over. software writes both bytes DCCR simultaneously 16-bit bus, command "set", command "clear both", particular type selected ones both MSByte LSByte, channel clears that type. other hand, command says "set" type LSbyte says "clear both" that type's DDCR5-0 channel sets that type's bit. addition, encoded commands that written Channel Command/Address Register (CCAR) allows general exit from interrupt service routine, regardless which type initiated routine. software writes Reset Highest command (00010) channel's RTCmd field (CCAR15-11), clears highestpriority that's channel.
DCCR7-6 field that channel interprets follows: Operation operation Clear both bit(s) type(s) selected DCCR5-0 Clear bit(s) type(s) selected DCCR5-0 bit(s) type(s) selected DCCR5-0
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7.13 INTERRUPT ENABLE BITS
Software read, set, clear Interrupt Enable (IE) bits interrupt types channel, LSByte Interrupt Control Register (ICR). Figure 7-17 shows ICR. Software read bits from ICR50; ICR7-6 always read When software writes LSByte ICR, field (ICR7-6) comprises command that channel applies bits selected ones written ICR5-0. channel interprets follows: Operation operation Clear bit(s) type(s) selected ICR5-0 bit(s) type(s) selected ICR5-0
7.14 CHANNEL INTERRUPT OPTIONS
Figure 7-17 shows that MSByte Interrupt Control Register (ICR) contains control bits that apply interrupts from channel. These bits fully under software control read written time. Master Interrupt Enable (MIE; ICR15) must allow channel request interrupt /INT pin. Whenever Disable Lower Chain (DLC; ICR14) channel forces output low, that devices further down daisy chain can't request interrupts respond interrupt acknowledge cycles. Vector (NV; ICR13) channel neither provides vector drives /WAIT//RDY during interrupt acknowledge cycle which highest-priority requesting type channel. However, such case channel still sets highest-priority requesting type.
IUSCmd (WO)
Misc IUSC
IPCmd (WO)
Misc
Figure 7-16. Daisy Chain Control Register (DCCR)
Rsrvd
IECmd (WO)
Misc
Figure 7-17. Interrupt Control Register (ICR)
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ZILOG Vector Includes Status field (VIS; ICR12-9) controls whether vector, that channel returns during interrupt acknowledge cycle which highest-priority requesting type channel, identifies type not. Such vector modification enabled types channel, only those above selected priority level: 0xxx 100x 1010 1011 1100 1101 1110 1111 Which types appear vectors types types above (not Misc) Transmit Data above Transmit Status above Receive Data Status Receive Status only types
Z16C30 USC® USER'S MANUAL contents allow highest-priority type, that's requesting time Interrupt Acknowledge cycle, modify interrupt vector, then bits returned vector identify that type described next section. not, channel returns 8-bit vector exactly host software programmed
7.15 INTERRUPT VECTORS
Software read write channel's interrupt vector information Interrupt Vector Register (IVR). This register also basis vector that channel returns during interrupt acknowledge cycle which highest priority requesting type channel. Figure 7-18 shows IVR. basic vector written read LSByte; software read modified version vector MSByte. (Writing MSByte effect.) Bits 15-12 image those corresponding bits LSByte, while TypeCode field (IVR11-9) gives identity highest priority interrupt type that (the state doesn't matter). TypeCode Meaning interrupt pending Miscellaneous Transmit Data Transmit Status Receive Data Receive Status (will read) state field (ICR12-9) effect reading IVR. simply controls channel decides whether return IVR15-8 IVR7-0 interrupt vector when responds interrupt acknowledge cycle.
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7.15 INTERRUPT VECTORS (Continued)
Interrupt Vector (RO) TypeCode (RO) (RO) Interrupt Vector (RW)
Figure 7-18. Interrupt Vector Register (IVR)
7.16 SOFTWARE REQUIREMENTS
This chapter having described features functions that relate interrupts, this final section will describe these features should used interrupt service routines. there's heavy interrupt traffic, wherein stack gets filled with multiple copies saved registers because another interrupt same type happens soon cleared.
7.16.1 Nested Interrupts
important characteristic interrupt-driven systems whether they allow nested interrupts, that whether they allow interrupt service routines (ISRs) themselves interrupted, whether each proceeds completion before another interrupt occur. supports nested interrupts including Interrupt Under Service (IUS) latch each type interrupt. When channel that's requesting interrupt sees interrupt acknowledge cycle high, automatically sets latch highest priority type that set. interrupt acknowledge cycles visible USC, software still allow nested interrupts reading bits from LSbyte DCCR, explicitly setting latch highest priority type that set, MSbyte same register. Regardless whether automatically explicitly software, once it's re-enable processor interrupts allow other interrupts. channel question will request another interrupt same type lower-priority type within until software clears near ISR. Interrupts from other devices controlled automatically devices arranged interrupt daisy-chain; otherwise central interrupt controller must control which devices interrupt which ISRs. re-enables interrupts allow nested interrupts from higher-priority types, it's good practice disable them once again, just before clearing near ISR. (They will enabled again standard mechanism processor being used, e.g., IRET RETI instruction, after saved registers restored from stack.) This procedure prevents "tail recursion" when
7.16.2 Which Type(s) Handle?
interrupt service routine (ISR) initiated interrupt acknowledge cycle that obtains vector from USC, "Vector Incudes Status" option enabled, service routine typically concerns itself only with type identified vector, returns from interrupt after handling that single type. Otherwise software should read Interrupt Pending bits Daisy Chain Control Register (DCCR) which type(s) need service. This particularly necessary IBM-type Personal Computers, which interrupt acknowledge cycles aren't visible add-in peripherals. more than DCCR, handle only most urgent type return from interrupt thereafter, like "Vector Includes Status" ISR. Alternatively choose handle types that have their bits set, before returning interrupted process. Without nested interrupts, worst-case interrupt response considerations limit each handling just type interrupt before re-enabling interrupts returning interrupted process. This allows interrupt prioritizing mechanism select which interrupt handle next. nested interrupts occur, it's more feasible handle pending types within device before returning interrupted process, because higherpriority ISRs will able while it's doing
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Z16C30 USC® USER'S MANUAL Typically, wants read fill level from RICR, read number times indicated that value. HDLC similar modes, because "RD" interrupt occurs frame well when fill level reaches Request Level, software can't blindly read number characters Request Level. 16-bit minimum Request Level (meaning interrupt when characters have been received). such system it's software read only pairs characters leave last (unpaired) character handled next interrupt. exception that HDLC similar modes, gets fill level from first read RICR, available character must last frame, such should read individually. Request level serial rate high, might happen that enough characters arrive while software reading number indicated initial read from RICR, that number characters RxFIFO never falls below Request Level. This particularly possible Request Level (meaning interrupt when empty slots) software only reads character pairs from RDR. this happen, after software finishes reading each block data, should read RICR again, read more data from needed, ensure that future Data interrupts will occur. HDLC similar modes, software will want know where frames end. 16-bit bus, oldest character RxFIFO last frame, software tries read characters from RDR, only removes oldest character from RxFIFO. routine handling Receive Data interrupts determine frame/message boundaries ways: Read RCSR after each read from RDR. 1stBE 2ndBE RxBound set, previous read included last character frame. this case, 1stBE then last read yielded only character, else included characters. Enable nested interrupts have Status ISR, when sees RxBound condition, something affect operation RxData when resumes. This tricky sort thing that help make life programmer interesting.
7.16.3 Handling Type
process handling single type interrupt same regardless whether overall handles only highest priority pending type, pending types within device. necessary steps vary various types USC. following descriptions don't attempt cover everything that each type should only minimum requirements needed keep interrupt subsystem operating correctly. Receive Status Transmit Status Type Write DCCR clear bit. Read RCSR TCSR handle indicated conditions appropriately. After conditions have been handled, write byte LSbyte RCSR TCSR, that each status that handled armed corresponding RICR TICR. This clears/unlatches these status bits. Write zero byte LSbyte RICR TICR, which disarms sources/status bits. Write byte same LSbyte, re-arm those sources/status bits that should armed future. Steps needed only these types, ensure that another interrupt will occur hardware sets armed sources/status bits after step bits otherwise left ISR. Miscellaneous Type Write DCCR clear bit. Read MISR handle indicated conditions appropriately. After conditions have been handled, write byte LSbyte MISR, that each "L/U" that handled armed corresponding SICR. This clears/unlatches these status bits. course, software want write ones other bits well, such those unarmed conditions.) Receive Data Type Write DCCR clear bit. Read often enough bring fill level below Data Interrupt Request Level" RICR. Under some conditions, writing Purge FIFO command CCAR would eliminate need read TDR.
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Z16C30 USC® USER'S MANUAL hardware automatically tags character that corresponds decrementing from After this character goes through TxFIFO onto link, Transmitter finishes frame, typically sending closing Flag. Software either read lengthtracking mechanism, know when each frame ends thus when write TCLR again. Using 32-bit TCBs: Before start first frame after Reset, software write Purge TxFIFO Load command CCAR, make expect first TCB. (For subsequent frames this step isn't necessary.) start each frame software should write 32bit TDR, which last bits number data characters frame. 16-bit after software written enough characters decrement down 0001, software writes bits TDR, will only place single character from AD7-0 pins into TxFIFO, ignoring character D15-8. Little-Endian (Intel-type) system this BigEndian (Motorola-type) system software avoid problems either copying last character each frame into next-higher byte location after memory buffer, writing last byte frame using byte write operation. hardware automatically tags character that corresponds decrementing from After this character goes through TxFIFO onto link, Transmitter finishes frame, typically sending closing Flag.
7.16.3 Handling Type (Continued)
Transmit Data Type Write DCCR clear Write often enough bring number empty bytes TxFIFO below Data Interrupt Request Level" TICR. Write (TCSR and) TICR with smaller Request Level, accomplish same purpose. Write disable Transmit Data interrupt. Typically wants read fill level from TICR write enough times fill TxFIFO, write enough character pairs fill except empty position. there isn't enough data available this, might want change Request Level (hex that next Transmit Data interrupt will occur when FIFO empty, then write available characters TDR. Request level serial rate high, might happen that Transmitter takes enough characters TxFIFO while software writing number indicated initial read from TICR, that number empty slots never falls below Request Level. This particularly possible Request Level (meaning interrupt when empty slots) software only writes character pairs TDR. this situation happen, after software finishes writing block data TDR, should read TICR again time write more data needed, ensure that future Data interrupts will occur. HDLC similar modes, part that handles Data interrupts typically needs take special actions each frame. this with without using Transmit Character Counter (TCC), either directly means 32-bit Transmit Control Block (TCB) feature. Using directly: start each frame software should load TCLR with number data characters frame/ message, then write Load command CCAR. 16-bit after software written enough characters decrement down 0001, software writes bits TDR, will only place single character from AD7-0 pins into TxFIFO, ignoring character D15-8. Little-Endian (Intel-type) system this BigEndian (Motorola-type) system software avoid problems either copying last character each frame into next-higher byte location after memory buffer, writing last byte frame using byte write operation.
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ZILOG using TCC: Software doesn't need anything special start frame, other than initialize frame-length-tracking mechanism. While writing frame 16-bit bus, there characters left frame, software must write second-last character LSbyte using byte write operation. Before writing last character frame LSbyte TDR, software should write EOF/ command MSbyte TCSR. After last character goes through TxFIFO onto link, Transmitter finishes frame, typically sending closing Flag.
Z16C30 USC® USER'S MANUAL
7.16.4 Exiting
interrupt acknowledge cycle explicitly software, then after handled more interrupt types described above, must clear that set. nested interrupts were enabled, it's good practice first disable interrupts again, avoid filling stack with multiple copies saved registers, case another interrupt same type happens right after cleared. normal mechanism provided processor ending ISR, e.g., IRET RETI instruction, will then re-enable interrupts after saved registers such restored from stack.) Software clear writing MSbyte DCCR, writing "Reset Highest IUS" command MSbyte CCAR. latter method more general than former.
1997 Zilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold Zilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale only. Zilog, Inc. makes warranty, express, statutory, implied description, regarding information forth herein regarding freedom described devices from intellectual property infringement. Zilog, Inc. makes warranty merchantability fitness purpose. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Zilog's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between customer Zilog prior use. Life support devices systems those which intended surgical implantation into body, which sustains life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 370-8056 Internet: http://www.zilog.com
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