Xilinx XAPP987 Single-Event Upset Mitigation Selection Guide application note

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Xilinx XAPP987 Single-Event Upset Mitigation Selection Guide application note

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Single-Event Upset Mitigation Selection Guide
Author: Brendan Bridgford, Carl Carmichael, Chen Tseng
XAPP987 (v1.0) March 2008
Summary
This application note discusses different aspects single-event upsets recommends appropriate mitigation schemes under each circumstance. concept constrained device family. Furthermore, this document provides guidelines choose most costeffective mitigation scheme.
Introduction
When designing in-orbit, space-based, extra-terrestrial applications hostile radiation environments, users must consider effects charged particles such heavy ions protons. these charged particles travel through FPGA (Figure they alter logic state static memory element, resulting single-event upsets (SEUs). configuration memory array have adverse effect expected FPGA functionality. Note: Static upset configuration memory synonymous with functional error. Depending
application requirement cost constraints, different mitigation should deployed.
X-Ref Target Figure
Cosmic
n-Substrate
p-Well
X987_01_080707
Figure
FPGA
Glossary
Some common terminology used throughout this document defined this section.
Cross Section
statistical representation sensitivity certain single-event effect represented relative area (cm2).
Device
single integrated circuit.
Failure
unrecoverable error.
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XAPP987 (v1.0) March 2008
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Glossary
Functional Error
logic error user function.
Functional Interrupt
disruption device operation requiring system level intervention regain normal functionality. Typically causes loss user system data.
Functional Disturbance
self-recovering disruption device operation that causes loss user system data.
Logic Error
Incorrect state signal transition.
Multiple-Bit Upset (MBU)
that results more than adjacent bits flipping oblique angle strike. probability steadily increases geometries shrink. maximum distance observed useful determine block interleaving required that even MBUs able corrected ECC.
Single-Bit Upset (SBU)
Same SEU.
Scrubbing
process correcting configuration cell upsets through FPGA partial reconfiguration. Scrubbing does interrupt user design function.
Single-Event Effect (SEE)
resulting electrical disturbances caused direct ionization silicon lattice energetic charged subatomic particle.
Single-Event Functional Interrupt (SEFI)
that results interference normal operation complex digital circuit. SEFI typically used indicate failure support circuit, such loss configuration capability, power reset, JTAG functionality, region configuration memory, entire configuration.
Single-Event Transient (SET)
signal transition caused SEE. Often observed glitch.
Single-Event Upset (SEU)
state change flip) single data storage memory cell caused SEE. affect configuration memory cell states, block contents, DFF, LUTRAM, SRL16 memory cell (which also configuration memory cells, directly accessible user).
System
integration multiple devices circuit boards modular sub-systems.
User Function
User-specified operational functions defined data stored device configuration memory.
XAPP987 (v1.0) March 2008
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Application Analysis Requirement
Application Analysis Requirement
Designing robust system against SEUs costly. Application radiation-tolerance requirements dramatically impact mitigation methods. FPGA deployed missioncritical applications harsh environment, mitigation scheme should involve redundant FPGAs with configuration management. contrary, application, such image capture, fault tolerant while operating window small, mitigation might necessary. Before selecting mitigation scheme, important answer following questions: application error tolerant? What expected operating time window? What FPGA performance requirement? What FPGA power requirement? cost sensitive application? application withstand possible FPGA downtime? does SEFI cross section specified data sheet meet application requirement?
Trade-offs between these application requirements dictate mitigation scheme. Figure provides overview mitigation scheme selection based application environmental needs. Note: matrix Figure does account power consumption design performance analysis. more detailed discussion each mitigation scheme follows "Mitigation Schemes."
X-Ref Target Figure
Data Criticality Error Persistence Minutes Operating Window Days Months Continuous
Mitigation XHigh
Rate
Scrubbing
Scrubbing XRedundant Devices
High
X987_02_051007
Figure
Mitigation Scheme Matrix
Table shows example error rates XQR2V6000CF1144V geosynchronous orbit (Solar Quiet conditions) configuration memory, block memory, SEFIs. Table Error Rates XQR2V6000(CREME96)
XRR2V6000 36,000 Configuration Memory Block Memory POR-SEFI SMAP-SEFI Mean Time Error 11.8 Units Hours Hours Years Years
XAPP987 (v1.0) March 2008
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Mitigation Schemes
error rates modeled Poisson process (Figure example, expected upset rate four events hour, possible that FPGA experiences upsets (1.8% chance), upsets chance) hour. Therefore, configuration mitigation rate least times expected upset rate, probability upset accumulation minimized.
X-Ref Target Figure
X987_03_031208
Figure
Rate Modeled Poisson Process
Mitigation Schemes
Power-Cycling Only
time FPGA power-cycled, contents refreshed. Therefore, power-cycling essentially simplest form scrubbing. Fault-tolerant applications radiation environments should consider this scheme. Bear mind that approximately every eight configuration bits routing bits. fully utilized FPGA, less than routing bits used. Therefore, even FPGA experiences SEU, likely have impact design.
Configuration Management (Advanced Scrubbing)
Upsets Xilinx FPGAs removed reconfiguring affected configuration bits. This process correcting SEUs referred scrubbing. Configuration management advanced scrubbing) serves purpose detecting correcting SEUs FPGA. Configuration management hosted radiation-hardened FGPA, CPU, ASIC, FPGA itself. most cases, configuration management implemented conjunction with Xilinx Triple Module Redundancy (XTMR) redundant FPGA mitigation schemes. Configuration management detect correct design alterations caused SEUs; however, cannot mitigate effects caused SEUs. mitigate these effects design, implementation triplicated logic devices must deployed. Many flavors configuration management exist. Different algorithms implemented performance resource utilization reasons. main functions configuration management include correction, SEFI detection, SEFI mitigation.
XAPP987 (v1.0) March 2008
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Mitigation Schemes more details Virtexand Virtex-E configuration management, refer XAPP216, Correcting Single-Event Upsets Through Virtex Partial Configuration.
more details Virtex-2 configuration management, refer XAPP779, Correcting SingleEvent Upsets Virtex-II Platform FPGA Configuration Memory. more details Virtex-4 configuration management, refer XAPP988, Correcting Single-Event Upsets Virtex-4 Platform FPGA Configuration Memory (available under nondisclosure agreement). Although configuration management typically hosted radiation-hardened device, possible shift most these functions back FPGA, leaving radiation-hardened device other functions. This option advantage guaranteeing implementation latest Xilinx-endorsed configuration management algorithm without need respin board. more details self-hosting configuration management, refer XAPP989, Correcting Single-Event Upsets Xilinx FPGAs with Self-Hosting Configuration Management Core.
Xilinx Triple Module Redundancy (XTMR)
Xilinx provides software tool, TMRTool, simplify task design triplication. TMRTool partially fully triplicate design, insert voters, synchronize feedback path loops, allow customized user-triplicated module insertion. triplicated design mitigates impacts user design. However, design single device still vulnerable SEFI. design also consumes more power suffer design performance hit. example, system clock frequencies over Virtex-II device might difficult achieve. Some other design considerations such board layout complexity, signal integrity analysis, asynchronous applications documented TMRTool user guide which obtained with evaluation TMRTool. more information regarding TMRTool, refer TMRTool product page:
Redundant Devices
Implementation configuration management duplicating design multiple FPGAs with voting outputs FPGAs provides most robust mitigation scheme. wide variation implementation exists, ranging from two, three more FPGAs. dual FPGA implementation (Figure each FPGA should host copies same design. outputs then voted radiation hardened device. output differs from other three, voter should ignore outputs from failing FPGA re-synchronizes with other FPGA. remaining FPGA mismatched outputs, data should then discarded system resets both FPGAs. three-plus FPGAs implementations (Figure each FPGA holds same design outputs voted hardened device. Four more FPGA implementations, voting done three FPGA outputs while other FPGAs stand reserve. three primary FPGAs down, reserve replaces failing FPGA while failing FPGA comes back online sync with other FPGAs. This scheme work well long there still matching FPGA outputs. Designing applications with redundant-device mitigation challenging. FPGA temporary dysfunctional, bringing failing device back sync with other FPGAs might require some thoughtful design considerations. approach designate reset stage design. application returns reset state either routinely when detects FPGA SEFI.
XAPP987 (v1.0) March 2008
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Mitigation Schemes
X-Ref Target Figure
Xilinx FPGA
User Design User Design (Duplicate)
Xilinx FPGA
User Design (Duplicate) User Design (Duplicate)
RadiationHardened Voter Device
X987_04_031707
Figure
X-Ref Target Figure
Dual FPGAs implementation
Xilinx FPGA
User Design
Xilinx FPGA
User Design (Duplicate) RadiationHardened Voter Device
Xilinx FPGA
User Design (Duplicate)
X987_05_031707
Figure
Three FPGA Implementation
also feasible employ board-level hard-wire voting scheme. hard-wire voting scheme, traces outputs converge board create voting scheme. this scheme, output standard strength must carefully selected ensure outputs override disagreeing output while downstream device correctly recognize logic level. This scheme requires intensive IBIS simulation board layout planning such trace length, termination resistors, etc., eliminate reflection protect signal integrity.
XAPP987 (v1.0) March 2008
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Conclusion
Selecting Mitigation Schemes
previously discussed, some mitigation schemes compliment each other. example, configuration management usually addition XTMR redundant-device schemes. Configuration management ensures design integrity while XTMR redundant devices mitigate design impacts. successful implementation XTMR with scrubbing lowers design's failure cross-section SEFI cross-section. Table Performance Overview Mitigation Schemes
Mitigation Scheme Mitigation Strength Weak Medium Medium Strong Strongest Board Layout Complexity High High Medium Ease Meeting Timing Constraints Normal Reduced Normal Reduced Normal Power Consumption Typical typical Typical Typical 2~4X typical Component Cost Medium Medium High
mitigation (power cycling) XTMR Configuration management (scrubbing) XTMR Configuration management Redundant devices configuration management
Conclusion
Although FPGA vulnerable SEUs hostile environments, Xilinx provides various software tools documentations mitigation techniques. Numerous mitigation schemes available; each with strengths weakness. Selecting most appropriate mitigation scheme ensures mission success while minimizing system cost.
Revision History
following table shows revision history this document.
Date 03/18/08 Version Initial Xilinx release. Revision
Notice Disclaimer
Xilinx disclosing this Application Note "AS-IS" with warranty kind. This Application Note possible implementation this feature, application, standard, subject change without further notice from Xilinx. responsible obtaining rights require connection with your implementation this Application Note. XILINX MAKES REPRESENTATIONS WARRANTIES, WHETHER EXPRESS IMPLIED, STATUTORY OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES MERCHANTABILITY, NONINFRINGEMENT, FITNESS PARTICULAR PURPOSE. EVENT WILL XILINX LIABLE LOSS DATA, LOST PROFITS, SPECIAL, INCIDENTAL, CONSEQUENTIAL, INDIRECT DAMAGES ARISING FROM YOUR THIS APPLICATION NOTE.
XAPP987 (v1.0) March 2008
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Xilinx XAPP987 Single-Event Upset Mitigation Selection Guide application note

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