XRT72L50
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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
GENERAL DESCRIPTION
XRT72L50, single Channel DS3/E3 Framer designed accept user data from Terminal Equipment insert this data into payload bitfields within outbound DS3/E3 Data Stream. Further, Framer also designed receive inbound DS3/E3 Data Stream from Remote Terminal Equipment extract user data. XRT72L50 DS3/E3 Framer device designed support full-duplex data flow between Terminal Equipment (Line Interface Unit) Framer Device will transmit, receive process data DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 E3ITU-T G.832 Framing Formats. XRT72L50 DS3/E3 Framer consists Transmit section, Receiver section, Performance Monitor Section Microprocessor interface. Transmit Section includes Transmit Payload Data Input Interface, Transmit Overhead data Input Interface Section, Transmit HDLC Controller, Transmit DS3/E3 Framer block Transmit Interface Block which permits Terminal Equipment transmit data remote terminal. Receive Section consists Receive Interface, Receive DS3/E3 Framer, Receive HDLC Controller, Receive Payload Data Output Interface, Receive Overhead Data Interface which allows
local terminal equipment receive data from remote terminal equipment. Microprocessor Interface used configure Framer different operating modes monitor performance Framer. Performance Monitor Sections consist large number Reset-upon-Read Read-Only registers that contain cumulative one-second statistics that reflect performance/health Framer system. FEATURES Transmits, Receives Processes data DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 E3-ITU-T G.832 Framing Formats. Channel HDLC Controller Interfaces Popular Microprocessors Integrated Framer Performance Monitor Available PQFP package 3.3V Power Supply with Tolerant Operating Temperature -40°C +85°C APPLICATIONS Network Interface Units CSU/DSU Equipment. Test Equipment Fiber Optic Terminals DS3/E3 Frame Relay Equipment
FIGURE BLOCK DIAGRAM XRT72L50
TRST TestM NibIntf HEnable HClk HFram TxAISEn HIns T3/E3 Transm verhead Interface T3/E3 Transm Fram T3/E3 transm Input HDLC controller HInd TxNibFram TxFram TxNibClk TxLnClk TxFram eRef TxNib TxSer
TxLineClk TxPO TxNEG Interface/ RxLineClk RxPO RxNEG ExtLO Controller FEAC Data Link Controller Perform ance Monitor Interrupt Controller
Interface
A[8:0] D[7:0] ALE_AS R_R/W RDY_DTCK Reset RD_DS
RxClk HEnable HClk RxRed HFram T3/E3 Receive verhead Interface T3/E3 Receive Fram T3/E3 Receive utput HDLC controller Hind RxFram RxNib RxSer utClk
Exar Corporation 48720 Kato Road, Fremont 94538 (510) 668-7000 (510) 668-7017 www.exar.com
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE XRT72L50
xtLO xLin ineC TxFram lk/S ndFC ibFram alFC Fram e/TxH nable/TxH /TxH /TxH /TxH
er/R xIdle xFram lk/R nable/R Fram
XRT72L50
ib3/TxH ib2/TxH ib1/TxH ib0/TxH er/S TxIn TxFram
ORDERING INFORMATION
PART NUMBER XRT72L50IQ PACKAGE TYPE 14x20mm, Lead Plastic OPERATING TEMPERATURE RANGE -40°C +85°C
ibIntf
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE CONTENTS
GENERAL DESCRIPTION
FEATURES APPLICATIONS Figure Block Diagram XRT72L50 Figure XRT72L50
ORDERING INFORMATION
TABLE CONTENTS
DESCRIPTIONS ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUMS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS (CONT.) Timing Diagrams
Figure Timing Diagram Transmit Payload Input Interface, when XRT72L50 Device operating both Loop-Timing Modes Figure Timing Diagram Transmit Payload Input Interface, when XRT72L50 Device operating both Local-Timing Modes Figure Timing Diagram Transmit Payload Data Input Interface, when XRT72L50 Device operating both DS3/Nibble Looped-Timing Modes Figure Timing Diagram Transmit Payload Data Input Interface, when XRT72L50 Device operating DS3/ Nibble Local-Timing Modes Figure Timing Diagram Transmit Overhead Data Input Interface (Method Access) Figure Timing Diagram Transmit Overhead Data Input Interface (Method Access) Figure Transmit Interface Timing TxPOS TxNEG updated rising edge TxLineClk Figure Transmit Interface Timing TxPOS TxNEG updated falling edge TxLineClk Figure Receive Interface timing RxPOS RxNEG sampled rising edge RxLineClk Figure Receive Interface timing RxPOS RxNEG sampled falling edge RxLineClk Figure Receive Payload Data Output Interface Timing Figure Receive Payload Data Output Interface Timing (Nibble Mode Operation) Figure Receive Overhead Data Output Interface Timing (Method Using RxOHClk) Figure Receive Overhead Data Output Interface Timing (Method Using RxOHEnable) Figure Microprocessor Interface Timing Intel-type Programmed Read Operation Figure Microprocessor Interface Timing Intel-type Programmed Write Operation Figure Microprocessor Interface Timing Motorola-type Programmed Read Operation Figure Microprocessor Interface Timing Motorola-type Programmed Write Operation Figure Microprocessor Interface Timing Reset Pulse Width
Microprocessor Interface Block
MICROPROCESSOR INTERFACE BLOCK SIGNASL
Figure Block Diagram Microprocessor Interface Block TABLE DESCRIPTION MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES BOTH INTEL MOTOROLA MODES TABLE DESCRIPTION MICROPROCESSOR INTERFACE SIGNALS OPERATING INTEL MODE
INTERFACING XRT72L50 DS3/E3 FRAMER LOCAL µC/µP MICROPROCESSOR INTERFACE BLOCK 2.2.1 Interfacing XRT72L50 DS3/E3 Framer Microprocessor over wide bi-directional Data
TABLE DESCRIPTION MICROPROCESSOR INTERFACE SIGNALS OPERATING MOTOROLA MODE
2.2.2 Data Access Modes 2.2.2.1 Data Access using Programmed
Figure Microprocessor Interface Timing Intel-type Programmed Read Operation Figure Microprocessor Interface Timing Intel-type Programmed Write Operation Figure Microprocessor Interface Timing Motorola-type Programmed Read Operation
ON-CHIP REGISTER ORGANIZATION 2.3.1 Framer Register Addressing
Figure Microprocessor Interface Timing Motorola-type Programmed Write Operation TABLE REGISTER ADDRESSING FRAMER PROGRAMMER REGISTERS
2.3.2 Framer Register Description
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.2.1 Operating Mode Register 2.3.2.2 Control Register 2.3.2.3 Part Number Register 2.3.2.4 Version Number Register 2.3.2.5 Block Interrupt Enable Register 2.3.2.6 Block Interrupt Status Register 2.3.2.7 Test Register 2.3.2.8 Receive Configuration Status Register 2.3.2.9 Receive Status Register 2.3.2.10 Receive Interrupt Enable Register 2.3.2.11 Receive Interrupt Status Register 2.3.2.12 Receive Sync Detect Enable Register 2.3.2.13 Receive FEAC Register 2.3.2.14 Receive FEAC Interrupt Enable/Status Register 2.3.2.15 Receive LAPD Control Register 2.3.2.16 Receive LAPD Status Register 2.3.3 Receive Framer Configuration Registers (ITU-T G.832) 2.3.3.1 Receive Configuration Status Register (E3, ITU-T G.832) 2.3.3.2 Receive Configuration Status Register (E3, ITU-T G.832) 2.3.3.3 Receive Interrupt Enable Register (E3, ITU-T G.832) 2.3.3.4 Receive Interrupt Enable Register (E3, ITU-T G.832) 2.3.3.5 Receive Interrupt Status Register (E3, ITU-T G.832) 2.3.3.6 Receive Interrupt Status Register (E3, ITU-T G.832) 2.3.3.7 Receive LAPD Control Register (E3, ITU-T G.832) 2.3.3.8 Receive LAPD Status Register (E3, ITU-T G.832 2.3.3.9 Receive Byte Register (E3, ITU-T G.832) 2.3.3.10 Receive Byte Register (E3, ITU-T G.832) 2.3.3.11 Receive TTB-0 Register (E3, ITU-T G.832) 2.3.3.12 Receive TTB-1 Register (E3, ITU-T G.832) 2.3.3.13 Receive TTB-2 Register (E3, ITU-T G.832) 2.3.3.14 Receive TTB-3 Register (E3, ITU-T G.832) 2.3.3.15 Receive TTB-4 Register (E3, ITU-T G.832) 2.3.3.16 Receive TTB-5 Register (E3, ITU-T G.832) 2.3.3.17 Receive TTB-6 Register (E3, ITU-T G.832) 2.3.3.18 Receive TTB-7 Register (E3, ITU-T G.832) 2.3.3.19 Receive TTB-8 Register (E3, ITU-T G.832) 2.3.3.20 Receive TTB-9 Register (E3, ITU-T G.832) 2.3.3.21 Receive TTB-10 Register (E3, ITU-T G.832) 2.3.3.22 Receive TTB-11 Register (E3, ITU-T G.832) 2.3.3.23 Receive TTB-12 Register (E3, ITU-T G.832) 2.3.3.24 Receive TTB-13 Register (E3, ITU-T G.832) 2.3.3.25 Receive TTB-14 Register (E3, ITU-T G.832) 2.3.3.26 Receive TTB-15 Register (E3, ITU-T G.832) 2.3.3.27 Receive Framer Register (E3, ITU-T G.832) 2.3.4 Receive Framer Configuration Registers (ITU-T G.751) 2.3.4.1 Receive Configuration Status Register (E3, ITU-T G.751) 2.3.4.2 Receive Configuration Status Register (E3, ITU-T G.751) 2.3.4.3 Receive Framer Interrupt Enable Register (E3, ITU-T G.751) 2.3.4.4 Receive Interrupt Enable Register (E3, ITU-T G.751) 2.3.4.5 Receive Interrupt Status Register (E3, ITU-T G.751) 2.3.4.6 Receive Interrupt Status Register (E3, ITU-T G.751) 2.3.4.7 Receive LAPD Control Register (E3, ITU-T G.751) 2.3.4.8 Receive LAPD Status Register (E3, ITU-T G.751) 2.3.4.9 Receive Service Bits Register (E3, ITU-T G.751) 2.3.5 Transmit Configuration Registers 2.3.5.1 Transmit Configuration Register 2.3.5.2 Transmit FEAC Configuration Status Register 2.3.5.3 Transmit FEAC Register 2.3.5.4 Transmit LAPD Configuration Register
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.5.5 Transmit LAPD Status Interrupt Register 2.3.5.6 Transmit M-Bit Mask Register 2.3.5.7 Transmit F-Bit Mask Register 2.3.5.8 Transmit F-Bit Mask Register 2.3.5.9 Transmit F-Bit Mask Register 2.3.5.10 Transmit F-Bit Mask Register 2.3.6 Transmit (ITU-T G.832) Configuration Registers 2.3.6.1 Transmit Configuration Register (E3, ITU-T G.832) 2.3.6.2 Transmit LAPD Configuration Register (E3, ITU-T G.832) 2.3.6.3 Transmit LAPD Status Interrupt Register (E3, ITU-T G.832) 2.3.6.4 Transmit Byte Register (E3, ITU-T G.832) 2.3.6.5 Transmit Byte Register (E3, ITU-T G.832) 2.3.6.6 Transmit Byte Register (E3, ITU-T G.832) 2.3.6.7 Transmit TTB-0 Register (E3, ITU-T G.832) 2.3.6.8 Transmit TTB-1 Register (E3, ITU-T G.832) 2.3.6.9 Transmit TTB-2 Register (E3, ITU-T G.832) 2.3.6.10 Transmit TTB-3 Register (E3, ITU-T G.832) 2.3.6.11 Transmit TTB-4 Register (E3, ITU-T G.832) 2.3.6.12 Transmit TTB-5 Register (E3, ITU-T G.832) 2.3.6.13 Transmit TTB-6 Register (E3, ITU-T G.832) 2.3.6.14 Transmit TTB-7 Register (E3, ITU-T G.832) 2.3.6.15 Transmit TTB-8 Register (E3, ITU-T G.832) 2.3.6.16 Transmit TTB-9 Register (E3, ITU-T G.832) 2.3.6.17 Transmit TTB-10 Register (E3, ITU-T G.832) 2.3.6.18 Transmit TTB-11 Register (E3, ITU-T G.832) 2.3.6.19 Transmit TTB-12 Register (E3, ITU-T G.832) 2.3.6.20 Transmit TTB-13 Register (E3, ITU-T G.832) 2.3.6.21 Transmit TTB-14 Register (E3, ITU-T G.832) 2.3.6.22 Transmit TTB-15 Register (E3, ITU-T G.832) 2.3.6.23 Transmit Byte Error Mask Register (E3, ITU-T G.832) 2.3.6.24 Transmit Byte Error Mask Register (E3, ITU-T G.832) 2.3.6.25 Transmit BIP-8 Error Mask Register (E3, ITU-T G.832) 2.3.6.26 TxE3 Register G.832 2.3.7 Transmit Framer Configuration Registers (ITU-T G.751) 2.3.7.1 Transmit Configuration Register (ITU-T G.751) 2.3.7.2 Transmit LAPD Configuration Register (ITU-T G.751) 2.3.7.3 Transmit LAPD Status Interrupt Register (ITU-T G.751) 2.3.7.4 Transmit Service Bits Register (ITU-T G.751) 2.3.7.5 Transmit Mask Register (ITU-T G.751) 2.3.7.6 Transmit Error Mask Register (ITU-T G.751) 2.3.7.7 Transmit BIP-4 Error Mask Register (ITU-T G.751) 2.3.8 Performance Monitor Registers 2.3.8.1 PMON Line Code Violation Count Register 2.3.8.2 PMON Line Code Violation Count Register 2.3.8.3 PMON Framing Bit/Byte Error Count Register 2.3.8.4 PMON Framing Bit/Byte Error Count Register 2.3.8.5 PMON Parity Error Count Register 2.3.8.6 PMON Parity Error Count Register 2.3.8.7 PMON FEBE Event Count Register 2.3.8.8 PMON FEBE Event Count Register 2.3.8.9 PMON CP-Bit Error Event Count Register 2.3.8.10 PMON CP-Bit Error Event Count Register 2.3.8.11 PRBS Error Count Register 2.3.8.12 PRBS Error Count Register 2.3.8.13 PMON Holding Register 2.3.8.14 One-Second Error Status Register 2.3.8.15 One-Second Line Code Violation Accumulator Register 2.3.8.16 One-Second Line Code Violation Accumulator Register 2.3.8.17 One-Second Frame Parity Error Accumulator Register
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
2.3.8.18 One-Second Frame Parity Error Accumulator Register 2.3.8.19 One-Second Frame CP-Bit Error Accumulator Register 2.3.8.20 One-Second Frame CP-Bit Error Accumulator Register 2.3.8.21 Line Interface Drive Register 2.3.8.22 Line Interface Scan Register 2.3.8.23 HDLC Control Register LOSS CLOCK ENABLE FEATURE USING PMON HOLDING REGISTER INTERRUPT STRUCTURE WITHIN FRAMER MICROPROCESSOR INTERFACE SECTION
TABLE LIST POSSIBLE CONDITIONS THAT GENERATE INTERRUPTS WITHIN EACH CHANNEL XRT72L50 FRAMER TABLE LISTING XRT72L50 FRAMER INTERRUPT BLOCK REGISTERS (FOR APPLICATIONS) TABLE LISTING XRT72L50 FRAMER INTERRUPT BLOCK REGISTERS (FOR ITU-T G.832 APPLICATIONS) TABLE LISTING XRT72L50 FRAMER INTERRUPT BLOCK REGISTER (FOR ITU-T G.751 APPLICATIONS)
2.6.1 Automatic Reset Interrupt Enable Bits
TABLE INTERRUPT SERVICE ROUTINE GUIDE (FOR APPLICATIONS) TABLE INTERRUPT SERVICE ROUTINE GUIDE (FOR ITU-T G.832 APPLICATIONS) TABLE INTERRUPT SERVICE ROUTINE GUIDE (FOR ITU-T G.751 APPLICATIONS)
2.6.2 One-Second Interrupts
Line Interface scan section
BIT-FIELDS WITHIN LINE INTERFACE DRIVE REGISTER
Figure XRT72L50 DS3/E3 Framer Interfaced XRT73L0x DS3/E3/STS-1 TABLE RELATIONSHIP BETWEEN STATES RLOOP, LLOOP RESULTING LOOP-BACK MODE WITH XRT73L0X
BIT-FIELDS WITHIN LINE INTERFACE SCAN REGISTER
Operation XRT72L50
DESCRIPTION FRAMES ASSOCIATED OVERHEAD BITS
Figure Frame Format C-bit Parity Figure Frame Format TABLE SETTING WITHIN FRAMER OPERATING MODE REGISTER RESULTING FRAMING FORMAT
4.1.1 Frame Synchronization Bits (Applies both C-bit Parity Framing Formats) 4.1.2 Performance Monitoring/Error Detection Bits (Parity)
TABLE C-BIT FUNCTIONS C-BIT PARITY FRAME FORMAT
4.1.3 Alarm Signaling-Related Overhead Bits 4.1.4 Data Link Related Overhead Bits TRANSMIT SECTION XRT72L50 (DS3 MODE OPERATION)
Figure XRT72L50 Transmit Section configured operate Mode
4.2.1 Transmit Payload Data Input Interface Block
Figure Transmit Payload Data Input Interface Block TABLE DESCRIPTIONS PINS ASSOCIATED WITH TRANSMIT PAYLOAD DATA INPUT INTERFACE
4.2.1.1 Mode Serial/Loop-Timing Mode Behavior XRT72L50
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode 1(Serial/ Loop-Timed) Operation Figure Behavior Terminal Interface signals between Transmit Payload Data Input Interface block XRT72L50 Terminal Equipment (Mode Operation)
4.2.1.2 Mode Serial/Local-Timed/Frame-Slave Mode Behavior XRT72L50
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (Serial/ Local-Timed/Frame-Slave) Operation
4.2.1.3 Mode Serial/Local-Timed/Frame-Master Mode Behavior XRT72L50
Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (Mode Operation) Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (Serial/ Local-Timed/Frame-Master) Operation
4.2.1.4 Mode Nibble-Parallel/Loop-Timed Mode Behavior XRT72L50
Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (DS3 Mode Operation) Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (NibbleParallel/Loop-Timed) Operation Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (Mode Operation)
4.2.1.5 Mode Interface Mode Behavior XRT72L50
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode Operation
4.2.1.6 Mode Interface Mode Behavior XRT72L50
Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (DS3 Mode Operation) Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode Operation Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (DS3 Mode Operation)
4.2.2 Transmit Overhead Data Input Interface
Figure Transmit Overhead Data Input Interface block
4.2.2.1 Method Using TxOHClk Clock Signal
TABLE OVERHEAD BITS WITHIN FRAME THEIR POTENTIAL SOURCES WITHIN XRT72L50 TABLE DESCRIPTION METHOD TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS Figure Terminal Equipment being interfaced Transmit Overhead Data Input Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER RISING CLOCK EDGES TXOHCLK SINCE TXOHFRAME LAST SAMPLED "HIGH" OVERHEAD THAT BEING PROCESSED Figure Illustration signal that must occur between Terminal Equipment XRT72L50, order configure XRT72L50 transmit Yellow Alarm remote terminal equipment
4.2.2.2 Method Using TxInClk TxOHEnable Signals
TABLE DESCRIPTION METHOD TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS Figure Terminal Equipment being interfaced Transmit Overhead Data Input Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER TXOHENABLE PULSES SINCE LAST OCCURRENCE TXOHFRAME PULSE, OVERHEAD THAT BEING PROCESSED XRT72L50
4.2.3 Transmit HDLC Controller 4.2.3.1 Bit-Oriented Signaling FEAC Message) processing Transmit HDLC Controller.
Figure Behavior Transmit Overhead Data Input Interface signals between XRT72L50 Terminal Equipment (for Method
4.2.3.2 Message-Oriented Signaling (e.g., LAP-D) processing Transmit HDLC Controller
Figure Flow Chart depicting transmit FEAC Message FEAC Transmitter Figure LAPD Message Frame Format TABLE LAPD MESSAGE TYPE CORRESPONDING VALUE FIRST BYTE WITHIN INFORMATION PAYLOAD TABLE RELATIONSHIP BETWEEN TXLAPD LENGTH LAPD MESSAGE SIZE TABLE RELATIONSHIP BETWEEN TXLAPD LENGTH LAPD MESSAGE SIZE Figure Flow Chart depict LAPD Transmitter
4.2.4 Transmit Framer Block 4.2.4.1 Brief Description Transmit Framer 4.2.4.2 Detailed Functional Description Transmit Framer Block
Figure Transmit Framer Block associated paths other Functional Blocks TABLE RELATIONSHIP BETWEEN CONTENTS YELLOW ALARM) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION TABLE RELATIONSHIP BETWEEN CONTENTS X-BITS) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION TABLE RELATIONSHIP BETWEEN CONTENTS IDLE) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER ACTION TABLE RELATIONSHIP BETWEEN CONTENTS PATTERN) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION TABLE RELATIONSHIP BETWEEN CONTENTS LOS) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION
4.2.5 Transmit Line Interface Block
Figure Interfacing XRT72L50 Framer XRT73L00 DS3/E3/STS-1 Figure Transmit Interface block
4.2.5.1 Selecting various Line Codes
Figure Behavior TxPOS TxNEG signals during data transmission while Transmit Interface operating Unipolar Mode TABLE RELATIONSHIP BETWEEN CONTENT (UNIPOLAR/BIPOLAR) WITHIN CONTROL REGISTER TRANSMIT FRAMER LINE INTERFACE OUTPUT MODE Figure Illustration Line Code
4.2.5.2 TxLineClk Clock Edge Selection
Figure Illustration examples B3ZS Encoding TABLE RELATIONSHIP BETWEEN (AMI/B3ZS*) WITHIN CONTROL REGISTER BIPOLAR LINE CODE THAT OUTPUT TRANSMIT INTERFACE BLOCK TABLE RELATIONSHIP BETWEEN CONTENTS (TXLINECLK INV) WITHIN CONTROL REGISTER
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TXLINECLK CLOCK EDGE THAT TXPOS TXNEG UPDATED Figure Waveform/Timing Relationship between TxLineClk, TxPOS TxNEG TxPOS TxNEG configured updated rising edge TxLineClk
4.2.6 Transmit Section Interrupt Processing 4.2.6.1 Enabling Transmit Section Interrupts
Figure Waveform/Timing Relationship between TxLineClk, TxPOS TxNEG TxPOS TxNEG configured updated falling edge TxLineClk
RECEIVE SECTION XRT72L50 (DS3 MODE OPERATION)
Figure XRT72L50 Receive Section configured operate Mode
4.3.1 Receive Interface Block 4.3.1.1 Unipolar Decoding
Figure Receive Interface Block
4.3.1.2 Bipolar Decoding
Figure Behavior RxPOS, RxNEG RxLineClk signals during data reception Unipolar Data TABLE RELATIONSHIP BETWEEN CONTENTS (UNIPOLAR/BIPOLAR) WITHIN CONTROL REGISTER TXLINECLK CLOCK EDGE THAT TXPOS TXNEG UPDATED Figure IInterfacing XRT72L50 Framer XRT73L00 DS3/E3/STS-1 Figure Line Code Figure Illustration examples B3ZS Decoding TABLE RELATIONSHIP BETWEEN CONTENTS (RXLINECLK INV) CONTROL REGISTER, SAMPLING EDGE RXLINECLK SIGNAL Figure Waveform/Timing Relationship between RxLineClk, RxPOS RxNEG When RxPOS RxNEG sampled rising edge RxLineClk
4.3.2 Receive Framer Block
Figure Waveform/Timing Relationship between RxLineClk, RxPOS RxNEG When RxPOS RxNEG sampled falling edge RxLineClk Figure Receive Framer Block Associated Paths Other Functional Blocks
4.3.2.1 Frame Acquisition Mode Operation
Figure State Machine Diagram Receive Framer block's Frame Acquisition/Maintenance Algorithm
4.3.2.2 Frame Maintenance Mode Operation
TABLE RELATIONSHIP BETWEEN CONTENTS (FRAMING PARITY) WITHIN CONFIGURATION STATUS REGISTER, RESULTING FRAMING ACQUISITION CRITERIA TABLE RELATIONSHIP BETWEEN CONTENTS (F-SYNC ALGO) WITHIN CONFIGURATION STATUS REGISTER, RESULTING F-BIT DECLARATION CRITERIA USED RECEIVE FRAMER BLOCK TABLE RELATIONSHIP BETWEEN CONTENTS (M-SYNC ALGO) WITHIN CONFIGURATION STATUS REGISTER, RESULTING M-BIT DECLARATION CRITERIA USED RECEIVE FRAMER BLOCK
4.3.2.3 Forcing Reframe Software Command 4.3.2.4 Performance Monitoring Receive Framer block 4.3.2.5 Receive Alarms 4.3.2.6 Performance Monitoring Transport Medium
Figure Simple Illustration Locations Source, Mid-Network Sink Terminal Equipment (for CP-Bit Processing)
4.3.3 Receive HDLC Controller Block
Figure Illustration Presumed Configuration Mid-Network Terminal Equipment
4.3.3.1 Bit-Oriented Signaling FEAC) Processing Receive HDLC Controller. 4.3.3.2 Message Oriented Signaling (e.g., LAP-D) Processing Receive HDLC Controller block
Figure Flow Diagram depicting Receive FEAC Processor Functions Figure LAPD Message Frame Format TABLE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] RESULTING LAPD MESSAGE TYPE SIZE
4.3.4 Receive Overhead Data Output Interface
Figure Flow Chart depicting Functionality LAPD Receiver
4.3.4.1 Method Using RxOHClk Clock signal
Figure Receive Overhead Output Interface block TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK Figure Terminal Equipment being interfaced Receive Overhead Data Output Interface Block (Method TABLE RELATIONSHIP BETWEEN NUMBER RISING CLOCK EDGES RXOHCLK, (SINCE RXOHFRAME LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING OUTPUT RXOH OUTPUT Figure Illustration signals that output Receive Overhead Output Interface (for Method
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (METHOD Figure Terminal Equipment being interfaced Receive Overhead Data Output Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING OUTPUT RXOH OUTPUT
4.3.5 Receive Payload Data Output Interface
Figure Illustration signals that output Receive Overhead Data Output Interface block (for Method Figure Receive Payload Data Output Interface block TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
4.3.5.1 Serial Mode Operation
Figure XRT72L50 DS3/E3 Framer being interfaced Receive Terminal Equipment (Serial Mode Operation)
4.3.5.2 Nibble-Parallel Mode Operation
Figure Illustration behavior signals between Receive Payload Data Output Interface block XRT72L50 Terminal Equipment (Serial Mode Operation) Figure XRT72L50 DS3/E3 Framer being interfaced Receive Section Terminal Equipment (NibbleParallel Mode Operation)
4.3.6 Receive Section Interrupt Processing 4.3.6.1 Enabling Receive Section Interrupts
Figure Illustration Behavior signals between Receive Payload Data Output Interface Block XRT72L50 Terminal Equipment (Nibble-Mode Operation).
4.3.6.2 Enabling/Disabling Servicing Receive Section Interrupts
E3/ITU-T G.751 Operation XRT72L50
DESCRIPTION ITU-T G.751 FRAMES ASSOCIATED OVERHEAD BITS 5.1.1 Definition Overhead Bits 5.1.1.1 (Alarm)
Figure Illustration ITU-T G.751 Framing Format.
5.1.1.2 TRANSMIT SECTION XRT72L50 (E3, ITU-T G.751 MODE OPERATION) 5.2.1 Transmit Payload Data Input Interface Block
Figure XRT72L50 Transmit Section configured operate Mode Figure Transmit Payload Data Input Interface Block TABLE LISTING DESCRIPTION PINS ASSOCIATED WITH TRANSMIT PAYLOAD DATA INPUT INTERFACE
5.2.1.1 Mode Serial/Loop-Timing Mode Behavior XRT72L50
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (Serial/ Loop-Timed) Operation Figure Behavior Terminal Interface signals between XRT72L50 Transmit Payload Data Input Interface block Terminal Equipment (for Mode Operation)
5.2.1.2 Mode Serial/Local-Timed/Frame-Slave Mode Behavior XRT72L50
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (Serial/ Local-Timed/Frame-Slave) Operation Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (Mode Operation)
5.2.1.3 Mode Serial/Local-Timed/Frame-Master Mode Behavior XRT72L50
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (Serial/ Local-Timed/Frame-Master) Operation
5.2.1.4 Mode Nibble-Parallel/Loop-Timed Mode Behavior XRT72L50
Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment Mode Operation) Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (NibbleParallel/Loop-Timed) Operation Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (Mode Operation)
5.2.1.5 Mode Interface Mode Behavior XRT72L50
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode Operation
5.2.1.6 4.2.1.6 Mode Interface Mode Behavior XRT72L50
Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (E3, Mode Operation)
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Figure Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode Operation Figure Behavior Terminal Interface signals between XRT72L50 Terminal Equipment Mode Operation)
5.2.2 Transmit Overhead Data Input Interface
Figure 100. Transmit Overhead Data Input Interface block
5.2.2.1 Method Using TxOHClk Clock Signal
TABLE LISTING OVERHEAD BITS WITHIN FRAME, THEIR POTENTIAL SOURCES, WITHIN XRT72L50 TABLE DESCRIPTION METHOD TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS Figure 101. Terminal Equipment being interfaced Transmit Overhead Data Input Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER RISING CLOCK EDGES TXOHCLK, (SINCE TXOHFRAME LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING PROCESSED Figure 102. Illustration signal that must occur between Terminal Equipment XRT72L50 order configure XRT72L50 transmit Yellow Alarm remote terminal equipment
5.2.2.2 Method Using TxInClk TxOHEnable Signals
TABLE DESCRIPTION METHOD TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS Figure 103. Terminal Equipment being interfaced Transmit Overhead Data Input Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER TXOHENABLE PULSES (SINCE LAST OCCURRENCE TXOHFRAME PULSE) OVERHEAD BIT, THAT BEING PROCESSED XRT72L50
5.2.3 Transmit HDLC Controller 5.2.3.1 Message-Oriented Signaling (e.g., LAP-D) processing Transmit HDLC Controller
Figure 104. Behavior Transmit Overhead Data Input Interface signals between XRT72L50 Terminal Equipment (for Method Figure 105. LAPD Message Frame Format TABLE LAPD MESSAGE TYPE CORRESPONDING VALUE FIRST BYTE, WITHIN INFORMATION PAYLOAD TABLE RELATIONSHIP BETWEEN TXLAPD LENGTH LAPD MESSAGE SIZE Figure 106. Flow Chart Depicting LAPD Transmitter
5.2.4 Transmit Framer Block 5.2.4.1 Brief Description Transmit Framer 5.2.4.2 Detailed Functional Description Transmit Framer Block
Figure 107. Transmit Framer Block associated paths other Functional Blocks TABLE RELATIONSHIP BETWEEN CONTENTS ENABLE) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION TABLE RELATIONSHIP BETWEEN CONTENTS LOS) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION
5.2.5 Transmit Line Interface Block
Figure 108. Interfacing XRT72L50 Framer XRT73L00 DS3/E3/STS-1 Figure 109. Transmit Interface block
5.2.5.1 Selecting various Line Codes
Figure 110. Behavior TxPOS TxNEG signals during data transmission while Transmit Interface operating Unipolar Mode TABLE RELATIONSHIP BETWEEN CONTENT (UNIPOLAR/BIPOLAR) WITHIN CONTROL REGISTER TRANSMIT FRAMER LINE INTERFACE OUTPUT MODE Figure 111. Illustration Line Code
5.2.5.2 TxLineClk Clock Edge Selection
Figure 112. Illustration examples HDB3 Encoding TABLE RELATIONSHIP BETWEEN (AMI/HDB3*) WITHIN CONTROL REGISTER BIPOLAR LINE CODE THAT OUTPUT TRANSMIT INTERFACE BLOCK TABLE RELATIONSHIP BETWEEN CONTENTS (TXLINECLK INV) WITHIN CONTROL REGISTER TXLINECLK CLOCK EDGE THAT TXPOS TXNEG UPDATED Figure 113. Waveform/Timing Relationship between TxLineClk, TxPOS TxNEG TxPOS TxNEG configured updated rising edge TxLineClk
5.2.6 Transmit Section Interrupt Processing 5.2.6.1 Enabling Transmit Section Interrupts
Figure 114. Waveform/Timing Relationship between TxLineClk, TxPOS TxNEG TxPOS TxNEG configured updated falling edge TxLineClk
RECEIVE SECTION XRT72L50 MODE OPERATION)
Figure 115. XRT72L50 Receive Section configured operate Mode
5.3.1 Receive Interface Block 5.3.1.1 Unipolar Decoding
Figure 116. Receive Interface Block
5.3.1.2 Bipolar Decoding
VIII
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Figure 117. Behavior RxPOS, RxNEG RxLineClk signals during data reception Unipolar Data TABLE RELATIONSHIP BETWEEN CONTENTS (TXLINECLK INV) WITHIN CONTROL REGISTER TXLINECLK CLOCK EDGE THAT TXPOS TXNEG UPDATED Figure 118. Interfacing XRT72L50 Framer XRT73L00 DS3/E3/STS-1 Figure 119. Illustration Line Code Figure 120. Illustration examples HDB3 Decoding TABLE RELATIONSHIP BETWEEN CONTENTS (RXLINECLK INV) CONTROL REGISTER, SAMPLING EDGE RXLINECLK SIGNAL Figure 121. Waveform/Timing Relationship between RxLineClk, RxPOS RxNEG When RxPOS RxNEG sampled rising edge RxLineClk
5.3.2 Receive Framer Block
Figure 122. Waveform/Timing Relationship between RxLineClk, RxPOS RxNEG When RxPOS RxNEG sampled falling edge RxLineClk Figure 123. Receive Framer Block Associated Paths Other Functional Blocks
5.3.2.1 Framing Acquisition Mode
Figure 124. State Machine Diagram Receive Framer Frame Acquisition/Maintenance Algorithm Figure 125. Illustration ITU-T G.751 Framing Format
5.3.2.2 Framing Maintenance Mode 5.3.2.3 Forcing Reframe Software Command 5.3.2.4 Performance Monitoring Frame Synchronization Section, within Receive Framer block 5.3.2.5 RxOOF RxLOF output pin.
TABLE RELATIONSHIP BETWEEN LOGIC STATE RXOOF RXLOF OUTPUT PINS, FRAMING STATE RECEIVE FRAMER BLOCK
5.3.2.6 Receive Alarms 5.3.2.7 Loss Signal (LOS) Alarm 5.3.2.8 (Alarm Indication Status) Condition 5.3.2.9 Far-End-Receive Failure (FERF) Condition 5.3.2.10 Error Checking Incoming Frames
Figure 126. Illustration Local Receive Framer block, receiving Frame (from Remote Terminal) with correct BIP-4 Value. Figure 127. Illustration Local Receive Framer block, transmitting Frame Remote Terminal) with Figure 128. Illustration Local Receive Framer block, receiving Frame (from Remote Terminal) with incorrect BIP-4 value. Figure 129. Illustration Local Receive Framer block, transmitting Frame Remote Terminal) with bit-field
5.3.3 Receive HDLC Controller Block
Figure 130. LAPD Message Frame Format TABLE RELATIONSHIP BETWEEN CONTENTS RXLAPDTYPE[1:0] BIT-FIELDS PMDL MESSAGE TYPE/SIZE
5.3.4 Receive Overhead Data Output Interface
Figure 131. Flow Chart depicting Functionality LAPD Receiver
5.3.4.1 Method Using RxOHClk Clock signal
Figure 132. Receive Overhead Output Interface block Figure 133. Terminal Equipment being interfaced Receive Overhead Data Output Interface (Method TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (FOR METHOD TABLE RELATIONSHIP BETWEEN NUMBER RISING CLOCK EDGES RXOHCLK, (SINCE RXOHFRAME LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING OUTPUT RXOH OUTPUT Figure 134. Illustration signals that output Receive Overhead Output Interface (for Method TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (METHOD Figure 135. Terminal Equipment being interfaced Receive Overhead Data Output Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING OUTPUT RXOH OUTPUT
5.3.5 Receive Payload Data Output Interface
Figure 136. Illustration signals that output Receive Overhead Data Output Interface block (for Method Figure 137. Receive Payload Data Output Interface block TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
5.3.5.1 Serial Mode Operation Behavior XRT72L50
Figure 138. Terminal Equipment being interfaced Receive Payload Data Input Interface Block (Serial Mode
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Operation)
5.3.5.2 Nibble-Parallel Mode Operation Behavior XRT72L50
Figure 139. Illustration behavior signals between Receive Payload Data Output Interface block XRT72L50 Terminal Equipment Figure 140. XRT72L50 DS3/E3 Framer being interfaced Receive Section Terminal Equipment (NibbleParallel Mode Operation)
5.3.6 Receive Section Interrupt Processing 5.3.6.1 Enabling Receive Section Interrupts
Figure 141. Illustration signals that output Receive Payload Data Output Interface block (for Nibble-Parallel Mode Operation).
5.3.6.2 Enabling/Disabling Servicing Interrupts
E3/ITU-T G.832 Operation XRT72L50
DESCRIPTION ITU-T G.832 FRAMES ASSOCIATED OVERHEAD BYTES 6.1.1 Definition Overhead Bytes
Figure 142. Illustration ITU-T G.832 Framing Format.
6.1.1.1 Frame Alignment (FA1 FA2) Bytes 6.1.1.2 Error Monitor (EM) Byte 6.1.1.3 Trail-Trace Buffer (TTB) Byte 6.1.1.4 Maintenance Adaptation (MA) Byte
TABLE DEFINITION TRAIL TRACE BUFFER BYTES, WITHIN ITU-T G.832 FRAMING FORMAT
6.1.1.5 Network Operator (NR) Byte 6.1.1.6 General Purpose Communications Channel (GC) Byte TRANSMIT SECTION XRT72L50 MODE OPERATION)
TABLE LISTING VARIOUS PAYLOAD TYPE VALUES THEIR CORRESPONDING MEANING
6.2.1 Transmit Payload Data Input Interface Block
Figure 143. Transmit Section configured operate Mode Figure 144. Transmit Payload Data Input Interface Block TABLE LISTING DESCRIPTION PINS ASSOCIATED WITH TRANSMIT PAYLOAD DATA INPUT INTERFACE
6.2.1.1 Mode Serial/Loop-Timing Mode
Figure 145. Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode 1(Serial/ Loop-Timed) Operation Figure 146. Behavior Terminal Interface signals between Transmit Payload Data Input Interface block XRT72L50 Terminal Equipment (for Mode Operation)
6.2.1.2 Mode Serial/Local-Timed/Frame-Slave Mode Behavior XRT72L50
Figure 147. Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (Serial/ Local-Timed/Frame-Slave) Operation
6.2.1.3 Mode Serial/Local-Timed/Frame-Master ModeBehavior XRT72L50
Figure 148. Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (Mode Operation) Figure 149. Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (Serial/ Local-Timed/Frame-Master) Operation
6.2.1.4 Mode Nibble-Parallel/Loop-Timed Mode Behavior XRT72L50
Figure 150. Behavior Terminal Interface signals between XRT72L50 Terminal Equipment Mode Operation) Figure 151. Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode (NibbleParallel/Loop-Timed) Operation Figure 152. Behavior Terminal Interface signals between XRT72L50 Terminal Equipment (Mode Operation)
6.2.1.5 Mode Interface Mode Behavior XRT72L50
Figure 153. Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode Operation
6.2.1.6 Mode Interface Mode Behavior XRT72L50
Figure 154. Behavior Terminal Interface signals between XRT72L50 Terminal Equipment Mode Operation) Figure 155. Terminal Equipment being interfaced Transmit Payload Data Input Interface block Mode Operation
6.2.2 Transmit Overhead Data Input Interface
Figure 156. Behavior Terminal Interface signals between XRT72L50 Terminal Equipment Mode Operation) Figure 157. Transmit Overhead Data Input Interface block TABLE LISTING OVERHEAD BITS WITHIN FRAME, THEIR POTENTIAL SOURCES, WITHIN XRT72L50
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
6.2.2.1 Method Using TxOHClk Clock Signal
TABLE DESCRIPTION METHOD TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS Figure 158. Terminal Equipment being interfaced Transmit Overhead Data Input Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER RISING CLOCK EDGES TXOHCLK, (SINCE "TXOHFRAME" LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING PROCESSED Figure 159. Illustration signal that must occur between Terminal Equipment XRT72L50, order configure XRT72L50 transmit Yellow Alarm remote terminal equipment
6.2.2.2 Method Using TxInClk TxOHEnable Signals
TABLE DESCRIPTION METHOD TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS Figure 160. Terminal Equipment being interfaced Transmit Overhead Data Input Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER TXOHENABLE PULSES (SINCE LAST OCCURRENCE TXOHFRAME PULSE) OVERHEAD BIT, THAT BEING PROCESSED XRT72L50
6.2.3 Transmit HDLC Controller 6.2.3.1 Message-Oriented Signaling (e.g., LAP-D) processing Transmit HDLC Controller
Figure 161. Behavior Transmit Overhead Data Input Interface signals between XRT72L50 Terminal Equipment (for Method Figure 162. LAPD Message Frame Format TABLE LAPD MESSAGE TYPE CORRESPONDING VALUE FIRST BYTE, WITHIN INFORMATION PAYLOAD TABLE RELATIONSHIP BETWEEN TXLAPD LENGTH LAPD MESSAGE SIZE Figure 163. Flow Chart depicting LAPD Transmitter (LAPD Transmitter configured re-transmit LAPD Message frame repeatedly One-Second intervals) Figure 164. Flow Chart depicting LAPD Transmitter (LAPD Transmitter configured transmit LAPD Message frame only once).
6.2.4 Transmit Framer Block 6.2.4.1 Brief Description Transmit Framer 6.2.4.2 Detailed Functional Description Transmit Framer Block
Figure 165. Transmit Framer Block associated paths other Functional Blocks TABLE RELATIONSHIP BETWEEN CONTENTS ENABLE) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION TABLE RELATIONSHIP BETWEEN CONTENTS LOS) WITHIN CONFIGURATION REGISTER, RESULTING TRANSMIT FRAMER BLOCK'S ACTION
6.2.5 Transmit Line Interface Block
Figure 166. Interfacing XRT72L50 Framer XRT73L00 DS3/E3/STS-1 Figure 167. Transmit Interface block Figure 168. Behavior TxPOS TxNEG signals during data transmission while Transmit Interface operating Unipolar Mode
6.2.5.1 Selecting various Line Codes
TABLE RELATIONSHIP BETWEEN CONTENT (UNIPOLAR/BIPOLAR) WITHIN CONTROL REGISTER TRANSMIT FRAMER LINE INTERFACE OUTPUT MODE Figure 169. Illustration Line Code Figure 170. Illustration examples HDB3 Encoding
6.2.5.2 TxLineClk Clock Edge Selection
TABLE RELATIONSHIP BETWEEN (AMI/HDB3*) WITHIN CONTROL REGISTER BIPOLAR LINE CODE THAT OUTPUT TRANSMIT INTERFACE BLOCK TABLE RELATIONSHIP BETWEEN CONTENTS (TXLINECLK INV) WITHIN CONTROL REGISTER TXLINECLK CLOCK EDGE THAT TXPOS TXNEG UPDATED
6.2.6 Transmit Section Interrupt Processing 6.2.6.1 Enabling Transmit Section Interrupts
Figure 171. Waveform/Timing Relationship between TxLineClk, TxPOS TxNEG TxPOS TxNEG configured updated rising edge TxLineClk Figure 172. Waveform/Timing Relationship between TxLineClk, TxPOS TxNEG TxPOS TxNEG configured updated falling edge TxLineClk
RECEIVE SECTION XRT72L50 MODE OPERATION) 6.3.1 Receive Interface Block
Figure 173. XRT72L50 Receive Section configured operate Mode
6.3.1.1 Unipolar Decoding
Figure 174. Receive Interface Block Figure 175. Behavior RxPOS, RxNEG RxLineClk signals during data reception Unipolar Data
6.3.1.2 Bipolar Decoding
TABLE RELATIONSHIP BETWEEN CONTENTS (UNIPOLAR/BIPOLAR) WITHIN CONTROL REGISTER
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
Figure 176. Interfacing XRT72L50 Framer XRT73L00 DS3/E3/STS-1 Figure 177. Illustration Line Code Figure 178. Illustration examples HDB3 Decoding TABLE RELATIONSHIP BETWEEN CONTENTS (RXLINECLK INV) CONTROL REGISTER, SAMPLING EDGE RXLINECLK SIGNAL Figure 179. Waveform/Timing Relationship between RxLineClk, RxPOS RxNEG When RxPOS RxNEG sampled rising edge RxLineClk Figure 180. Waveform/Timing Relationship between RxLineClk, RxPOS RxNEG When RxPOS RxNEG sampled falling edge RxLineClk
6.3.2 Receive Framer Block 6.3.2.1 Framing Acquisition Mode
Figure 181. Receive Framer Block Associated Paths Other Functional Blocks Figure 182. State Machine Diagram Receive Framer Frame Acquisition/Maintenance Algorithm Figure 183. Illustration ITU-T G.832 Framing Format
6.3.2.2 Framing Maintenance Mode 6.3.2.3 Forcing Reframe Software Command 6.3.2.4 Performance Monitoring Frame Synchronization Section, within Receive Framer block 6.3.2.5 RxOOF RxLOF output pin. 6.3.2.6 Receive Alarms
TABLE RELATIONSHIP BETWEEN LOGIC STATE RXOOF RXLOF OUTPUT PINS, FRAMING STATE RECEIVE FRAMER BLOCK
6.3.2.7 Error Checking Incoming Frames
Figure 184. Illustration Local Receive Framer block, receiving Frame (from Remote Terminal) with correct Byte. Figure 185. Illustration Local Receive Framer block, transmitting Frame Remote Terminal) with FEBE (within byte-field) Figure 186. Illustration Local Receive Framer block, receiving Frame (from Remote Terminal) with incorrect Byte. Figure 187. Illustration Local Receive Framer block, transmitting Frame Remote Terminal) with FEBE (within byte-field)
6.3.2.8 Processing Far-End-Block Error (FEBE) Bit-fields 6.3.2.9 Receiving Trail Trace Buffer Messages 6.3.3 Receive HDLC Controller Block
Figure 188. LAPD Message Frame Format TABLE RELATIONSHIP BETWEEN CONTENTS RXLAPDTYPE[1:0] BIT-FIELDS PMDL MESSAGE TYPE/SIZE
6.3.4 Receive Overhead Data Output Interface
Figure 189. Flow Chart depicting Functionality LAPD Receiver
6.3.4.1 Method Using RxOHClk Clock signal
Figure 190. Receive Overhead Output Interface block Figure 191. Terminal Equipment being interfaced Receive Overhead Data Output Interface (Method TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK TABLE RELATIONSHIP BETWEEN NUMBER RISING CLOCK EDGES RXOHCLK, (SINCE RXOHFRAME LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING OUTPUT RXOH OUTPUT
6.3.4.2 Method Using RxOutClk RxOHEnable signals
Figure 192. Illustration signals that output Receive Overhead Output Interface (for Method TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (METHOD Figure 193. Terminal Equipment being interfaced Receive Overhead Data Output Interface (Method TABLE RELATIONSHIP BETWEEN NUMBER RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME LAST SAMPLED "HIGH") OVERHEAD BIT, THAT BEING OUTPUT RXOH OUTPUT
6.3.5 Receive Payload Data Output Interface
Figure 194. Illustration signals that output Receive Overhead Data Output Interface block (for Method Figure 195. Receive Payload Data Output Interface block TABLE LISTING DESCRIPTION ASSOCIATED WITH RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
6.3.5.1 Serial Mode Operation Behavior XRT72L50
Figure 196. Terminal Equipment being interfaced Receive Payload Data Input Interface Block (Serial Mode Operation)
6.3.5.2 Nibble-Parallel Mode OperationBehavior XRT72L50
Figure 197. Illustration behavior signals between Receive Payload Data Output Interface block
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
XRT72L50 Terminal Equipment Figure 198. XRT72L50 DS3/E3 Framer being interfaced Receive Section Terminal Equipment (NibbleParallel Mode Operation)
6.3.6 Receive Section Interrupt Processing
Figure 199. Illustration signals that output Receive Overhead Data Output Interface block (for Method
6.3.6.1 Enabling Receive Section Interrupts 6.3.6.2 Enabling/Disabling Servicing Interrupts
diagnostic operation xrt72L50 framer
Figure 200. Framer Local Loop-back Path within XRT72L50 DS3/E3 Framer
High Speed HDLC Controller Mode Operation
CONFIGURING XRT72L50 OPERATE HIGH SPEED HDLC CONTROLLER MODE OPERATING HIGH SPEED HDLC CONTROLLER 8.2.1 Operating Transmit HDLC Controller Block
TABLE DESCRIPTION EACH TRANSMIT HDLC CONTROLLER Figure 201. TxHDLC timing CRC16 Figure 202. TxHDLC timing CRC32 Figure 203. Outbound HDLC Frame when CRC-32 selected. Figure 204. Outbound HDLC Frame when CRC-16 selected
8.2.2 Operating Receive HDLC Controller Block 8.2.2.1 Receive Payload HDLC Processor
TABLE DESCRIPTION EACH RECEIVE HDLC CONTROLLER PINS Figure 205. Timing Diagram RxHDLC Operation
ORDERING INFORMATION PACKAGE DIMENSIONS
REVISION HISTORY
XIII
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTIONS
DESCRIPTION
NAME TRST RDY_DTCK TYPE **** **** DESCRIPTION Test Data Out: Boundary Scan test data output. Test Data Boundary Scan Test data input. Power Supply 3.3V JTAG Reset Pin: Resets Boundary Scan Logic. Ground READY DTACK: This active-low output will function READY output, when microprocessor interface running Intel Mode; will function DTACK output, when microprocessor interface running Motorola Mode. Intel Mode READY Output: When Framer negates this output (e.g., toggles "Low"), indicates that current READ WRITE cycle completed. Motorola Mode DTACK (Data Transfer Acknowledge) Output: Framer device will assert this order inform local microprocessor that present READ WRITE cycle nearly complete. Framer device requires that current READ WRITE cycle extended, then Framer will delay assertion this signal. 68000 family requires this signal from peripheral devices, order quickly properly complete READ WRITE cycle. Write Data Strobe (Intel Mode): microprocessor interface operating Intel Mode, then this activelow input functions (Write Strobe) input signal from Once this active-low signal asserted, then Framer will latch contents Data Bus, into addressed register location) within Framer Intel Mode, data gets latched rising edge Input (Motorola Mode): When Microprocessor Interface operating Motorola Mode, this functionally equivalent pin. Motorola Mode, READ operation occurs this logic "1". Similarly, WRITE operation occurs this logic "0". Chip Select Input: This active-low input signal selects Microprocessor Interface Section Framer device enables READ/WRITE operations between Local Microprocessor Framer on-chip registers locations. Address Latch Enable/Address Strobe: This input used latch address (present Microprocessor Interface Address Bus, A(8:0)) into Framer Microprocessor Interface circuitry indicate start READ/WRITE cycle. This input active-high Intel Mode (MOTO "Low") active-low Motorola Mode (MOTO "High").
WR_R/W
ALE_AS
DESCRIPTION
NAME RD_DS TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Read Data Strobe (Intel Mode): microprocessor interface operating Intel Mode, then this input will function (READ STROBE) input signal from local Once this active-low signal asserted, then Framer will place contents addressed registers (within Framer) Microprocessor Data (D(7:0)). When this signal negated, Data will tri-stated. Data Strobe (Motorola Mode): microprocessor interface operating Motorola mode, then this will function active-low Data Strobe signal. Test Clock: Boundary Scan clock input. Test Mode Select: Boundary Scan Mode Select input. Interrupt Request Output: This open-drain, active-low output signal will asserted when Framer device requesting interrupt service from local microprocessor. This output should typically connected Interrupt Request input local microprocessor. Ground Address Input (Microprocessor Interface) (Least Significant Bit): (Please description A(8) Address Input (Microprocessor Interface) description Address Input (Microprocessor Interface) description Address Input (Microprocessor Interface) description Address Input (Microprocessor Interface) description Address Input (Microprocessor Interface) description Address Input (Microprocessor Interface) description Address Input (Microprocessor Interface) description Address Input (Microprocessor Interface) (Most Significant Bit): This input pin, along with inputs used select on-chip Framer register space READ/WRITE operations with local microprocessor. Power Supply 3.3V
A(0)
****
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
****
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME NibIntf TYPE DESCRIPTION Nibble Interface Select Input Pin: This input allows user configure Transmit Payload Data Input Interface Receive Payload Data Output Interface operate either Serial-Mode Nibble/Parallel-Mode. Setting this input "High" configures Transmit Receive Terminal Interfaces operate Nibble/Parallel-Mode. this mode, Transmit Payload Data Input Interface block will accept outbound payload data (from Terminal Equipment) nibble-parallel manner TxNib[3:0] input pins. Further, Receive Payload Data Output Interface block will output inbound payload data Terminal Equipment) nibble-parallel manner RxNib[3:0] output pin. HDLC mode operation requires Nibble/Parallel mode setup. Setting this input "Low" configures Transmit Receive Terminal Interfaces operate Serial Mode. this mode, Transmit Payload Data Input Interface block will accept outbound payload data (from Terminal Equipment) serial manner TxSer input pin. Further, Receive Payload Data Output Interface block will output inbound payload data Terminal Equipment) serial manner RxSer output pin. Ground Motorola/Intel Processor Interface Select Mode: This input allows user configure Microprocessor Interface interface with either Motorola-type Intel-type microprocessor/microcontroller. Tying this input VCC, configures microprocessor interface operate Motorola mode (e.g., Framer device readily interfaced Motorola type local microprocessor). Tying this input configures Microprocessor Interface operate Intel Mode (e.g., Framer device readily interfaced Intel type local microprocessor). Reset Input: When this active-low signal asserted, Framer device will asynchronously reset. Additionally, outputs will tri-stated, on-chip registers will reset their default values. Factory Test Pin: user should this Ground. Power Supply 3.3V Ground Bi-Directional Data (Microprocessor Interface Section): description D(7) Bi-Directional Data (Microprocessor Interface Section): description D(7) Bi-Directional Data (Microprocessor Interface Section): description D(7) Bi-Directional Data (Microprocessor Interface Section): description D(7) Bi-Directional Data (Microprocessor Interface Section): description D(7)
MOTO
****
Reset
TestMode
D(0)
**** ****
D(1)
D(2)
D(3)
D(4)
DESCRIPTION
NAME D(5) TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Bi-Directional Data (Microprocessor Interface Section): description D(7) Bi-Directional Data (Microprocessor Interface Section): description D(7) Bi-Directional Data (Microprocessor Interface Section): This pin, along with pins function Microprocessor Interface bidirectional data bus, intended interfaced local microprocessor. Power Supply 3.3V Transmit Framer Reference Input: This input functions Transmit Frame Generation reference signal, XRT72L50 been configured operate Local-Time/Frame Slave Mode. XRT72L50 been configured operate Local-Time/ Frame-Slave Mode, then user's terminal equipment expected apply pulse this input pin) once every 106.4 microseconds (for applications); once every microseconds (for ITU-T G.832 applications) once every 44.7 microseconds (for ITU-T G.751 applications). Local-Time/Frame-Slave Mode, Transmit Section XRT72L50 Framer will initiate generation outbound frame, upon rising edge this signal. NOTE: user configure XRT72L50 Framer operate Local Time/Frame Slave Mode writing xxxx xx01 into Framer Operating Mode Register (Address 0x00). Ground Transmit Framer Reference Clock Input: This input functions Timing Reference Transmit Section XRT72L50 Framer device been configured operate Local-Time Mode. Further, XRT72L50 Framer been configured operate Local-Time Mode, Transmit Payload Data Input Interface will sample data TxSer input pin, upon rising edge TxInClk. applications, user should apply 34.368MHz clock signal. applications, user should apply 44.736MHz clock signal. user configure XRT72L50 Framer operate Local-Time mode writing xxxx xx01 xxxx xx1x into Framer Operating Mode register (Address 0x00) Transmit Command Input: Setting this input "High" configures Transmit Section generate transmit Pattern. Setting this input "Low" configures Transmit Section generate traffic normal manner.
D(6)
D(7)
TxFrameRef
****
TxInClk
****
TxAISEn
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME TxSer/ TYPE DESCRIPTION Transmit Serial Payload Data Input Pin: Terminal Equipment expected input data, that intended transmitted remote terminal, over transport medium. Framer will take data, applied this pin, insert into outbound frame. XRT72L50 Framer been configured operate Local Time Mode, then will sample data this pin) upon rising edge TxInClk. XRT72L50 Framer been configured operate LoopTime Mode, then will sample data this pin) upon rising edge RxOutClk. NOTE: This input active only Serial Mode been selected. Send Message: This input remain "High" during entire duration HDLC packet (including bytes) transmitted, when HDLC controller turned Transmit Nibble-Parallel Payload Data Input Terminal Equipment expected input data, that intended transmitted remote terminal, over transport medium. Framer will take data, applied this (along with TxNib1, TxNib2, TxNib3), insert into outbound frame. XRT72L50 will sample data that these input pins, upon rising edge TxNibClk signal. NOTE: This input active only Nibble-Parallel Mode been selected. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned Transmit Nibble-Parallel Payload Data Input Terminal Equipment expected input data, that intended transmitted remote terminal, over transport medium. Framer will take data, applied this pin, insert into outbound frame. XRT72L50 will sample data that these input pins, upon rising edge TxNibClk signal. NOTE: This input active only Nibble-Parallel Mode been selected. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned Transmit Nibble-Parallel Payload Data Input Terminal Equipment expected input data, that intended transmitted remote terminal, over transport medium. Framer will take data, applied this pin, insert into outbound frame. XRT72L50 will sample data that these input pins, upon rising edge TxNibClk signal. NOTE: This input active only Nibble-Parallel Mode been selected. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned
SndMsg
TxNib0/
TxHDLCDat0
TxNib1/
TxHDLCDat1 TxNib2/
TxHDLCDat2
DESCRIPTION
NAME TxNib3/ TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Transmit Nibble-Parallel Payload Data Input Terminal Equipment expected input data, that intended transmitted remote terminal, over transport medium. Framer will take data, applied this (along with TxNib1, TxNib2, TxNib3), insert into outbound frame. XRT72L50 will sample data that these input pins, upon rising edge TxNibClk signal. NOTE: This input active only Nibble-Parallel Mode been selected. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned Ground Power Supply 3.3V Transmit Overhead Clock: This output signal serves purposes: Transmit Overhead Data Input Interface block will provide rising clock edge this signal, bit-period prior start instant that Transmit Overhead Data Input Interface block processing overhead bit. Transmit Overhead Data Input Interface will sample data TxOH input pin, falling edge this clock signal (provided that TxOHIns input "High"). NOTE: Transmit Overhead Data Input Interface block will supply clock edge overhead bits within frame (via TxOHClk output signal). This includes those overhead bits that Transmit Overhead Data Input Interface will accept from Terminal Equipment. Transmit Overhead Data Insert Input: Asserting this input signal (e.g., setting "High") enables Transmit Overhead Data Input Interface accept overhead data from Terminal Equipment. other words, while this input "High", Transmit Overhead Data Input Interface will sample data TxOH input pin, falling edge TxOHClk output signal. Conversely, setting this "Low" configures Transmit Overhead Data Input Interface sample (e.g., ignore) data TxOH input pin, falling edge TxOHClk output signal. NOTE: Terminal Equipment attempts insert overhead that cannot accepted Transmit Overhead Data Input Interface (e.g., Terminal Equipment asserts TxOHIns signal, time when these non-insertable overhead bits being processed); that particular insertion effort will ignored. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned
TxHDLCDat3
TxOHClk
**** ****
TxOHIns/
TxHDLCDat4
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME TxOH/ TYPE DESCRIPTION Transmit Overhead Input Pin: Transmit Overhead Data Input Interface accepts overhead data this input pin, inserts into overhead position within very next outbound frame. TxOHIns pulled "High", Transmit Overhead Data Input Interface will sample data this input (TxOH), falling edge TxOHClk output pin. Conversely, TxOHIns pulled "Low", then Transmit Overhead Data Input Interface will sample data this input (TxOH). Consequently, this data will ignored. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned Transmit Overhead Data Indicator: This output will pulse "High" one-bit period prior time that Transmit Section XRT72L50 will processing Overhead bit. purpose this output warn Terminal Equipment that, during very next bit-period, XRT72L50 going processing Overhead will ignoring data that applied TxSer input pin. NOTE: applications, this output only active XRT72L50 operating Serial Mode. This output will pulled "Low" device operating Nibble-Parallel Mode. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned Transmit Overhead Input Enable: XRT72L50 will assert this signal, TxInClk period, just prior instant that Transmit Overhead Data Input Interface will sampling processing overhead bit. Terminal Equipment intends insert value overhead bit, into outbound frame, expected sample state this signal, upon falling edge TxInClk. Upon sampling TxOHEnable "High", Terminal Equipment should place desired value overhead bit, onto TxOH input assert TxOHIns input pin. Transmit Overhead Data Input Interface" block will sample latch data TxOH signal, upon rising edge very next TxInClk input signal. Transmit HDLC Data Input This accepts TxHDLC data when HDLC controller turned Transmit Overhead Framing Pulse: This output pulses "High" when Transmit Overhead Data Input Interface block expecting first Overhead bit, within frame applied TxOH input pin. This "High" clock period TxOHClk. Transmit HDLC Output Clock: When HDLC controller TxHDLCDat updated 72L53 this clock signal.
TxHDLCDat5
TxOHInd/
TxHDLCDat6 TxOHEnable/
TxHDLCDat7
TxOHFrame/
TxHDLCClk
DESCRIPTION
NAME TxNibFrame/ TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Transmit Frame Boundary Indicator Nibble/Parallel Interface: This output pulses "High" when last nibble given frame expected TxNib[3:0] input pins. purpose this output alert Terminal Equipment that needs begin transmission frame XRT72L50. Valid Frame Check Sequence: When HDLC this will "High" valid Frame Check Sequence. Transmit Nibble Clock Signal:
ValFCS
TxNibClk/
user opts operate XRT72L50 Nibble-Parallel mode, then XRT72L50 will derive this clock signal from either TxInClk RxLineClk signal (depending upon which signal selected timing reference). user advised configure Terminal Equipment output outbound payload data XRT72L50 Framer onto TxNib[3:0] input pins, upon rising edge this clock signal.
NOTES: applications, XRT72L50 Framer will output 1176 clock edges Terminal Equipment) each outbound frame. ITU-T G.832 applications, XRT72L50 Framer will output 1074 clock edges Terminal Equipment) each outbound frame. ITU-T G.751 applications, XRT72L50 Framer will output clock edges Terminal Equipment) each outbound frame. Send Frame Check Sequence: When HDLC controller turned this driven "High" during time when bytes being sent after valid HDLC message.
Ground Transmit Frame Indicator: Transmit Section XRT72l50 will pulse this output "High" (for bit-period), when Transmit Payload Data Input Interface processing last given frame. purpose this output alert Terminal Equipment that needs begin transmission frame XRT72l50 (e.g., permit XRT72l50 maintain Transmit DS3/E3 framing alignment control over Terminal Equipment). Power Supply 3.3V Transmit Line Interface Clock: This clock signal output Line Interface Framer, along with TxPOS TxNEG signals. purpose this output clock signal provide with timing information that generate pulses deliver them over transmission medium Far-End Receiver. user configure source this clock either RxLineClk (from Receiver portion Framer) TxInClk input. nominal frequency this clock signal 34.368 MHz.
SndFCS
TxFrame
****
TxLineClk
****
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME TxNEG TYPE DESCRIPTION Transmit Negative Polarity Pulse: exact role this output depends upon whether Framer operating Unipolar Bipolar Mode. Unipolar Mode: This output signal pulses "High" period, each outbound frame. This output signal logic "Low" remaining bit-periods outbound frames Bipolar Mode: This output functions dual-rail output signals that commands sequence pulses driven line. TxPOS other output pin. This input typically connected TNDATA input external DS3/E3 Line Interface Unit When this output asserted, will command generate negative polarity pulse line. Transmit Positive Polarity Pulse: exact role this output depends upon whether Framer operating Unipolar Bipolar Mode. Unipolar Mode: This output functions Single-Rail output signal outbound data stream. signal, this output pin, will updated user-selected edge TxLineClk signal. Bipolar Mode: This output functions dual rail output signals that commands sequence pulses driven line. TxNEG other output pin. This input typically connected TPDATA input external Line Interface Unit When this output asserted, will command generate positive polarity pulse line Encoder (HDB3) Disable Output (intended connected XRT73L00 DS3/E3 Line Interface Unit IC): This output intended connected ENDECDIS input XRT73L00 DS3/E3 Line Interface Unit when device being used Hardware mode. user control state this output writing (Encodis) within Line Interface Driver Register (Address 0x80). user commands this signal toggle "High" then will disable B3ZS/HDB3 encoder circuitry within XRT73L00 Conversely, user commands this output signal toggle "Low", then B3ZS/HDB3 Encoder circuitry, within XRT73L00 will enabled. user advised disable B3ZS/HDB3 encoder (within XRT73L00 XRT72L50 Framer been configured operate B3ZS/ HDB3 line code. NOTE: customer using XRT73L00 DS3/E3 Line Interface Unit then this output used other purposes.
TxPOS
ENCODIS
DESCRIPTION
NAME TxLEV TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Transmit Line Build-Out Enable/Disable Select Output connected XRT73L00 DS3/E3 Line Interface Unit IC): This output intended connected TxLev input XRT73L00 DS3/E3 Line Interface Unit user control state this output writing (TxLev) within Line Interface Driver Register (Address 0x80). Application: user commands this signal toggle "High" then Transmit Line BuildOut circuit (within XRT73L00) will disabled. this mode, XRT73L00 will output unshaped (e.g., square) pulses onto line (via TTIP TRING output pins). Conversely, user commands this signal toggle "Low" then Transmit Line Build-Out circuit (within XRT73L00) will disabled. this mode, XRT73L00 will output shaped (e.g., more rounded) pulses onto line (via TTIP TRING output pins). order comply with DSX-3 Isolated Pulse Template Requirement (per Bellcore GR-499-CORE), user advised command this output "High" cable length (between transmit output XRT73L00 DSX-3 Cross-Connect System) greater than feet. Conversely, user advised command this output "Low" cable length (between transmit output XRT73L00 DSX-3Cross Connect System) less than feet. Applications: This used General Purpose Output pin. Transmit Line Build-Out circuitry (within XRT73L00) active applications. NOTE: customer using XRT73L00 DS3/E3 Line Interface Unit then this output used other purposes. Transmit Ones Signal (TAOS) Command (for XRT73L00 Line Interface Unit IC): This output intended connected TAOS input XRT73L00 DS3/E3 Line Interface Unit user control state this output writing (TAOS) Line Interface Drive Register (Address 0x80). user commands this signal toggle "High" then will force XRT73L00 Line Interface Unit transmit "All Ones" pattern onto line. Conversely, user commands this output signal toggle "Low" then XRT73L00 DS3/E3 Line Interface Unit will proceed transmit data based upon pattern that receives TxPOS TxNEG output pins. NOTE: customer using XRT73L00 DS3/E3 Line Interface Unit then this output used other purposes. Local Loopback Output XRT73L00 DS3/E3 Line Interface Unit IC): This output intended connected LLOOP input XRT73L00 user command this signal toggle "High" and, turn, force into Local Loop-back mode. (For detailed description XRT73L00 DS3/E3 Line Interface Unit IC's operation during Local Loopback, please XRT73L00 DS3/STS-1/E3 Line Interface Unit IC's Data Sheet). NOTE: customer using XRT73L00 DS3/E3 Line Interface Unit then this output used other purposes.
TAOS
LLOOP
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME RLOOP TYPE DESCRIPTION Remote Loopback Output XRT73L00 DS3/E3 Line Interface Unit IC): This output intended connected RLOOP input XRT73L00 DS3/E3 Line Interface Unit user command this signal toggle "High" and, turn, force XRT73L00 DS3/E3 Line Interface Unit into Remote Loop-back mode. Conversely, user command this signal toggle "Low" allow XRT73L00 operate normal mode. (For detailed description XRT73L00 DS3/E3 Line Interface Unit IC's operation during Remote Loopback, please XRT73L00 DS3/ STS-1/ Line Interface Unit IC's Data Sheet). NOTE: customer using XRT73L00 DS3/E3 Line Interface Unit then this output used other purposes. NOTE: Receive Equalization Enable/Disable Select output connected XRT73L00 DS3/E3 Line Interface Unit IC): This output intended connected input XRT73L00 DS3/E3 (REQDIS REQEN XRT73L03 73L04) Line Interface Unit user control state this output writing (REQ) within Line Interface Driver Register (Address 0x80). user commands this signal toggle "High" then internal Receive Equalizer (within XRT73L00) will disabled. Conversely, user commands this output signal toggle "Low", then internal Receive Equalizer (within XRT73L00) will enabled. information criteria that should used when deciding whether bypass equalization circuitry not, please consult XRT73L00 DS3/E3 Line Interface Unit data sheet. NOTE: customer using XRT73L00 DS3/E3 Line Interface Unit then this output used other purposes. Ground Connection Receiver (Recovered) Clock: This input signal serves three purposes: Receive Framer uses sample latch signals RxPOS RxNEG input pins (into Receive Framer circuitry). This input signal functions timing reference Receive Framer block. Transmit Framer block configured this input signal timing reference. This signal recovered clock from external DS3/E3 (Line Interface Unit) which derived from incoming DS3/E3 data.
RxLineClk
****
DESCRIPTION
NAME RxNEG TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Receive Negative Data Input: exact role this input depends upon whether Framer operating Unipolar Bipolar Mode. Unipolar Mode: This input inactive, should pulled ("Low" "High") when Framer operating Unipolar Mode. Bipolar Mode: This input functions dual rail inputs incoming AMI/ HDB3 encoded data that been received from external Line Interface Unit (LIU) RxPOS functions other dual rail input Framer. When this input asserted, means that received negative polarity pulse from line. Receive Positive Data Input: exact role this input depends upon whether Framer operating Unipolar Bipolar Mode. Unipolar Mode: This input functions Single-Rail input incoming data stream. signal this input will sampled latched (into Receive DS3/E3 Framer) user-selected edge RxLineClk signal. Bipolar Mode: This input functions dual rail inputs incoming AMI/HDB3 encoded data that been received from external Line Interface Unit (LIU) RxNEG functions other dual rail input Framer. When this input asserted, means that received positive polarity pulse from line. Receive Loss Lock Indicator from XRT73L00 DS3/E3 Line Interface Unit This input intended connected RLOL (Receive Loss Lock) output XRT73L00 Line Interface Unit user monitor state this reading state (RLOL) within Line Interface Scan Register (Address 0x81). this input "Low", then means that clock recovery phase-lockedloop circuitry, within XRT73L00 properly locked onto incoming data-stream; properly recovering clock data from this DS3/E3 data-stream. However, this input "High", then means that phaselocked-loop circuitry, within XRT73L00 lost lock with incoming data-stream, properly recovering clock data. more information operation XRT73L00 DS3/E3 Line Interface Unit please consult XRT73L00 DS3/E3 Line Interface Unit data sheet. NOTE: customer using XRT73L00 DS3/E3 Line Interface Unit then this output used other purposes.
RxPOS
RLOL
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME ExtLOS TYPE DESCRIPTION Receive (Loss Signal) Indicator Input (from XRT73L00 IC): This input intended connected RLOS (Receive Loss Signal) output XRT73L00 Line Interface Unit user monitor state this reading state (RLOS) within Line Interface Scan Register (Address 0x81). this input "Low", then means that XRT73L00 currently declaring (Loss Signal) condition. However, this input "High", then means that XRT73L00 currently declaring (Loss Signal) condition. more information operation XRT73L00 DS3/E3 Line Receiver please consult XRT73L00 DS3/STS-1/E3 Line Interface Unit data sheet. Asserting RLOS input will cause XRT72L50 DS3/E3 Framer device declare (Loss Signal) condition. Therefore, this input should used general purpose input pin. Drive Monitor Output Input (from XRT73L00 DS3/E3 Line Interface Unit IC): This input intended connected output XRT73L00 DS3/E3 Line Interface Unit user determine state this input reading (DMO) within Line Interface Scan Register (Address 0x81). this input signal "High", then means that drive monitor circuitry (within XRT73L00 DS3/E3 Line Interface Unit detected bipolar signals MTIP MRING inputs within last bit-periods. this input signal "Low", then means that bipolar signals being detected MTIP MRING input pins XRT73L00. this customer using XRT73L00 DS3/E3 Line Interface Unit then he/she this input variety other purposes. Power Supply 3.3V Ground Receive Nibble Output Framer will output Received data (from Remote Terminal) local Terminal Equipment this along with RxNib0, RxNib1 RxNib2. data this updated rising edge RxClk output signal. NOTE: This output active only Nibble-Parallel Mode been selected. Receive HDLC Data Output This contains RxHDLC data when HDLC controller Receive Nibble Output Framer will output Received data (from Remote Terminal) local Terminal Equipment this along with RxNib0, RxNib1 RxNib2. data this updated rising edge RxClk output signal. NOTE: This output active only Nibble-Parallel Mode been selected. Receive HDLC Data Output This contains RxHDLC data when HDLC controller
RxNib3/
**** ****
RxHDLCDat3 RxNib2/
RxHDLCDat2
DESCRIPTION
NAME RxNib1/ TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Receive Nibble Output Framer will output Received data (from Remote Terminal) local Terminal Equipment this along with RxNib0, RxNib2 RxNib3. data this updated rising edge RxClk output signal. NOTE: This output active only Nibble-Parallel Mode been selected. Receive HDLC Data Output This contains RxHDLC data when HDLC controller Receive Nibble Output Framer will output Received data (from Remote Terminal) local Terminal Equipment this along with RxNib1, RxNib2 RxNib3. data this updated rising edge RxClk output signal. NOTE: This output active only Nibble-Parallel Mode been selected. Receive HDLC Data Output This contains RxHDLC data when HDLC controller Receive Serial Output: user opts operate XRT72L50 serial mode, then chip will output payload data, incoming frames, this pin. XRT72L50 will output this data upon rising edge RxClk. user advised design Terminal Equipment such that will sample this data falling edge RxClk. NOTE: This signal only active NibIntf input pulled "Low". Receive Idle: This will "High" indicating idle period sent HDLC data packets. Also, combination with ValFCS indicate error conditions. Receive Alarm Indication Signal Output pin: Framer will assert this indicate that Alarm Indication Signal (AIS) been identified Receive data stream. Applications: Framer will assert this indicate that Alarm Indication Signal (AIS) been identified Receive data stream. detected payload consists recurring pattern 1010. this pattern persists M-frames. additional requirement indication that C-bits X-bits This will negated when sufficient number frames, exhibiting 1010. pattern payload been detected. Applications: Receive Section will declare condition, detects consecutive frames, each containing less "0s".
RxHDLCDat1 RxNib0/
RxHDLCDat0 RxSer/
RxIdle
RxAIS
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME RxClk TYPE DESCRIPTION Receive Clock Output Signal Serial Nibble/Parallel Data Interface: exact behavior this signal depends upon whether XRT72L50 operating Serial Nibble-Parallel-Mode. Serial Mode Operation: serial mode, this signal 44.736MHz clock output signal (for applications) 34.368MHz clock output signal (for applications). Receive Payload Data Output Interface will update data RxSer output pin, upon rising edge this clock signal. user advised design configure) Terminal Equipment sample data RxSer pin, upon falling edge this clock signal. Nibble-Parallel Mode Operation: this Nibble-Parallel Mode, XRT72L50 will derive this clock signal, from RxLineClk signal. XRT72L50 will pulse this clock signal 1176 times each inbound frame 1074 times each inbound E3/ITU-T G.832 frame, times each inbound E3/ITU-T G.751 frame). Receive Payload Data Output interface will update data, RxNib[3:0] output pins upon falling edge this clock signal. user advised design configure) Terminal Equipment sample data RxNib[3:0] output pins, upon rising edge this clock signal Ground Receive Boundary Frame Output Indicator: exact functionality this output depends upon whether XRT72L50 Framer operating Serial Nibble-Parallel Mode. Serial Mode Operation: Receive Section XRT72L50 will pulse this output "High" (for bit-period) when Receive Payload Data Output Interface block driving very first given frame, onto RxSer output pin. Nibble-Parallel Operation: Receive Section XRT72L50 will pulse this output "High" (for nibble-period), when Receive Payload Data Output Interface block driving very first nibble given frame, onto RxNib[3:0] output pins. RxOutClk/ **** Power Supply 3.3V Receive Clock Transmit Terminal Interface Clock Loop-Timing: This clock signal functions Terminal Interface clock source, XRT72L50 Framer operating loop-timing mode. this mode, Transmitting Terminal Equipment expected input data Framer TxSer input pin, upon rising edge this clock signal. XRT72L50 will rising edge this clock signal sample data TxSer input. This clock signal buffered version RxLineClk signal. Receive HDLC Data Output This contains RxHDLC data when HDLC controller
RxFrame
****
RxHDLCDat7
DESCRIPTION
NAME RxRed TYPE
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION Receiver Alarm Indicator Receive Framer: Framer asserts this output denote that following events been detected Receive Framer: Loss Signal Condition Frame Condition Alarm Indication Signal Detection Receiver Frame Indicator: Receive Section XRT72L50 Framer will assert this output signal whenever declared Frame (OOF) condition with incoming frames. This signal negated when framer correctly locates framing alignment bits bytes correctly aligns itself with incoming frames. Receive Section Loss Signal Output Indicator: This asserted when Receive Section encounters string consecutive (for operation) consecutive (for operation) RxPOS RxNEG pins. This will negated once Receive Section detected least pulses within bit-periods (for operation); Receive Section detected string consecutive bits, that does contain string consecutive "0s" (for operation). Receive Overhead Output Clock Signal: XRT72L50 will output Overhead bits (within incoming frames), RxOH output pin, upon falling edge this clock signal. consequence, user's data link equipment should rising edge this clock signal sample data both RxOH RxOHFrame output pins. NOTE: This clock signal always active. Receive HDLC Output Clock: When HDLC controller RxHDLCDat updated 72L53 this clock signal. Receive Overhead Indicator: exact functionality this output depends upon whether XRT72L50 Framer operating Serial Nibble-Parallel Mode. Serial Mode Operation: This output pulses "High" (for bit-period) whenever overhead being output RxSer output pin, Receive Payload Data Output Interface block. Nibble-Parallel Mode Operation: This output pulses "High" (for nibble-period) whenever overhead nibble being output RxNib[3:0] output pins, Receive Payload Data Output Interface block. NOTE: purpose this output alert Receive Terminal Equipment that overhead being output RxSer output pin, that this data should ignored.
RxOOF
RxLOS
RxOHClk/
RxHDLCClk RxOHInd
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
DESCRIPTION
NAME RxOH/ TYPE DESCRIPTION Receive Overhead Output Port: overhead bits, which received Receive Section Framer will output this output pin, upon rising edge RxOHClk. Receive HDLC Data Output This contains RxHDLC data when HDLC controller Receive Overhead Enable Indicator: XRT72L50 will assert this output signal RxOutClk period when safe Terminal Equipment sample data RxOH output pin. Receive HDLC Data Output This contains RxHDLC data when HDLC controller Receive Overhead Frame Boundary Indicator: This output pulses "High" whenever Receive Overhead Data Output Interface" block outputs first overhead nibble) frame. Receive HDLC Data Output This contains RxHDLC data when HDLC controller
RxHDLCDat6 RxOHEnable/
RxHDLCDat5 RxOHFrame/
RxHDLCDat4
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUMS
Power Supply. -0.3V +3.6V Storage Temperature .-55°C 150°C Voltage -0.3V 0.3V Power Dissipation PQFP Package. 1.2W Input Voltage (Any Pin) .-0.3V 0.3V Input Current (Any Pin) 100mA
ELECTRICAL CHARACTERISTICS
Test Conditions: 25°C, 3.3V unless otherwise specified SYMBOL PARAMETER Power Supply Current Input Voltage Input High Voltage Output Voltage Output High Voltage Input High Voltage Current Input Voltage Current 0.7*VDD MIN. TYP. 0.3*VDD MAX. UNITS -1.6mA 40µA CONDITIONS Channels
ELECTRICAL CHARACTERISTICS
Test Conditions: 25°C, 3.3V unless otherwise specified SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
Transmit Payload Data Input Interface Loop-Timed/Serial Mode (See Figure Payload data (TxSer) set-up time rising edge RxOutClk Payload data (TxSer) hold time, from rising edge RxOutClk RxOutClk TxFrame output delay RxOutClk TxOHInd output delay
Transmit Payload Data Input Interface Local Timed/Serial Mode (See Figure Payload data (TxSer) set-up time rising edge TxInClk Payload data (TxSer) hold time, from rising edge TxInClk TxFrameRef set-up time rising edge TxInClk TxFrameRef hold-time, from rising edge TxInClk Framer Frame Slave Frame Frame Slave
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
ELECTRICAL CHARACTERISTICS
Test Conditions: 25°C, 3.3V unless otherwise specified SYMBOL PARAMETER TxInClk TxOHInd output delay TxInClk TxFrame output delay MIN. TYP. MAX. UNITS CONDITIONS
Transmit Payload Data Input Interface Looped-Timed/Nibble Mode (See Figure TxNib set-up time third rising edge RxOutClk Payload Nibble hold time, from latching edge RxOutClk TxNibClk TxNibFrame output delay t13A Delay Rising Edge TxNibClk Data Valid TxNib[3:0] Transmit Payload Data Input Interface Local-Timed/Nibble Mode (See Figure TxNib set-up time third rising edge TxInClk Payload Nibble hold time, from latching edge TxInClk TxFrameRef set-up time, latching edge TxInClk Applications Applications Framer Frame Slave TxFrameRef hold time, from latching edge TxNibClk TxNibClk TxNibFrame output delay time Framer Frame Slave Applications Applications Applications Applications Applications Applications Applications Applications
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: 25°C, 3.3V unless otherwise specified SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
Transmit Overhead Input Interface Timing Method (Figure TxOHClk TxOHFrame output delay Applications ITU-T G.832 Applications ITU-T G.751 Applications Applications ITU-T G.832 Applications ITU-T G.751 Applications Applications ITU-T G.832 Applications ITU-T G.751 Applications Applications ITU-T G.832 Applications ITU-T G.751 Applications Applications ITU-T G.832 Applications ITU-T G.751 Applications
TxOHIns set-up time, falling edge TxOHClk
TxOHIns hold time, from falling edge TxOHClk
TxOH data set-up time, falling edge TxOHClk
TxOH data hold time, from falling edge TxOHClk
Transmit Overhead Data Input Interface Method (Figure TXOHIns TxInClk (rising edge) set-up Time
Applications ITU-T G.832 Applications ITU-T G.751 Applications
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: 25°C, 3.3V unless otherwise specified SYMBOL PARAMETER TxInClk clock (rising edge) TxOHIns hold-time MIN. TYP. MAX. UNITS CONDITIONS Applications ITU-T G.832 Applications ITU-T G.751 Applications Applications ITU-T G.832 Applications ITU-T G.751 Applications Applications ITU-T G.832 Applications ITU-T G.751 Applications
TXOH TxInClk (rising edge) set-up Time
TxInClk clock (rising edge) TxOH hold-time
t29A TxOHEnable TxOHIns/TxOH Delay
Transmit Interface Timing (see Figure Figure Rising falling edge TxLineClk rising edge TxPOS TxNEG Period TxLineClk 22.36 29.10 RxPOS, RxNEG hold time from rising edge TxLnClk Applications Applications
Receive Interface Timing (see Figure Figure RxPOS RxNEG set-up time rising edge falling edge RxLineClk. RxPOS RxNEG hold time, from rising edge falling edge RxLineClk (Framer configured sample data RxPOS RxNEG input pins rising edge RxLineClk) Period RxLineClk
22.36 29.10
Applications Applications
Receive Payload Data Output Interface Timing Serial Mode Operation (See Figure Rising edge RxClk Payload Data (RxSer) output delay Applications Applications
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: 25°C, 3.3V unless otherwise specified SYMBOL PARAMETER Rising edge RxClk RxFrame output delay MIN. TYP. MAX. Rising edge RxClk RxOHInd output delay. Receive Payload Data Output Interface Timing Nibble Mode Operation (see Figure Falling edge RxClk rising edge RxFrame output delay Falling edge RxClk rising edge RxNib[3:0] output delay UNITS CONDITIONS Applications Applications Applications Applications
Receive Overhead Data Output Interface Timing Method Using RxOHClk (see Figure t59A Falling edge RxOHClk RxOHFrame output t59B Falling edge RxOHClk RxOH output delay Applications Applications Applications Applications
Receive Overhead Data Output Interface Timing Method Using RxOHEnable (see Figure t60A Rising edge RxOutClk rising edge RxOHEnable delay. Rising edge RxOHFrame rising edge RxOHEnable delay Applications ITU-T G.832 Applications ITU-T G.751 Applications Applications ITU-T G.832 Applications ITU-T G.751 Applications
t60B RxOH Data Valid rising edge RxOHEnable delay
Microprocessor Interface Intel (See Figure Setup Time ALE_AS Hold Time from ALE_AS Low. RD_DS, WR_R/W Pulse Width
Intel Type Read Operations (See Figure Data Valid from RD_DS Low. Data Floating from RD_DS High read write Time
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: 25°C, 3.3V unless otherwise specified SYMBOL t701 PARAMETER Time READY (e.g., RDY_DTCK toggling Low) READY Time (e.g., RDY_DTCK toggling high) MIN. TYP. MAX. UNITS CONDITIONS
Intel Type Write Operations (Figure Data Setup Time WR_R/W High Data Hold Time from WR_R/W High High Time between Reads and/or Writes Time
Microprocessor Interface Motorola (See Figure A[8:0] Setup Time falling edge ALE_AS
Motorola Type Read Operations (See Figure Rising edge RD_DS rising edge RDY_DTCK delay Rising edge RDY_DTCK tri-state D[7:0]
Motorola Type Write Operations (See Figure D[7:0] Set-up time falling edge RD_DS Rising edge RD_DS rising edge RDY_DTCK delay
Reset Pulse Width Both Motorola Intel Operations (See Figure Reset pulse width
TIMING DIAGRAMS
BOTH
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE TIMING DIAGRAM TRANSMIT PAYLOAD INPUT INTERFACE, WHEN XRT72L50 DEVICE OPERATDS3 LOOP-TIMING MODES
XRT72L5x Transmit Payload Data Signals
RxOutClk
TxSer TxFrame
Payload[4702]
Payload[4703]
X-Bit
Payload[0]
TxOH_Ind
Frame Number Frame Number
FIGURE TIMING DIAGRAM TRANSMIT PAYLOAD INPUT INTERFACE, WHEN XRT72L50 DEVICE OPERATING BOTH LOCAL-TIMING MODES
XRT72L5x Transmit Payload Data Signals
TxInClk
TxSer TxFrameRef
Payload[4702]
Payload[4703]
X-Bit
Payload[1]
TxOH_Ind
Frame Number
Frame Number
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE TIMING DIAGRAM TRANSMIT PAYLOAD DATA INPUT INTERFACE, WHEN OPERATING BOTH DS3/NIBBLE LOOPED-TIMING MODES
XRT72L50 DEVICE
t13A
RxOutClk TxNibClk TxNib[3:0] TxNibFrame Nibble [1175] Nibble
Sampling Edge XRT72L5x Device
FIGURE TIMING DIAGRAM TRANSMIT PAYLOAD DATA INPUT INTERFACE, WHEN XRT72L50 DEVICE OPERATING DS3/NIBBLE LOCAL-TIMING MODES
TxInClk TxNibClk TxNib[3:0] TxNibFrame TxFrameRef Nibble [1175] Nibble
Frame Number
Frame Number
Sampling Edge XRT72L5x
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE TIMING DIAGRAM TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD ACCESS)
TxOHClk
TxOHFrame
TxOHIns
TxOH
Remaining Overhead Bits with Frame
FIGURE TIMING DIAGRAM TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD ACCESS)
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE TRANSMIT INTERFACE TIMING TXPOS TXNEG UPDATED RISING EDGE TXLINECLK
FIGURE TRANSMIT INTERFACE TIMING TXPOS TXNEG UPDATED FALLING EDGE TXLINECLK
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE RECEIVE INTERFACE TIMING RXPOS RXNEG SAMPLED RISING EDGE RXLINECLK
RxLineClk
RxPOS
RxNEG
FIGURE RECEIVE INTERFACE TIMING RXPOS RXNEG SAMPLED FALLING EDGE RXLINECLK
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE RECEIVE PAYLOAD DATA OUTPUT INTERFACE TIMING
XRT72L5x Receive Payload Data Signals
RxClk
RxSer
Payload[4702]
Payload[4703]
X-Bit
Payload[0]
RxFrame
RxOHInd
FIGURE RECEIVE PAYLOAD DATA OUTPUT INTERFACE TIMING (NIBBLE MODE OPERATION)
XRT72L5x Receive Payload Data Signals
RxOutClk RxClk RxNib[3:0] RxFrame
Nibble
Nibble
Frame Number
Frame Number Recommended Sampling Edge Terminal Equipment
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE RECEIVE OVERHEAD DATA OUTPUT INTERFACE TIMING (METHOD USING RXOHCLK)
t59A
RxOHClk
RxOHFrame
RxOH
FEAC
t59B
FIGURE RECEIVE OVERHEAD DATA OUTPUT INTERFACE TIMING (METHOD USING RXOHENABLE)
RxOutClk
t60A
RxOHEnable
RxOHFrame
t60B RxOH
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE MICROPROCESSOR INTERFACE TIMING INTEL-TYPE PROGRAMMED READ OPERATION
[8:0]
alid ddress
[7:0] alid
FIGURE MICROPROCESSOR INTERFACE TIMING INTEL-TYPE PROGRAMMED WRITE OPERATION
[8:0] [7:0]
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE MICROPROCESSOR INTERFACE TIMING MOTOROLA-TYPE PROGRAMMED READ OPERATION
[8:0] [7:0] alid ddress alid
DTACK
FIGURE MICROPROCESSOR INTERFACE TIMING MOTOROLA-TYPE PROGRAMMED WRITE OPERATION
[8:0] [7:0] ritten DTACK
alid ddress
FIGURE MICROPROCESSOR INTERFACE TIMING RESET PULSE WIDTH
Reset
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
MICROPROCESSOR INTERFACE BLOCK Microprocessor Interface section supports following operations communication between local Microprocessor (µP) Framer
writing configuration data into Framer on-chip addressable registers. writing outbound PMDL (Path Maintenance Data Link) message into Transmit LAPD Message
buffer.
Framer IC's generation Interrupt Request Microprocessor. Microprocessor's servicing interrupt request from Framer monitoring system's health periodically reading on-chip Performance Monitor registers. reading inbound PMDL Message from Receive LAPD Message Buffer. Receiving sending FEAC Codes
Figure simple block diagram Microprocessor Interface Section within Framer. FIGURE BLOCK DIAGRAM MICROPROCESSOR INTERFACE BLOCK
[8:0] eset [7:0] icroprocessor rogram able egisters
Microprocessor Interface Block Signasl
Framer configured into wide variety different operating modes have performance monitored software through standard microprocessor interface using data, address control signals. local Microprocessor configures Framer into desired operating mode writing data into specific addressables, on-chip Read/Write registers, on-chip RAM. microprocessor interface provides signals which required general purpose microprocessor read write data into these registers. Microprocessor Interface also supports polled interrupt driven environments. These interface signals described below Table Table Table microprocessor interface configured operate Motorola Mode Intel mode. Motorola mode, control signals function required Motorola 68000 family microprocessors. Likewise, Intel Mode, these control signals function required Intel family microprocessors.
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE DESCRIPTION MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES BOTH INTEL MOTOROLA MODES
NAME MOTO TYPE DESCRIPTION Selection input Intel/Motorola Microprocessor Interface. Setting this logic "High" configures Microprocessor Interface operate Motorola mode. Setting this logic "Low" configures Microprocessor Interface operate Intel Mode. Bi-Directional Data register read write operations Nine Address input: This Nine Address provided allow user select on-chip register on-chip location select desired Framer Channel address. Chip Select input. This active-low signal selects Microprocessor Interface framer enables read/write operations with on-chip registers/on-chip RAM. Interrupt Request Output: This open-drain/active-low output signal informs local Microprocessor that Framer interrupt condition that needs servicing. Master Reset Input: Setting this input "Low" resets internal logic power-on default settings. This input should return "High" normal operation.
D[7:0] A[8:0]
RESET
TABLE DESCRIPTION MICROPROCESSOR INTERFACE SIGNALS OPERATING INTEL MODE
NAME ALE_AS EQUIVALENT INTEL
ENVIRONMENT
TYPE
DESCRIPTION Address-Latch Enable: This active-high signal used latch contents address bus, A[8:0]. contents Address latched into A[8:0] inputs falling edge ALE_AS. Read Signal: This active-low input functions read signal from local When this signal goes "Low", framer places contents addressed register Data pins (D[7:0]). Data tri-stated once this input signal returns "High". Write Signal: This active-low input functions write signal from local contents Data (D[7:0]) written into addressed register A[8:0] rising edge this signal. Ready Output: This active-low signal provided Framer indicates that current read write cycle extended until this signal asserted. local typically inserts WAIT states until this signal asserted. This output toggles "Low" when current read write cycle complete.
RD_DS
WR_R/W
RDY_DTCK
READY
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE DESCRIPTION MICROPROCESSOR INTERFACE SIGNALS OPERATING MOTOROLA MODE
NAME ALE_AS EQUIVALENT MOTOROLA
ENVIRONMENT
TYPE
DESCRIPTION Address Strobe: This active-low signal used latch contents address input pins A[8:0] into Microprocessor Interface circuitry. contents Address latched into Framer rising edge ALE_AS signal. Data Strobe: This signal latches contents bi-directional data pins into Addressed Register during Write Cycle. Read/Write Input: When this "High" indicates Read Cycle. When this "Low" indicates Write cycle. Data Transfer Acknowledge: Framer asserts DTACK order inform that present READ WRITE cycle complete. 68000 family CPUs requires this signal from peripheral devices order quickly properly complete READ WRITE cycle.
RD_DS WR_R/W
DTACK
RDY_DTCK
Interfacing XRT72L50 DS3/E3 Framer Local µC/µP Microprocessor Interface Block
Microprocessor Interface block within Framer very flexible provides following options user.
interface Framer µC/µP over 8-bit wide bi-directional data bus. interface Framer Intel-type Motorola-type µC/µP. transfer data between Framer µC/µP Programmed Burst Mode
2.2.1 Interfacing XRT72L50 DS3/E3 Framer Microprocessor over wide bidirectional Data
general, interfacing Framer 8-bit µC/µP straight-forward because registers except PMON registers described below) within Framer 8-bits wide. Further, this mode µC/µP read write data into both even numbered addresses within Framer address space. Performance Monitor (PMON) Registers XRT72L50 DS3/E3 Framer consists following PMON Registers.
PMON Event Count Register PMON Framing Error Event Count Register PMON Received FEBE Event Count Register PMON Parity Error Event Count Register
Unlike most registers, PMON registers 16-bits wide. Table lists each these PMON registers consisting 8-bit registers. these 8-bit register labeled (Most Significant Byte) other register labeled (Least Significant Byte). 8-bit PMON Register reading, concatenated with companion 8-bit PMON Register, yields full 16-bit expression within that PMON Register. 8-bit µC/µP perform consecutive read operations order read full 16-bit expression contained within given PMON register. These PMON Registers Reset-Upon-Read registers. entire 16-bit contents within given PMON Register reset soon 8-bit µC/µP reads either byte this two-byte (e.g., bit) expression. unread companion byte placed PMON Holding register detailed below. example, consider that 8-bit µC/µP needs read PMON Event Count Register. order accomplish this task, 8-bit µC/µP going have read contents PMON Event Count Register (located Address 0x50) contents PMON Event Count Register
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
(located Address 0x51). These eight-bit registers, when concatenated together, make PMON Event Count Register. 8-bit µC/µP reads PMON Event Count-LSB register first, then entire PMON Event Count register will reset 0x0000. 8-bit µC/µP attempts read PMON Event CountMSB register very next read cycle, will read value 0x00. PMON Holding Register resolve this Reset-Upon-Read problem, XRT72L50 DS3/E3 Framer includes special register which permits 8-bit µC/µP read full 16-bit contents these PMON registers. This register called PMON Holding Register located 0x6c within Framer Address space. Whenever 8-bit µC/µP reads bytes 2-byte PMON register, contents unread byte will stored PMON Holding Register. 8-bit µC/µP must then read contents PMON Holding Register very next read operation. Whenever 8-bit µC/µP needs read PMON Register, must execute following steps. Step Read contents given 8-bit PMON Register. does matter whether µC/µP reads register. Step Read contents PMON Holding Register (located Address 0x6c). This register will contain contents other byte. 2.2.2 Data Access Modes Microprocessor Interface block supports data transfer between Framer µC/µP (e.g., Read Write operations) modes: Programmed Burst Modes. 2.2.2.1
Data Access using Programmed
Programmed conventional manner which microprocessor exchanges data with peripheral device. also slowest method data exchange between Framer µC/µP 2.2.2.1.1 Programmed Access Intel Mode XRT72L50 DS3/E3 Framer interfaced Intel-type µC/µP, then should configured operate Intel mode tying MOTO ground. Intel Mode Read Cycle Whenever Intel-type µC/µP wishes read contents register some location within Receive LAPD Message buffer, should following. Place address target register buffer location Address input pins A[8:0]. While µC/µP placing this address value Address Bus, Address Decoding circuitry (within user's system) should assert (Chip Select) Framer, toggling "Low". This action enables further communication between µC/µP Framer Microprocessor Interface block. Toggle ALE_AS (Address Latch Enable) input "High". This step enables Address input drivers, within Microprocessor Interface block Framer. After allowing data Address pins settle waiting appropriate Address Data Setup time), µC/µP should toggle ALE_AS "Low". This step causes Framer latch contents Address into internal circuitry. this point, address register buffer locations been selected. Next, µC/µP should indicate that this current cycle Read Operation toggling RD_DS (Read Strobe) input "Low". This action also enables bi-directional data output drivers Framer. this point, bi-directional data output drivers will proceed drive contents latched addressed register buffer location onto bi-directional data bus, D[7:0]. After µC/µP toggles Read Strobe signal "Low", Framer will keep RDY_DTCK output "High" order inform µC/µP that data read from data READY latched into µC/µP
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
After some settling time, data bi-directional data will stabilize read µC/µP XRT72L50 DS3/E3 Framer will indicate that this data read toggling RDY_DTCK (READY) signal "Low". After µC/µP detects RDY_DTCK signal, then terminate Read Cycle toggling RD_DS (Read Strobe) input "High". Figure presents timing diagram which illustrates behavior Microprocessor Interface signals during Intel-type Programmed Read Operation. FIGURE MICROPROCESSOR INTERFACE TIMING INTEL-TYPE PROGRAMMED READ OPERATION
[8:0]
ddress arget egister
[7:0]
alid
alid
Intel Mode Write Cycle Whenever Intel-type µC/µP wishes write byte word data into register buffer location, should following. Place address target register buffer location Address input pins, A[8:0]. While µC/µP placing this address value onto Address Bus, Address Decoding circuitry (within user's system) should assert input Framer toggling "Low". This enables further communication between µC/µP Framer Microprocessor Interface block. Assert ALE_AS input toggling "High". When µC/µP asserts ALE_AS input pin, enables Address Input Drivers within Framer chip. After allowing data Address pins settle waiting appropriate Address Setup time), µC/µP should toggle ALE_AS input "Low". This step causes Framer latch contents Address into internal circuitry. this point, address register buffer location been selected. µC/µP should then place byte word that intends write into target register, bi-directional data bus, D[7:0]. Next, µC/µP should indicate that this current cycle Write Operation toggling WR_R/W (Write Strobe) input "Low". This action also enables bi-directional data input drivers Framer. After some amount time when data bi-directional data settles, will "low indicating that data been written destination, µC/µP will toggle WR_R/W (Write Strobe) input "High", which terminates write cycle. Figure presents timing diagram which illustrates behavior Microprocessor Interface signals during Intel-type Programmed Write Operation.
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE MICROPROCESSOR INTERFACE TIMING INTEL-TYPE PROGRAMMED WRITE OPERATION
ddress arget egister
[8:0]
[7:0]
ritten
2.2.2.1.2
Programmed Access Motorola Mode
XRT72L50 DS3/E3 Framer interfaced Motorola-type µC/µP (e.g., MC680X0 family, etc.), should configured operate Motorola mode tying MOTO "High". Motorola Mode Read Cycle Whenever Motorola-type µC/µP wishes read contents register some location within Receive LAPD Message. Place address target register buffer location Address input pins, A[8:0]. same time, Address Decoding circuitry (within user's system) should assert (Chip Select) input Framer, toggling "Low". This action enables further communication between µC/µP Framer Microprocessor Interface block. Assert ALE_AS (Address-Strobe) input toggling "Low". This step enables Address input drivers within Microprocessor Interface Block Framer After allowing data Address pins settle waiting appropriate Address Setup time), µC/µP should toggle ALE_AS input "High". This step causes Framer latch contents Address into internal circuitry. this point, address register buffer location been selected. µC/µP should indicate that this cycle Read cycle setting WR_R/W (R/W) input "High". Next µC/µP should initiate current cycle toggling RD_DS (Data Strobe) input "Low". This step enables bi-directional data output drivers within XRT72L50 DS3/E3 Framer. this point, bi-directional data output drivers will proceed drive contents Address register onto bi-directional data bus, D[7:0]. After some settling time, data bi-directional data will stabilize read µC/µP XRT72L50 DS3/E3 Framer will indicate that this data read asserting RDY_DTCK (DTACK) signal. After µC/µP detects RDY_DTCK signal, terminates Read Cycle toggling RD_DS input "High". Figure presents timing diagram which illustrates behavior Microprocessor Interface signals during Motorola-type Programmed Read Operation.
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE MICROPROCESSOR INTERFACE TIMING MOTOROLA-TYPE PROGRAMMED READ OPERATION
[8:0]
ddress arget egister
[7:0]
alid
alid
Motorola Mode Write Cycle Whenever Motorola-type µC/µP wishes write byte word data into register buffer location, should following. Assert ALE_AS input toggling "Low". This step enables Address input drivers. Place address target register buffer location Address input pins, A[8:0]. While µC/µP placing this address value onto Address Bus, Address-Decoding circuitry (within user's system) should assert input pins Framer toggling "Low". This step enables further communication between µC/µP Framer Microprocessor Interface block. After allowing data Address pins settle waiting appropriate Address Setup time), µC/µP should toggle ALE_AS input "High". This step causes Framer latch contents Address into circuitry. this point, Address register buffer location been selected. Further, µC/µP should indicate that this current cycle Write operation toggling WR_R/W (R/W) input "Low". µC/µP should then place byte word that intends write into target register, bi-directional data bus, D[7:0]. Next, µC/µP should initiate cycle toggling RD_DS input "Low". When XRT72L50 DS3/E3 Framer senses that WR_R/W (R/W) input "High" RD_DS input toggled "Low", will enable input drivers bi-directional data bus, D[7:0]. After waiting appropriate time this newly placed data settle bi-directional data (e.g., Data Setup time) Framer will assert RDY_DTCK output signal. After µC/µP detects RDY_DTCK signal, µC/µP should toggle RD_DS input "High" terminates Write cycle. Figure presents timing diagram which illustrates behavior Microprocessor Interface signals, during Motorola-type Programmed Write Operation.
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
FIGURE MICROPROCESSOR INTERFACE TIMING MOTOROLA-TYPE PROGRAMMED WRITE OPERATION
[8:0]
ddress arget egister
[7:0]
ritten
On-Chip Register Organization
Microprocessor Interface section allows user following.
Configure Framer into wide variety operating modes Employ various features Framer Perform status monitoring Enable/Disable service Interrupt Conditions
these things accomplished reading from writing many on-chip registers. Table lists each these registers their corresponding address locations within Framer Address space. 2.3.1 Framer Register Addressing array on-chip registers consists variety register types. These registers denoted Table follows. Read Only Registers. Read/Write Registers Reset-upon-Read Registers Some these registers consists both bit-fields. bit-format definitions each these registers presented Section 2.3.2. TABLE REGISTER ADDRESSING FRAMER PROGRAMMER REGISTERS
ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06-0x0B REGISTER NAME Operating Mode register G.751 default) Control Register Part Number Register (XRT72L50) Version Number Register (Device Dpenent) Block Interrupt Enable Register Block Interrupt Status Register Reserved POWER DEFAULT VALUE b00101011 b10100000 b00000111 b00000001 b00000000 b00000001 DEFAULT VALUE 0x2B 0xA0 0x07 0x01 0x00 0x01 REGISTER TYPE R/W,
XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
TABLE REGISTER ADDRESSING FRAMER PROGRAMMER REGISTERS
ADDRESS 0x0C 0x0D-0x0F 0x10 Test Register Reserved RxDS3 Configuration Status Register RxE3 Configuration Status Register G.832 RxE3 Configuration Status Register G.751 RxDS3 Status Register RxE3 Configuration Status Register G.832 RxE3 Configuration Status Register G.751 RxDS3 Interrupt Enable Register RxE3 Interrupt Enable Registers G.832 RxE3 Interrupt Enable Registers G.751 RxDS3 Interrupt Status Register RxE3 Interrupt Enable Register G.832 RxE3 Interrupt Enable Register G.751 RxDS3 Sync Detect Enable Register RxE3 Interrupt Status Register G.832 RxE3 Interrupt Status Register G.751 RxE3 Interrupt Status Register G.832 RxE3 Interrupt Status Register G.751 RxDS3 FEAC Register RxDS3 FEAC Interrupt Enable/Status Register RxDS3 LAPD Control Register RxE3 LAPD Control Register RxDS3 LAPD Status Register RxE3 LAPD Status Register RxE3 Byte Register G.832 RxE3 Service Register G.751 RxE3 Byte Register G.832 RxE3 TTB-0 Register G.832 RxE3 TTB-1 Register G.832 Rx
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