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XR16M581 - XR16M581
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
FEBRUARY 2009 REV. 1.0.0
XR16M5811 (M581) enhanced Universal Asynchronous Receiver Transmitter (UART) with VLIO interface bytes transmit receive FIFOs, programmable transmit receive FIFO trigger levels, automatic hardware software flow control, data rates Mbps 3.3V, Mbps 2.5V Mbps 1.8V with data sampling rate. Auto RS-485 Half-Duplex Direction control feature simplifies both hardware software half-duplex RS-485 applications. addition, Multidrop mode with Auto Address detection increases performance simplifying software routines. Independent TX/RX Baud Rate Generator feature allows transmitter receiver operate different baud rates. Power consumption M581 minmized enabling sleep mode PowerSave mode. M581 16550 compatible register that provide users with operating status control, receiver error indications, modem serial interface controls. internal loopback capability allows onboard diagnostics. M581 available 24-pin QFN, 32-pin 25-pin packages.
NOTE:
Covered U.S. Patent #5,649,122.
FEATURES
VLIO interface Pin-to-pin compatible with SC16C850V
SC16C850SV 32-QFN package
Mbps maximum data rate Programmable TX/RX FIFO Trigger Levels TX/RX FIFO Level Counters Independent TX/RX Baud Rate Generator Fractional Baud Rate Generator Auto RTS/CTS Hardware Flow Control Auto XON/XOFF Software Flow Control Auto RS-485 Half-Duplex Direction Control Multidrop mode Auto Address Detect Sleep Mode with Automatic Wake-up PowerSave mode Infrared (IrDA 1.1) mode 1.62V 3.63V supply operation Crystal oscillator external clock input
APPLICATIONS
Personal Digital Assistants (PDA) Cellular Phones/Data Devices Battery-Operated Devices Global Positioning System (GPS) Bluetooth
FIGURE XR16M581 BLOCK DIAGRAM
(1.62 3.63 UART Byte FIFO ENDEC Byte FIFO RTS#, CTS#, DTR#, DSR#, RI#,
rSave
LLA# AD7:AD0 IOR# RESET#
VLIO Interface
Regs
Crystal Osc/Buffer
XTAL1 XTAL2
Exar Corporation 48720 Kato Road, Fremont 94538 (510) 668-7000 (510) 668-7017 www.exar.com
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE FIGURE ASSIGNMENT
REV. 1.0.0
RESET#
CTS# RESET# DTR#
RTS#
CTS#
RTS#
LLA#
24-pin
IOR# IOW# XTAL2 XTAL1 PWRSAVE
LLA# IOR# IOW# XTAL2 XTAL1 PWRSAVE
DSR#
32-pin
Corner Transparent View CTS# RESET# RTS# DTR# LLA# DSR# PWRSAVE IOR# XTAL2 XTAL1 IOW#
ORDERING INFORMATION
PART NUMBER XR16M581IL24 XR16M581IL32 XR16M581IB25 PACKAGE 24-Pin 32-Pin 25-Pin OPERATING TEMPERATURE RANGE -40°C +85°C -40°C +85°C -40°C +85°C DEVICE STATUS Active Active Active
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
DESCRIPTIONS
Description
NAME 24-QFN PIN# 32-QFN PIN# 25-BGA PIN# TYPE DESCRIPTION
DATA INTERFACE IOR# Multiplexed Address/Data lines [7:0]. register address latched rising edge LLA#. After LLA# signal goes high, UART enters data phase where data placed these lines.
Read strobe (active low). falling edge instigates internal read cycle retrieves data byte from internal register pointed latched address. UART places data byte data allow host processor read rising edge. Write strobe (active low). falling edge instigates internal write cycle rising edge transfers data byte data internal register pointed latched address. Chip select (active low). falling edge starts access UART. read write determined IOR# IOW# signals. Latch Lower Address (active low). register address latched rising edge LLA# signal. After LLA# goes high, device enters data phase where data placed AD[7:0] lines. Interrupt output (active high). output state defined user through software setting MCR[3]. active mode when MCR[3] logic three state mode when MCR[3] logic MCR[3].
IOW#
LLA#
MODEM SERIAL INTERFACE UART Transmit Data infrared encoder data. Standard transmit receive interface enabled when MCR[6] this mode, signal will logic during reset idle data). Infrared IrDA transmit receive interface enabled when MCR[6] Infrared mode, inactive state data) Infrared encoder/decoder interface logic used, leave unconnected. UART Receive Data infrared receive data. Normal receive data input must idle logic condition. infrared receiver idles logic This input should connected when used. UART Request-to-Send (active low) general purpose output. This output must asserted prior using auto flow control, EFR[6], MCR[1] IER[6]. This also used Auto RS-485 Half-duplex Direction control output, FCTR[3] EMSR[3].
RTS#
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE Description
NAME CTS# 24-QFN PIN# 32-QFN PIN# 25-BGA PIN# TYPE DESCRIPTION UART Clear-to-Send (active low) general purpose input. used auto flow control, EFR[7], MSR[4] IER[7]. This input should connected when used. UART Data-Terminal-Ready (active low) general purpose output. UART Data-Set-Ready (active low) general purpose input. This input should connected when used. UART Carrier-Detect (active low) general purpose input. This input should connected when used. UART Ring-Indicator (active low) general purpose input. This input should connected when used.
REV. 1.0.0
DTR# DSR#
ANCILLARY SIGNALS XTAL1 XTAL2 PwrSave Crystal external clock input. Crystal buffered clock output. Power-Save (active high). This feature isolates M581's data interface from host preventing other activities that cause higher power drain during sleep mode. Sleep Mode with Auto Wake-up Power-Save Feature section details. This does have internal pull-down resistor. This input should connected when used. Device reset (active low). minimum pulse this will reset internal registers outputs UART. UART transmitter output will held HIGH, receiver input will ignored outputs reset during reset period (see UART Reset Conditions). 1.62V 3.63V power supply. Power supply common, ground. center backside package metallic should connected PCB. thermal size should approximate size this center should solder mask defined. solder mask opening should least 0.0025" inwards from edge thermal pad. Connects.
RESET#
Center
Center
15-18
type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
PRODUCT DESCRIPTION XR16M581 (M581) high performance single-channel UART with VLIO interface. device configuration registers. configuration registers 16550 UART compatible control, status data transfer. Additionally, M581 channel bytes transmit receive FIFOs, Automatic RTS/ Hardware Flow Control, Automatic Xon/Xoff Special Character Software Flow Control, infrared encoder decoder (IrDA 1.1), programmable fractional baud rate generator with prescaler divide data rate Mbps. XR16M581 operate from 1.62 3.63 volts. M581 fabricated with advanced CMOS process. Data Rate M581 capable operation Mbps 3.3V with internal sampling clock rate. device operate 3.3V with crystal pins XTAL1 XTAL2, external clock source XTAL1 pin. With typical crystal 14.7456 through software option, user prescaler sampling rate data rates 3.68 Mbps. Enhanced Features rich feature M581 available through internal registers. Automatic hardware/software flow control, programmable transmit receive FIFO trigger levels, selectable baud rates, infrared encoder/ decoder, modem interface controls, sleep mode standard features. bit-5 provides facility turning (Xon) software flow control with incoming (RX) character. M581 includes features such 9-bit (Multidrop) mode, auto RS-485 half-duplex direction control, different baud rate fast mode fractional baud rate generator.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE FUNCTIONAL DESCRIPTIONS Interface interface VLIO interface. VLIO interface 8-bit multiplexed address/data interface. Each cycle asynchronous using CS#, LLA# IOR# IOW# inputs. typical data interconnection VLIO interface shown Figure FIGURE XR16M581 TYPICAL VLIO DATA INTERCONNECTIONS
REV. 1.0.0
DTR# RTS# CTS# Serial Transceivers RS-232 RS-485 RS-422 Infrared
UART_IOR# UART_IOW# UART_CS# UART_INT POWERSAVE UART_RESET#
IOR# IOW# PWRSAVE RESET#
DSR#
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
Serial Interface
M581 typically used with RS-232, RS-485 transceivers. following figure shows typical connections from UART different transceivers. more information RS-232 RS-485/422 transceivers, www.exar.com send e-mail uarttechsupport@exar.com. FIGURE XR16M581 TYPICAL SERIAL INTERFACE CONNECTIONS
R1OUT
DTR#
UART
RTS# CTS# DSR#
RTS#
RS-485 Transceiver Full-duplex
UART
DTR# CTS# DSR#
RXRE#
RS-485 Full-Duplex Serial Interface
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE FIGURE XR16M581 TYPICAL SERIAL INTERFACE CONNECTIONS
REV. 1.0.0
RTS#
RS-485 Transceiver Half-duplex
UART
DTR# CTS# DSR#
RS-485 Half-Duplex Serial Interface
Transceiver
DTR#
UART
RTS# CTS# DSR#
frared ectio
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
Device Reset
RESET# input resets internal registers serial interface outputs their default state (see Table 16). active pulse longer than duration will required activate reset function device. Following power-on reset external reset, M581 software compatible with previous generation UARTs. Internal Registers M581 16550 compatible registers controlling, monitoring data loading unloading. These registers function data holding registers (THR/RHR), interrupt status control registers (ISR/IER), FIFO control register (FCR), receive line status control registers (LSR/LCR), modem status control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), user accessible scratchpad register (SPR). Beyond general 16C550 features capabilities, M581 offers enhanced feature registers (EFR, Xon1/ Xoff Xon2/Xoff DLD, FCTR, EMSR, TRIG) that provide automatic hardware flow control, automatic Xon/Xoff software flow control, 9-bit (Multidrop) mode, auto RS-485 half duplex control, different baud rate fractional baud rate generator. register functions discussed full detail later "Section 3.0, UART INTERNAL REGISTERS" page Ouput interrupt outputs change according operating mode enhanced features setup. Table summarize operating behavior transmitter receiver. Also Figure through TABLE OPERATION TRANSMITTER
BIT-0 (FIFO DISABLED) byte HIGH empty BIT-0 (FIFO ENABLED) FIFO above trigger level HIGH FIFO below trigger level FIFO empty
TABLE OPERATION RECEIVER
BIT-0 (FIFO DISABLED) HIGH byte empty BIT-0 (FIFO ENABLED) FIFO below trigger level HIGH FIFO above trigger level Data Timeout
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE Crystal Oscillator External Clock Input
REV. 1.0.0
M581 includes on-chip oscillator produce clock baud rate generators device when crystal connected between XTAL1 XTAL2 show below. data does require this clock operation. crystal oscillator provides system clock Baud Rate Generators (BRGs) UART. XTAL1 input oscillator external clock buffer input with XTAL2 being output. programming details, "Section 2.7, Programmable Baud Rate Generator with Fractional Divisor" page FIGURE TYPICAL CRYSTAL CONNECTIONS
XTAL1
XTAL2 0-120 (Optional) 1.8432
500K 22-47pF 22-47pF
on-chip oscillator designed industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 capacitance load, 20-120 ohms 100ppm frequency tolerance) connected externally between XTAL1 XTAL2 pins. Typical oscillator connections shown Figure Alternatively, external clock connected XTAL1 clock internal baud rate generator standard custom rates. package XTAL1 only, external clock required. further reading oscillator circuit, application note DAN108 EXAR's site.
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
Programmable Baud Rate Generator with Fractional Divisor
M581 independent Baud Rate Generators (BRGs) with prescalers transmitter receiver. prescalers controlled software register. register bit-7 sets prescalers divide input crystal external clock output prescaler clocks BRG. further divides this clock programmable divisor between (216 0.0625) increments 0.0625 obtain sampling clock serial data rate. sampling clock used transmitter data shifting receiver data sampling. transmitter receiver, M581 provides respective divisors. divisor (DLL, DLM, registers) defaults value (DLL 0x01, 0x00 0x00) upon reset. Therefore, must programmed during initialization operating data rate. registers provide integer part divisor registers provides fractional part divisor. four lower bits used select value from (for setting 0000) 0.9375 15/16 (for setting 1111). Programming Baud Rate Generator Registers DLL, provides capability selecting operating data rate. Table shows standard data rates available with 24MHz crystal external clock clock rate. pre-scaler used (MCR bit-7 output data rate will times less than that shown Table sampling rate, these data rates would double. sampling rate, they would quadruple. Also, when using sampling mode, please note that bit-time will have jitter (+/- 1/16) whenever non-zero number. When using non-standard data rate crystal external clock, divisor value calculated with following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency prescaler) /(serial data rate 16), with mode, DLD[5:4]='00' Required Divisor (decimal)= (XTAL1 clock frequency prescaler (serial data rate with mode, DLD[5:4] '01' Required Divisor (decimal)= (XTAL1 clock frequency prescaler (serial data rate with mode, DLD[5:4] '10'
closest divisor that obtainable M581 calculated using following formula: ROUND( (Required Divisor TRUNC(Required Divisor) )*16)/16 TRUNC(Required Divisor), where
TRUNC(Required Divisor) TRUNC(Required Divisor) 0xFF ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
formulas above, please note that: TRUNC Integer Part example, TRUNC (5.6) ROUND rounded towards closest integer. example, ROUND (7.3) ROUND (9.9) indicates right shifting value number bits. example, 0x78A3 0x0078. 2.7.1 Independent TX/RX XR16M581 independent sets baud rate generator. Figure work different baud rate setting DLD, register. example, transmit data remote UART 9600 while receives data from remote UART 921.6 Kbps. baud rate setting, please "Section 4.13, Baud Rate Generator Registers (DLL, DLD) Read/Write" page
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE FIGURE BAUD RATE GENERATOR
REV. 1.0.0
DLD[7]=0 Prescaler Divide XTAL1 XTAL2 Crystal Buffer Prescaler Divide (default)
DLD[5:0]
Sampling Rate Clock Transmitter
-7=1 DLD[7]=1
DLD[5:0]
DLD[6]
Sampling Rate Clock Receiver
TABLE TYPICAL DATA RATES WITH CRYSTAL EXTERNAL CLOCK SAMPLING
Required Output Data Rate 2400 4800 9600 10000 19200 25000 28800 38400 50000 57600 75000 100000 115200 153600 200000 225000 230400 250000 300000 400000 460800 500000 750000 921600 1000000 DIVISOR Clock (Decimal) 3750 312.5 156.25 78.125 52.0833 39.0625 26.0417 13.0208 9.7656 6.6667 6.5104 3.75 3.2552 1.6276 DIVISOR OBTAINABLE M581 3750 8/16 4/16 2/16 1/16 1/16 1/16 12/16 8/16 11/16 8/16 12/16 4/16 10/16 8/16 PROGRAM VALUE (HEX) PROGRAM VALUE (HEX) PROGRAM VALUE (HEX) DATA ERROR RATE 0.04 0.08 0.16 0.16 0.31 0.16 0.16 0.16
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
Transmitter
transmitter section comprises 8-bit Transmit Shift Register (TSR) bytes FIFO which includes byte-wide Transmit Holding Register (THR). shifts every data with 16X/8X/4X internal clock. time 16/8/4 clock periods. transmitter sends start-bit followed number data bits, inserts proper parity-bit enabled, adds stop-bit(s). status FIFO reported Line Status Register (LSR bit-5 bit-6). 2.8.1 Transmit Holding Register (THR) Write Only transmit holding register 8-bit register providing data interface host processor. host writes transmit data byte converted into serial data stream including start-bit, data bits, parity-bit stop-bit(s). least-significant-bit (Bit-0) becomes first data out. input register transmit FIFO bytes when FIFO operation enabled bit-0. Every time write operation made THR, FIFO data pointer automatically bumped next sequential data location. 2.8.2 Transmitter Operation non-FIFO Mode host loads transmit data character time. empty flag (LSR bit-5) when data byte transferred TSR. flag generate transmit empty interrupt (ISR bit-1) when enabled bit-1. flag (LSR bit-6) when becomes completely empty. FIGURE TRANSMITTER OPERATION NON-FIFO MODE
Data Byte
Transmit Holding Register (THR)
Interrupt (ISR bit-1) Enabled bit-1
Clock DLD[5:4]
Transmit Shift Register (TSR)
TXNOFIFO1
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE 2.8.3 Transmitter Operation FIFO Mode
REV. 1.0.0
host fill transmit FIFO with bytes transmit data. empty flag (LSR bit-5) whenever FIFO empty. empty flag generate transmit empty interrupt (ISR bit-1) when FIFO becomes empty. transmit empty interrupt enabled bit-1. flag (LSR bit-6) when TSR/FIFO becomes empty. FIGURE TRANSMITTER OPERATION FIFO FLOW CONTROL MODE
Transmit Data Byte
Transmit FIFO
Interrupt (ISR bit-1) falls below programmed Trigger Level then when becomes empty. FIFO Enabled bit-0=1
Auto Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 Xon1/2 Reg.) Auto Software Flow Control
Clock (DLD[5:4])
Transmit Data Shift Register (TSR)
TXFIFO1
Receiver
receiver section contains 8-bit Receive Shift Register (RSR) bytes FIFO which includes byte-wide Receive Holding Register (RHR). uses 16X/8X/4X clock (DLD[5:4]) timing. verifies validates every incoming character middle each data bit. falling edge start false start bit, internal receiver counter starts counting 16X/8X/4X clock rate. After clocks start period should center start bit. this time start sampled still logic validated. Evaluating start this manner prevents receiver from assembling false character. rest data bits stop bits sampled validated this same manner prevent false framing. there were error(s), they reported register bits 2-4. Upon unloading receive data byte from RHR, receive FIFO pointer bumped error tags immediately updated reflect status data byte register. generate receive data ready interrupt upon receiving character delay until reaches FIFO trigger level. Furthermore, data delivery host guaranteed receive data ready time-out interrupt when data received word lengths defined LCR[1:0] plus bits time. This equivalent 3.7-4.6 character times. interrupt enabled bit-0. Figure Figure below. 2.9.1 Receive Holding Register (RHR) Read-Only Receive Holding Register 8-bit register that holds receive data byte from Receive Shift Register. provides receive data interface host processor. register part receive FIFO bytes 11-bits wide, extra bits error tags reported register. When FIFO enabled bit-0, contains first data character received FIFO. After read, next character byte loaded into errors associated with current data byte immediately updated bits 2-4.
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
FIGURE RECEIVER OPERATION NON-FIFO MODE
Clock DLD[5:4]
Receive Data Shift Register (RSR)
Data Validation
Receive Data Characters
Receive Data Byte Errors
Error Tags bits
Receive Data Holding Register (RHR)
Interrupt (ISR bit-2)
RXFIFO1
FIGURE RECEIVER OPERATION FIFO AUTO FLOW CONTROL MODE
lock [5:4]
eceive Shift egister
alidation
eceive haracters
bytes 11-bit FIFO
FIFO trigger level selected bytes (See Below falls Error Tags (16-sets)
eceive FIFO
re-asserts data falls below flow control trigger level restart transm itter. Enable bit-6=1, bit-1. Interrupt bit-2) program desired FIFO trigger level. FIFO Enabled bit-0=1 de-asserts data fills above flow control trigger level suspend transm itter. Enable bit-6=1, bit-1.
FIFO Trigger=8
fills Error Tags bits
eceive Byte Errors
eceive
XFIFO
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE 2.10 Auto (Hardware) Flow Control
REV. 1.0.0
Automatic hardware flow control used prevent data overrun local receiver FIFO. RTS# output used request remote unit suspend/resume data transmission. auto flow control features enabled specific application requirement (see Figure 12):
Enable auto flow control using bit-6. auto function must started asserting RTS# output (MCR bit-1 logic after enabled).
using Auto interrupt:
Enable interrupt through bit-6 (after setting bit-4). UART issues interrupt when
RTS# makes transition from high: bit-5 will logic 2.11 Auto Hysteresis With Auto function enabled, interrupt generated when receive FIFO reaches selected trigger level. RTS# will forced HIGH (RTS off) until receive FIFO reaches trigger level above selected trigger level trigger table (Table RTS# will return after FIFO unloaded level below selected trigger level. Under above described conditions, M581 will continue accept data until receive FIFO gets full. Auto function initiated when RTS# output asserted (RTS On). TABLE AUTO (HARDWARE) FLOW CONTROL
TRIGGER LEVEL ACTIVATION RTS# DE-ASSERTED (HIGH) (CHARACTERS FIFO) RTS# ASSERTED (LOW) (CHARACTERS FIFO)
2.12
Auto Flow Control
Automatic flow control used prevent data overrun remote receiver FIFO. CTS# input monitored suspend/restart local transmitter. auto flow control feature selected specific application requirement (see Figure 12):
Enable auto flow control using bit-7.
needed, interrupt enabled through bit-7 (after setting bit-4). UART issues interrupt when CTS# de-asserted (HIGH): bit-5 will UART will suspend
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
transmission soon stop character process shifted out. Transmission resumed after CTS# input re-asserted (LOW), indicating more data sent. FIGURE AUTO FLOW CONTROL OPERATION
Local UART UARTA Receiver FIFO Trigger Reached Auto Trigger Level Transmitter Auto Monitor Remote UART UARTB Transmitter Auto Monitor Receiver FIFO Trigger Reached Auto Trigger Level
RTSA#
CTSB#
CTSA# Assert RTS# Begin Transmission
RTSB#
RTSA# CTSB#
Data Starts FIFO INTA (RXA FIFO Interrupt) Receive Data FIFO Trigger Level
Suspend
Restart
High Threshold
Threshold
FIFO Trigger Level
RTSCTS1
local UART (UARTA) starts data transfer asserting RTSA# (1). RTSA# normally connected CTSB# remote UART (UARTB). CTSB# allows transmitter send data (3). data arrives fills UARTA receive FIFO (4). When data fills receive FIFO trigger level, UARTA activates data ready interrupt continues receive data into FIFO. interrupt service latency long data being unloaded, UARTA monitors receive data fill level match upper threshold delay de-assert RTSA# (6). CTSB# follows request UARTB transmitter suspend data transfer. UARTB stops finishes sending data bits transmit shift register (8). When receive FIFO data UARTA unloaded match lower threshold delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes change (11) restarts transmitter data flow again until next receive FIFO trigger (12). This same event applies reverse direction when UARTA sends data UARTB with RTSB# CTSA# controlling data flow.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE 2.13 Auto Xon/Xoff (Software) Flow Control
REV. 1.0.0
When software flow control enabled (See Table 15), M581 compares sequential receive data characters with programmed Xoff-1,2 character value(s). receive character(s) (RX) match programmed values, M581 will halt transmission (TX) soon current character completed transmission. When match occurs, Xoff enabled bit-5) flag will interrupt output will activated. Following suspension match Xoff character, M581 will monitor receive data stream match Xon-1,2 character. match found, M581 will resume operation clear flags (ISR bit-4). Reset initially sets contents Xon/Xoff 8-bit flow control registers logic Following reset user write Xon/Xoff value desired software flow control. Different conditions detect Xon/ Xoff characters (See Table suspend/resume transmissions. When double 8-bit Xon/Xoff characters selected, M581 compares consecutive receive characters with software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) controls transmissions accordingly. Under above described flow control mechanisms, flow control characters placed (stacked) user accessible data buffer FIFO. event that receive buffer overfilling flow control needs executed, M581 automatically sends Xoff message (when enabled) serial output remote modem. M581 sends Xoff-1,2 characters two-character-times time taken send characters programmed baud rate) after receive FIFO crosses programmed trigger level. clear this condition, M581 will transmit programmed Xon-1,2 characters soon receive FIFO less than trigger level below programmed trigger level. Table below explains this. TABLE AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
TRIGGER LEVEL ACTIVATION XOFF CHARACTER(S) SENT (CHARACTERS FIFO) CHARACTER(S) SENT (CHARACTERS FIFO)
After trigger level reached, xoff character sent after short span time time required send characters); example, after 2.083ms elapsed 9600 baud 10-bit word length setting.
2.14
Special Character Detect
special character detect feature provided detect 8-bit character when bit-5 Enhanced Feature Register (EFR). When this character (Xoff2) detected, will placed FIFO along with normal incoming data. M581 compares each incoming receive character with Xoff-2 data. match exists, received data will transferred FIFO bit-4 will indicate detection special character. Although Internal Register Table shows Xon, Xoff Registers with eight bits character information, actual number bits dependent programmed word length. Line Control Register (LCR) bits defines number character bits, i.e., either bits, bits, bits, bits. word length selected bits also determines number bits that will used special character comparison. Bit-0 Xon, Xoff Registers corresponds with receive character. 2.15 Normal Multidrop Mode Normal multidrop mode enabled when MSR[6] (requires EFR[4] EFR[5] (Special Character Detect disabled). receiver Force Parity (LCR[5:3] '111') order detect address bytes. With receiver initially disabled, ignores data bytes (parity until address byte received (parity This address byte will cause UART parity error. UART will generate
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
interrupt place address byte FIFO. software then examines byte enables receiver address matches slave address, otherwise, does enable receiver. receiver been enabled, receiver will receive subsequent data. address byte received, will generate interrupt. software again examines byte address matches slave address, does have anything. address does match slave address, then receiver should disabled. 2.15.1 Auto Address Detection Auto address detection mode enabled when MSR[6] (requires EFR[4] bit-5 desired slave address will need written into XOFF2 register. receiver will detect address byte that matches porgrammed character XOFF2 register. received byte data byte address byte that does match programmed character XOFF2 register, receiver will discard these data. Upon receiving address byte that matches XOFF2 character, receiver will automatically enabled already enabled, address character pushed into FIFO along with parity place parity error bit). receiver also generates interrupt. receiver will then receive subsequent data. another address byte received this address does match programmed XOFF2 character, then receiver will automatically disabled address byte ignored. address byte matches XOFF2, receiver will this byte FIFO along with parity parity error bit. 2.16 Infrared Mode M581 UART includes infrared encoder decoder compatible IrDA (Infrared Data Association) version 1.1. IrDA standard that stipulates infrared encoder sends 3/16 wide HIGH-pulse each transmit data stream with data rate 115.2 Kbps. IrDA standard, infrared encoder sends time wide HIGH-pulse each transmit data stream with data rate 1.152 Mbps. This signal encoding reduces on-time infrared LED, hence reduces power consumption. Figure below. infrared encoder decoder enabled setting register bit-6 `1'. With this enabled, infrared encoder decoder compatible IrDA standard. infrared encoder decoder compatible IrDA standard, bit-7 will also need when bit-4 '1'. Likewise, input assumes idle level logic zero from reset power Figure Typically, wireless infrared decoder receives input pulse from infrared sensing diode pin. Each time senses light pulse, returns logic data stream.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE FIGURE INFRARED TRANSMIT DATA ENCODING RECEIVE DATA DECODING
REV. 1.0.0
Character Start Data Bits Stop Time 3/16 Time
IrEncoder-1
Data
Transmit Pulse Pin) Time
Receive Pulse pin)
Time 1/16 Clock Delay
Data
Start
Stop
IRdecoder-1
Data Bits Character
2.17
Sleep Mode with Auto Wake-Up Power-Save feature
M581 supports voltage system designs, hence, sleep mode with auto wake-up power-save feature included reduce power consumption when chip actively used. 2.17.1 Sleep mode these conditions must satisfied M581 enter sleep mode:
interrupts pending (ISR bit-0 sleep mode enabled (IER bit-4 modem inputs toggling (MSR bits input idling HIGH normal mode infrared mode divisor non-zero FIFOs empty
M581 stops crystal oscillator conserve power sleep mode. User check XTAL2 clock output indication that device entered sleep mode. M581 resumes normal operation following:
receive data start transition (HIGH LOW) data byte loaded transmitter, FIFO change logic state modem general purpose serial inputs: CTS#, DSR#, CD#,
M581 awakened above conditions, will return sleep mode automatically after interrupting conditions have been serviced cleared. M581 awakened modem inputs, read required reset modem inputs. case, sleep mode will entered while
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
interrupt pending from channel. M581 will stay sleep mode operation until disabled setting bit-4 logic word caution: owing starting delay crystal oscillator after waking from sleep mode, first receive characters lost. Also, make sure idling HIGH "marking" condition during sleep mode. This occur when external interface transceivers (RS-232, RS-485 another type) also sleep mode cannot maintain "marking" condition. avoid this, system design engineer pull-up resistor each input. 2.17.2 Power-Save Feature address lines, data lines, IOW#, IOR#, modem input lines remain steady when M581 sleep mode, maximum current will microamp range specified Electrical Characteristics page input lines floating toggling while M581 sleep mode, current times more. using Power-Save feature, external buffer would required keep address data lines from toggling floating achieve current. PowerSave feature enabled (PwrSave connected VCC), this will eliminate need external buffer internally isolating address, data control signals (see Figure page from other activities that could cause wasteful power drain. M581 enters Power-Save mode when this connected M581 sleep mode (see Sleep Mode section above). Since Power-Save mode isolates address, data control signals, device will wake-up only
receive data start transition (HIGH LOW) input change logic state modem general purpose serial input CTS#, DSR#, CD#,
M581 will return Power-Save mode automatically after read reset modem input CTS#) interrupting conditions have been serviced cleared. M581 will stay Power-Save mode operation until disabled setting bit-4 logic and/or Power-Save connected GND. 2.17.3 Wake-up Interrupt M581 wake interrupt. setting bit-3, wake interrupt enabled disabled. default status wake interrupt disabled. Please "Section 4.5, FIFO Control Register (FCR) Write-Only" page
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE 2.18 Internal Loopback
REV. 1.0.0
M581 UART provides internal loopback capability system diagnostic purposes. internal loopback mode enabled setting register bit-4 logic regular UART functions operate normally. Figure shows modem port signals re-configured. Transmit data from transmit shift register output internally routed receive shift register input allowing system receive same data that sending. held HIGH mark condition while RTS# DTR# de-asserted, CTS#, DSR# inputs ignored. Caution: input must held HIGH during loopback test else upon exiting loopback test UART detect report false "break" signal. FIGURE INTERNAL LOOPBACK
it-4 Internal Data Lines Control Signals RTS# Modem General Purpose Control Logic RTS#
CTS# DTR#
CTS# DTR#
DSR# OP1# OP2#
DSR#
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
UART INTERNAL REGISTERS complete register M581 shown Table Table TABLE UART INTERNAL REGISTERS
ADDRESSES REGISTER READ/WRITE COMMENTS
16C550 COMPATIBLE REGISTERS DREV Device Revision DVID Device Identification Register Divisor Register Divisor Register Divisor Fractional Register Receive Holding Register Transmit Holding Register Interrupt Enable Register Interrupt Status Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Modem Status Register Scratch Register EMSR Enhanced Mode Select Register RX/TX FIFO Level Counter Register ENHANCED REGISTERS RX/TX FIFO Level Counter Register TRIG RX/TX FIFO Trigger Level Register FCTR Feature Control Register Enhanced Function Xon-1 Character Xon-2 Character Xoff-1 Xoff Character Xoff-2 Xoff Character Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 0xBF Read-only Read-only Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Write-only Read/Write Write-only Read-only 0xBF, FCTR[6] 0xBF EFR[4] 0xBF, FCTR[6] 0xBF LCR[7] EFR[4] 0xBF EFR[4] LCR[7] 0xBF, 0x00, 0x00 LCR[7] 0xBF DLD[7:6] LCR[7] 0xBF, EFR[4]
LCR[7]
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
REV. 1.0.0
TABLE INTERNAL REGISTERS DESCRIPTION. SHADED BITS ENABLED WHEN BIT-4=1
ADDRESS A2-A0 NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers RD/WR Bit-7 Bit-7 CTS# Int. Enable Bit-6 Bit-6 RTS# Int. Enable Bit-5 Bit-5 Xoff Int. Enable Bit-4 Bit-4 Sleep Mode Enable Bit-3 Bit-3 Bit-2 Bit-2 Bit-1 Bit-1 Bit-0 Bit-0
Modem Line LCR[7] Stat. Int. Stat. Empty Data Enable Int. Int. Enable Enable Enable Source Bit-3
Source Source Source LCR[7] Xoff Bit-2 Bit-1 Bit-0 EFR[4]=1 Interrupt Interrupt LCR0xBF FIFO FIFO FIFO FIFO Wake FIFOs EFR[4]=0 Trigger Trigger Trigger Trigger Enable FIFO FIFO Enable Reset Reset Divisor Enable Break Parity Even Parity Parity Enable Stop Bits Word Word Length Length Bit-1 Bit-0 RTS# DTR# Output Output Control Control
FIFOs FIFOs Enabled Enabled
RD/WR
RD/WR
Prescaler
Mode XonAny ENable Empty Empty
Internal Lopback Enable
Output Enable (OP2#)
OP1#
FIFO Global Error
Break Framing Error
Parity Error
Overrun Error Delta DSR#
Data Ready LCR0xBF Delta CTS#
Input Fast
Input Enable 9-bit mode Bit-6
DSR# Input Disable
CTS# Input Disable
Delta
Delta
EMSR
RD/WR
Bit-7
Bit-5
Bit-4
Bit-3 Invert RS485 mode Bit-3
Bit-2 Send immediate Bit-2
Bit-1
Bit-0
LCR0xBF FCTR[6]=0
Xoff interrupt interrupt mode mode select select Bit-7 Bit-6
FIFO FIFO count count control control LCR0xBF bit-1 bit-0 FCTR[6]=1 Bit-1 Bit-0
Bit-5
Bit-4
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
TABLE INTERNAL REGISTERS DESCRIPTION. SHADED BITS ENABLED WHEN BIT-4=1
ADDRESS A2-A0 NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
Baud Rate Generator Divisor DREV DVID Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] LCR0xBF DLL= 0x00 DLM= 0x00 LCR[7] LCR0xBF DLD[7:6] LCR[7] LCR0xBF EFR[4]
RD/WR RD/WR RD/WR
Bit-7 Bit-7 select
Bit-6 Bit-6
Bit-5 Bit-5
Bit-4 Bit-4
Bit-3 Bit-3 Bit-3
Bit-2 Bit-2 Bit-2
Bit-1 Bit-1 Bit-1
Bit-0 Bit-0 Bit-0
Enable Mode Mode Independent Enhanced Registers
TRIG
Bit-7 Bit-7 RX/TX select Auto CTS# Enable
Bit-6 Bit-6 Swap Auto RTS# Enable
Bit-5 Bit-5
Bit-4 Bit-4
Bit-3 Bit-3 RS485 interrupt mode Software Flow Cntl Bit-3 Bit-3 Bit-3 Bit-3 Bit-3
Bit-2 Bit-2 invert Software Flow Cntl Bit-2 Bit-2 Bit-2 Bit-2 Bit-2
Bit-1 Bit-1
Bit-0 Bit-0
FCTR RD/WR
RD/WR
Special Char Select
Enable [7:4], [5:4], FCR[5:3], MCR[7:5], Bit-4 Bit-4 Bit-4 Bit-4
Software Flow Cntl Bit-1 Bit-1 Bit-1 Bit-1 Bit-1
Software Flow Cntl Bit-0 Bit-0 Bit-0 Bit-0 Bit-0
LCR=0XBF
XON1 RD/WR XON2 RD/WR XOFF1 RD/WR XOFF2 RD/WR
Bit-7 Bit-7 Bit-7 Bit-7
Bit-6 Bit-6 Bit-6 Bit-6
Bit-5 Bit-5 Bit-5 Bit-5
INTERNAL REGISTER DESCRIPTIONS Receive Holding Register (RHR) Read- Only Transmit Holding Register (THR) Write-Only SEE"RECEIVER" PAGE SEE"TRANSMITTER" PAGE
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE Interrupt Enable Register (IER) Read/Write
REV. 1.0.0
Interrupt Enable Register (IER) masks interrupts from receive data ready, transmit empty, line status modem status registers. These interrupts reported Interrupt Status Register (ISR). 4.3.1 versus Receive FIFO Interrupt Mode Operation When receive FIFO (FCR BIT-0 receive interrupts (IER BIT-0 enabled, interrupts (see bits status will reflect following: receive data available interrupts issued host when FIFO reached programmed trigger level. will cleared when FIFO drops below programmed trigger level. FIFO level will reflected register when FIFO trigger level reached. Both register status interrupt will cleared when FIFO drops below trigger level. receive data ready (LSR BIT-0) soon character transferred from shift register receive FIFO. reset when FIFO empty. 4.3.2 versus Receive/Transmit FIFO Polled Mode Operation When BIT-0 equals logic FIFO enable; resetting bits enables XR16M581 FIFO polled mode operation. Since receiver transmitter have separate bits either both used polled mode selecting respective transmit receive control bit(s). BIT-0 indicates there data FIFO. BIT-1 indicates overrun error occurred that data FIFO valid. provides type receive data errors encountered data byte RHR, any. BIT-5 indicates empty. BIT-6 indicates when both transmit FIFO empty. BIT-7 indicates data error least character FIFO. IER[0]: Interrupt Enable receive data ready interrupt will issued when data character non-FIFO mode when receive FIFO reached programmed trigger level FIFO mode. Logic Disable receive data ready interrupt (default). Logic Enable receiver data ready interrupt. IER[1]: Interrupt Enable This enables Transmit Ready interrupt which issued whenever becomes empty nonFIFO mode when data FIFO falls below programmed trigger level FIFO mode. empty when this enabled, interrupt will generated. Logic Disable Transmit Ready interrupt (default). Logic Enable Transmit Ready interrupt. IER[2]: Receive Line Status Interrupt Enable register bits logic will generate interrupt inform host controller about error status current data byte FIFO. bit-1 generates interrupt immediately when overrun occurs. bits generate interrupt when character error. However, when EMSR bit-6 changes (default generate interrupt when character received FIFO. Please refer "Section 4.12, Enhanced Mode Select Register (EMSR) Write-only" page
Logic Disable receiver line status interrupt (default). Logic Enable receiver line status interrupt.
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
IER[3]: Modem Status Interrupt Enable
Logic Disable modem status register interrupt (default). Logic Enable modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR[4]
Logic Disable Sleep Mode (default). Logic Enable Sleep Mode. Sleep Mode section further details.
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
Logic Disable software flow control, receive Xoff interrupt. (default) Logic Enable software flow control, receive Xoff interrupt. Software Flow Control section
details. IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
Logic Disable RTS# interrupt (default). Logic Enable RTS# interrupt. UART issues interrupt when RTS# makes transition
from HIGH enabled bit-6). IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
Logic Disable CTS# interrupt (default). Logic Enable CTS# interrupt. UART issues interrupt when CTS# makes transition from
HIGH enabled bit-7). Interrupt Status Register (ISR) Read-Only UART provides multiple levels prioritized interrupts minimize external software interaction. Interrupt Status Register (ISR) provides user with interrupt status bits. Performing read cycle will give user current highest pending interrupt level serviced, others queued serviced next. other interrupts acknowledged until pending interrupt serviced. Interrupt Source Table, Table shows data values (bit 0-5) interrupt priority levels interrupt sources associated with each these interrupt levels. 4.4.1 Interrupt Generation:
bits RXRDY trigger level. RXRDY Time-out 4-char plus bits delay timer. TXRDY trigger level FIFO empty. bits Receive Xon/Xoff/Special character detection Xon, Xoff Special character. CTS# when remote transmitter toggles input (from HIGH) during auto flow control. RTS# when receiver toggles output (from HIGH) during auto flow control. Wakeup interrupt generated when M581 wakes from sleep mode.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE 4.4.2 Interrupt Clearing:
REV. 1.0.0
interrupt cleared read register. RXRDY interrupt cleared reading data until FIFO falls below trigger level. RXRDY Time-out interrupt cleared reading RHR. TXRDY interrupt cleared read register writing THR. interrupt cleared read register. Xoff interrupt cleared read register. EMSR[7]. Special character interrupt cleared read register after next character received.
EMSR[7].
RTS# CTS# flow control interrupts cleared read register. Wakeup interrupt cleared read register.
TABLE INTERRUPT SOURCE PRIORITY LEVEL
PRIORITY LEVEL BIT-5 REGISTER STATUS BITS BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 (Receiver Line Status Register) RXRDY (Receive Data Time-out) RXRDY (Received Data Ready) TXRDY (Transmit Ready) (Modem Status Register) RXRDY (Received Xon, Xoff Special character) CTS#, RTS# change state None (default) Wakeup interrupt SOURCE INTERRUPT
ISR[0]: Interrupt Status
Logic interrupt pending contents used pointer appropriate interrupt
service routine.
Logic interrupt pending (default condition).
ISR[3:1]: Interrupt Status These bits indicate source pending interrupt interrupt priority levels (See Interrupt Source Table ISR[4]: Interrupt Status (requires bit-4 This enabled when bit-4 logic bit-4 indicates that receiver detected data match Xoff, special character(s). ISR[5]: Interrupt Status (requires bit-4 bit-5 indicates that CTS# RTS# changed state from HIGH. ISR[7:6]: FIFO Enable Status These bits logic when FIFOs disabled. They logic when FIFOs enabled.
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
FIFO Control Register (FCR) Write-Only
This register used enable FIFOs, clear FIFOs, transmit/receive FIFO trigger levels, enable wake interrupt. They defined follows: FCR[0]: FIFO Enable
Logic Disable transmit receive FIFO (default). Logic Enable transmit receive FIFOs. This must logic when other bits
written they will programmed. FCR[1]: FIFO Reset This only active when bit-0 `1'.
Logic receive FIFO reset (default) Logic Reset receive FIFO pointers FIFO level counter logic (the receive shift register
cleared altered). This will return logic after resetting FIFO. FCR[2]: FIFO Reset This only active when bit-0 `1'.
Logic transmit FIFO reset (default). Logic Reset transmit FIFO pointers FIFO level counter logic (the transmit shift register
cleared altered). This will return logic after resetting FIFO. FCR[3]: Enable wake interrupt (requires bit-4
Logic Disable wake interrupt (default). Logic Enable wake interrupt.
Please refer "Section 2.17.3, Wake-up Interrupt" page FCR[5:4]: Transmit FIFO Trigger Select (requires bit-4 These bits trigger level transmit FIFO. UART will issue transmit interrupt when number characters FIFO falls below selected trigger level, when gets empty case that FIFO filled over trigger level last re-load. Table below shows selections. Note that receiver transmitter cannot different trigger tables. Whichever selection made last applies both side. FCR[7:6]: Receive FIFO Trigger Select These bits used trigger level receive FIFO. UART will issue receive interrupt when number characters FIFO crosses trigger level. Table shows complete selections. Note that receiver transmitter cannot different trigger tables. Whichever selection made last applies both side.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE TABLE TRANSMIT RECEIVE FIFO TRIGGER TABLE LEVEL SELECTION
BIT-7 BIT-6 BIT-5 BIT-4 RECEIVE TRIGGER LEVEL TRANSMIT TRIGGER LEVEL COMPATIBILITY 16L580
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Line Control Register (LCR) Read/Write
Line Control Register used specify asynchronous data communication format. word character length, number stop bits, parity selected writing appropriate bits this register. LCR[1:0]: Word Length Select These bits specify word length transmitted received.
BIT-1
BIT-0
WORD LENGTH (default)
LCR[2]: Stop-bit Length Select length stop specified this conjunction with programmed word length.
BIT-2
WORD
LENGTH
STOP LENGTH (BIT TIME(S)) (default) 1-1/2
5,6,7,8 6,7,8
LCR[3]: Parity Select Parity parity selected this bit. parity simple used communications data integrity check. Table parity selection summary below.
Logic parity. Logic parity generated during transmission while receiver checks parity error
data character received.
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
LCR[4]: Parity Select parity enabled with bit-3 logic BIT-4 selects even parity format.
Logic Parity generated forcing number logic transmitted character.
receiver must programmed check same format (default).
Logic EVEN Parity generated forcing even number logic transmitted character.
receiver must programmed check same format. LCR[5]: Parity Select parity enabled, BIT-5 selects forced parity format.
BIT-5 logic parity forced (default). BIT-5 logic BIT-4 logic parity forced logical transmit receive
data.
BIT-5 logic BIT-4 logic parity forced logical transmit receive
data. TABLE PARITY SELECTION
BIT-5 BIT-4 BIT-3 PARITY SELECTION parity parity Even parity Force parity mark, HIGH Forced parity space,
LCR[6]: Transmit Break Enable When enabled, Break control causes break condition transmitted (the output forced "space', logic state). This condition remains, until disabled setting bit-6 logic
Logic break condition. (default) Logic Forces transmitter output (TX) "space", logic alerting remote receiver line
break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM/DLD) enable.
Logic Data registers selected. (default) Logic Divisor latch registers selected.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE Modem Control Register (MCR) General Purpose Outputs Control Read/Write
REV. 1.0.0
register used controlling serial/modem interface signals general purpose inputs/outputs. MCR[0]: DTR# Output DTR# modem control output. modem interface used, this output used general purpose output.
Logic Force DTR# output HIGH (default). Logic Force DTR# output LOW.
MCR[1]: RTS# Output RTS# modem control output used automatic hardware flow control enabled bit-6. modem interface used, this output used general purpose output.
Logic Force RTS# output HIGH (default). Logic Force RTS# output LOW. required start Auto Flow Control.
MCR[2]: Reserved OP1# available output M581. available during Internal Loopback Mode. Loopback Mode, this used write state modem interface signal. MCR[3]: Output Enable Enable disable outputs become active three-state. This also used control OP2# signal during internal loopback mode.
Logic output disabled (three state). During internal loopback mode, OP2# HIGH. Logic output enabled (active). During internal loopback mode, OP2# LOW.
TABLE OUTPUT MODES
BIT-3 OUTPUT Three-State Active
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
MCR[4]: Internal Loopback Enable
Logic Disable loopback mode (default). Logic Enable local loopback mode, loopback section Figure
MCR[5]: Xon-Any Enable (requires bit-4
Logic Disable Xon-Any function (for 16C550 compatibility, default). Logic Enable Xon-Any function. this mode, character received will resume transmit operation.
character will loaded into FIFO unless character Xoff character M581 programmed Xon/Xoff flow control. MCR[6]: Infrared Encoder/Decoder Enable (requires bit-4
Logic Enable standard modem receive transmit input/output interface. (Default) Logic Enable infrared IrDA receive transmit inputs/outputs. TX/RX output/input routed
infrared encoder/decoder. data input output levels conform IrDA infrared interface requirement. FIFO need flushed upon enable. While this mode, infrared output will during idle data conditions. MCR[7]: Clock Prescaler Select (requires bit-4
Logic Divide one. input clock from crystal external clock directly Programmable
Baud Rate Generator without further modification, i.e., divide (default).
Logic Divide four. prescaler divides input clock from crystal external clock four
feeds Programmable Baud Rate Generator, hence, data rates become forth. Line Status Register (LSR) Read Only This register provides status data transfers between UART host. bit-2 enabled, will generate interrupt immediately bits will generate interrupt when character with error RHR. LSR[0]: Receive Data Ready Indicator
Logic data receive holding register FIFO (default). Logic Data been received saved receive holding register FIFO.
LSR[1]: Receiver Overrun Flag
Logic overrun error (default). Logic Overrun error. data overrun error condition occurred receive shift register. This happens
when additional data arrives while FIFO full. this case previous data receive shift register overwritten. Note that under this condition data byte receive shift register transferred into FIFO, therefore data FIFO corrupted error. LSR[2]: Receive Data Parity Error
Logic parity error (default). Logic Parity error. receive character does have correct parity information suspect.
This error associated with character available reading RHR. LSR[3]: Receive Data Framing Error
Logic framing error (default). Logic Framing error. receive character have valid stop bit(s). This error associated with
character available reading RHR.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE LSR[4]: Receive Break
REV. 1.0.0
Logic break condition (default). Logic receiver received break signal least character frame time).
FIFO mode, only break character loaded into FIFO. break indication remains until input returns idle condition, "mark" HIGH. LSR[5]: Transmit Holding Register Empty Flag This Transmit Holding Register Empty indicator. logic when last data byte transferred from transmit holding register transmit shift register. reset logic concurrently with data loading transmit holding register host. FIFO mode this when transmit FIFO empty, cleared when transmit FIFO contains least byte. LSR[6]: Empty Flag This logic whenever transmitter goes idle. logic whenever either contains data character. FIFO mode this logic whenever transmit FIFO transmit shift register both empty. LSR[7]: Receive FIFO Data Error Flag
Logic FIFO error (default). Logic global indicator error bits FIFO. least parity error, framing error
break indication FIFO data. This clears when there more error(s) bytes FIFO. Modem Status Register (MSR) Read Only This register provides current state modem interface input signals. Lower four bits this register used indicate changed information. These bits logic whenever signal from modem changes state. These bits used general purpose inputs when they used with modem signals. Reading higher four bits shows status modem signals. MSR[0]: Delta CTS# Input Flag
Logic change CTS# input (default). Logic CTS# input changed state since last time monitored. modem status interrupt
will generated interrupt enabled (IER bit-3). MSR[1]: Delta DSR# Input Flag
Logic change DSR# input (default). Logic DSR# input changed state since last time monitored. modem status interrupt
will generated interrupt enabled (IER bit-3). MSR[2]: Delta Input Flag
Logic change input (default). Logic input changed from HIGH, ending ringing signal. modem status
interrupt will generated interrupt enabled (IER bit-3). MSR[3]: Delta Input Flag
Logic change input (default). Logic Indicates that input changed state since last time monitored. modem
status interrupt will generated interrupt enabled (IER bit-3).
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
MSR[4]: Input Status CTS# function automatic hardware flow control signal input enabled selected Auto (EFR bit-7). Auto Flow Control allows starting stopping local data transmissions based modem CTS# signal. HIGH CTS# will stop UART transmitter soon current character finished transmission, will resume data transmission. Normally bit-4 complement CTS# input. However loopback mode, this equivalent RTS# register. CTS# input used general purpose input when modem interface used. MSR[5]: Input Status Normally this complement DSR# input. loopback mode, this equivalent DTR# register. DSR# input used general purpose input when modem interface used. MSR[6]: Input Status Normally this complement input. loopback mode this equivalent bit-2 register. input used general purpose input when modem interface used. MSR[7]: Input Status Normally this complement input. loopback mode this equivalent bit-3 register. input used general purpose input when modem interface used. 4.10 Modem Status Register (MSR) Write Only This register provides advanced features XR16M581. Lower four bits this register reserved. Writing higher four bits enables additional functions. MSR[3:0]: Reserved MSR[4]: Enable/Disable Transmitter (Requires EFR[4]
Logic Enable Transmitter (default). Logic Disable Transmitter.
MSR[5]: Enable/Disable Receiver (Requires EFR[4]
Logic Enable Receiver (default). Logic Disable Receiver.
MSR[6]: Enable/Disable 9-bit mode (Requires EFR[4] 9-bit mode information, "Section 2.15, Normal Multidrop Mode" page
Logic Normal 8-bit mode (default). Logic Enable 9-bit Multidrop mode.
MSR[7]: Enable/Disable fast mode (Requires EFR[4] M581 supports fast transmission with data rate 1.152 Mbps.
Logic IrDA version 1.0, 3/16 pulse ratio, data rate 115.2 Kbps (default). Logic IrDA version 1.1, pulse ratio, data rate 1.152 Mbps. more mode information, please
"Section 2.16, Infrared Mode" page 4.11 Scratch Register (SPR) Read/Write This 8-bit general purpose register user store temporary data. content this register preserved during sleep mode becomes 0xFF (default) after reset power off-on cycle.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE 4.12 Enhanced Mode Select Register (EMSR) Write-only This register replaces (during Write) accessible only when FCTR[6] EMSR[1:0]: Receive/Transmit FIFO Level Count When Scratchpad Swap (FCTR[6]) asserted, EMSR bits controls what mode FIFO Level Counter operating TABLE SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0] Scratchpad Scratchpad FIFO Level Counter Mode FIFO Level Counter Mode Alternate RX/TX FIFO Counter Mode
REV. 1.0.0
During Alternate RX/TX FIFO Level Counter Mode, first value read after EMSR bits have been asserted will always FIFO Level Counter. second value read will correspond with FIFO Level Counter. next value will FIFO Level Counter again, then FIFO Level Counter forth. EMSR[2]: Send Immediately
Logic send immediately (default). Logic Send immediately. When FIFO enabled this set, next data will written
shift register. Thus, data will sent immediately instead queuing FIFO. Every time, only byte will send out. Once this byte been sent out, EMSR[2] will back automatically. more than byte will sent out, EMSR[2] needs each byte. EMSR[3]: Invert RS485 mode
Logic RTS# output logic during logic during (default). Logic RTS# output logic during logic during
EMSR[5:4]: Reserved EMSR[6]: Interrupt Mode
Logic Interrupt Delayed (default). bits will generate interrupt when character
with error RHR.
Logic Interrupt Immediate. bits will generate interrupt soon character
received into FIFO. EMSR[7]: Xoff/Special character Interrupt Mode Select This selects Xoff Special character interrupt cleared. interrupt only cleared reading register.
Logic Xoff interrupt cleared either reading register when character received.
Special character interrupt cleared either reading register when next character received. (default).
Logic Xoff/Special character interrupt only cleared reading register.
XR16M581
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1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
4.13
Baud Rate Generator Registers (DLL, DLD) Read/Write
These registers make-up value baud rate divisor. M581 different DLL, transmitter receiver. provides more convenience transmitter receiver transmit data with different rate. M581 uses DLD[7:6] select Then provides DLD[5:0] select sampling frequency fractional baud rate divisor. concatenation contents gives 16-bit divisor value. value added DLD[3:0]/16 achieve fractional baud rate divisor. must enabled bit-4 before accessed. Table below "Section 2.7, Programmable Baud Rate Generator with Fractional Divisor" page DLD[5:4]: Sampling Rate Select These bits select data sampling rate. default, data sampling rate 16X. maximum data rate will double mode selected will quadruple mode selected. Table below. TABLE SAMPLING RATE SELECT
DLD[5] DLD[4] SAMPLING RATE
DLD[6]: Independent enable
Logic Transmitter Receiver uses same Baud Rate Generator. (default). Logic Transmitter Receiver uses different Baud Rate Generators. DLD[7] selecting
which baud rate generator configure. DLD[7]: select When DLD[6] this selects whether values written DLL, DLD[5:0] will Transmit Baud Rate Generator Receive Baud Rate Generator. When DLD[6] (same Baud Rate Generator used both RX), this must logic properly write appropriate DLL, DLD[5:0]. TABLE SELECT
DLD[7] DLD[6] Transmitter Receiver uses same BRG. Writing DLL, DLD[5:0] configures both Transmitter Receiver uses different BRGs. Writing DLL, DLD[5:0] configures Transmitter Receiver uses different BRGs. Writing DLL, DLD[5:0] configures Transmitter Receiver uses same BRG. Writing DLL, DLD[5:0] effect used
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE 4.14 Trigger Level Register (TRG) Write-Only User Programmable Transmit/Receive Trigger Level Register. TRG[7:0]: Trigger Level Register These bits used program desired trigger levels when trigger Table-D selected. FCTR bit-7 selects between programming Trigger Level logic Trigger Level logic 4.15 RX/TX FIFO Level Count Register (FC) Read-Only This register replaces (during read) accessible when FCTR[6] This register also accessible when 0xBF. suggested read FIFO Level Count Register Scratchpad Register location when FCTR bit-6 Table FC[7:0]: RX/TX FIFO Level Count Receive/Transmit FIFO Level Count. Number characters Receiver FIFO (FCTR[7] Transmitter FIFO (FCTR[7] read this register. Reading this register recommended when transmitting receiving data. 4.16 Feature Control Register (FCTR) Read/Write FCTR[1:0]: Reserved FCTR[2]: IrDa Inversion
REV. 1.0.0
Logic Select input encoded IrDa data (Idle state will LOW). Logic Select input inverted encoded IrDa data (Idle state will HIGH).
FCTR[3]: Auto RS-485 Direction Control
Logic Standard ST16C550 mode. Transmitter generates interrupt when transmit holding register
becomes empty transmit shift register shifting data out.
Logic Enable Auto RS485 Direction Control function. direction control signal, RTS# pin, changes
output logic state from HIGH time after last stop last character shifted out. Also, Transmit interrupt generation delayed until transmitter shift register becomes empty. RTS# output will automatically return when data byte loaded into FIFO. However, RTS# behavior inverted setting EMSR[3] FCTR[5:4]: Reserved FCTR[6]: Scratchpad Swap
Logic Scratch register selected general read write register. ST16C550 compatible mode. Logic FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number
characters transmit receive FIFO read scratch register when this set. Enhanced Mode Select Register selected when written into. FCTR[7]: Programmable Trigger Register Select
Logic Registers selected Logic Registers selected
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
4.17
Enhanced Feature Register (EFR) Read/Write
Enhanced features enabled disabled using this register. provide single dual consecutive character software flow control selection (see Table 15). When Xon1 Xon2 Xoff1 Xoff2 modes selected, double 8-bit words concatenated into sequential characters. Caution: note that whenever changing flow control bits, always reset bits back logic (disable) before programming setting. EFR[3:0]: Software Flow Control Select Single character dual sequential characters software flow control supported. Combinations software flow control selected programming these bits. TABLE SOFTWARE FLOW CONTROL FUNCTIONS
BIT-3 CONT-3 BIT-2 CONT-2 BIT-1 CONT-1 BIT-0 CONT-0 TRANSMIT RECEIVE SOFTWARE FLOW CONTROL flow control (default reset) transmit flow control Transmit Xon1, Xoff1 Transmit Xon2, Xoff2 Transmit Xon1 Xon2, Xoff1 Xoff2 receive flow control Receiver compares Xon1, Xoff1 Receiver compares Xon2, Xoff2 Transmit Xon1, Xoff1 Receiver compares Xon1 Xon2, Xoff1 Xoff2 Transmit Xon2, Xoff2 Receiver compares Xon1 Xon2, Xoff1 Xoff2 Transmit Xon1 Xon2, Xoff1 Xoff2, Receiver compares Xon1 Xon2, Xoff1 Xoff2 transmit flow control, Receiver compares Xon1 Xon2, Xoff1 Xoff2
EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This enables bits 4-7, bits 4-5, bits 3-5, bits 5-7, modified. After modifying enhanced bits, bit-4 logic latch values. This feature prevents legacy software from altering overwriting enhanced functions once set. Normally, recommended leave enabled, logic
Logic modification disable/latch enhanced features. bits 4-7, bits 4-5, bits 3-5, bits saved retain user settings. After reset, bits 4-7, bits 4-5, bits 3-5, bits 5-7, logic compatible with ST16C550 mode (default).
Logic Enables EFR[3:0] register bits modified user.
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE EFR[5]: Special Character Detect Enable
REV. 1.0.0
Logic Special Character Detect Disabled (default). Logic Special Character Detect Enabled. UART compares each incoming receive character with
data Xoff-2 register. match exists, receive data will transferred FIFO bit-4 will indicate detection special character. Bit-0 corresponds with receive character. flow control comparing Xon1, Xoff1 (EFR [1:0]= `10') then flow control special character work normally. However, flow control comparing Xon2, Xoff2 (EFR[1:0]= `01') then flow control works normally, Xoff2 will FIFO, will generate Xoff interrupt special character interrupt, enabled bit-5. EFR[6]: Auto Flow Control Enable RTS# output used hardware flow control setting bit-6 logic When Auto selected, interrupt will generated when receive FIFO filled programmed trigger level de-asserts HIGH next upper trigger level/hysteresis level. RTS# will return when FIFO data falls below next lower trigger level/hysteresis level. RTS# output must asserted (LOW) before auto take effect. RTS# will function general purpose output when hardware flow control disabled.
Logic Automatic flow control disabled (default). Logic Enable Automatic flow control.
EFR[7]: Auto Flow Control Enable Automatic Flow Control.
Logic Automatic flow control disabled (default). Logic Enable Automatic flow control. Data transmission stops when CTS# input de-asserts logic
Data transmission resumes when CTS# returns logic 4.18 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) Read/Write These registers used programmable software flow control characters xoff1, xoff2, xon1, xon2. more details, Table xoff2 also used auto address detect register when auto 9-bit mode enabled. "Section 2.15.1, Auto Address Detection" page
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE TABLE UART RESET CONDITIONS
REGISTERS RESET STATE
DLM, 0x00 0x01. Only resets these val(Both during power They reset when Reset asserted. EMSR FCTR XON1 XON2 XOFF1 XOFF2 SIGNALS RTS# DTR# HIGH HIGH HIGH Three-State Condition Bits 0x00 Bits 0xXX Bits 0xXX Bits 0x00 Bits 0x00 Bits 0x01 Bits 0x00 Bits 0x00 Bits 0x60 Bits =0xX0 (Read-only) Bits 0000 (Write-only) Bits 0xFF Bits 0x00 Bits 0x00 Bits 0x00 Bits 0x00 Bits 0x00 Bits 0x00 Bits 0x00 Bits 0x00 Bits 0x00 RESET STATE
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
REV. 1.0.0
ABSOLUTE MAXIMUM RATINGS
Power Supply Range Voltage Operating Temperature Storage Temperature Package Dissipation Volts GND-0.3 -40o +85oC -65o +150oC
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN ERROR: 15%)
Thermal Resistance (24-QFN) Thermal Resistance (32-QFN) Thermal Resistance (25-BGA) theta-ja 38oC/W, theta-jc 26oC/W theta-ja 33oC/W, theta-jc 22oC/W theta-ja 166oC/W, theta-jc 98.2oC/W
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: -40O +85OC, 1.62 3.63V
SYMBOL VILCK VIHCK PARAMETER Clock Input Level Clock Input High Level Input Voltage Input High Voltage Output Voltage Output High Voltage ISLEEP/ IPWRSV Test following inputs remain steady state minimize Sleep current: AD0-AD7, IOR#, IOW#, LLA#. Also, input must idle HIGH while asleep. Input Leakage Current Input High Leakage Current Input Capacitance Power Supply Current Sleep Power Save Current 5MHz Test LIMITS 1.8V -0.3 -0.3 LIMITS 2.5V -0.3 -0.3 LIMITS 3.3V -0.3 -0.3 UNITS -200 CONDITIONS
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
Power-Save, UART internally isolates these inputs (except modem inputs Reset pins) therefore eliminating unnecessary external buffers keep inputs steady. SEE"POWER-SAVE FEATURE" PAGE achieve minimum power drain, voltage inputs M581 should lower than supply.
ELECTRICAL CHARACTERISTICS -40O +85OC, 1.62 3.6V, LOAD WHERE APPLICABLE
SYMBOL XTAL1 ECLK TECLK TCSL TLLA TLLAR TLLAW TRDV TWDO TMOD TRSI TSSI TRRI TINT TWRI TSSR PARAMETER UART Crystal Frequency External Clock Frequency External Clock Time Period Address Setup Time Address Hold Time Delay from LLA#/IOR#/IOW# LLA# Strobe Width IOR# Strobe Width Delay from LLA# IOR# Delay from LLA# IOW# Read/Write Cycle Delay Data Access Time Data Disable Time IOW# Strobe Width Data Setup Time Data Hold Time Delay From IOW# Output Delay Interrupt From MODEM Input Delay Reset Interrupt From IOR# Delay From Stop Interrupt Delay From IOR# Reset Interrupt Delay From Start Interrupt Delay From Initial Reset Transmit Start Delay From IOW# Reset Interrupt Delay From Stop RXRDY# LIMITS 1.8V LIMITS 2.5V LIMITS 3.3V UNIT Bclk Bclk Bclk
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE ELECTRICAL CHARACTERISTICS -40O +85OC, 1.62 3.6V, LOAD WHERE APPLICABLE
SYMBOL TSRT TRST Bclk PARAMETER Delay From IOR# Reset RXRDY# Delay From IOW# TXRDY# Delay From Center Start Reset TXRDY# Reset Pulse Width Baud Clock LIMITS 1.8V data rate LIMITS 2.5V LIMITS 3.3V UNIT Bclk
REV. 1.0.0
FIGURE CLOCK TIMING
EXTERNAL CLOCK
FIGURE MODEM INPUT/OUTPUT TIMING
RTS# DTR#
CTS# DSR# TMOD
TMOD
TMOD
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
FIGURE DATA READ TIMING
AD7AD0
Upper Address
Lower Address
Data
TCSL LLA# TLLA TCSL TRDV TLLAR IOR#
FIGURE DATA WRITE TIMING
AD7AD0
Upper Address
Lower Address
Data
TCSL LLA# TLLA TCSL TLLAW IOW#
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE FIGURE RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE]
Start Stop TSSR Byte TSSR Active Data Ready
REV. 1.0.0
D0:D7
D0:D7 TSSR Byte TSSR Active Data Ready
D0:D7 TSSR Byte TSSR Active Data Ready
RXRDY#
IOR#
(Reading data RHR)
RXNFM
FIGURE TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE]
Start Stop
(Unloading) IER[1] enabled
D0:D7
D0:D7
D0:D7
read
read
read
INT*
TWRI TSRT TWRI TSRT TWRI TSRT
TXRDY#
IOW#
(Loading data into THR)
*INT cleared when read when data loaded into THR.
TXNonFIFO
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
FIGURE RECEIVE READY INTERRUPT TIMING [FIFO MODE]
Start
D0:D7 Stop
D0:D7
D0:D7
TSSI
D0:D7
D0:D7 D0:D7
D0:D7
FIFO drops below Trigger Level
TSSR
RXRDY# First Byte Received FIFO IOR#
(Reading data FIFO)
FIFO fills Trigger Level Data Timeout
FIFO Empties
TRRI
RXINTDMA#
FIGURE TRANSMIT READY INTERRUPT TIMING [FIFO MODE]
Start Stop
FIFO Empty
Last Data Byte Transmitted D0:D7 D0:D7 D0:D7 D0:D7 read TSRT D0:D7
(Unloading) IER[1] enabled
D0:D7 read
INT*
FIFO fills trigger level FIFO drops below trigger level
FIFO Empty TWRI
TXRDY#
Data FIFO
IOW#
(Loading data into FIFO)
*INT cleared when read when FIFO fills trigger level.
TXDMA#
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
REV. 1.0.0
PACKAGE DIMENSIONS
Note: actual center metallic size (D2) device-dependent with typical tolerance 0.3mm
Note: control dimension millimeter. INCHES SYMBOL 0.031 0.000 0.006 0.154 0.098 0.007 0.039 0.002 0.010 0.161 0.110 0.012 MILLIMETERS 0.80 0.00 0.15 3.90 2.50 0.18 0.50 0.35 0.20 0.45 1.00 0.05 0.25 4.10 2.80 0.30
0.0197 0.014 0.008 0.018
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
PACKAGE DIMENSIONS
Note: actual center metallic size (D2) device-dependent with typical tolerance 0.3mm
Note: control dimension millimeter. INCHES SYMBOL 0.031 0.000 0.006 0.193 0.138 0.007 0.039 0.002 0.010 0.201 0.150 0.012 MILLIMETERS 0.80 0.00 0.15 4.90 3.50 0.18 0.50 0.35 0.20 0.45 1.00 0.05 0.25 5.10 3.80 0.30
0.0197 0.012 0.008 0.020
XR16M581
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
REV. 1.0.0
PACKAGE DIMENSIONS
corner
corner feature mfger option)
Seating Plane
Note: control dimension millimeter column INCHES SYMBOL 0.028 0.005 0.022 0.114 0.031 0.007 0.024 0.122 MILLIMETERS 0.70 0.13 0.57 2.90 2.00 0.20 0.50 0.30 0.80 0.19 0.61 3.10
0.079 0.008 0.012
0.020
XR16M581
REV. 1.0.0
1.62V 3.63V UART WITH 16-BYTE FIFO VLIO INTERFACE
REVISION HISTORY
DATE February 2009 REVISION 1.0.0 Final Datasheet. DESCRIPTION
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed inaccuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 2009 EXAR Corporation Datasheet February 2009. Send your UART technical inquiry with technical details hotline: uarttechsupport@exar.com. Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
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