XC4000E

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XC4000E High-Reliability Field Programmable Gate Arrays
November 1997 (Version 1.3)
Product Specification Program verification Internal node observability Backward Compatible with XC4000 Devices Development System runs most common computer platforms Interfaces popular design environments Fully automatic mapping, placement routing Interactive design editor design optimization Available class fully compliant Military temperature range only Certified MIL-PRF-38535, appendix (Qualified Manufacturers Listing)
XC4000E High-Reliability Features
System featured Field-Programmable Gate Arrays Select-RAMmemory: on-chip ultra-fast with synchronous write option dual-port option Abundant flip-flops Flexible function generators Dedicated high-speed carry logic Wide edge decoders each edge Hierarchy interconnect lines Internal 3-state capability global low-skew clock signal distribution networks System Performance beyond Flexible Array Architecture Power Segmented Routing Architecture Systems-Oriented Features IEEE 1149.1-compatible boundary scan logic support Individually programmable output slew rate Programmable input pull-up pull-down resistors 12-mA sink current XC4000E output Configured Loading Binary File Unlimited reprogrammability Readback Capability Table XC4000E Field Programmable Gate Arrays Max. Typical Logic Max. Gate Range Gates Bits (Logic RAM) Logic) RAM)* 5,000 6,272 3,000 9,000 10,000 13,000 25,000 12,800 18,432 32,768
Xilinx High-Reliability
XC4000E family supplied under following standard microcircuit drawings (SMDs): XC4005E 5962-97522 XC4010E 5962-97523 XC4013E 5962-97524 XC4025E 5962-97525 more information contact DSCC (Defense Supply Center Columbus) Columbus, Ohio.
Device XC4005E XC4010E XC4013E XC4025E
Matrix
Total CLBs 1,024
Number Flip-Flops 1,120 1,536 2,56
Max. Decode Inputs side
Max. User
7,000 20,000 10,000 30,000 15,000 45,000
Packages PG156, CB164 PG191, CB196 PG223, CB228 PG299, CB228
values Typical Gate Range include 20-30% CLBs used RAM.
November 1997 (Version 1.3)
8-11
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Switching Characteristics
XC4000E Absolute Maximum Ratings
Symbol TSTG TSOL
Note
Description Supply voltage relative Input voltage relative (Note Voltage applied 3-state output (Note Storage temperature (ambient) Maximum soldering temperature 1/16 Junction temperature Ceramic packages
Value -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150 +260
Units
Note
Maximum overshoot undershoot above below must limited either whichever easier achieve. During transitions, device pins undershoot -2.0 overshoot provided this over- undershoot lasts less than Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those listed under Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time affect device reliability.
XC4000E Recommended Operating Conditions
Symbol
Note:
Description Supply voltage relative GND, -55°C +125°C High-level input voltage Low-level input voltage Input signal transition time
inputs inputs
Units
case temperatures above those listed Recommended Operating Conditions, delay parameters increase 0.35% Input output Measurement thresholds are: 1.5V 2.5V CMOS. specifications subject change without notice.
8-12
November 1997 (Version 1.3)
XC4000E Characteristics Over Operating Conditions
Symbol ICCO IRIN* IRLL*
Note Note
Description High-level output voltage -4.0mA, outputs Low-level output voltage 12.0mA, (Note outputs Quiescent FPGA supply current (Note Input output leakage current Input capacitance (sample tested) pull-up (when selected) (sample tested) Horizontal Longline pull-up (when selected) logic
-0.25
-0.02
Units
With outputs simultaneously sinking 12mA, maximum pins. With output current loads, active input Longline pull-up resistors, package pins GND, FPGA configured with development system option. Characterized Only.
XC4000E Global Buffer Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values where global clock input drives vertical clock line each accessible column, where accessible flip-flops clocked global clock net. When fewer vertical clock lines connected, clock distribution faster; when multiple clock lines column driven from same global clock, delay longer. more specific, more precise, worst-case guaranteed data, reflecting actual routing structure, values provided static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature) Speed Grade Device XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E 11.0 11.5 12.5 11.5 12.0 13.0 Units
Description From through Primary buffer, clock From through Secondary buffer, clock
Symbol
November 1997 (Version 1.3)
8-13
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Horizontal Longline Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000E devices unless otherwise noted. following guidelines reflect worst-case values over recommended operating conditions. Speed Grade Symbol Device TIO1
XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E
Description
TBUF driving Horizontal Longline (LL):
11.0 10.5 11.0 12.0 11.0 23.0 29.0 32.0 42.0 10.0 13.5 15.0
Units
going High going High Low, while Low. Buffer constantly active. (Note1) going going from resistive pull-up High active Low. TBUF configured open-drain. (Note1) going going from resistive pull-up floating High active Low. TBUF configured open-drain active buffer with Low. (Note1) going High TBUF going inactive, driving
TIO2
TOFF
going High going from High, pulled single resistor. (Note going High going from High, pulled resistors. (Note1)
TPUS
TPUF
Note
These values include minimum load. static timing analyzer determine delay each destination.
8-14
November 1997 (Version 1.3)
XC4000E Wide Decoder Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000E devices unless otherwise noted. following guidelines reflect worst-case values over recommended operating conditions. Speed Grade Device XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E 15.0 16.0 18.0 12.5 18.0 19.0 21.0 10.5 16.0 17.0 19.0 12.5 18.0 19.0 21.0 Units
Description Full length, both pull-ups, inputs from I-pins
Symbol TWAF
Full length, both pull-ups, inputs from internal logic
TWAFL
Half length, pull-up, inputs from I-pins
TWAO
Half length, pull-up, inputs from internal logic
TWAOL
Notes: These delays specified from decoder input decoder output. Fewer than specified number pullup resistors used, desired. Using fewer pullups reduces power consumption increases delays. static timing analyzer determine delays fewer pullups used.
November 1997 (Version 1.3)
8-15
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000E devices unless otherwise noted. Speed Grade Symbol TILO TIHO THH1O TOPCY TASCY TINCY TSUM TBYP TCKO TICK TIHCK THH1CK THH2CK TDICK TECCK TRCK Units
Description Combinatorial Delays inputs outputs inputs outputs inputs outputs Fast Carry Logic Operand inputs (F1, COUT Add/Subtract input (F3) COUT Initialization inputs (F1, COUT through function generators outputs COUT, bypass function generators Sequential Delays Clock outputs Setup Time before Clock inputs inputs inputs through inputs through inputs inputs inputs S/R, going (inactive)
8-16
November 1997 (Version 1.3)
XC4000E Switching Characteristic Guidelines (continued)
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters measured directly. They derived from benchmark timing patterns that taken device introduction, prior process improvements. more detailed, more precise, more up-todate information, values provided static timing analyzer used simulator. following guidelines reflect worst-case values over recommended operating conditions. They expressed units nanoseconds apply XC4000E devices unless otherwise noted. Speed Grade Device 4005E 4010E 4013E 4025E 4005E 4010E 4013E 4025E 13.0 55.0 70.0 112.0 23.0 60.0 77.0 134.0 Units
Description Hold Time after Clock inputs inputs inputs through inputs inputs inputs going (inactive) Clock Clock High time Clock time Set/Reset Direct Width (High) Delay from inputs S/R, going High Master Set/Reset Width (High Low)
Symbol TCKI TCKIH TCKHH1 TCKDI TCKEC TCKR TRPW TRIO TMRW
Delay from Global Set/Reset
TMRQ
November 1997 (Version 1.3)
8-17
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Edge-Triggered (Synchronous) Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000E devices unless otherwise noted.
Single Port
Write Operation Address write cycle time (clock period) Clock pulse width (active edge) Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock Data valid after clock
Notes:
Speed Grade Size Symbol
Units
16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1
TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS
15.0 15.0 10.3 11.6
Timing 16x1 option identical 16x2 timing. Applicable Read timing specifications identical Level-Sensitive Read timing.
Dual-Port
Write Operation Address write cycle time (clock period) Clock pulse width (active edge) Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock Data valid after clock
Note:
Speed Grade Size Symbol
Units
16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1
TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS
15.0
Applicable Read timing specifications identical Level-Sensitive Read timing.
8-18
November 1997 (Version 1.3)
XC4000E Synchronous (Edge-Triggered) Write Timing
TWPS WCLK TWSS TDSS DATA TASS ADDRESS TILO TAHS TDHS TWHS
TILO
TWOS
DATA
X6461
XC4000E Dual-Port Synchronous (Edge-Triggered) Write Timing
TWPDS WCLK TWSDS TDSDS DATA TASDS ADDRESS TILO TWODS DATA
X6474
TWHDS
TDHDS
TAHDS
TILO
November 1997 (Version 1.3)
8-19
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Level-Sensitive Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000E devices unless otherwise noted. Speed Grade Description Write Operation Address write cycle time Write Enable pulse width (High) Address setup time before Address hold time after setup time before hold time after Read Operation Address read cycle time Data valid after address change Write Enable) Read Operation, Clocking Data into Flip-Flop Address setup time before clock Read During Write Data valid after goes active (DIN stable before Data valid after (DIN changes during Read During Write, Clocking Data into Flip-Flop setup time before clock Data setup time before clock 16x2 32x1 16x2 32x1 TWCK TWCKT TDCK TDCKT 16x2 32x1 16x2 32x1 TWOT TDOT 10.0 12.0 11.0 16x2 32x1 TICK TIHCK 16x2 32x1 16x2 32x1 TRCT TILO TIHO 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWCT TWPT TAST TAHT TDST TDHT Size Symbol Units
Note:
Timing 16x1 option identical 16x2 timing.
November 1997 (Version 1.3)
XC4000E Level-Sensitive Timing Characteristics
ADDRESS
WRITE
WRITE ENABLE
DATA
REQUIRED
READ WITHOUT WRITE
OUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
CLOCK
OUTPUTS VALID (OLD) VALID (NEW)
READ DURING WRITE
WRITE ENABLE
DATA (stable during OUTPUTS VALID VALID
DATA (changing during
VALID (OLD)
OUTPUTS
VALID (PREVIOUS)
VALID (NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE DATA
CLOCK
OUTPUTS
X264
November 1997 (Version 1.3)
8-21
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Guaranteed Input Output Parameters (Pin-to-Pin, I/O)
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Pin-to-pin timing parameters derived from measuring external internal test patterns guaranteed over worst-case operating conditions (supply voltage junction temperature). Listed below representative values typical locations normal clock loading. more specific, more precise, worst-case guaranteed data, reflecting actual routing structure, values provided static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. Values apply XC4000E devices unless otherwise noted. Speed Grade Device
XC4005E XC4010E XC4013E XC4025E
14.0 16.0 16.5
Description Global Clock Output (fast) using
Global Clock-to-Output Delay
Symbol TICKOF
Units
X3202
(Max)
Global Clock Output (slew-limited) using
Global Clock-to-Output Delay
TICKO
X3202
(Max)
XC4005E XC4010E XC4013E XC4025E
18.0 20.0 20.5
Input Setup Time, using delay)
Input Hold Time
TPSUF
(Min)
XC4005E XC4010E XC4013E XC4025E
X3201
Input Hold Time, using delay)
Input Hold Time
TPHF
(Min)
XC4005E XC4010E XC4013E XC4025E
X3201
Input Setup Time, using (with delay)
Input Hold Time
TPSU
(Min)
XC4005E XC4010E XC4013E XC4025E
X3201
Input Hold Time, using (with delay)
Input Hold Time
(Min)
XC4005E XC4010E XC4013E XC4025E
X3201
Output Flip-Flop
Input Flip-Flop Latch
8-22
November 1997 (Version 1.3)
XC4000E Input Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Pin-to-pin timing parameters derived from measuring external internal test patterns guaranteed over worst-case operating conditions (supply voltage junction temperature). Listed below representative values typical locations normal clock loading. more specific, more precise, worst-case guaranteed data, reflecting actual routing structure, values provided static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. Values apply XC4000E devices unless otherwise noted. Speed Grade Device devices devices XC4005E XC4010E XC4013E XC4025E devices devices devices devices 12.0 12.2 12.6 15.0 Units
Description
Propagation Delays (TTL Inputs)
Symbol TPID TPLI TPDLI
transparent latch, delay with delay
Propagation Delays
Clock (IK) (flip-flop) Clock (IK) (latch enable, active Low)
Hold Times (Note
TIKRI TIKLI TIKPI TIKPID
Clock (IK), delay with delay
Note Note
Input setup hold times specified with respect internal clock (IK). setup hold times with respect clock input pin, pin-to-pin parameters Guaranteed Input Output Parameters table. Voltage levels unused pads, bonded unbonded, must valid logic levels. Each configured with internal pullup (default) pull-down resistor, configured driven output, driven from external source.
November 1997 (Version 1.3)
8-23
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Input Switching Characteristic Guidelines (continued)
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000E devices unless otherwise noted. Speed Grade Device devices XC4005E XC4010E XC4013E XC4025E 10.9 11.3 11.8 14.0 Units
Description Setup Times (TTL Inputs) Clock (IK), delay with delay
Symbol TPICK TPICKD
(TTL CMOS) Clock Enable (EC) Clock (IK), delay with delay
TECIK TECIKD
devices XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E XC4005E XC4010E XC4013E XC4025E
10.4 10.7 11.1 14.0 12.0 21.0 23.0 29.0 13.0 55.0 70.0 112.0 15.0 20.3 22.0
Global Set/Reset (Note Delay from through width inactive first active Clock (IK) edge
TRRI
TMRW
TRPO
Note Note Note
Input setup hold times specified with respect internal clock (IK). setup hold times with respect clock input pin, pin-to-pin parameters Guaranteed Input Output Parameters table. Voltage levels unused pads, bonded unbonded, must valid logic levels. Each configured with internal pullup (default) pull-down resistor, configured driven output, driven from external source. Timing based XC4005E. other devices static timing analyzer.
8-24
November 1997 (Version 1.3)
XC4000E Output Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000E devices unless otherwise noted. Speed Grade Symbol TOKPOF TOKPOS TOPF TOPS TTSHZ 11.5 12.0 10.0 Units
Description Propagation Delays (TTL Output Levels) Clock (OK) Pad, fast slew-rate limited Output Pad, fast slew-rate limited 3-state hi-Z (slew-rate independent) 3-state active valid, fast slew-rate limited
Note
TTSONF TTSONS
10.0 13.7
Note
Output timing measured threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times approximately times longer than fast output rise/fall times. effect capacitive loads ground bounce, "Additional XC4000 Data" section Programmable Logic Data Book. Voltage levels unused pads, bonded unbonded, must valid logic levels. Each configured with internal pullup (default) pull-down resistor, configured driven output, driven from external source.
November 1997 (Version 1.3)
8-25
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Output Switching Characteristic Guidelines (continued)
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Propagation Delays, slew-rate fast unless otherwise noted. Values apply XC4000E devices unless otherwise noted. Speed Grade Device Units
Description Setup Hold Output clock (OK) setup time Output clock (OK) hold time Clock Clock High Clock
Note
Symbol TOOK TOKO
Note Note
Output timing measured threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times approximately times longer than fast output rise/fall times. effect capacitive loads ground bounce, "Additional XC4000 Data" section Programmable Logic Data Book. Voltage levels unused pads, bonded unbonded, must valid logic levels. Each configured with internal pullup (default) pull-down resistor, configured driven output, driven from external source. Timing based XC4005E. other devices static timing analyzer.
8-26
November 1997 (Version 1.3)
XC4000E High-Reliability Field Programmable Gate Arrays
November 1997 (Version 1.3)
Device-Specific Pinout Tables
Locations XC4005E Devices
XC4005E Name (A8) (A9) (A10) (A11) (A12) (A13) (A14) I/O, SGCK1 (A15) I/O, PGCK1 (A16) (A17) I/O, I/O, I/O, I/O, SGCK2 (M1) (M0) (M2) I/O, PGCK2 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P157 P158 P160 P161 P162 P163 P164 Bndry Scan XC4005E Name (HDC) (LDC) (INIT) I/O, SGCK3 DONE PROGRAM (D7) I/O, PGCK3 (D6) (D5) (CS0) (D4) (D3) (RS) P100 P101 P102 P103 P104 P105 P106 P107 P108 Bndry Scan XC4005E Name (D2) (D1) (RCLK, RDY/BUSY) (D0, DIN) I/O, SGCK4 (DOUT) CCLK (A0, I/O, PGCK4 (A1) (CS1, (A3) (A4) (A5) (A6) (A7) 8/13/97 P109 P110 P111 P112 P113 P115 P116 P117 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P130 P131 P132 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 Bndry Scan
Additional XC4005E Package Pins
PG156 8/14/97 N.C. Pins
CB164 P133 P159 8/14/97 N.C. Pins P114 P118 P134 P155 P129 P156
November 1997 (Version 1.3)
8-27
XC4000E High-Reliability Field Programmable Gate Arrays
Locations XC4010E Devices
XC4010E Name (A8) (A9) (19) (18) (A10) (A11) (A12) (A13) (A14) I/O, SGCK1 (A15) I/O, PGCK1 (A16) (A17) I/O, I/O, I/O, P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 Bndry Scan XC4010E Name I/O, SGCK2 (M1) (M0) (M2) I/O, PGCK2 (HDC) (LDC) (INIT) I/O, SGCK3 DONE PROGRAM (D7) I/O, PGCK3 P100 P101 P102 P104 Bndry Scan XC4010E Name (D6) (D5) (CS0) (D4) (D3) (RS) (D2) (D1) (RCLK, RDY/BUSY) (D0, DIN) I/O, SGCK4 (DOUT) CCLK (A0, I/O, PGCK4 (A1) (CS1, (A3) (A4) (A5) P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 Bndry Scan
8-28
November 1997 (Version 1.3)
XC4010E Name (A6) (A7) 8/14/97
P167 P168 P169 P170 P171 P172
Bndry Scan
Additional XC4010E Package Pins
CB196 P192 8/14/97 N.C. Pins P103 P152
Locations XC4013E Devices
XC4013E Name (A8) (A9) (A10) (A11) (A12) (A13) (A14) I/O, SGCK1 (A15) I/O, PGCK1(A16) (A17) I/O, I/O, I/O, P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228 Bndry Scan XC4013E Name I/O, SGCK2 (M1) (M0) (M2) I/O, PGCK2 (HDC) (LDC) Bndry Scan XC4013E Name (INIT) I/O, SGCK3 DONE PROGRAM (D7) I/O, PGCK3 (D6) P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 Bndry Scan
November 1997 (Version 1.3)
8-29
XC4000E High-Reliability Field Programmable Gate Arrays
XC4013E Name (D5) (CS0) (D4) (D3) (RS) (D2) P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 Bndry Scan XC4013E Name (D1) (RCLK, RDY/BUSY) (D0, DIN) I/O, SGCK4 (DOUT) CCLK (A0, I/O, PGCK4 (A1) P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 Bndry Scan XC4013E Name (CS1, (A3) (A4) (A5) (A6) (A7) 8/14/97 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 Bndry Scan
Locations XC4025E Devices
XC4025E Name (A8) (A9) (A10) (A11) (A12) (A13) P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 Bndry Scan XC4025E Name (A14) I/O, SGCK1 (A15) I/O, PGCK1 (A16) (A17) I/O, I/O, I/O, P223 P224 P225 P226 P227 P228 Bndry Scan XC4025E Name Bndry Scan
November 1997 (Version 1.3)
XC4025E Name I/O, SGCK2 (M1) (M0) (M2) I/O, PGCK2 (HDC) (LDC) (INIT)
VCC*
Bndry Scan
XC4025E Name I/O, SGCK3 DONE PROGRAM (D7) I/O, PGCK3 (D6) (D5) (CS0)
P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139
Bndry Scan
XC4025E Name (D4) (D3) (RS) (D2) (D1) (RCLK, RDY/BUSY) (D0, DIN) I/O, SGCK4 (DOUT) CCLK (A0, I/O, PGCK4 (A1) (CS1, (A3)
P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189
VCC* GND*
Bndry Scan
November 1997 (Version 1.3)
8-31
XC4000E High-Reliability Field Programmable Gate Arrays
XC4025E Name (A4) (A5) (A6) (A7) 8/14/97 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 Bndry Scan
8-32
November 1997 (Version 1.3)
Ordering Information
Example Part:
Generic Standard Microcircuit Drawing (SMD) Prefix Device Type XC4005E 97522 XC4010E 97523 XC4013E 97524 XC4025E 97525
5962-97523
Lead Finish Gold Package Type Grid Quad Flatpack (Base Mark) Quad Flatpack (Lid Mark) Certified
Speed Grade
Example XC4010E Military Tempeture Only Part:
Device Type XC4005E XC4010E XC4013E XC4025E Temperature Range Military -55o +125o Number Pins
Speed Grade
Package Type Braxed Ceramic Quad Flat Pack Ceramic Grid Array
November 1997 (Version 1.3)
8-33

XC4000E

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