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XC4000 Series Field Programmable Gate Arrays
September 1996 (Version 1.04)
XC4000-Series Features
Note: XC4000-Series devices described this data sheet include XC4000E, XC4000EX, XC4000L, XC4000XL. This information does apply older Xilinx families: XC4000, XC4000A, XC4000D XC4000H. information these devices, Xilinx WEBLINX http://www.xilinx.com. Third Generation Field-Programmable Gate Arrays Select-RAMmemory: on-chip ultra-fast with synchronous write option dual-port option Fully compliant (speed grades faster) Abundant flip-flops Flexible function generators Dedicated high-speed carry logic Wide edge decoders each edge Hierarchy interconnect lines Internal 3-state capability global low-skew clock signal distribution networks System Performance Flexible Array Architecture Systems-Oriented Features IEEE 1149.1-compatible boundary scan logic support Individually programmable output slew rate Programmable input pull-up pull-down resistors 12-mA sink current XC4000E output XC4000L output) Configured Loading Binary File Unlimited reprogrammability Readback Capability Backward Compatible with XC4000 Devices XACTstep Development System runs '386/'486/ Pentium-type Sun-4, Hewlett-Packard series Interfaces popular design environments Fully automatic mapping, placement routing Interactive design editor design optimization RAM/ROM compiler
Additional XC4000EX/XL Features
Highest Capacity Over 130,000 Usable Gates Additional Routing Over XC4000E almost twice routing capacity high-density designs Buffered Interconnect Maximum Speed Latch Capability Configurable Logic Blocks Improved VersaRingI/O Interconnect Better Fixed Pinout Flexibility Flexible High-Speed Clock Network additional Early Buffers shorter clock delays additional FastCLKbuffers fastest clock input Virtually unlimited number clock signals Optional Multiplexer 2-input Function Generator Device Outputs High-Speed Parallel ExpressConfiguration Mode Improved Setup Clock-to-Output with FastCLK Global Early Buffers Additional Address Bits Master Parallel Configuration Mode
Introduction
XC4000-Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide benefits custom CMOS VLSI, while avoiding initial cost, long development cycle, inherent risk conventional masked gate array. result eleven years FPGA design experience feedback from thousands customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered dual-port modes, increased speed, abundant routing resources, new, sophisticated software achieve fully automated implementation complex, high-density, high-performance designs. XC4000 Series currently members, shown Table
Low-Voltage Versions Available
Low-Voltage Devices Function Volts XC4000L: Low-Voltage Versions XC4000E devices XC4000XL: Low-Voltage Versions XC4000EX devices
September 1996 (Version 1.04)
XC4000 Series Field Programmable Gate Arrays
Table XC4000-Series Field Programmable Gate Arrays Logic Max. Typical Total Number Gates Bits Gate Range Logic RAM) Logic) (Logic RAM)* Matrix Blocks Flip-Flops 3,000 3,200 2,000 5,000 5,000 6,272 3,000 9,000 6,000 8,192 4,000 12,000 8,000 10,368 6,000 15,000 10,000 12,800 7,000 20,000 1,120 13,000 18,432 10,000 30,000 1,536 20,000 25,088 13,000 40,000 2,016 25,000 32,768 15,000 45,000 1,024 2,560 28,000 32,768 18,000 50,000 1,024 2,560 36,000 41,472 22,000 65,000 1,296 3,168 44,000 51,200 27,000 80,000 1,600 3,840 52,000 61,952 33,000 100,000 1,936 4,576 62,000 73,728 40,000 130,000 2,304 5,376 Larger Devices Available First Half 1997 Max. Decode Inputs side
Device XC4003E XC4005E/L XC4006E XC4008E XC4010E/L XC4013E/L XC4020E XC4025E XC4028EX/XL XC4036EX/XL XC4044EX/XL XC4052XL XC4062XL
Max. User
values Typical Gate Range include 20-30% CLBs used RAM.
Note: Throughout functional descriptions this document, references XC4000E device family include XC4000L, references XC4000EX device family include XC4000XL, unless explicitly stated otherwise. References XC4000 Series include XC4000E, XC4000EX, XC4000L, XC4000XL families. functionality low-voltage families same corresponding 5-Volt family, except where numerical references made timing, power, current-sinking capability.
written into FPGA from external device (slave, peripheral Express modes). XC4000-Series FPGAs supported powerful sophisticated software, covering every aspect design from schematic behavioral entry, floorplanning, simulation, automatic block placement routing interconnects, creation, downloading, readback configuration stream. Because Xilinx FPGAs reprogrammed unlimited number times, they used innovative designs where hardware changed dynamically, where hardware must adapted different user applications. FPGAs ideal shortening design development cycles, also offer cost-effective solution production rates well beyond 5,000 systems month. lowest high-volume unit cost, design first implemented XC4000E XC4000EX, then migrated Xilinx' compatible HardWire mask-programmed devices. Table shows density performance common circuit functions that implemented XC4000-Series devices.
Description
XC4000-Series devices implemented with regular, flexible, programmable architecture Configurable Logic Blocks (CLBs), interconnected powerful hierarchy versatile routing resources, surrounded perimeter programmable Input/Output Blocks (IOBs). They have generous routing resources accommodate most complex interconnect patterns. devices customized loading configuration data into internal memory cells. FPGA either actively read configuration data from external serial byteparallel PROM (master modes), configuration data
September 1996 (Version 1.04)
Table Density Performance Several Common Circuit Functions XC4000E1 Design Class Memory Function Single Port (read/modify/write) FIFO simultaneous read/write MUXed read/write Shift Register (with enable) Pre-Scaled Counter Loadable Counter Accumulator bit, Filter sample rate parallel serial Parallel Multiplier single stage, register register Address Decoder (internal decode) Parity Checker CLBs Used XC4000E-3 XC4000E-2 Units
Logic
Note:
Most functions faster XC4000EX faster carry logic, direct connects, other additional interconnect.
Taking Advantage Reconfiguration
FPGA devices reconfigured change logic function while resident system. This capability gives system designer degree freedom available with other type logic. Hardware changed easily software. Design updates modifications easy, made products already field. FPGA even recon-
figured dynamically perform different functions different times. Reconfigurable logic used implement system self-diagnostics, create systems capable being reconfigured different environments operations, implement multi-purpose hardware given application. added benefit, using reconfigurable FPGA devices simplifies hardware design debugging shortens product time-to-market.
September 1996 (Version 1.04)
XC4000 Series Field Programmable Gate Arrays
XC4000E XC4000EX Families Compared XC4000
readers already familiar with XC4000 family Xilinx Field Programmable Gate Arrays, major features XC4000-Series devices listed this section. biggest advantages XC4000E XC4000EX devices significantly increased system speed, greater capacity, architectural features, particularly Select-RAM memory. XC4000EX devices also offer many routing features, including special high-speed clock buffers that used capture input data with minimal delay. XC4000E device pinout- bitstream-compatible with corresponding XC4000 device. existing XC4000 bitstream used program XC4000E device. However, since XC4000E includes many features, XC4000E bitstream cannot loaded into XC4000 device. Most XC4000EX devices have corresponding XC4000 devices, because larger arrays. XC4028EX same array size XC4025 XC4025E, bitstream-compatible. However, XC4025, XC4025E, XC4028EX pinout-compatible.
Select-RAM Memory: Edge-Triggered, Synchronous Modes configured synchronous, edge-triggered, write operation. read operation affected this change edge-triggered write. Dual-Port separate option converts 16x2 into 16x1 dual-port with simultaneous Read/Write. function generators each configured either level-sensitive (asynchronous) single-port RAM, edge-triggered (synchronous) single-port RAM, edge-triggered (synchronous) dual-port RAM, combinatorial logic. Configurable Content content loaded configuration time, that starts with user-defined data. Function Generator XC4000-Series devices, function generator more versatile than XC4000. inputs come only from function generators also from three four control input lines. function generator thus totally partially independent other function generators, increasing maximum capacity device. Clock Enable flip-flops each have common clock enable input, which through configuration activated individually input output flip-flop both. This clock enable operates exactly like XC4000 CLB. This feature makes IOBs more versatile, avoids need clock gating. Output Drivers output pull-up structure defaults TTL-like totempole. This driver n-channel pull-up transistor, pulling voltage transistor threshold below Vcc, just like XC4000 outputs. Alternatively, XC4000-Series devices globally configured with CMOS outputs, with p-channel pull-up transistors pulling Vcc. Also, configurable pullup resistor XC4000 Series p-channel transistor that pulls Vcc, whereas XC4000 n-channel transistor that pulls voltage transistor threshold below Vcc. Input Thresholds input thresholds globally configured either (1.2 threshold) CMOS (2.5 threshold), just like XC2000 XC3000 inputs. global adjustments input threshold output level independent each other.
Improvements XC4000E XC4000EX
Increased System Speed Delays FPGA-based designs layout dependent. There rule thumb designers consider-the system clock rate should exceed third half specified toggle rate. Critical portions design, such shift registers simple counters, faster-approximately thirds specified toggle rate. XC4000E XC4000EX devices synchronous system clock rates MHz, internal performance exceed MHz. This increase performance over previous families stems from improvements both device processing system architecture. XC4000Series devices sub-micron triple-layer metal process. addition, many architectural improvements have been made, described below. Compliance XC4000-Series faster speed grades fully compliant. XC4000E XC4000EX devices used implement one-chip solution. Carry Logic speed carry logic chain increased dramatically. Some parameters, such delay carry chain through single (TBYP), have improved much from XC4000 values. "Fast Carry Logic" page more information.
September 1996 (Version 1.04)
Global Signal Access Logic There additional access from global clocks function generator inputs. Configuration Pull-Up Resistors During configuration, three mode pins, have weak pull-up resistors. most popular configuration mode, Slave Serial, mode pins thus left unconnected. three mode inputs individually configured with without weak pull-up pull-down resistors after configuration. PROGRAM input permanent weak pull-up. Soft Start-up Like XC3000A, XC4000-Series devices have "Soft Start-up." When configuration process finished device starts first activation outputs automatically slew-rate limited. This feature avoids potential ground bounce when outputs turned simultaneously. Immediately after start-up, slew rate individual outputs XC4000 family, determined individual configuration option. XC4000 XC4000A Compatibility Existing XC4000 bitstreams used configure XC4000E device. XC4000A bitstreams must recompiled with XC4000E improved routing resources, although devices pin-for-pin compatible.
Faster Input Output fast, dedicated early clock sourced global clock buffers available IOBs. ensure synchronization with regular global clocks, Fast Capture latch driven early clock available. input data initially loaded into Fast Capture latch with early clock, then transferred input flip-flop latch with low-skew global clock. programmable delay input used avoid hold-time requirements. "IOB Input Signals" page more information. Latch Capability CLBs Storage elements XC4000EX configured either flip-flops latches. This capability makes FPGA highly synthesis-compatible. Output From Output Clock multiplexer allows output clock select either output data clock enable output pad. Thus, different data signals share single output pad, effectively doubling number device outputs without requiring larger, more expensive package. This multiplexer also configured ANDgate implement very fast pin-to-pin path. "IOB Output Signals" page more information. Express Configuration Mode slave configuration mode accepts parallel data input. Data processed parallel, rather than serialized internally. Therefore, data rate eight times that conventional configuration modes. Additional Address Bits Larger devices require more bits configuration data. daisy chain several large XC4000EX devices require PROM that cannot addressed eighteen address bits supported XC4000E. XC4000EX family therefore extends addressing Master Parallel configuration mode bits.
Additional Improvements XC4000EX Only
Increased Routing interconnect XC4000EX includes twenty-two additional vertical lines each column CLBs twelve horizontal lines each CLBs. twelve "Quad Lines" each column include optional repowering buffers maximum speed. Additional highperformance routing near IOBs enhances flexibility.
September 1996 (Version 1.04)
XC4000 Series Field Programmable Gate Arrays
Table Count Selected XC4000-Series Soft Macros 7400 Equivalents CLBs `138 `139 `147 `148 `150 `151 `152 `153 `154 `157 `158 `160 `161 `162 `163 `164 `165s `166 `168 `174 `194 `195 `280 `283 `298 `352 `390 `518 `521 Explanation nomenclature single-port edge-triggered dual-port edge-triggered extension level-sensitive Barrel Shifters brlshft4 brlshft8 4-Bit Counters cd4cd cd4cle cd4rle cb4ce cb4cle cb4re 16-Bit Counters cb8ce cb8re cc16ce cc16cle cc16cled Identity Comparators comp4 comp8 comp16 Magnitude Comparators compm4 compm8 compm16 CLBs Multiplexers CLBs m2-1e m4-1e m8-1e m16-1e Registers rd4r rd8r rd16r Shift Registers sr8ce sr16re Decoders d2-4e d3-8e d4-16e Explanation counter nomenclature binary counter counter cascadable binary counter bidirectional loadable clock enable synchronous reset asynchronous clear
RAMs ram16x4 ram16x4s ram16x4d
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Detailed Functional Description
XC4000-Series devices achieve high speed through advanced semiconductor technology improved architecture. XC4000E XC4000EX support system clock rates internal performance excess MHz. Compared older Xilinx FPGA families, XC4000-Series devices more powerful. They offer on-chip edge-triggered dual-port RAM, clock enables flip-flops, wide-input decoders. They more versatile many applications, especially those involving RAM. Design cycles faster combination increased routing resources more sophisticated software.
zero, one, both these inputs outputs other input(s) from outside CLB. can, therefore, implement certain functions nine variables, like parity check expandable-identity comparison sets four inputs. Each contains storage elements that used store function generator outputs. However, storage elements function generators also used independently. These storage elements configured flip-flops both XC4000E XC4000EX devices; XC4000EX they optionally configured latches. used direct input either storage elements. drive other through function generator. Function generator outputs also drive outputs independent storage element outputs. This versatility increases logic capacity simplifies routing. Thirteen inputs four outputs provide access function generators storage elements. These inputs outputs connect programmable interconnect resources outside block.
Basic Building Blocks
Xilinx user-programmable gate arrays include major configurable elements: configurable logic blocks (CLBs) input/output blocks (IOBs). CLBs provide functional elements constructing user's logic. IOBs provide interface between package pins internal signal lines.
Function Generators
Four independent inputs provided each function generators G4). These function generators, with outputs labeled each capable implementing arbitrarily defined Boolean function four inputs. function generators implemented memory look-up tables. propagation delay therefore independent function implemented. third function generator, labeled implement Boolean function three inputs. these inputs optionally functional generator outputs. Alternatively, both these inputs come from outside (H2, H0). third input must come from outside block (H1). Signals from function generators exit outputs. connected output. connected output. used implement following functions: function four variables, plus second function four unrelated variables, plus third function three unrelated variables1 single function five variables function four variables together with some functions variables some functions nine variables.
Three other types circuits also available: 3-State buffers (TBUFs) driving horizontal longlines associated with each CLB. Wide edge decoders available around periphery each device. on-chip oscillator provided.
Programmable interconnect resources provide routing paths connect inputs outputs these configurable elements appropriate networks. functionality each circuit block customized during configuration programming internal static memory cells. values stored these memory cells determine logic functions interconnections implemented FPGA. Each these available circuits described this section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most logic FPGA. principal elements shown Figure number CLBs needed implement selected soft macros shown Table 4-input function generators offer unrestricted versatility. Most combinatorial logic functions need four fewer inputs. However, third function generator provided. function generator three inputs. Either
When three separate functions generated, function outputs must captured flip-flop internal CLB. Only unregistered function generator outputs available from CLB.
September 1996 (Version 1.04)
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XC4000 Series Field Programmable Gate Arrays
SR/H
LOGIC FUNCTION LOGIC FUNCTION F1-F4 LOGIC FUNCTION G1-G4
CONTROL
Bypass
CONTROL Bypass
(CLOCK) Multiplexer Controlled Configuration Program
X6692
Figure Simplified Block Diagram XC4000-Series (RAM Carry Logic functions shown) Implementing wide functions single block reduces both number blocks required delay signal path, achieving both increased capacity speed. versatility function generators significantly improves system speed. addition, design-software tools deal with each function generator independently. This flexibility improves cell usage. Table Storage Element Functionality (active rising edge shown) Mode Power-Up Flip-Flop
Flip-Flops
pass combinatorial output(s) interconnect network, also store combinatorial results other incoming data flip-flops, connect their outputs interconnect network well. edge-triggered D-type flip-flops have common clock clock enable (EC) inputs. Either both clock inputs also permanently enabled. Storage element functionality described Table
Latch Both
Legend:
Don't care Rising edge Reset value. Reset default. Input unconnected (default value) Input High unconnected (default value)
Latches (XC4000EX only)
storage elements also configured latches. latches have common clock clock enable (EC) inputs. Storage element functionality described Table
Clock Input
Each flip-flop triggered either rising falling clock edge. clock shared both storage elements. However, clock individually invertible each storage element. inverter placed clock input automatically absorbed into CLB.
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September 1996 (Version 1.04)
Clock Enable
clock enable signal (EC) active High. shared both storage elements. left unconnected either, clock enable that storage element defaults active state. invertible within CLB.
Data Inputs Outputs
source storage element data input programmable. driven functions Direct (DIN) block input. flip-flops latches drive outputs. fast feed-through paths available, shown Figure two-to-one multiplexer each outputs selects between storage element output control inputs. This bypass sometimes used automated router repower internal signals.
Set/Reset
asynchronous storage element input (SR) configured either reset. This configuration option determines state which each flip-flop becomes operational after configuration. also determines effect Global Set/Reset pulse during normal operation, effect pulse CLB. three set/ reset functions single flip-flop controlled same configuration data bit. set/reset state independently specified each flip-flop. This input also independently disabled either flip-flop. set/reset state specified using INIT attribute, placing appropriate reset flip-flop library symbol. active High. invertible within CLB.
Control Signals
Multiplexers four control inputs Figure into four internal control signals (H1, DIN/ SR/H0, EC). these inputs drive four internal control signals. When logic function enabled, four inputs are: Enable Clock SR/H0 Asynchronous Set/Reset function generator Input DIN/H2 Direct function generator Input function generator Input
Global Set/Reset
separate Global Set/Reset line (not shown Figure sets clears each storage element during power-up, reconfiguration, when dedicated Reset driven active. This global (GSR) does compete with other routing resources; uses dedicated distribution network. Each flip-flop configured either globally reset same that local set/reset (SR) specified. Therefore, flip-flop also GSR. Similarly, reset flip-flop reset both GSR. driven from user-programmable global reset input. this global net, place input input buffer schematic code, driving STARTUP symbol. (See Figure specific location assigned this input using attribute property, just with other user-programmable pad. inverter optionally inserted after input buffer invert sense Global Set/ Reset signal. Alternatively, driven from internal node.
When memory function enabled, four inputs are: Enable Clock Write Enable Data Input and/or function generator Data input function generator (16x1 16x2 modes) Address (32x1 mode).
Using FPGA Flip-Flops Latches
abundance flip-flops XC4000 Series invites pipelined designs. This powerful increasing performance breaking function into smaller subfunctions executing them parallel, passing results through pipeline flip-flops. This method should seriously considered wherever throughput more important than latency. include flip-flop, place appropriate library symbol. example, FDCE D-type flip-flop with clock enable asynchronous clear. corresponding latch symbol (for XC4000EX only) called LDCE. XC4000-Series devices, flip flops used registers shift registers without blocking function generators from performing different, perhaps unrelated task. This ability increases functional capacity devices. setup time specified between function generator inputs clock input Therefore, specified flip-flop setup time includes delay through function generator.
STARTUP IBUF Q1Q4 DONEIN
X5260
Figure Schematic Symbols Global Set/Reset
September 1996 (Version 1.04)
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XC4000 Series Field Programmable Gate Arrays
Using Function Generators
Optional modes each make memory look-up tables function generators usable array Read/Write memory cells. Available modes level-sensitive (similar XC4000/A/H families), edgetriggered, dual-port edge-triggered. Depending selected mode, single configured either 16x2, 32x1, 16x1 array. Supported memory configurations timing modes single- dual-port modes shown Table XC4000-Series devices first programmable logic devices with edge-triggered (synchronous) dual-port accessible user. Edge-triggered simplifies system timing. Dual-port doubles effective throughput FIFO applications. These features individually programmed XC4000-Series CLB. Advantages On-Chip Edge-Triggered on-chip extremely fast. read access time same logic delay. write access time slightly slower. Both access times much faster than off-chip solution, because they avoid delays. Edge-triggered RAM, also called synchronous RAM, feature never before available Field Programmable Gate Array. simplicity designing with edge-triggered RAM, markedly higher achievable performance, significant improvement over existing devices with on-chip RAM. Three application notes available from Xilinx that discuss edge-triggered RAM: "XC4000E Edge-Triggered Dual-Port Capability," "Implementing FIFOs XC4000E RAM," "Synchronous Asynchronous FIFO Designs." three application notes apply both XC4000E XC4000EX RAM.
Configuration Options function generators configured arrays following sizes: 16x1 RAMs: data inputs data outputs with identical preferred, different addressing each 32x1 RAM: data input data output.
function generator configured 16x1 while other function generators used implement function inputs. Additionally, XC4000-Series have either timing modes: Edge-Triggered (Synchronous): data written designated edge clock. acts true clock enable. Level-Sensitive (Asynchronous): external signal acts write strobe.
selected timing mode applies both function generators within when both configured RAM. number read ports also programmable: Single Port: each function generator common read write port Dual Port: both function generators configured together single 16x1 dual-port with write port read ports. Simultaneous read write operations same different addresses supported.
configuration options selected placing appropriate library symbol. Choosing Configuration Mode appropriate choice mode given design should based timing resource requirements, desired functionality, simplicity design process. Recommended usage shown Table difference between level-sensitive, edge-triggered, dual-port only write operation. Read operation timing identical modes operation. Table Mode Selection LevelSensitive Designs? Size (16x1, Registered) Simultaneous Read/Write Relative Performance EdgeTriggered Dual-Port EdgeTriggered effective)
Table Supported Modes EdgeTriggered Timing LevelSensitive Timing
Single-Port Dual-Port
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September 1996 (Version 1.04)
WRITE DECODER LATCH ENABLE
16-LATCH ARRAY
WRITE PULSE
READ ADDRESS
WRITE DECODER LATCH ENABLE
16-LATCH ARRAY
(CLOCK)
WRITE PULSE
READ ADDRESS X6752
Figure
16x2 16x1) Edge-Triggered Single-Port
D1/A4
WRITE DECODER LATCH ENABLE
16-LATCH ARRAY
WRITE PULSE
READ ADDRESS
WRITE DECODER LATCH ENABLE
16-LATCH ARRAY
(CLOCK)
WRITE PULSE
READ ADDRESS X6754
Figure 32x1 Edge-Triggered Single-Port addresses identical)
September 1996 (Version 1.04)
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XC4000 Series Field Programmable Gate Arrays
Inputs Outputs F1-F4 G1-G4 inputs function generators address lines, selecting particular memory cell each look-up table. functionality control signals changes when function generators configured RAM. DIN/ SR/H0 lines become data inputs (D0, Write Enable (WE) input 16x2 memory. When 32x1 configuration selected, acts fifth address data input. contents memory cell(s) being addressed available function-generator outputs. They exit through outputs, captured flip-flop(s). Configuring function generators Read/Write memory does affect functionality other portions CLB, with exception redefinition control signals. 16x2 16x1 modes, function generator used implement Boolean functions flip-flops latch signals. Single-Port Edge-Triggered Mode Edge-triggered (synchronous) simplifies timing requirements. XC4000-Series edge-triggered timing operates like writing data register. Data address presented. register enabled writing logic High write enable input, Then rising falling clock edge loads data into register, shown Figure Complex timing relationships between address, data, write enable signals required, external write enable pulse becomes simple clock enable. active edge WCLK latches address, input data, signals. internal write pulse generated that performs write. Figure Figure block diagrams configured 16x2 32x1 edge-triggered, singleport RAM. relationships between pins inputs outputs single-port, edge-triggered mode shown Table Write Clock input (WCLK) configured active either rising edge (default) falling edge. uses same used clock flip-flops, independently inverted. Consequently, output optionally registered within same
WCLK TWSS TDSS DATA TASS ADDRESS TAHS TDHS TWHS
TWPS
TILO
TWOS
TILO
DATA
X6461
Figure
Edge-Triggered Write Timing
either same clock edge RAM, opposite edge this clock. sense WCLK applies both function generators when both configured RAM. active-High invertible within CLB. Note: pulse following active edge WCLK (TWPS Figure must less than millisecond wide. most applications, this requirement overly restrictive; however, must forgotten. Stopping WCLK this point write cycle could result excessive current even damage larger devices many CLBs configured edge-triggered RAM. Table Single-Port Edge-Triggered Signals Signal (16x2, 16x1) (32x1) F1-F4 G1-G4 (32x1) Function Data
A[3:0] A[4] WCLK (Data Out)
Address Address Write Enable Clock Single Port (Data Out)
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September 1996 (Version 1.04)
Dual-Port Edge-Triggered Mode dual-port mode, both function generators used create single 16x1 array with write port read ports. resulting array read written simultaneously independent addresses. Simultaneous read write operations same address also supported. Dual-port mode always edge-triggered write timing, shown Figure Figure shows simple model XC4000-Series configured dual-port RAM. address port, labeled A[3:0], supplies both read write address function generator. This function generator behaves same 16x1 single-port edge-triggered array. output, Single Port (SPO), appears function generator output. SPO, therefore, reflects data address A[3:0]. other address port, labeled DPRA[3:0] Dual Port Read Address, supplies read address function generator. write address function generator, however, comes from address A[3:0]. output from this 16x1 array, Dual Port (DPO), appears function generator output. DPO, therefore, reflects data address DPRA[3:0].
Therefore, using A[3:0] write address DPRA[3:0] read address, reading only output, FIFO that read write simultaneously easily generated. Simultaneous access doubles effective throughput FIFO. relationships between pins inputs outputs dual-port, edge-triggered mode shown Table Figure block diagram configured this mode. Note: pulse following active edge WCLK (TWPS Figure must less than millisecond wide. most applications, this requirement overly restrictive; however, must forgotten. Stopping WCLK this point write cycle could result excessive current even damage larger devices many CLBs configured edge-triggered RAM. Table Dual-Port Edge-Triggered Signals Signal A[3:0] F1-F4 DPRA[3:0] WCLK G1-G4 Function Data Read Address Write Address Read Address Write Enable Clock Single Port (addressed A[3:0]) Dual Port (addressed DPRA[3:0])
RAM16X1D Primitive (Dual Port Out) DPRA[3:0] AR[3:0] AW[3:0] Registered
Function Generator
(Single Port Out) A[3:0] AR[3:0] AW[3:0] Registered
Function Generator
WCLK
X6755
Figure XC4000-Series Dual-Port RAM, Simple Model
September 1996 (Version 1.04)
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XC4000 Series Field Programmable Gate Arrays
WRITE DECODER LATCH ENABLE
16-LATCH ARRAY
WRITE PULSE
READ ADDRESS
WRITE DECODER
16-LATCH ARRAY
LATCH ENABLE WRITE PULSE READ ADDRESS
(CLOCK)
X6748
Figure 16x1 Edge-Triggered Dual-Port
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September 1996 (Version 1.04)
Single-Port Level-Sensitive Timing Mode Note: Edge-triggered mode recommended designs. Level-sensitive mode, also called asynchronous mode, still supported XC4000-Series backward-compatibility with XC4000 family. Level-sensitive timing simple concept complicated execution. Data address signals presented, then positive pulse write enable (WE) performs write into designated address. indicated "level-sensitive" label, this acts like latch. During High pulse, changing data lines results data written address. Changing address lines while High results spurious data written address-and possibly other addresses well, address lines inevitably change simultaneously. user must generate carefully timed signal. delay signal address lines must carefully verified ensure that does become active until after address lines have settled, that goes inactive before address lines change again. data must stable before after falling edge practical terms, usually generated clock. clock available, falling edge system clock used. However, there inherent risks this approach, since pulse must guaranteed inactive before next rising edge system clock. Several older application notes available from Xilinx that discuss design level-sensitive RAMs. These application notes include XAPP031, "Using XC4000 Capability," XAPP042, "High-Speed Design XC4000."
However, edge-triggered available XC4000 Series superior level-sensitive almost every application. Figure shows write timing level-sensitive, singleport RAM. relationships between pins inputs outputs single-port level-sensitive mode shown Table Figure Figure show block diagrams configured 16x2 32x1 level-sensitive, single-port RAM. Initializing Configuration Both implementations XC4000Series devices initialized during configuration. initial contents defined INIT attribute property attached symbol, described schematic library guide. defined, contents initialized zeros, default. initialization occurs only during configuration. content affected Global Set/Reset. Table Single-Port Level-Sensitive Signals Signal A[3:0] F1-F4 G1-G4 Function Data Address Write Enable Data
ADDRESS
WRITE ENABLE
DATA REQUIRED
X6462
Figure Level-Sensitive Write Timing
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XC4000 Series Field Programmable Gate Arrays
Enable
WRITE DECODER
16-LATCH ARRAY
READ ADDRESS
Enable
WRITE DECODER
16-LATCH ARRAY
X6746
READ ADDRESS
Figure 16x2 16x1) Level-Sensitive Single-Port
D1/A4
Enable
WRITE DECODER
16-LATCH ARRAY
READ ADDRESS
Enable
WRITE DECODER
16-LATCH ARRAY
READ ADDRESS X6749
Figure 32x1 Level-Sensitive Single-Port addresses identical)
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Fast Carry Logic
Each function generator contains dedicated arithmetic logic fast generation carry borrow signals. This extra output passed function generator adjacent CLB. carry chain independent normal routing resources. Dedicated fast carry logic greatly increases efficiency performance adders, subtractors, accumulators, comparators counters. also opens door many applications involving arithmetic operation, where previous generations FPGAs were fast enough inefficient. High-speed address offset calculations microprocessor graphics systems, high-speed addition digital signal processing typical applications. 4-input function generators configured 2-bit adder with built-in hidden carry that expanded length. This dedicated carry circuitry fast efficient that conventional speed-up methods like carry generate/propagate meaningless even 16-bit level, marginal benefit 32-bit level. This fast carry logic more significant features XC4000 Series, speeding arithmetic counting into range. carry chain XC4000E devices either down. bottom columns where there CLBs above below, carry propagated right. (See Figure 11.) order improve speed high-capacity XC4000EX devices, which potentially have very long carry chains, carry chain travels upward only, shown Figure This restriction should have little impact, because smallest XC4000EX device, XC4028EX, accommodate 64-bit carry chain single column. Additionally, standard interconnect used route carry signal downward direction. Figure page shows XC4000E with dedicated fast carry logic. carry logic XC4000EX similar, except that COUT exits only, signal CINDOWN does exist. shown Figure carry logic shares operand control inputs with function generators. carry outputs connect function generators, where they combined with operands form sums. Figure Figure page show details carry logic XC4000E XC4000EX respectively. These diagrams show contents labeled "CARRY LOGIC" Figure shown, XC4000EX carry logic eliminated multiplexer reduce delay pass-through carry chain. Additionally, multiplexer path memory-programmable input, which permits directly connect COUT. thus becomes additional high-speed initialization path carry-in.
dedicated carry logic discussed detail Xilinx document XAPP 013: "Using Dedicated Carry Logic XC4000." This discussion also applies XC4000E devices, XC4000EX devices when minor logic changes taken into account. fast carry logic accessed placing special library symbols, using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.
X6687
Figure Available XC4000E Carry Propagation Paths
X6610
Figure Available XC4000EX Carry Propagation Paths (dotted lines general interconnect)
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XC4000 Series Field Programmable Gate Arrays
CARRY LOGIC
DOWN
CARRY
COUT0
CARRY
X6699
Figure Fast Carry Logic XC4000E (shaded area present XC4000EX)
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OUT0 FUNCTION GENERATORS
X2000
DOWN
Figure Detail XC4000E Dedicated Carry Logic
COUT
COUT0 X6701 FUNCTION GENERATORS
Figure Detail XC4000EX Dedicated Carry Logic (shaded areas show differences from XC4000E carry logic)
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XC4000 Series Field Programmable Gate Arrays
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide interface between external package pins internal logic. Each controls package configured input, output, bidirectional signals. Figure shows simplified block diagram XC4000E IOB. more complete diagram XC4000E found Figure page "Boundary Scan" section. Figure includes boundary scan logic IOB. Figure shows simplified block diagram XC4000EX IOB. XC4000EX contains some special features included XC4000E IOB. These features highlighted Figure discussed throughout this section. When XC4000EX special features discussed, they clearly identified text. feature identified present both XC4000E XC4000EX devices.
Table Supported Sources XC4000-Series Device Inputs XC4000-Series Inputs CMOS CMOS Danger1 Unreliable Data
Source device, CMOS outputs XC4000-Series, outputs device, outputs (Voh device, CMOS outputs
Acceptable XC4000XL designated 5-Volt supply (VTT) tied
Registered Inputs signals that exit block each carry either direct registered input signal. input output storage elements each have common clock enable input, which, through configuration, activated individually input output flip-flop, both. This clock enable operates exactly like XC4000-Series CLB. cannot inverted within IOB. storage element behavior shown Table Table Input Register Functionality (active rising edge shown) Mode Power-Up Flip-Flop Latch Both
Legend:
Input Signals
paths, labeled Figure Figure bring input signals into array. Inputs also connect input register that programmed either edgetriggered flip-flop level-sensitive latch. choice made placing appropriate library symbol. example, basic input flip-flop (rising edge triggered), basic input latch (transparent-High). Variations with inverted clocks available, some combinations latches flip-flops implemented single IOB, described XACT Libraries Guide. inputs globally configured either (1.2V, default) CMOS thresholds, using option MakeBits program. There slight hysteresis about 300mV. output levels also configurable; global adjustments input threshold output level independent. Inputs low-voltage devices must configured CMOS times. They driven outputs 5-Volt XC4000-Series devices, provided that 5-Volt outputs mode. They also driven output that does exceed 5-Volt XC3000-family device outputs, example, TTL-compatible, since output voltage exceed they cannot used drive XC4000L XC4000XL input. inputs XC4000-Series 5-Volt devices driven outputs 3.3-Volt device, 5-Volt inputs mode. Supported sources XC4000-Series device inputs shown Table
Clock
Clock Enable
Don't care Rising edge Reset value. Reset default. Input unconnected (default value) Input High unconnected (default value)
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September 1996 (Version 1.04)
Slew Rate Control
Passive Pull-Up/ Pull-Down
Flip-Flop Output Clock FlipFlop/ Latch Delay Input Buffer Output Buffer
Clock Enable Input Clock
X6704
Figure Simplified Block Diagram XC4000E
Slew Rate Control
Passive Pull-Up/ Pull-Down
Output
Flip-Flop Output Clock Flip-Flop/ Latch
Delay Delay
Output Buffer Input Buffer
Clock Enable
Fast Capture Latch
Latch
Input Clock
X5984
Figure Simplified Block Diagram XC4000EX (shaded areas indicate differences from XC4000E)
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XC4000 Series Field Programmable Gate Arrays
Optional Delay Guarantees Zero Hold Time data input register optionally delayed several nanoseconds. With delay enabled, setup time input flip-flop increased that normal clock routing does result positive hold-time requirement. positive hold time requirement lead unreliable, temperature- processing-dependent operation. input flip-flop setup time defined between data measured device clock input (not clock pin). routing delay from device clock clock input must, therefore, subtracted from this setup time arrive real setup time requirement relative device pins. short specified setup time might, therefore, result negative setup time device pins, i.e., positive hold-time requirement. When delay inserted data line, more clock delay tolerated without causing positive hold-time requirement. Sufficient delay eliminates possibility data hold-time requirement external pin. maximum delay therefore inserted default. XC4000E one-tap delay element: either delay inserted (default), not. delay guarantees zero hold time with respect clocks routed through XC4000E global clock buffers. (See "Global Nets Buffers (XC4000E only)" page description global clock buffers XC4000E.) shorter input register setup time, with non-zero hold, attach NODELAY attribute property flip-flop. XC4000EX two-tap delay element, with choices full delay, partial delay, delay. attributes properties used select desired delay shown Table choices added attribute, MEDDELAY, NODELAY. default setting, with added attribute, ensures hold time with respect XC4000EX clock buffers, including Global LowSkew buffers. MEDDELAY ensures hold time with respect Global Early FastCLK buffers. Inputs with NODELAY have positive hold time with respect clock buffers, including FastCLK buffers. description each these buffers, "Global Nets Buffers (XC4000EX only)" page Table XC4000EX Input Delay Element Value full delay (default, attribute added) MEDDELAY NODELAY When Zero Hold with respect Global LowSkew Buffer, Global Early Buffer, FastCLK Buffer Zero Hold with respect Global Early Buffer FastCLK Buffer Short Setup, positive Hold time
Additional Input Latch Fast Capture (XC4000EX only) XC4000EX additional optional latch input. This latch, shown Figure clocked output clock clock used output flip-flop rather than input clock. Therefore, different clocks used clock input storage elements. This additional latch allows very fast capture input data, which then synchronized internal clock flip-flop latch. this Fast Capture technique, drive output clock (the Fast Capture latching signal) from output Global Early FastCLK buffers supplied XC4000EX. second storage element should clocked Global Low-Skew buffer, synchronize incoming data internal logic. (See Figure 18.) These special buffers described "Global Nets Buffers (XC4000EX only)" page Fast Capture latch designed primarily with Global Early buffer. Fast Capture, single clock signal routed through both Global Early buffer Global Low-Skew buffer. (The buffers share input pad.) Fast Capture latch clocked Global Early buffer, standard flip-flop latch clocked Global Low-Skew buffer. This mode safest Fast Capture latch, because clock buffers both storage elements driven same pad. There external skew between clock pads create potential problems. Alternatively, FastCLK buffer used minimize setup time device inputs, positive hold time acceptable. FastCLK buffer clock Fast Capture latch, slower clock buffer clock standard flip-flop latch. Either Global Early buffer Global Low-Skew buffer used second storage ele-
ILFFX
IPAD internal logic
BUFGE IPAD BUFGLS
ILFFX
IPAD internal logic
IPAD BUFFCLK IPAD BUFGLS
NODELAY
X6705
Figure Examples Using XC4000EX Fast Capture Latch
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September 1996 (Version 1.04)
ment, whichever used should same clock related internal logic. Since FastCLK pads different from Global Early Global Low-Skew pads, care must taken ensure that skew external device does create internal timing difficulties. place Fast Capture latch design, special library symbols, ILFFX ILFLX. ILFFX transparent-Low Fast Capture latch followed active-High input flip-flop. ILFLX transparent-Low Fast Capture latch followed transparent-High input latch. clock inputs inverted before driving library element, inverter absorbed into IOB. single BUFG output used drive both clock inputs, software automatically runs clock through both Global Low-Skew buffer Global Early buffer, clocks Fast Capture latch appropriately. Figure page also shows two-tap delay input. default, Fast Capture latch used, Xilinx software assumes Global Early buffer driving clock, selects MEDDELAY ensure zero hold time. This default overridden remove delay, FastClk used, attaching NODELAY attribute property ILFFX ILFLX latch. Select desired delay based discussion previous subsection.
Table Output Flip-Flop Functionality (active rising edge shown) Mode Power-Up Flip-Flop Clock Clock Enable
Legend:
Don't care Rising edge Reset value. Reset default. Input unconnected (default value) Input High unconnected (default value) 3-state
default, output pull-up structure configured TTL-like totem-pole. High driver n-channel pullup transistor, pulling voltage transistor threshold below Vcc. Alternatively, outputs globally configured CMOS drivers, with p-channel pull-up transistors pulling Vcc. This MakeBits option applies outputs device. individually programmable. Outputs low-voltage devices must configured CMOS times. They drive inputs 5-Volt device with TTL-compatible thresholds. XC4000-Series 5-Volt device with outputs configured mode drive inputs typical 3.3Volt device. (For detailed discussion interface between devices, Products section Programmable Logic Data Book.) Supported destinations XC4000-Series device outputs shown Table Table Supported Destinations XC4000-Series Outputs XC4000-Series Outputs Destination CMOS CMOS typical device, some1 CMOS-threshold inputs device, TTL-threshold inputs Unreliable device, Data CMOS-threshold inputs
Only destination device tolerant inputs
Output Signals
Output signals optionally inverted within IOB, pass directly stored edgetriggered flip-flop. functionality this flip-flop shown Table active-High 3-state signal used place output buffer high-impedance state, implementing 3-state outputs bidirectional I/O. Under configuration control, output (OUT) output 3-state signals inverted. polarity these signals independently configured each IOB. 4-mA maximum output current specification many FPGAs often forces user external buffers, which especially cumbersome bidirectional lines. XC4000E XC4000EX devices solve many these problems providing guaranteed output sink current adjacent outputs interconnected externally sink (XC4000L XC4000XL outputs sink adjacent XC4000L XC4000XL outputs sink mA.) XC4000E XC4000EX FPGAs thus directly drive buses printed circuit board.
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XC4000 Series Field Programmable Gate Arrays
OPAD OBUFT
X6702
Figure Open-Drain Output output configured open-drain (open-collector) placing OBUFT symbol schematic code, then tying 3-state output signal, input Ground. (See Figure 19.) Output Slew Rate slew rate each output buffer default, reduced, minimize power transients when switching non-critical signals. critical signals, attach FAST attribute property output buffer flip-flop. XC4000E devices, maximum total capacitive load simultaneous fast mode switching same direction package pins between each Power/Ground pair. XC4000EX devices, additional internal Power/ Ground pairs connected special Power Ground planes within packages, reduce ground bounce. Therefore, maximum total capacitive load between each external Power/Ground pair. Maximum loading vary low-voltage devices. slew-rate limited outputs this total times larger each device type: XC4000E devices XC4000EX devices. This maximum capacitive load should exceeded, result ground bounce greater than amplitude more than duration. This level ground bounce cause undesired transient behavior output, internal logic. This restriction common high-speed digital ICs, particular Xilinx XC4000 Series. XC4000-Series devices have feature called "Soft Startup," designed reduce ground bounce when outputs turned simultaneously configuration. When configuration process finished device starts first activation outputs automatically slew-rate limited. Immediately following initial activation I/O, slew rate individual outputs determined individual configuration option each IOB. Global Three-State separate Global 3-State line (not shown Figure Figure forces FPGA outputs high-impedance state, unless boundary scan enabled executing EXTEST instruction. This global (GTS) does compete with other routing resources; uses dedicated distribution network.
driven from user-programmable global 3-state input. this global net, place input input buffer schematic code, driving STARTUP symbol. specific location assigned this input using attribute property, just with other user-programmable pad. inverter optionally inserted after input buffer invert sense Global 3-State signal. Using similar GSR. Figure page details. Alternatively, driven from internal node. Output Multiplexer/2-Input Function Generator (XC4000EX only) shown Figure page output path XC4000EX contains additional multiplexer available XC4000E IOB. multiplexer also configured 2-input function generator, implementing pass-gate, AND-gate, OR-gate, XOR-gate, with inverted inputs. logic used implement these functions shown upper gray area Figure When configured multiplexer, this feature allows output signals time-share same output pad; effectively doubling number device outputs without requiring larger, more expensive package. When configured 2-input function generator, logic implemented within itself. Combined with either FastCLK Global Early buffer, this arrangement allows very high-speed gating single signal. example, wide decoder implemented CLBs, output gated with Read Write Strobe driven FastCLK buffer, shown Figure critical-path pin-to-pin delay this circuit less than nanoseconds. (This value achievable XC4000XL devices.) shown Figure input pins Out, Output Clock, Clock Enable have different delays different flexibilities regarding polarity. Additionally, Output Clock sources more limited than other inputs. Therefore, Xilinx software does move logic into function generators unless explicitly directed
IPAD BUFFCLK from internal logic OAND2 OPAD FAST
X6698
Figure Fast Pin-to-Pin Path XC4000E
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OMUX2
independent, except that XC4000EX, Fast Capture latch shares input with output clock pin. Early Clock IOBs (XC4000EX only) Special early clocks available IOBs. These clocks sourced same sources Global Low-Skew buffers, separately buffered. They have fewer loads therefore less delay. early clock drive either output clock input clock, both. early clock allows fast capture input data, fast clockto-output output data. Global Early buffers that drive these clocks described "Global Nets Buffers (XC4000EX only)" page Fast Clock IOBs (XC4000EX only) Very fast clocks driven FastCLK buffers also available IOBs. These clocks sourced semi-dedicated pads-the pads used general used drive FastCLK buffers. There FastCLK buffers left edge, right edge device. They provide fastest method reaching clock pins. FastCLK buffer drive either output clock input clock, both. These buffers allow fastest possible setup times clock-to-output times. FastCLK buffers described "Global Nets Buffers (XC4000EX only)" page Global Set/Reset with registers, Global Set/Reset signal (GSR) used clear input output registers, depending value INIT attribute property. flip-flops individually configured clear reset after configuration. Other than global net, user-controlled set/reset signal available flip-flops. choice clear applies both initial state flip-flop response Global Set/Reset pulse. "Global Set/Reset" page description GSR. JTAG Support Embedded logic attached IOBs contains test structures compatible with IEEE Standard 1149.1 boundary scan testing, permitting easy chip board-level testing. More information provided "Boundary Scan" page
OAND2
X6598
X6599
Figure Output Symbols XC4000EX user specify that function generator used, placing special library symbols beginning with letter "O." example, 2-input AND-gate function generator called OAND2. symbol input labelled signal critical path. This signal placed input with shortest delay function generator. examples shown Figure
Other Options
There number other programmable options XC4000-Series IOB. Pull-up Pull-down Resistors Programmable pull-up pull-down resistors useful tying unused pins Ground minimize power consumption reduce noise sensitivity. configurable pull-up resistor p-channel transistor that pulls Vcc. configurable pull-down resistor n-channel transistor that pulls Ground. value these resistors This high value makes them unsuitable wired-AND pull-up resistors. pull-up resistors most user-programmable IOBs active during configuration process. Table page list pins with pull-ups active before during configuration. After configuration, voltage levels unused pads, bonded unbonded, must valid logic levels, reduce noise sensitivity avoid excess current. Therefore, default, unused pads configured with internal pull-up resistor active. Alternatively, they individually configured with pull-down resistor, driven output, driven external source. activate internal pullup, attach PULLUP library component attached pad. activate internal pull-down, attach PULLDOWN library component attached pad. Independent Clocks Separate clock signals provided input output flip-flops. clock independently inverted each flip-flop within IOB, generating either falling-edge rising-edge triggered flip-flops. clock inputs each
Three-State Buffers
pair 3-state buffers associated with each array. (See Figure page 34.) These 3-state buffers used drive signals onto nearest horizontal longlines above below CLB. They therefore used implement multiplexed bidirectional buses horizontal longlines, saving logic resources. Programmable pull-up resistors attached these longlines help implement wide wired-AND function.
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XC4000 Series Field Programmable Gate Arrays
buffer enable active-High 3-state (i.e. activeLow enable), shown Table Another 3-state buffer with similar access located near each block along right left edges array. (See Figure page 39.) horizontal longlines driven 3-state buffers have weak keeper each end. This circuit prevents undefined floating levels. However, overridden driver, even pull-up resistor. Special longlines running along perimeter array used wire-AND signals coming from nearby IOBs from internal longlines. These longlines form wide edge decoders discussed "Wide Edge Decoders" page
WAND4, WAND8, WAND16 also available. XACT Libraries Guide further information. internally tied pin. Connect input output pin. Connect outputs WAND1s together attach PULLUP symbol. Wired OR-AND buffer configured Wired OR-AND. High level either input turns output. WOR2AND library symbol, which essentially opendrain 2-input gate. input pins functionally equivalent. Attach inputs pins output pin. outputs WOR2ANDs together attach PULLUP symbol.
Three-State Buffer Modes
3-state buffers configured three modes: Standard 3-state buffer Wired-AND with input Wired OR-AND
Three-State Buffer Examples
Figure shows 3-state buffers implement wired-AND function. When buffer inputs High, pull-up resistor(s) provide High output. Figure shows 3-state buffers implement multiplexer. selection accomplished buffer 3-state signal. particular attention polarity when using these buffers design. Active-High 3-state identical active-Low output enable, shown Table Table Three-State Buffer Functionality
Standard 3-State Buffer three pins used. Place library element BUFT. Connect input output pin. active-High 3-state (i.e. active-Low enable). Ground implement standard buffer. Wired-AND with Input buffer used Wired-AND. WAND1 library symbol, which essentially open-drain buffer.
WAND1
WAND1
W0R2AND
W0R2AND
X6465
Figure Open-Drain Buffers Implement Wired-AND Function
~100
BUFT "Weak Keeper"
BUFT
BUFT
BUFT
X6466
Figure 3-State Buffers Implement Multiplexer
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Wide Edge Decoders
INTERCONNECT
Dedicated decoder circuitry boosts performance wide decoding functions. When address data field wider than function generator inputs, FPGAs need multi-level decoding thus slower than PALs. XC4000-Series CLBs have nine inputs. decoder nine inputs therefore, compact fast. However, there also need much wider decoders, especially address decoding large microprocessor systems. XC4000-Series FPGA four programmable decoders located each edge device. inputs each decoder signals that edge plus local interconnect column. Each column CLBs provides three variables their compliments., shown Figure Each decoder generates High output (resistor pull-up) when condition selected inputs, their complements, true. This analogous product term typical devices. Each these wired-AND gates capable accepting inputs XC4005E XC4013E. There inputs each decoder XC4028EX XC4052EX. decoders also split when larger number narrower decoders required, maximum decoders device. decoder outputs drive inputs, they combined with other logic form PAL-like AND/OR structure. decoder outputs also routed directly chip outputs. fastest speed, output should same chip edge decoder. Very large PALs emulated ORing decoder outputs CLB. This decoding feature covers what long been considered weakness older FPGAs. Users often resorted external PALs simple fast decoding functions. Now, dedicated decoders XC4000-Series device implement these functions fast efficiently. wide edge decoders, place more WAND library symbols (WAND1, WAND4, WAND8, WAND16). Attach DECODE attribute property each WAND symbol. outputs together attach PULLUP symbol. Location attributes properties such (left edge) (right half edge) should also used ensure correct placement decoder inputs.
X2627
Figure XC4000-Series Edge Decoding Example
On-Chip Oscillator
XC4000-Series devices include internal oscillator. This oscillator used clock power-on time-out, configuration memory clearing, source CCLK Master configuration modes. oscillator runs nominal frequency that varies with process, Vcc, temperature. output frequency falls between MHz. (The oscillator operates more slowly lower voltages. output frequency reduced much low-voltage devices.) oscillator output optionally available after configuration. four resynchronized taps built-in divider also available. These taps fourth, ninth, fourteenth nineteenth bits divider. Therefore, primary oscillator output running nominal MHz, user access clock, plus kHz, 16kHz, 490Hz 15Hz lower low-voltage devices). These frequencies vary much -50% +25%. These signals accessed placing OSC4 library element schematic code (see Figure 25). oscillator automatically disabled after configuration OSC4 symbol used design.
OSC4
F500K F16K F490
X6703
Figure XC4000-Series Oscillator Symbol
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XC4000 Series Field Programmable Gate Arrays
Programmable Interconnect
internal connections composed metal segments with programmable switching points switching matrices implement desired routing. structured, hierarchical matrix routing resources provided achieve efficient automated routing. XC4000E XC4000EX share basic interconnect structure. XC4000EX devices, however, have additional routing available XC4000E. extra routing resources allow high utilization high-capacity devices. XC4000EX-specific routing resources clearly identified throughout this section. resources identified XC4000EX-specific present XC4000-Series devices. This section describes varied routing resources available XC4000-Series devices. implementation software automatically assigns appropriate resources based density timing requirements design.
Routing Connections
high-level diagram routing resources associated with shown Figure shaded arrows represent routing present only XC4000EX devices. Table shows much routing each type available XC4000E XC4000EX arrays. Clearly, very large designs, designs with great deal interconnect, will route more easily XC4000EX. Smaller XC4000E designs, typically requiring significantly less interconnect, require additional routing. Figure page detailed diagram both XC4000E XC4000EX CLB, with associated routing. shaded square programmable switch matrix, present both XC4000E XC4000EX. L-shaped shaded area present only XC4000EX devices. shown figure, XC4000EX block essentially XC4000E block with additional routing. inputs outputs distributed four sides, providing maximum routing flexibility. general, entire architecture symmetrical regular. well suited established placement routing algorithms. Inputs, outputs, function generators freely swap positions within avoid routing congestion during placement routing operation. Table Routing XC4000-Series Devices XC4000E XC4000EX Vertical Horizontal Vertical Horizontal
Interconnect Overview
There several types interconnect. routing associated with each column array. routing forms ring (called VersaRing) around outside array. connects with internal logic blocks. Global routing consists dedicated networks primarily designed distribute clocks throughout device with minimum delay skew. Global routing also used other high-fanout signals.
Five interconnect types distinguished relative length their segments: single-length lines, double-length lines, quad octal lines (XC4000EX only), longlines. XC4000EX, direct connects allow fast data flow between adjacent CLBs, between IOBs CLBs. Extra routing included ring. XC4000EX also includes ring octal interconnect lines near IOBs improve pin-swapping routing locked pins. XC4000E devices include types global buffers, while XC4000EX devices have three different types. These global buffers have different properties, intended different purposes. They discussed detail later this section.
Singles Doubles Quads Longlines Direct Connects Globals Carry Logic Total
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Quad Single Double Long
Direct Connect
Long
Quad
Long
Global Clock
Long
Double Single Global Clock
Carry Direct Chain Connect x5994
Figure High-Level Routing Diagram XC4000-Series (shaded arrows indicate XC4000EX only)
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XC4000 Series Field Programmable Gate Arrays
QUAD
DOUBLE
SINGLE
DOUBLE LONG
DIRECT
FEEDBACK
LONG
Common XC4000E XC4000EX XC4000EX only Programmable Switch Matrix
Figure Detail Programmable Interconnect Associated with XC4000-Series
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Single-Length Lines
Single-length lines provide greatest interconnect flexibility offer fast routing between adjacent blocks. There eight vertical eight horizontal single-length lines associated with each CLB. These lines connect switching matrices that located every column CLBs.
Pass Transistors Switch Matrix Interconnect Point
Double
Singles
Double
Single-length lines connected programmable switch matrices, shown Figure Routing connectivity shown Figure Single-length lines incur delay whenever they through switching matrix. Therefore, they suitable routing signals long distances. They normally used conduct signals within localized area provide branching nets with fanout greater than one.
X6600
Figure Programmable Switch Matrix (PSM)
Programmable Switch Matrices
horizontal vertical single- double-length lines intersect called programmable switch matrix (PSM). Each switch matrix consists programmable pass transistors used establish connections between lines (see Figure 28). example, single-length signal entering right side switch matrix routed single-length line top, left, bottom sides, combination thereof, multiple branches required. Similarly, double-length signal routed double-length line other three edges programmable switch matrix.
Double-Length Lines
double-length lines consist grid metal segments, each twice long single-length lines: they past CLBs before entering switch matrix. Double-length lines grouped pairs with switch matrices staggered, that each line goes through switch matrix every other column CLBs (see Figure 29). There four vertical four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing flexibility. Double-length lines connected programmable switch matrices. Routing connectivity shown Figure
Doubles Singles Doubles
X6601
Figure Single- Double-Length Lines, with Programmable Switch Matrices (PSMs)
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XC4000 Series Field Programmable Gate Arrays
Quad Lines (XC4000EX only)
XC4000EX devices also include twelve vertical twelve horizontal quad lines column. Quad lines four times long single-length lines. They interconnected buffered switch matrices (shown diamonds Figure page 34). Quad lines past four CLBs before entering buffered switch matrix. They grouped fours, with buffered switch matrices staggered, that each line goes through buffered switch matrix every fourth location that column. (See Figure 30.) buffered switch matrixes have four pins, each edge. pins bidirectional. drive other pins.
Each buffered switch matrix contains buffer pass transistors. resembles programmable switch matrix shown Figure with addition programmable buffer. There independent inputs independent outputs. Only independent inputs buffered. place route software automatically uses timing requirements design determine whether quad line signal should buffered. heavily loaded signal typically buffered, while lightly loaded not. scenario alternate buffers pass transistors. This allows both vertical horizontal quad lines buffered alternating buffered switch matrices. buffered switch matrices, quad lines very fast. They provide fastest available method routing heavily loaded signals long distances across device.
X6602
Figure Quad Lines (XC4000EX only)
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Longlines
Longlines form grid metal interconnect segments that entire length width array. Longlines intended high fan-out, time-critical signal nets, nets that distributed over long distances. XC4000EX devices, quad lines preferred critical nets, because buffered switch matrices make them faster high fanout nets. horizontal longlines driven 3-state open-drain drivers (TBUFs). They therefore implement unidirectional bidirectional buses, wide multiplexers, wired-AND functions. (See "Three-State Buffers" page more details.) Each horizontal longline driven TBUFs either (XC4000E) eight (XC4000EX) pull-up resistors. activate these resistors, attach PULLUP symbol longline net. software automatically activates appropriate number pull-ups. There also weak keeper each these horizontal longlines. This circuit prevents undefined floating levels. However, overridden driver, even pull-up resistor. Each XC4000E longline programmable splitter switch center, does each XC4000EX longline driven TBUFs. This switch separate line into independent routing channels, each running half width height array. Each XC4000EX longline driven TBUFs buffered programmable splitter switch 1/4, 1/2, points array. buffering, XC4000EX longline performance does deteriorate with larger array sizes. longline split, resulting partial longlines independent. Routing connectivity longlines shown Figure page
Direct Interconnect (XC4000EX only)
XC4000EX offers direct, efficient fast connections between adjacent CLBs. These nets facilitate data flow from left right side device, from bottom, shown Figure Signals routed direct interconnect exhibit minimum interconnect propagation delay general routing resources. direct interconnect also present between CLBs adjacent IOBs. Each left device edges direct path nearest CLB. Each right bottom edges array direct path nearest IOBs, since there IOBs each column CLBs. place route software uses direct interconnect whenever possible, maximize routing resources minimize interconnect delays.
Figure XC4000EX Direct Interconnect
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X6603
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XC4000 Series Field Programmable Gate Arrays
Routing
XC4000-Series devices have additional routing around ring. This routing called VersaRing. VersaRing facilitates pin-swapping redesign without affecting board layout. Included eight double-length lines spanning CLBs (four IOBs), four longlines. Global lines Wide Edge Decoder lines provided. XC4000EX devices also include eight octal lines. high-level diagram VersaRing shown Figure shaded arrows represent routing present only XC4000EX devices.
Figure detailed diagram XC4000E XC4000EX VersaRing. area shown includes IOBs. There IOBs column, therefore this diagram corresponds routing diagram shown Figure page shaded areas represent routing routing connections present only XC4000EX devices.
Quad Single Double
INTERCONNECT
Long Direct Connect
Long
Direct Connect
Edge Double Long Global Octal Decode Clock
X5995
Figure High-Level Routing Diagram XC4000-Series VersaRing (Left Edge) Wide Edge Decoder, Block (shaded arrows indicate XC4000EX only)
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QUAD
DOUBLE
SINGLE
DOUBLE LONG
DECODER
DIRECT
DECODER
DECODER
LONG
Figure Detail Programmable Interconnect Associated with XC4000-Series (Left Edge)
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Common XC4000E XC4000EX XC4000EX only
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XC4000 Series Field Programmable Gate Arrays
Octal Routing (XC4000EX only)
Between XC4000EX array ring, eight interconnect tracks provide versatility assignment fixed pinout flexibility. (See Figure 34.) These routing tracks called octals, because they broken every eight CLBs (sixteen IOBs) programmable buffer that also functions splitter switch. buffers staggered, each line goes through buffer every eighth location around device edge. octal lines bend around corners device. lines cross corners such that segment
most recently buffered before turn farthest distance travel before next buffer, shown Figure inputs outputs interface with octal lines single-length interconnect lines. Single-length lines also used communication between octals double-length lines, quads, longlines within array. Segmentation into buffered octals found optimal distributing signals over long distances around device.
Segment with nearest buffer connects segment with furthest buffer
X6607
Figure XC4000EX Octal Routing
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Global Nets Buffers
Both XC4000E XC4000EX have dedicated global networks. These networks designed distribute clocks other high fanout control signals throughout devices with minimal skew. global buffers described detail following sections. text descriptions diagrams summarized Table table shows which clock pins sourced which global buffers. both XC4000E XC4000EX devices, placement library symbol called BUFG results software choosing appropriate clock buffer, based timing requirements design. detailed information these sections included only reference.
Four Primary Global buffers offer shortest delay negligible skew. Four Secondary Global buffers have slightly longer delay slightly more skew potentially heavier loading, offer greater flexibility when used drive non-clock inputs. Primary Global buffers must driven semidedicated pads. Secondary Global buffers sourced either semi-dedicated pads internal nets. Each column four dedicated vertical Global lines. Each these lines accessed particular Primary Global buffer, Secondary Global buffers, shown Figure Each corner device Primary buffer Secondary buffer. IOBs along left right edges have four vertical global longlines. bottom IOBs clocked from global lines adjacent column. global buffer should specified timing-sensitive global signal distribution. global buffer, place BUFGP (primary buffer), BUFGS (secondary buffer), BUFG (either primary secondary buffer) element schematic code. desired, attach attribute property direct placement designated location. example, attach LOC=L attribute property BUFGS symbol direct that buffer placed Secondary Global buffers left edge device, LOC=BL indicate Secondary Global buffer bottom edge device, left.
Global Nets Buffers (XC4000E only)
Four vertical longlines each column driven exclusively special global buffers. These longlines addition vertical longlines used standard interconnect. four global lines driven either types global buffers. clock pins every also sourced from local interconnect. different types clock buffers available XC4000E: Primary Global Buffers (BUFGP) Secondary Global Buffers (BUFGS)
Table Clock Access XC4000E BUFGP CLBs Quadrant CLBs Device IOBs Adjacent Vertical Half Edge IOBs Adjacent Vertical Full Edge IOBs Adjacent Horizontal Half Edge (Direct) IOBs Adjacent Horizontal Half Edge (through globals) IOBs Adjacent Horizontal Full Edge (through globals)
Left, Right, Top, Bottom
BUFGS
BUFGLS
XC4000EX BUFGE BUFGE
BUFFCL
Local Interconnect
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XC4000 Series Field Programmable Gate Arrays
locals
locals
locals
BUFGS PGCK1 SGCK1
locals
BUFGP SGCK4 PGCK4
BUFGP locals locals BUFGS BUFGP Global Line locals BUFGS locals
BUFGS locals
BUFGS BUFGP Global Line locals BUFGP locals locals
PGCK2 locals locals locals BUFGP locals SGCK2 BUFGS
SGCK3 PGCK3
X6604
Figure XC4000E Global Distribution
BUFGLS
BUFGLS
GCK1
GCK8 BUFGE BUFGE
GCK7
GCK6
locals
locals
locals
BUFGLS
locals
BUFGE
BUFGE
BUFGLS
BUFFCLK
BUFFCLK
FCLK1 BUFGLS
BUFGLS
BUFGLS
BUFGLS
FCLK4
locals
CLOCKS (PER COLUMN)
locals
locals
locals
locals
CLOCKS
CLOCKS (PER COLUMN)
CLOCKS
locals
locals
CLOCKS CLOCKS (PER COLUMN) CLOCKS (PER COLUMN) CLOCKS
locals
locals
BUFGLS FCLK2
locals
BUFGLS
FCLK3
locals
BUFGLS
locals
BUFGLS
BUFFCLK
BUFFCLK
locals
locals
locals
BUFGLS
locals
BUFGE BUFGE
BUFGE BUFGE GCK4
BUFGLS
GCK2
GCK3 BUFGLS BUFGLS
GCK5 X6694
Figure XC4000EX Global Distribution
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September 1996 (Version 1.04)
Global Nets Buffers (XC4000EX only)
Eight vertical longlines each column driven special global buffers. These longlines addition vertical longlines used standard interconnect. global lines broken center array, allow faster distribution minimize skew across whole array. Each half-column global line buffered multiplexer, shown Figure bottom global lines cannot connected across center device, this connection might introduce unacceptable skew. bottom halves global lines must separately driven although they driven same global buffer. eight global lines each column driven either types global buffers. They also driven internal logic, because they accessed single, double, quad lines top, bottom, half, quarter points. Consequently, number different clocks that used simultaneously XC4000EX device very large. There four global lines feeding IOBs left edge device. IOBs along right edge have eight global lines. There single global line along bottom edges with access IOBs. global lines broken center. They cannot connected across center device, this connection might introduce unacceptable skew. global lines driven from three types global buffers, from local interconnect. Alternatively, bottom IOBs clocked from global lines adjacent column. Three different types clock buffers available XC4000EX: Global Low-Skew Buffers (BUFGLS) Global Early Buffers (BUFGE) FastCLK Buffers (BUFFCLK)
Early Global Low-Skew buffers share common input; they cannot driven different signals. Choosing XC4000EX Clock Buffer clocking structure XC4000EX provides large variety features. However, simple use, without understanding details. software automatically handles clocks, along with other routing, when appropriate clock buffer placed design. fact, buffer symbol called BUFG placed, rather than specific type buffer, software even chooses buffer most appropriate design. detailed information this section provided those users want finer level control over their designs. fine control desired, following summary Table page choose appropriate clock buffer. simplest thing Global Low-Skew buffer. faster clock path needed, BUFG. software will first Global Low-Skew Buffer. timing requirements met, faster buffer will automatically used. single quadrant chip sufficient clocked logic, timing requires faster clock than Global Low-Skew buffer, Global Early buffer. special cases, where both external internal timing have been carefully studied, FastCLK buffer used, fastest possible clock path.
Global Low-Skew Buffers Each corner XC4000EX device Global LowSkew buffers. eight Global Low-Skew buffers drive eight vertical Global lines column CLBs. addition, buffers drive four vertical lines accessing IOBs left edge device, eight vertical lines accessing IOBs right edge device. (See Figure page 44.) IOBs bottom edges device accessed through vertical Global lines array, XC4000E. Global Low-Skew buffer can, therefore, access every device. Global Low-Skew buffers driven either semidedicated pads internal logic. Global Low-Skew buffer, place BUFGLS element schematic code. desired, attach attribute property direct placement designated location. example, attach LOC=T attribute property direct that BUFGLS placed Global Low-Skew buffers edge device, LOC=TR indicate Global Low-Skew buffer edge device, right.
Global Low-Skew Buffers standard clock buffers. They should used most internal clocking, whenever large portion device must driven. Global Early Buffers designed provide faster clock access, access limited one-fourth device. They also facilitate faster interface. FastCLK buffers specifically designed provide fastest possible clock. They have only standard input access CLBs, through local interconnect. Figure conceptual diagram global structure XC4000EX. Global Early buffers Global Low-Skew buffers share single pad. Therefore, same IPAD symbol drive buffer each type, parallel. This configuration particularly useful when using Fast Capture latches, described "IOB Input Signals" page Paired Global
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XC4000 Series Field Programmable Gate Arrays
X6753
X6751
Figure BUFGLS (GCK1 GCK8) Drive Clock Inputs Device Global Early Buffers Each corner XC4000EX device Global Early buffers. primary purpose Global Early buffers provide earlier clock access than potentially heavily-loaded Global Low-Skew buffers. clock source applied both buffers will result Global Early clock edge occurring several nanoseconds earlier than Global Low-Skew buffer clock edge, lighter loading. Global Early buffers also facilitate fast capture device inputs, using Fast Capture latches described "IOB Input Signals" page Fast Capture, take single clock signal, route through both Global Early buffer Global Low-Skew buffer. (The buffers share input pad.) Global Early buffer clock Fast Capture latch, Global Low-Skew buffer clock normal input flip-flop latch, shown Figure page Global Early buffers also used provide fast Clock-to-Out device output pins. However, early clock output flip-flop must taken into consideration when calculating internal clock speed design. Global Early buffers left right edges chip have slightly different capabilities than ones bottom. Refer Figure Figure Figure page while reading following explanation. Each Global Early buffer access eight vertical Global lines CLBs quadrant. Therefore, only onefourth clock pins accessed. This restriction large part responsible faster speed buffers, relative Global Low-Skew buffers.
Figure Left Right BUFGEs Drive Clock Inputs Same Quadrant Edge (GCK1 shown. GCK2, GCK5 GCK6 similar.) left-side Global Early buffers each drive four vertical lines accessing IOBs entire left edge device. right-side Global Early buffers each drive eight vertical lines accessing IOBs entire right edge device. (See Figure 38.) Each left right Global Early buffer also drive half IOBs along either bottom edge device, using dedicated line that only accessed through Global Early buffers. bottom Global Early buffers drive half IOBs along either left right edge device, shown Figure They only access bottom IOBs global lines.
X6747
Figure Bottom BUFGEs Drive Clock Inputs Same Quadrant (GCK8 shown. GCK3, GCK4 GCK7 similar.)
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September 1996 (Version 1.04)
Global Early buffers driven either semi-dedicated pads internal logic. They share pads with Global Low-Skew buffers, single drive both global buffers, described above. Global Early buffer, place BUFGE element schematic code. desired, attach attribute property direct placement designated location. example, attach LOC=T attribute property direct that BUFGE placed Global Early buffers edge device, LOC=TR indicate Global Early buffer edge device, right. FastCLK Buffers fastest bring clock into XC4000EX device through FastCLK buffer. FastCLK buffers present left edge, right edge, XC4000EX die. There FastCLK buffers bottom edges. purpose FastCLK buffers create very fast pin-to-pin path using 2-input function generator conjunction with FastCLK. Drive input function generator with FastCLK buffer output, described "IOB Output Signals" page Alternatively, FastCLK buffer used minimize setup time device inputs, positive hold time acceptable. FastCLK buffer clock Fast Capture latch, slower clock buffer clock standard flip-flop latch. Either Global Early buffer Global Low-Skew buffer used second storage element, whichever used should same clock related internal logic. Since FastCLK pads different from Global Early Global Low-Skew pads, care must taken ensure that skew external device does create internal timing difficulties. FastCLK buffers also used provide fast Clock-to-Out device output pins. However, fast clock output flip-flop must taken into consideration when calculating internal clock speed design.
X6745
Figure Each BUFFCLK Drive Clock Inputs Same Half-Edge (FCLK1 shown. FCLK2, FCLK3 FCLK4 similar.) FastCLK buffers limited accessing IOBs onehalf edge only, shown Figure Figure page They each drive four vertical lines accessing IOBs left edge device, eight vertical lines accessing IOBs right edge device. They only access array through single- double-length lines. FastCLK buffers must driven semi-dedicated IOBs. They accessible from internal nets. Other than FastCLK feature, these IOBs identical other IOBs. FastCLK buffer, place BUFFCLK element schematic code. desired, attach attribute property direct placement designated location. example, attach LOC=LB attribute property direct that BUFFCLK placed left edge device bottom, LOC=L indicate either buffers left edge. input BUFFCLK symbol must driven input symbol, such IPAD, input flip-flop latch, such INFF, ILD, ILFFX, ILFLX.
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XC4000 Series Field Programmable Gate Arrays
Power Distribution
Power FPGA distributed through grid achieve high noise immunity isolation between logic I/O. Inside FPGA, dedicated Ground ring surrounding logic array provides power drivers, shown Figure independent matrix Ground lines supplies interior logic device. This power distribution grid provides stable supply ground internal logic, providing external package power pins connected appropriately decoupled. Typically, capacitor connected near Ground pins package will provide adequate decoupling. Output buffers capable driving/sinking specified (XC4000E) (XC4000EX) loads under specified worst-case conditions capable driving/sinking times much current under best case conditions. Noise reduced minimizing external load capacitance reducing simultaneous output transitions same direction. also beneficial locate heavily loaded output buffers near Ground pads. Block output buffers have slew-rate limited mode (default) which should used where output rise fall times speed-critical.
Ground Ring Drivers
Descriptions
There three types pins XC4000-Series devices: Permanently dedicated pins User pins that have special functions Unrestricted user-programmable pins.
Before during configuration, outputs used configuration process 3-stated with pull-up resistor. After configuration, unused configured input with pull-up resistor. XC4000-Series devices have dedicated Reset input. user configured drive Global Set/ Reset net, GSR. "Global Set/Reset" page more information GSR. XC4000-Series devices have Powerdown control input, XC3000 XC2000 families XC3000/ XC2000 Powerdown control also 3-stated device pins. XC4000-Series devices, global 3-state net, GTS, instead. This 3-states outputs, does place device low-power mode. "IOB Output Signals" page more information GTS. Device pins XC4000-Series devices described Table functions during configuration each seven configuration modes summarized Table page "Configuration Timing" section.
Logic Power Grid
X5422
Figure XC4000-Series Power Distribution
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September 1996 (Version 1.04)
Table Descriptions During After Name Config. Config. Permanently Dedicated Pins
Description
Eight more (depending package) connections nominal supply voltage (+3.3 low-voltage devices). must connected, each must decoupled with 0.01 capacitor Ground. Eight more (depending package type) connections Ground. must conGND nected. During configuration, Configuration Clock (CCLK) output Master modes Asynchronous Peripheral mode, input Slave mode, Synchronous Peripheral mode, Express mode. After configuration, CCLK weak pull-up resistor CCLK selected Readback Clock. There CCLK High time restriction XC4000-Series devices, except during Readback. "Violating Maximum High Time Specification Readback Clock" page explanation this exception. DONE bidirectional signal with optional internal pull-up resistor. output, indicates completion configuration process. input, level DONE configured delay global logic initialization enabling outDONE puts. optional pull-up resistor selected option MakeBits, XACTstep program that creates configuration bitstream. resistor included default. PROGRAM active input that forces FPGA clear configuration memory. used initiate configuration cycle. When PROGRAM goes High, FPGA finishes current clear cycle executes another complete clear cycle, before PROGRAM goes into WAIT state releases INIT. PROGRAM permanent weak pull-up, need externally pulled Vcc. User Pins That Have Special Functions During Peripheral mode configuration, this indicates when appropriate write another byte data into FPGA. same status also available AsynRDY/BUSY chronous Peripheral mode, read operation performed when device selected. After configuration, RDY/BUSY user-programmable pin. RDY/BUSY pulled High with high-impedance pull-up prior INIT going High. During Master Parallel configuration, each change A0-A17 outputs XC4000EX) preceded rising edge RCLK, redundant output signal. RCLK RCLK useful clocked PROMs. rarely used during configuration. After configuration, RCLK user-programmable pin. Mode inputs, these pins sampled after INIT goes High determine configuration mode used. After configuration, used inputs, used 3-state output. These three pins have associated input output registers. (M0), During configuration, these pins have weak pull-up resistors. most popular conM0, (M1), figuration mode, Slave Serial, mode pins thus left unconnected. three (M2) mode inputs individually configured with without weak pull-up pull-down resistors. pull-down resistor value recommended. These pins only used inputs outputs when called special schematic definitions. these pins, place library components MD0, MD1, instead usual symbols. Input output buffers must still used.
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XC4000 Series Field Programmable Gate Arrays
Table Descriptions (Continued) During After Config. Config.
Name
TDI, TCK,
(JTAG)
INIT
PGCK1 PGCK4 (XC4000E only)
Weak Pull-up
SGCK1 SGCK4 (XC4000E only)
Weak Pull-up
GCK1 GCK8 (XC4000EX only) FCLK1 FCLK4 (XC4000EX only)
Weak Pull-up
Weak Pull-up
Description boundary scan used, this Test Data Output. boundary scan used, this 3-state output without register, after configuration completed. This user output only when called special schematic definitions. this pin, place library component instead usual symbol. output buffer must still used. boundary scan used, these pins Test Data Test Clock, Test Mode Select inputs respectively. They come directly from pads, bypassing IOBs. These pins also used inputs logic after configuration completed. BSCAN symbol placed design, boundary scan functions inhibited once configuration completed, these pins become user-programmable I/O. this case, they must called special schematic definitions. these pins, place library components TDI, TCK, instead usual symbols. Input output buffers must still used. High During Configuration (HDC) driven High until active. available control output indicating that configuration completed. After configuration, user-programmable pin. During Configuration (LDC) driven until active. available control output indicating that configuration completed. After configuration, user-programmable pin. Before during configuration, INIT bidirectional signal. external pull-up resistor recommended. active-Low open-drain output, INIT held during power stabilization internal clearing configuration memory. active-Low input, used hold FPGA internal WAIT state before start configuration. Master mode devices stay WAIT state additional after INIT gone High. During configuration, this output indicates that configuration data error occurred. After active, INIT user-programmable pin. Four Primary Global inputs each drive dedicated internal global with short delay minimal skew. used drive global buffer, these pins user-programmable I/O. PGCK1-PGCK4 pins drive four Primary Global Buffers. input symbol connected directly input BUFGP symbol automatically placed these pins. Four Secondary Global inputs each drive dedicated internal global with short delay minimal skew. These internal global nets also driven from internal logic. used drive global net, these pins user-programmable pin. SGCK1-SGCK4 pins provide shortest path four Secondary Global Buffers. input symbol connected directly input BUFGS symbol automatically placed these pins. Eight inputs each drive Global Low-Skew buffer. addition, each drive Global Early buffer. Each pair global buffers also driven from internal logic, must share input signal. used drive global buffer, these pins user-programmable I/O. input symbol connected directly input BUFGLS BUFGE symbol automatically placed these pins. Four FCLK inputs each drive FastCLK buffer. FastCLK buffers cannot driven from internal logic. used drive global buffer, these pins userprogrammable I/O. input symbol connected directly input BUFFCLK symbol automatically placed these pins.
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September 1996 (Version 1.04)
Table Descriptions (Continued) During After Config. Config.
Description These four inputs used Asynchronous Peripheral mode. chip selected when High. While chip selected, Write Strobe (WS) loads data present inputs into internal data buffer. CS0, CS1, Read Strobe (RS) changes into status output High Ready, Busy drives High. Express mode, used serial-enable signal daisy-chaining. should mutually exclusive, both simultaneously, Write Strobe overrides. After configuration, these user-programmable pins. During Master Parallel configuration, these output pins address configuration EPROM. After configuration, they user-programmable pins. During Master Parallel configuration with XC4000EX master, these output pins (XC4000EX more bits address configuration EPROM. After configuration, they user-proonly) grammable pins. During Master Parallel Peripheral configuration, these eight input pins receive conD0 figuration data. After configuration, they user-programmable pins. During Slave Serial Master Serial configuration, serial configuration data input receiving data rising edge CCLK. During Parallel configuration, input. After configuration, user-programmable pin. During configuration mode Express mode, DOUT serial configuration data output that drive daisy-chained slave FPGAs. DOUT data changes falling edge CCLK, one-and-a-half CCLK periods after received DOUT input. Express mode, DOUT status output that drive daisy-chained FPGAs, enable disable downstream devices. After configuration, DOUT user-programmable pin. Unrestricted User-Programmable Pins These pins configured input and/or output after configuration completed. Weak Before configuration completed, these pins have internal high-value pull-up resisPull-up that defines logic level High.
Name
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XC4000 Series Field Programmable Gate Arrays
Boundary Scan
`bed nails' been traditional method testing electronic assemblies. This approach become less appropriate, closer spacing more sophisticated assembly methods like surface-mount technology multi-layer boards. IEEE Boundary Scan Standard 1149.1 developed facilitate board-level testing electronic assemblies. Design test engineers imbed standard test logic structure their device achieve high fault coverage internal logic. This structure easily implemented with four-pin interface boundary scan-compatible IEEE 1149.1-compatible devices serial daisy-chained together, connected parallel, combination two. XC4000 Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE EXTEST boundary scan instructions. When boundary scan configuration option selected, three normal user pins become dedicated inputs these functions. Another user output becomes dedicated boundary scan output. details enable this circuitry covered later this section. exercising these input signals, user serially load commands data into these devices control driving their outputs examine their inputs. This method improvement over bed-of-nails testing. avoids need over-drive device outputs, reduces user interface four pins. optional fifth pin, reset control logic, described standard implemented Xilinx devices. dedicated on-chip logic implementing IEEE 1149.1 functions includes 16-state state machine, instruction register number data registers. functional details found IEEE 1149.1 specification also discussed Xilinx application note XAPP 017: "Boundary Scan XC4000 Devices." Figure shows simplified block diagram XC4000E Input/Output Block with boundary scan implemented. XC4000EX boundary scan logic identical. Figure page diagram XC4000-Series boundary scan logic. includes three bits Data Register IOB, IEEE 1149.1 Test Access Port controller, Instruction Register with decodes. XC4000-Series devices also configured through boundary scan logic. "Configuration Through Boundary Scan Pins" page
Data Registers
primary data register boundary scan register. each FPGA, bonded not, includes three bits 3-State Control. Non-IOB pins have appropriate partial population only. PROGRAM, CCLK DONE included boundary scan register. Each EXTEST CAPTURE-DR state captures Out, 3-state pins. data register also includes following non-pin bits: TDO.T, TDO.O, which always bits data register, respectively, BSCANT.UPD, which always last data register. These three boundary scan bits special-purpose Xilinx test signals. other standard data register single flip-flop BYPASS register. synchronizes data being passed through FPGA next downstream boundary scan device. FPGA provides additional data registers that specified using BSCAN macro. FPGA provides user pins (BSCAN.SEL1 BSCAN.SEL2) which decodes user instructions. these instructions, corresponding pins (BSCAN.TDO1 BSCAN.TDO2) allow user scan data shifted TDO. data register clock (BSCAN.DRCK) available control test logic which user wish implement with CLBs. NAND RUN-TEST-IDLE also provided (BSCAN.IDLE).
Instruction
XC4000-Series boundary scan instruction also includes instructions configure device read back configuration data. instruction coded shown Table Table Boundary Scan Instructions Instruction Test Source Selected EXTEST SAMPLE/ PRELOAD USER BSCAN. TDO1 USER BSCAN. TDO2 READBACK Readback Data CONFIGURE DOUT Reserved BYPASS Bypass Register Data Source Pin/Logic User Logic User Logic Pin/Logic Disabled
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September 1996 (Version 1.04)
EXTEST TS/OE Boundary Scan OUTPUT INVERT OUTPUT Ouput Data Ouput Clock INVERT capture update
SLEW RATE
PULL DOWN
PULL
3-State
Clock Enable
Boundary Scan
capture capture update
capture Boundary Scan update DELAY FLIP-FLOP/LATCH Input Clock INPUT INVERT Input Data
Input Data
GLOBAL
X5792
Figure Block Diagram XC4000E with Boundary Scan (some details shown). XC4000EX Boundary Scan Logic Identical.
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XC4000 Series Field Programmable Gate Arrays
DATA
IOB.Q IOB.T
IOB.I
IOB.Q IOB.T
BYPASS REGISTER INSTRUCTION REGISTER
INSTRUCTION REGISTER BYPASS REGISTER
IOB.I
IOB.O DATAOUT SHIFT/ CAPTURE CLOCK DATA REGISTER UPDATE
EXTEST
X1523
Figure XC4000-Series Boundary Scan Logic
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September 1996 (Version 1.04)
Sequence
sequence within each Out, 3-State. input-only mode pins contribute only boundary scan data register, while outputonly contributes three bits. first bits data register TDO.T TDO.O, which used capture internal signals. final BSCANT.UPD, which used drive internal net. These locations primarily used Xilinx internal testing. From cavity-up view chip shown Epic), starting upper right chip corner, boundary scan data-register bits ordered shown Figure device-specific pinout tables XC4000 Series include boundary scan locations each pin. BSDL (Boundary Scan Description Language) files XC4000-Series devices available Xilinx BBS.
Even boundary scan symbol used schematic, input pins TMS, TCK, still used inputs routed internal logic. Care must taken force chip into undesired boundary scan state inadvertently applying boundary scan input patterns these pins. simplest prevent this keep High, then apply whatever signal desired TCK.
Avoiding Inadvertent Boundary Scan Activation
used user I/O, care must taken ensure that least these pins held constant during configuration. some applications, situation occur where driven during configuration. This cause device into boundary scan mode disrupt configuration process. prevent activation boundary scan during configuration, either following: TMS: High Test Access Port controller benign RESET state TCK: High Low-don't toggle this clock input.
Including Boundary Scan Schematic
boundary scan only used during configuration, special schematic elements need included schematic code. this case, special boundary scan pins TDI, TMS, used user functions after configuration. indicate that boundary scan remain enabled after configuration, place BSCAN library symbol connect TDI, TMS, symbols appropriate pins, shown Figure
more information regarding boundary scan, refer Xilinx Application Note XAPP 017.001, "Boundary Scan XC4000E Devices."
Optional
end)
TDO.T TDO.O Top-edge IOBs (Right Left)
TDO1 TDO2
User Logic IBUF
BSCAN
DRCK IDLE SEL1 SEL2 X2675
Left-edge IOBs (Top Bottom) MD1.T MD1.O MD1.I MD0.I MD2.I Bottom-edge IOBs (Left Right)
From User Logic
User Logic
Figure Boundary Scan Schematic Example
Right-edge IOBs (Bottom Top) (TDI end) SCANT.UPD
X6075
Figure
Boundary Scan Sequence
September 1996 (Version 1.04)
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XC4000 Series Field Programmable Gate Arrays
Configuration
Configuration process loading design-specific programming data into more FPGAs define functional operation internal blocks their interconnections. This somewhat like loading command registers programmable peripheral chip. XC4000-Series devices several hundred bits configuration data associated interconnects. Each configuration defines state static memory cell that controls either function look-up table bit, multiplexer input, interconnect pass transistor. XACTstep development system translates design into netlist file. automatically partitions, places routes logic generates configuration data PROM format.
Table Configuration Modes Mode Master Serial Slave Serial Master Parallel Master Parallel Down Peripheral Synchronous* Peripheral Asynchronous Express (XC4000EX only) Reserved
Note:
CCLK output input output
output
input output input
Data Bit-Serial Bit-Serial Byte-Wide, increment from 00000 Byte-Wide, decrement from 3FFFF Byte-Wide Byte-Wide Byte-Wide
Special Purpose Pins
Three configuration mode pins (M2, sampled prior configuration determine configuration mode. After configuration, these pins used auxiliary connections. used inputs, used output. XACTstep development system does these resources unless they explicitly specified design entry. This done placing special symbol called MD2, MD1, instead input output symbol. XC4000-Series devices, mode pins have weak pullup resistors during configuration. With three mode pins High, Slave Serial mode selected, which most popular configuration mode. Therefore, most common configuration mode, mode pins left unconnected. (Note, however, that internal pull-up resistor value high After configuration, these pins individually have weak pull-up pull-down resistors, specified design. pull-down resistor value recommended. These pins located lower left chip corner near readback nets. This location allows convenient routing compatibility with XC2000 XC3000 family conventions M0/RT, M1/RD desired.
Peripheral Synchronous considered bytewide Slave Parallel
detailed description each configuration mode, with timing information, included later this data sheet. During configuration, some pins used temporarily configuration process. pins used during configuration shown Table page
Master Modes
three Master modes internal oscillator generate Configuration Clock (CCLK) driving potential slave devices. They also generate address timing external PROM(s) containing configuration data. Master Parallel Down) modes generate CCLK signal PROM addresses receive byte parallel data. data internally serialized into FPGA data-frame format. down selection generates starting addresses either zero 3FFFF, compatibility with different microprocessor addressing conventions. Master Serial mode generates CCLK receives configuration data serial form from Xilinx serial-configuration PROM. CCLK speed selectable either (default) lower low-voltage devices). Configuration always starts default slow frequency, then switch higher frequency during first frame. Frequency tolerance -50% +25%.
Configuration Modes
XC4000E devices have configuration modes. XC4000EX devices have same modes, plus additional configuration mode. These modes selected 3-bit input code applied inputs. There three self-loading Master modes, Peripheral modes, Serial Slave mode, which used primarily daisy-chained devices. seventh mode, called Express mode, additional slave mode that allows high-speed parallel configuration high-capacity XC4000EX devices. coding mode selection shown Table
Peripheral Modes
Peripheral modes accept byte-wide data from bus. RDY/BUSY status available handshake signal. Asynchronous Peripheral mode, internal oscillator generates CCLK burst signal that serializes bytewide data. CCLK also drive slave devices. syn-
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September 1996 (Version 1.04)
chronous mode, externally supplied clock input CCLK serializes data.
Slave Serial Mode
Slave Serial mode, FPGA receives serial configuration data rising edge CCLK and, after loading configuration, passes additional data out, resynchronized next falling edge CCLK. Multiple slave devices with identical configurations wired with parallel inputs. this way, multiple devices configured simultaneously. Serial Daisy Chain Multiple devices with different configurations connected together "daisy chain," single combined bitstream used configure chain slave devices. configure daisy chain devices, wire CCLK pins devices parallel, shown Figure page Connect DOUT each device next. lead master FPGA following slaves each passes resynchronized configuration data coming from single source. header data, including length count, passed through captured each FPGA when recognizes 0010 preamble. Following length-count data, each FPGA outputs High DOUT until received required number data frames. After FPGA received configuration data, passes additional frame start bits configuration data DOUT. When total number configuration clocks applied after memory initialization equals value 24-bit length count, FPGAs begin start-up sequence become operational together. FPGA normally released CCLK cycles after last configuration received. Figure page shows startup timing XC4000-Series device. daisy-chained bitstream simply concatenation individual bitstreams. MakePROM program must used combine bitstreams daisychained configuration. Multi-Family Daisy Chain Xilinx FPGAs XC2000, XC3000, XC4000 Series compatible bitstream format can, therefore, connected daisy chain arbitrary sequence. There however, limitation. lead device must belong highest family chain. chain contains XC4000-Series devices, master normally cannot XC2000 XC3000 device. reason this rule shown Figure page Since devices chain store same length count value generate receive common sequence CCLK pulses, they recognize length-count match same CCLK edge, indicated left edge Figure master device then generates additional
CCLK pulses until reaches finish point different families generate require different numbers additional CCLK pulses until they reach reaching means that device does really finish configuration, although DONE have gone High, outputs became active, internal reset released. XC4000Series device, reaching means that readback cannot initiated most boundary scan instructions cannot used. user some control over relative timing these events can, therefore, make sure that they occur proper time finish point reached. Timing controlled using MakeBits options. XC3000 Master with XC4000-Series Slave Some designers want inexpensive lead device peripheral mode have more precious pins XC4000-Series devices available user I/O. Figure provides solution that case. This solution requires CLB, pin, internal oscillator with frequency clock source. XC3000 master device must configured with late Internal Reset, which default option. lead XC3000-family device used generate additional CCLK pulse required XC4000-Series devices. When lead device removes internal RESET signal, 2-bit shift register responds clock input generates active output signal duration subsequent clock period. external connection between this output CCLK thus creates extra CCLK
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