XAPP388

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XAPP388 - XAPP388

Application Note: CoolRunner-II CPLDs
Reconfiguration with CoolRunner-II CPLDs
XAPP388 (v1.2) 2003
Summary
This application notes describes CoolRunnerTM-II CPLD capability called Fly" (OTF) Reconfiguration. permits CPLD operating with design pattern simultaneously acquire second pattern during operation first pattern. second pattern configured into device with minimal disturbance operation device. Additional capabilities, applications limits this operation will discussed further sections.
Introduction
system programming (ISP) initially seen program Complex Programmable Logic Devices (CPLD) while devices were attached printed circuit boards (PCB). Originally, this capability primarily focused delivering device configuration without having external programmer. Many changes that capability have evolved, including JTAG testing pin-locking architectures capable sustaining multiple design edits while attached PCB. takes level, will undoubtedly spawn many applications take advantage this capability. permits subsequent designs reloaded succession device while operating previous design configuration. optimized reconfiguration Xilinx-patented Real Digital technology which permits simultaneous design images reside within part point time.
Discussion
Real Digital technology combines nonvolatile programming cell with volatile one. Most digital designers familiar with shadow memories, where memory array tracks another one. some point, their contents different, they become "resynchronized" another point. With Real Digital, nonvolatile cell version EPROM that electrically programmable volatile cell similar SRAM cell, organized with same random architecture SRAM. When pattern programmed into CPLD through JTAG pins, first delivered into staging shift register, then transferred into nonvolatile cells. After programming nonvolatile cells completes, there specific step where nonvolatile contents transfer into volatile cells. Operation logic actually occurs outside volatile cells. Once nonvolatile cells duplicate contents into volatile cells, nonvolatile cells available accepting pattern. Figure shows high level CoolRunner-II CPLD family architecture (further detailed application notes data sheets listed Appendix CoolRunner-II Resources, page Figure shows underlying structure area programmable cells that dictate actual functional behavior CPLD when programmed with pattern.
2003 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, further disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice. NOTICE DISCLAIMER: Xilinx providing this design, code, information is." providing design, code, information possible implementation this feature, application, standard, Xilinx makes representation that this implementation free from claims infringement. responsible obtaining rights require your implementation. Xilinx expressly disclaims warranty whatsoever with respect adequacy implementation, including limited warranties representations that this implementation free from claims infringement implied warranties merchantability fitness particular purpose.
XAPP388 (v1.2) 2003
www.xilinx.com 1-800-255-7778
Reconfiguration with CoolRunner-II CPLDs
Path Clock Control Signals
Function Block
Function Block
Blocks
MC16
Fast Inputs
MC16
Fast Inputs
JTAG
DS090_01_12
Figure CoolRunner-II CPLD High Level Architecture Figure expands detail single programmable cell, revealing two-element nature, with nonvolatile portion (NV) left volatile SRAM portion right. particular, Figure show successive stages programming. Initially, cell virgin state shown Figure where both cell portions blank. Then, first pattern (P1) delivered into portion, portion still blank. This shown Figure After such cells programmed, part undergoes transistion where cells copy into cells, which shown Figure this point, part loaded running with pattern programmed into configuration cells. Figure shows part operating with pattern volatile cells, pattern (P2) loaded into cells. Note that will require specific command delivered transfer contents cells into cells, this occurred. Upon issuing command accomplish OTF, pattern copies into volatile cells part operating with pattern. this point, needed, would possible keep going deliver third programming pattern.
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XAPP388 (v1.2) 2003
Blocks
Reconfiguration with CoolRunner-II CPLDs
WP000_00_062402
Figure CoolRunner-II Architecture with Configuration Memory Exposed
XAPP388 (v1.2) 2003
www.xilinx.com 1-800-255-7778
Reconfiguration with CoolRunner-II CPLDs
element cell
both initially blank
with
Operating both elements
with staged transfer
complete with both elements
X388_03_022703
Figure Two-Element Cell Structure Transition Steps Reconfiguration
Operation Details
Naturally, important that designers given easy-to-use tools that permit seamless operation OTF. Xilinx provides this Design Software (including WebPACKTM). Design-creation using design software standard flow starting with design capture moving through fitting, application constraints, device programming. Details this flow well outlined Xilinx software help packages numerous software tutorials. return process reconfiguration outlined earlier, will assume existence programming patterns, which already exist JEDEC files design directory. Going further, will assume that pattern already programmed into part with iMPACT software. IMPACT many options, interested chosen from menu shown Figure this case, showing single XC2C64 macrocell part JTAG chain. possible target part within chain program needed. After clicking OKAY window shown Figure progress will indicate that cells being loaded. When that progress completes, target part will condition similar that shown Figure Specifically, will operating pattern with pattern already loaded into memory.
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XAPP388 (v1.2) 2003
Reconfiguration with CoolRunner-II CPLDs
Figure iMPACT Programmer Window with Programming Option Checked appropriate point time, when wish activate pattern will need supply appropriate JTAG commands. possible this with JTAG operations coming from microprocessor, consistent with this example, will proceed activate that operation from iMPACT shown Figure
XAPP388 (v1.2) 2003
www.xilinx.com 1-800-255-7778
Reconfiguration with CoolRunner-II CPLDs
Figure Delivering Activation Command from iMPACT After issuing activate command, image will copy from cells into volatile ones pattern comes running. There brief (~50 µsec) time period when pattern transitioning pins assume momentary tri-state (weakly pulled configuration, that ends with pins their "P2" configuration. brief transition time substantial improvement over stopping operation full program operation.
Applications
This section outlines several applications that take advantage programming.
Example Configuring FPGA
Figure shows classic CPLD applications being done single CPLD. First, quite common CPLD used configuration controller FPGA. figure outlines sequence. power CPLD already FPGA configuration internally loaded (P1). With task CPLD drives FPGA pattern through FPGAs parallel configuration port called Select mode. After completing that task, loads pattern into CPLD, giving identity (P2) interrupt handler. After loading subsequently loads copy back into CPLD (taken from "Select JEDEC" EPROM), does activate into volatile cells. Note that next power CPLD will already loaded ready configure FPGA again, planned that eventuality.The advantage this configuration that CPLD actually serves purposes with chip.
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XAPP388 (v1.2) 2003
Reconfiguration with CoolRunner-II CPLDs
Select FPGA Bitstream CPLD FPGA
Select JEDEC Interrupt Handler JEDEC
System power CPLD Configures FPGA Select FPGA active configures CPLD JTAG with interrupt handler program
CPLD active configures CPLD JTAG with Select program (P1) does configure volatile cells. System power cycled time
XAPP388_06_013003
Figure Combining Classic CPLD Applications
Example Updating Instruction
PicoBlaze microcontroller design another option interesting operation. this case, possible take program that running with version processor executing specific instruction stream substitute another version, with exactly same pinout, while operating. program sufficiently small, even folded within design that both program well architecture become simultaneously updated with same activation command. XAPP387 PicoBlaze 8-bit microcontroller more information.
XAPP388 (v1.2) 2003
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Reconfiguration with CoolRunner-II CPLDs
Figure CoolRunner-II Design Board with PicoBlaze
Example Reprogramming fixed Cross-Bar Switch
XAPP380 shows design generic cross switch. This design version uses external signals select switch connections made, easily altered make that selection internally hardwired, need Then, switch selections accomplished dropping alternate version design into chip through even while chip currently switching.
Example Updating small EPROM table
PLDs were originally built replacements EPROMs. fitting that emulate EPROM inside CoolRunner-II CPLD order whatever functions might wish. instance, possible make small multiplication table, logarithm table simply insert preferred profile converter table look values use. possible have multiple designs where only thing that changes within design outside world tell) internal EPROM. Using make those changes permits "real time" transition behaviors, needed.
Example Re-keying Stream Cipher
Flip flops, EX-ORs clocks about need build LFSR based stream cipher designs. Switching keys permits robust protocols that tough crack data communication designs. Stream Ciphers particular interest CPLD implementations that today's CPLDs contain lots flip flops logic without speed restrictions fitting difficulties designs tend underuse architecture. Additional references this given appendix. Figure shows extremely simple stream cipher. Many more elaborate structures found literature.
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XAPP388 (v1.2) 2003
Reconfiguration with CoolRunner-II CPLDs
LFSR Clear Bits
X388_08_022703
Encrypted Bits
Figure Simple Stream Cipher with
Example Board level testing
Similar Example possible CPLD multiple very different applications. Instead first programming FPGA, then assuming processor support task like interrupt vector handling, possible insert signature analysis circuitry perform board level tests during initialization periods alternately during some other board level BIST functionality. course, after that occurs, third personality overlayed such previously mentioned support function. Again, additional references this application given Appendix CoolRunner-II Resources, page
Conclusions
Applications beyond those listed above envisioned. CoolRunner-II both fast enough power that portable applications communications even signal processing possibility. Portable filters brainwaves would possibility additional high speed cryptography wireless cellphone applications another. limits what types applications might take advantage programming just being explored. Although there upper limit number times part programmed, high. Jump
Appendix Additional References Appendix CoolRunner-II Resources
"Pseudorandom generator based dynamic linear feedback topology," Mita, Palumbo, Pennisi Poli, Electronic Letters, Vol. 1097 -98. Logic Design Principles, E.J. McCluskey, Prentice-Hall 1986. Digital Design Principles Practices, J.F. Wakerly, Prentice-Hall, 2000
Application Notes
(Timing Model) (Logic Engine) (Low Power Design) (Advanced Features) (High Speed Design) (Cross Point Switch) (Demo Board) (I/O Characteristics) (Single Error Correction Double Error Detection) (DDR SDRAM Interface) (PicoBlaze Microcontroller) Reconfiguration) (Powering CoolRunner-II CPLDs)
XAPP388 (v1.2) 2003
www.xilinx.com 1-800-255-7778
Reconfiguration with CoolRunner-II CPLDs (8051 Microcontroller Interface) (Interfacing with Mobile SDRAM)
CoolRunner-II Data Sheets
(CoolRunner-II Family Datasheet) (XC2C32 Datasheet) (XC2C64 Datasheet) (XC2C128 Datasheet) (XC2C256 Datasheet) (XC2C384 Datasheet) (XC2C512 Datasheet)
CoolRunner-II White Papers
(Chip Scale Packaging) (Security)
Revision History
following table shows revision history this document. Date 02/28/03 03/13/03 05/15/03 Version Initial Xilinx release. Minor revisions. Minor revisions Revision
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XAPP388 (v1.2) 2003

XAPP388

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