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LAPKIT-X88C75-SLIC - LAPKIT-X88C75-SLIC
X88C75DEMO - X88C75DEMO
AN65 LAPKIT LapKitX88C75DEMO
LapKitX88C75 SLIC® Microperipheral
Port Expander Memory
-Low Power 60mA Active 100µA Standby PDIP, PLCC, TQFP Packaging Available DESCRIPTION X88C75 SLIC highly integrated peripheral 80C51 family microcontrollers. device integrates 8K-bytes byte-alterable nonvolatile memory, bidirectional 8-bit ports, general purpose registers, programmable internal address decoding multiplexed address data bus. byte-alterable nonvolatile memory used program storage, data storage, combination both. memory array separated into 4K-bytes sections which allows read accesses section while write operation taking place other section. nonvolatile memory also features Software Data Protection protect contents during power transitions, advanced Block Protect register which allows Individual blocks memory configured read-only read/write.
FEATURES Highly Integrated Microcontroller Peripheral Memory General Purpose Bidirectional Ports General Purpose Registers -Integerated Interrupt Controller Module -Internal Programmable Address Decoding Concurrent Read During Write -Dual Plane Architecture Isolates Read/Write Functions Between Planes Allows Continuous Execution Code From Plane While Writing Other Plane Multiplexed Address/Data -Direct Interface Popular 80C51 Family Microcontrollers Software Data Protection -Protect Entire Array During Power-up/-down Block LockData Protection -Set Write Lockout Blocks Toggle Polling High Performance CMOS -Fast Access Time, CONFIGURATIONS
RESET PSEN STRA A/D0 A/D1 A/D2 A/D3 A/D4 X88C75
STRA PSEN RESET
STRB A/D7 A/D6 A/D5
SLIC® Concurrent Read During Write, Block Lock, Lapkit registered trademarks Xicor, Inc. ©Xicor, 1994, 1996 Patents Pending 6340-1.7 7/9/96 T0/C2/D0
Characteristics subject change without notice
Each bidirectional port consists general purpose lines data strobe line. ports also feature configurable interrupt request output. Access X88C75 accomplished through multiplexed address/data 80C51 type controllers. internal programmable address decoder maps internal memory register locations into desired address space. ARCHITECTURAL OVERVIEW X88C75 incorporates interface circuitry normally needed decode control signals demultiplex address/data provide "seamless" interface. control inputs X88C75 configured such that possible directly connect them proper interface signals 80C51 microcontroller. reading data from chip controlled either PSEN signal, which essentially maps X88C75 into both Program Data Memory address map. Reading writing nonvolatile memory array analogous operation. During write operation either nonvolatile memory control registers, latches address written into X88C75. FUNCTIONAL DIAGRAM
ADDRESS A0-A15 LATCH LEFT PLANE DECODE RIGHT PLANE DECODE GENERAL PURPOSE REGISTERS
rising edge latches data written. nonvolatile memory X88C75 internally organized independent arrays 4K-bytes with input selecting which planes memory accessed. While processor executing code plane, write operations take place other plane; allowing processor continue execution code X88C75 during byte page write device. This feature called Concurrent Read During Write. X88C75 also features advanced implementation Software Data Protection scheme, called Block Lock Protect, which allows nonvolatile memory array treated independent sections 1K-bytes. Each these sections independently enabled write operations. This allows segmentation memory contents into writable non-writable sections, thereby, allowing certain sections device secured that updates only occur controlled environment. (e.g. automotive application, only authorized service center). Block Protect configuration stored nonvolatile register, ensuring that configuration data will maintained after device powered-down.
BUFFER LATCH E2PROM
PSEN RESET DECODE
DATA MASTER CONTROL LOGIC
PORT SPECIAL FUNCTION REGISTERS
X88C75 write control input, serves external control over completion previously initiated page load cycle. X88C75 also features industry standard memory characteristics such byte page mode write Toggle Polling. Read HIGH transition latches address; data will output pins after either PSEN goes (tRDLV). Write write performed latching addresses falling edge ALE. strobed followed DESCRIPTIONS
NAME RESET PSEN STRA, STRB DESCRIPTION RESET used initialize internal static registers effect memory operations. default active level HIGH, reconfigured register. Content memory read lowering PSEN holding both HIGH. device then places data (AD7-AD0) contents memory latched address. STRA controls port STRB controls port When ports configured inputs, valid transition their strobe pins will latch into their port data register data present port input pins. Writing output port data register generates pulse fixed duration corresponding strobe pin. output data presented output pins stay valid until next data written output port data register. lines port output driver configured either CMOS open-drain using direction (DIRA) used select port mode. lines port output driver configured either CMOS open-drain using direction (DIRB) used select port mode. Non-multiplexed high-order Address inputs upper byte address. Multiplexed low-order Address Data Bus. addresses latched when makes HIGH transition. During byte/page write cycle brought while held HIGH data placed Data Bus. rising edge will latch data into device. input active used read content either memory latched address. Both PSEN signals must held HIGH during controlled read operation. open-drain output. configured signal latching data into ports, and/or completion memory internal write cycle. input held during write cycle. permanently tied HIGH order disable write memory. Taking HIGH prior tBIC (100µs; time delay from last write cycle start internal programming cycle) will inhibit write operation. device select (CE) active input. This signal asserted prior HIGH transition order generate valid internal device select signal. Holding this HIGH will place device standby mode. ports stay active times. Address Latch Enable input used latch addresses present address lines A15-A8 AD7-AD0 into device. addresses latched when transitions from HIGH LOW.
valid data being presented AD0-AD7 pins. data will latched into X88C75 rising edge Page Write Operation X88C75 supports page mode write operations. This allows microcontroller write from thirty-two bytes data X88C75. Each individual write within page write operation must conform byte write timing requirements. falling edge starts timer delaying internal programming cycle 100µs: therefore, each successive write operation must begin within 100µs last byte written. waveform page illustrates sequence timing requirements.
PA7-PA0 PB7-PB0 A15-A8 AD7-AD0
Figure Page Write Operation
OPERATION BYTE BYTE BYTE LAST BYTE READ (1)(2) AFTER READY NEXT WRITE OPERATION
Toggle Polling Because X88C75 typical write timing less than specified 5ms, Toggle Polling been provided determine early completion write cycle. During internal programming cycle, I/O6 will toggle from subsequent attempts read from memory plane that being updated. When internal cycle complete, toggling will cease device will accessible additional read write operations. dual plane architecture, reads polling must occur from plane that written; that state during write must match state during polling.
Figure Toggle Polling
OPERATION LAST BYTE WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X X88C75 READY NEXT OPERATION
DATA PROTECTION X88C75 provides levels data protection through software control. There global software data protection feature similar industry standard E2PROMs Block Lock Protect write lockout protection providing secondary level data security option. Software Data Protection Software Data Protection (SDP) employed protect entire array against inadvertent writes during power-up/power-down operations. X88C75 shipped from factory with enabled. With enabled, inadvertent attempts write X88C75 will blocked. system still write data, only when write operation (page byte) preceded three-byte command sequence. write operations, both command sequence data write operations must conform page write timing requirements. mode also enabled anytime nonvolatile configuration registers modified. These include writing map, map, BPR. Figure Writing With Enabled
Figure Sequence Deactivate Software Data Protection
Reference A15-A13 setting register Address (A12) memory plane being read.
Block Lock Protect Write Lockout X88C75 provides second level data security referred Block Lock Protect write lockout Block Protect). This accessed through extension command sequence. Block Protect allows user lockout writes blocks memory. Unlike which prevents inadvertent writes, still allows easy system access writing memory, Block Protect will lockout attempts unless specifically disabled issuing deactivation sequence. This feature used higher level protection system where portion memory used store system kernel protect from application programs residing other blocks.
Perform Byte Page Write Operations
Reference A15-A13 setting register Address (A12) updated memory plane
Setting write lockout accomplished writing fivebyte command sequence opening access Block Protect Register (BPR). After fifth byte written, user writes BPR, selecting which blocks protect unprotect. write operations, both command sequence writing data BPR, must conform
page write timing requirements. should noted that accessing automatically sets upper level SDP. some reason user does want enabled, they reset using normal reset command sequence. This will affect state blocks that were write lockout state will remain write lockout state. Figure Block Protect Register Format
BLOCK ADDRESS 0000-03FF 0400-07FF 0800-0BFF 0C00-0FFF 1000-13FF 1400-17FF 1800-1BFF 1C00-1FFF Protect, Unprotect Block Specified
Figure Setting Command Sequence
Write mask value address
format block illustrated above. command sequence illustrated right. Figure Microcontroller
80C51 SLIC 0000H RESET VECTORS PHOENIX KEYBOARD CODE SLIC LOADER (SLIC) STORE REGS SUBROUTINES LAPKIT X88C75 SLIC CUSTOMIZED KEYBOARD MATRICES
(BPR Register Global Set) Reference A15-A13 setting register Address (A12) memory plane being read.
CHK_ENABLE SPECIAL FUNCTION TABLE SERVICE INTERRUPT VECTORS
3000H 3334H 3370H 3FFFH 4000H 5FFFH 7800H 7BFFH
BYTES BYTE ALTERABLE DUAL PLANE ARCHITECTURED NON-VOLATILE MEMORY (MAPPABLE PAGE BITS 2-0)
CUSTOM CODE 5FFF
(SPECIAL FUNCTION REGISTER) BLOCK (MAPPABLE PAGE SFRM REGISTER)
Figure Chip Registers
Special Function Register Memory Register Port Data Register
Port Data Register
Interrupt Status Register
DIRA DIRB STRA STRB
Bytes General Purpose SRAM
NOTE: value returned reading these registers complement actual data. These registers nonvolatile special sequence used alter their contents. other registers initialized valid reset input signal when device power cycled.
Programmable Address Decoding X88C75 features internal programmable address decoder which allows nonvolatile memory array internal registers mapped various locations 64K-byte memory map. register mappable into 1K-byte block, while nonvolatile memory array mappable into 8K-byte block. mapping controlled nonvolatile configuration registers, Register Memory Register. Their bits mapped follows:
A15-A10 upper address bits 1K-byte page where memory mapped.
Setting these bits combination other than "00" "11" will interfere with device proper operation. Memory Register (EEM)
Figure Setting Register
Modifying these three bits changes location program memory within address map.The A15-A13 correspond upper three address bits 8Kbyte page where program memory will mapped.
controls polarity RESET input pin. RESET Active RESET Active HIGH
Exit Routine Don't Care B[2:0] [2:0] Address (A12) memory plane being read.
Port configured either general purpose port (normal mode), latched address mode (LAM). option programs port output demultiplexed order byte address latched into X88C75 ALE. selects between these modes. PORT Port Port outputs address byte (A7-A0) Setting Mapping Registers mapping registers written using modified version Software Data Protection sequence. timings must adhere normal Software Data Protection sequence. complemented contents register memory register read microcontroller their corresponding addresses. physical memory location these registers derived adding following offset base address: Register Memory Register
Figure Setting Program Memory Register
Exit Routine Don't Care B[2:0] [2:0] Address (A12) memory plane being read.
regions specified registers overlap, only will accessible.
Interrupt Status Register (ISR) Interrupt Status Register volatile register used configure interrupt condition ports well determine interrupt status ports. X88C75 ports generate interrupt microcontroller upon proper transition specified configuration register) either STRA STRB pins when corresponding port configured input. flag when input strobes toggled provided that their corresponding interrupt enable bits (ENA, ENB) set. flag cleared when latched data read (PDR) pending interrupt Figure Interrupt Status Register status flag (INTA, INTB) forced interrupt service routine. Interrupt service routine should examine interrupt status flags (INTA, INTB) identify source pending interrupt. memory interrupt status flag (EOW) another means detect early completion write cycle. When ENEE enabled, hardware will flag, interrupt microcontroller internal programming cycle. Toggle Polling replaced this hardware interrupt, which reduces software overhead. flag should cleared software. interrupt status register bits mapped follows.
Interrupt Flag pending interrupt Interrupt request Port Interrupt Status pending interrupt Port latched data when valid transition occurred STRA port input port. Port Interrupt Status pending interrupt Port latched data when valid transition occurred STRB port input port. Port Interrupt Enable Mask interrupt Interrupt enabled
EEPROM Interrupt Status Programming progress hardware when completes programming previously written data
EEPROM Interrupt Enable Mask interrupt Interrupt enabled
Port Interrupt Enable Mask interrupt Interrupt enabled
Configuration Register (CR) Configuration Register volatile register used configure operation ports. configuration register allows microcontroller designate whether each ports input output, what type output drive used, what polarity strobe lines, STRA STRB. configuration register shown below. IRST configuration register controls method used clear port interrupt request flags(INTA, INTB). interrupts reset either reading interrupt source writing Interrupt Status Register. interrupt must disabled prior changing strobe polarity bits(STPA, SPTB), port direction bits (DIRA, DIRB) Otherwise, attempt modify status these bits cause interrupt occur. Port Data Registers (PDR) PDRA/PDRB byte-wide latches which hold port data. When port configured output, outputs latch connected port pins. Writing generates pulse port strobe latches data. port configured input, inputs latch connected port pins. External data latched into positive edge clock. port strobe input strobe polarity bit(STPA, STPB) XORed generate input clock. Port Registers (PPR) read-only Port Registers used reading current status external port pins. Accessing causes values port pins placed data bus. port direction control bits configuration register direction entire port control mechanism provided program direction individual pins. However, ports have flexible architecture which allows operating ports bidirectional mode using read feature. port operated input/output mode configuring open-drain output port. port wire-OR (AWO, port data direction (DIRA, DIRB should "1". bits which correspond port pins assigned inputs should programmed "1". monitoring status input pins, read. this application port strobe latch output mode. open-drain mode, there weak internal pull-ups port pins, however external pull-ups must used proper switching lines.
Figure Configuration Register
DIRA DIRB STPA STPB
Interrupt Request Reset Mode This controls clearing interrupt request flag. Reading interrupt source Writing request register
Strobe Strobe Polarity Active Active HIGH
Strobe Strobe Polarity Active Active HIGH
Port Outputs CMOS Open-drain
Port Direction Flag Input mode Output mode
Port Outputs CMOS Open-drain
Port Direction Flag Input mode Output mode
STATIC BLOCK There bytes volatile static registers mapped region. They reside 200H20FH area offset from base address. Accessing these registers done through external operations both writes reads. PRINCIPLES OPERATION Port Operation expansion ports accessible software using their assigned memory mapped addresses. Each port occupies addresses plane, Port Data Register Port Register. These registers their location 1K-byte register memory space shown page ports configured either inputs outputs, DIRA DIRB bits configuration register used select between modes. input signal strobe pin, when corresponding port configured input, clock input port latch. These transparent latches trailing edge strobe pulse used latch data present input pins. strobe signal polarity configurable using STPA STPB bits configuration register. Writing port data register output port will generate pulse fixed duration strobe pin. data also simultaneously arrives port output pins. latched data stays there until data written port data register. strobe pulse shape controlled state STPA STPB bits configuration register. forces valid transition corresponding strobe active HIGH sets active When external strobe signal applied input port, latching input data followed setting interrupt flags. INTA INTB interrupt flags used ports respectively, along with interrupt flag strobe pulse input. External interrupt (IRQ) generated interrupt enable flags (ENA ENB) software. former enables port interrupt latter enables port interrupt.
Figure Block Diagram Ports
STROBE (Port Input)
Port WRITE (Port Output) Input LATCH Output Port READ (Port Input)
READ (Port Output)
port output drivers either CMOS opendrain. wire-OR bits (AWO, BWO) configuration register used make selection. When bits CMOS drivers enabled. Setting these bits will enable open-drain output drivers. Small pullup resistors should used pins open-drain ports. active open-drain output. embedded systems applications, this signal connected microcontroller interrupt input through either direct connection interrupt controller. Table depicts three sources interrupts their associated flags. Under normal conditions, port interrupt flags set, port which configured input strobe line toggled. port interrupt enable flag set, gets while flag set, then signal asserted. stays valid long interrupt flags cleared software hardware. Another interrupt source Write flag (EOW) which hardware every internal programming cycle. interrupt from this source controlled ENEE ISR. ENEE enabled, then generate external interrupt. interrupt cleared setting "0". Table X88C75 Interrupt Sources Interrupt Source PORT PORT Interrupt Enable ENEE Status Flag INTA INTB Flag
PORTS INTERRUPTS X88C75 features 8-bit ports which equipped with configurable interrupt module. interrupts used signal reception data input port data latch. When port configured output, longer generate interrupts. input port interrupt mechanism controlled external strobe pins (STRA, STRB). Detecting valid transition will interrupt flags latch input data. external interrupts from ports masked using interrupt enable bits (ENA, ENB) ISR. Once external interrupt asserted, clearing interrupt flags will cause signal return idle state. There ways resetting interrupt flags. selection made using IRST configuration register. IRST set, then interrupt flags cleared writing positions corresponding interrupt flags (INTA, INTB) ISR. When IRST cleared, reading automatically clears interrupt flags. SOFTWARE CONTROLLED PORT OPERATIONS individual clock signals, that control input latches load external data present port pins, generated XORing strobe polarity strobe input port. strobe polarity bits (STPA, STPB) used program active edge strobe inputs. However, external strobe input permanently tied VCC, then strobe polarity controls input latch clock signal. When port strobe polarity have identical logic levels, corresponding latch active change port inputs will show latch outputs. Holding strobe input current levels changing strobe polarity value will generate positive transition clock signal, causing latch outputs reflect previous logic state port pins. clock transition sets interrupt flags, interrupts have been enabled, then external interrupt signal will asserted.
This feature allows port input operation permanently tying STRx inputs VSS, using STPx bits control latches. Another advantage this feature software generated interrupts. Since clocking latch causes corresponding port INTx flags set, enabling interrupts microcontroller forced execute responsible service newly latched data. WRITE (EOW) INTERRUPT internal programming cycle requires several milliseconds either single byte write page write. updated memory plane inaccessible while programming progress. However, opposite plane still available program fetch data read operations. X88C75 means signaling internal programming cycle. Toggle Polling technique, last written byte successively read. read data toggles while programming cycle still progress. software continually monitor device responses determine again access plane. other method, internal programming cycle, hardware sets flag. software either poll this flag enable interrupts setting ENEE ISR. Effective made clearing prior initiating write operation. interrupt enabled, external interrupt will asserted completion internal write cycle. interrupt cleared setting "0". USING PORT BIDIRECTIONAL MODE order port bidirectional mode, configured open drain output port. Small pull-up resistors required port output pins. positions Port Data Register corresponding port inputs should contain "1". inputs then read accessing PPR. Data latched into device, inputs must stay valid throughout read cycle. port strobe configured output cannot used port latch clock input.
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X88C75 -10°C +85°C X88C75I -65°C +135°C Storage Temperature -65°C +150°C Voltage with Respect D.C. Output Current Lead Temperature (Soldering, seconds) 300°C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. -40°C -55°C Max. +70°C +85°C +125°C
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Supply Voltage X88C75
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol ISB1(CMOS) ISB2(TTL) VlL(3) VIH(3) Parameter Current (Active) Current (Standby) Current (Standby) Input Leakage Current Output Leakage Current Input Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage Min. Max. Units Test Conditions VIL, I/O's Open,Other Inputs VIH, I/O's Open, Other Inputs VIH, VIH, I/O's Open, Other Inputs VIH, VOUT VCC, PSEN
CAPACITANCE +25°C, 1MHz, Symbol CI/O(4) CIN(4) POWER-UP TIMING Symbol tPUR(4) tPUW(4) Parameter Power-Up Read Power-Up Write Max. Units
Test Input/Output Capacitance Input Capacitance
Notes: min. max. reference only tested. This parameter periodically sampled 100% tested.
A.C. CONDITIONS TEST Input Pulse Levels Input Rise Fall Times Input Output Timing Levels 10ns 1.5V
EQUIVALENT A.C. TEST CIRCUIT
1.92K OUTPUT 1.37K 100pF
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) PSEN Controlled Read Cycle Symbol tLHLL tAVLL tLLAX tPLDV tPHDX tELLL PWPL tPHDZ tPLDX Parameter Pulse Width Address Setup Time Address Hold Time PSEN Read Access Time Data Hold Time Chip Enable Setup Time PSEN Pulse Width PSEN Setup Time PSEN Hold Time PSEN Disable Output High PSEN Output Min. Max. Units
PSEN Controlled Read Timing Diagram
tLHLL tAVLL A/D0-A/D7 tPLDX tPLDV A8-A12 PSEN PWPL tLLAX DOUT tPHDX tPHDZ ADDRESS tELLL
This parameter periodically sampled 100% tested.
Controlled Read Cycle Symbol tLHLL tAVLL tLLAX tRLDV tRHDX tELLL PWRL tRDS tRDH tRHDZ tRLDX Parameter Pulse Width Address Setup Time Address Hold Time Read Access Time Data Hold Time Chip Enable Setup Time Pulse Width Setup Time Hold Time Disable Output High Output Min. Max. Units
Controlled Read Timing Diagram
tRDH tLHLL tAVLL A/D0-A/D7 tRLDX tRLDV A8-A12 tRDS
tLLAX DOUT tRHDX tRHDZ ADDRESS PWRL
This parameter periodically sampled 100% tested.
Controlled Write Cycle Symbol tLHLL tAVLL tLLAX tDVWH tWHDX tELLL tWLWH tWRS tWRH tBLC Parameter Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Enable Setup Time Pulse Width Setup Time Hold Time Byte Load Time (Page Write) Write Cycle Time Min. Max. Units
Controlled Write Timing Diagram
tWRH tLHLL tAVLL A/D0-A/D7 tLLAX tDVWH A8-A12 tWRS
minimum cycle time allowed from system perspective unless polling techniques used. maximum time device requires automatically complete internal write operation.
Port Read Diagram
DATA VALID INTERRUPT RECOGNIZED
DATA VALID 6340 F27.1
NOTE: *Figure shows active HIGH strobes.
PORT READ TIMING Symbol tSVSX tDVSV tSVDX tSVIV tIAD tLHLL tRXIX tAVLL tLLAX tLLWL tRLDV Parameter Strobe Pulse Width Data Port Setup Data Port Hold Time Interrupt Request Strobe Pulse Width Address setup time Address hold time Access Time Min. Max. Units
Port Write Diagram
NOTE: *Figure shows active HIGH strobes.
PORT WRITE TIMING Symbol tLHLL tWCS tLLWL tWLWH tAVLL tLLAX tDVWH tWHDX tSVSX tQVSV tPOS Parameter Pulse Width Write Chip Select Setup Time Pulse Width Write Address Setup Time Write Address Hold Time Data Setup Time Data Hold Time Strobe Pulse Width Strobe Access Time Port Output Setup Time Min. Max. Units
(Latch Address Mode) Diagram
TIMING Symbol tLHLL tAVLL tLLAX tPOS Parameter Pulse Width Address Setup Time Address Hold Time Port Output Setup Time Min. Max. Units
WAVEFORM INPUTS Must steady change from HIGH change from HIGH Don't Care: Changes Allowed OUTPUTS Will steady Will change from HIGH Will change from HIGH Changing: State Known Center Line High Impedance
44-PIN PLASTIC LEADED CHIP CARRIER PACKAGE TYPE
0.695 (17.65) 0.685 (17.40) 0.655 (16.64) 0.650 (16.51) 0.500 (12.70) REF.
SEATING PLANE ±0.004 LEAD PLANARITY 0.020 (0.51) 0.110 (2.79) 0.100 (2.54) 0.180 (4.57) 0.165 (4.19) 0.156 (3.96) 0.145 (3.68)
0.695 (17.65) 0.685 (17.40) 0.655 (16.64) 0.650 (16.51) 0.500 (12.70)REF.
0.050 (1.27) REF.
0.021 (0.63) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.630 (16.00) 0.590 (14.99)
0.011 (0.28) 0.009 (0.23)
NOTES: DIMENSIONS INCHES PARENTHESES MILLIMETERS) DIMENSIONS WITH TOLERANCE REFERENCE ONLY
PACKAGING INFORMATION 44-LEAD THIN QUAD FLAT PACK (TQFP) PACKAGE TYPE
GAGE PLANE 0.25
MILLIMETERS 1.20 0.15 1.05 0.38 0.200 10.10 10.10 12.10 12.10 0.75 1.00 0.05 0.95 0.22 0.090 9.90 9.90 11.90 11.90 0.45
INCHES 0.039 0.002 0.037 0.009 0.004 0.390 0.390 0.468 0.468 0.018 0.047 0.006 0.041 0.015 0.008 0.398 0.398 0.476 0.476 0.030
NOTES: GAGE PLANE DIMENSION LEAD COPLANARITY SHALL 0.10MM [0.004] MAXIMUM.
48-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE
2.480 (62.99) 2.385 (60.58)
0.580 (14.73) 0.485 (12.32) INDEX 2.300 (58.42) REF. 0.088 (2.24) 0.040 (1.02)
SEATING PLANE 0.200 (5.08) 0.115 (2.92)
0.195 (4.95) 0.125 (3.18)
0.030 (0.76) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29)
0.070 (17.78) 0.030 (7.62)
0.022 (0.56) 0.014 (0.36)
0.625 (15.88) 0.590 (14.99)
TYP. 0.010 (0.25)
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS) PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Temperature Range Blank Commercial +70°C Industrial -40°C +85°C Military -55°C +125°C Package 44-Lead PLCC 44-Lead TQFP 48-Lead Plastic
LIMITED WARRANTY Devices sold Xicor, Inc. covered warranty patent indemnification provisions appearing Terms Sale only. Xicor, Inc. makes warranty, express, statutory, implied, description regarding information forth herein regarding freedom described devices from patent infringement. Xicor, Inc. makes warranty merchantability fitness purpose. Xicor, Inc. reserves right discontinue production change specifications prices time without notice. Xicor, Inc. assumes responsibility circuitry other than circuitry embodied Xicor, Inc. product. other circuits, patents, licenses implied. PATENTS Xicor products covered more following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents additional patents pending. LIFE RELATED POLICY situations where semiconductor component failure endanger life, system designers using this product should design system with appropriate error detection correction, redundancy back-up features prevent such occurrence. Xicor's products authorized critical components life support devices systems. Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
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