WM8759

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WM8759 - WM8759

WM8759 high performance stereo with integrated headphone driver. designed audio applications such portable DVD, players consumer equipment with line output headphone output connections. WM8759 supports data input word lengths from 24-bits sampling rates 192kHz. WM8759 consists serial interface port, digital interpolation filters, multi-bit sigma delta modulators stereo 14-pin SOIC package. hardware control interface used selection audio data interface format, enable de-emphasis. WM8759 supports I2S, right Justified interfaces. Operating split analog digital supplies WM8759 allows very lower power consumption from digital section, whilst supporting large output powers from analog headphone driver.
WM8759
24-bit 192kHz Stereo with Headphone Buffer
FEATURES
Stereo with headphone driver 50mW power into load 3.3V supply Audio Performance 100dB (`A' weighted 48kHz) -88dB line level
-72dB headphone Sampling Frequency: 8kHz 192kHz Selectable Audio Data Interface Format I2S, 16-bit Right Justified 2.7V 5.5V Supply Operation, Split Analog-digital supplies 14-lead SOIC Package Typical power consumption 20mW 2.7V supply
APPLICATIONS
Portable music Players Home music players Digital
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS
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Pre-Production, June 2006,
Copyright 2006 Wolfson Microelectronics
WM8759
Pre-Production
TABLE CONTENTS DESCRIPTION FEATURES.1 APPLICATIONS BLOCK DIAGRAM TABLE CONTENTS CONFIGURATION.3 ORDERING INFORMATION DESCRIPTION ABSOLUTE MAXIMUM RATINGS.5 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS
MASTER CLOCK TIMING DIGITAL AUDIO INTERFACE
DEVICE DESCRIPTION.9
GENERAL INTRODUCTION CIRCUIT DESCRIPTION CLOCKING SCHEMES DIGITAL AUDIO INTERFACE AUDIO DATA SAMPLING RATES.13 HARDWARE CONTROL MODES DIGITAL FILTER CHARACTERISTICS.15 FILTER RESPONSES.15 DIGITAL DE-EMPHASIS CHARACTERISTICS.16
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS POWER UP/DOWN SEQUENCE.17 LAYOUT RECOMMENDATIONS
PACKAGE DRAWING.19 IMPORTANT NOTICE
ADDRESS:
June 2006
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WM8759
CONFIGURATION
ORDERING INFORMATION
DEVICE WM8759GED/V TEMPERATURE RANGE +85oC PACKAGE 14-lead SOIC (Pb-free) 14-lead SOIC WM8759GED/RV
MOISTURE SENSITIVITY LEVEL MSL3
PEAK SOLDERING TEMPERATURE 260°C
(Pb-free, tape reel)
MSL3
260°C
Note: Reel quantity 3,000
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WM8759
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NAME LRCIN BCKIN ENABLE HPOUTR AGND AVDD HPOUTL DGND DVDD DEEMPH TYPE Digital input Digital input Digital input Digital input Analogue output Analogue output Supply Supply Analogue output Digital Supply Digital Supply Digital input Sample rate clock input Serial audio data input clock input Enable input powered down, enabled Analogue internal reference Right channel output Ground reference analog circuits substrate connection Positive supply analog circuits Left channel output Digital ground supply Digital positive supply De-emphasis select, Internal pull down High de-emphasis de-emphasis Data input format select, Internal pull 16-bit right justified `late' High 16-24-bit `early' Master clock input
FORMAT
Digital input
MCLK
Digital input
Note: Digital input pins have Schmitt trigger input buffers.
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WM8759
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings stress ratings only. Permanent damage device caused continuously operating beyond these limits. Device functional operating limits guaranteed performance specifications given under Electrical Characteristics test conditions specified. Sensitive Device. This device manufactured CMOS process. therefore generically susceptible damage from excessive static voltages. Proper precautions must taken during handling storage this device. Wolfson tests package types according IPC/JEDEC J-STD-020B Moisture Sensitivity determine acceptable storage conditions prior surface mount assembly. These levels are: MSL1 unlimited floor life <30°C Relative Humidity. normally stored moisture barrier bag. MSL2 storage year <30°C Relative Humidity. Supplied moisture barrier bag. MSL3 storage hours <30°C Relative Humidity. Supplied moisture barrier bag. Moisture Sensitivity Level each package type specified Ordering Information. CONDITION Supply voltage Voltage range digital inputs Master Clock Frequency Operating temperature range, Storage temperature prior soldering Storage temperature after soldering -25°C -0.3V -0.3V +0.3V 50MHz +85°C
30°C -65°C +150°C
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WM8759
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ELECTRICAL CHARACTERISTICS
PARAMETER Supply range Ground Analog supply current Digital supply current Power down current (note SYMBOL AVDD, DVDD AGND, DGND AVDD AVDD 3.3V DVDD DVDD 3.3V AVDD=DVDD=5V 0.01 TEST CONDITIONS UNIT
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD DVDD 3.3V, 48kHz, MCLK 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input level Input HIGH level Output Output HIGH Analogue Reference Levels Reference voltage (CAP) Potential divider resistance Output (Load 10k. 50pF) 0dBFs Full scale output voltage (Note 5,6,7) (Note 5,6,7) (Note 5,6,7) (Note 5,6,7) outputs A-weighted, 48kHz A-weighted 96kHz A-weighted 192kHz A-weighted, 48kHz 3.3V A-weighted 96kHz 3.3V weighted 48kHz 1kHz, 0dBFs 1kHz, 0dBFs AVDD/5 Vrms RCAP AVDD AVDD/2 DVDD 0.3V DGND 0.3V SYMBOL TEST CONDITIONS UNIT
(Note 5,6,7)
(Note 5,6,7) THD+N (Note THD+N driving headphone channel separation load load
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Pre-Production Test Conditions AVDD DVDD 3.3V, +25oC, 48kHz, MCLK 256fs unless otherwise stated. PARAMETER Analogue Output Levels Output level Load 10k, 0dBFS Load 10k, 0dBFS, (AVDD 3.3V) 0.72 midrail a.c. coupled midrail a.c. coupled (AVDD 3.3V) SYMBOL TEST CONDITIONS
WM8759
UNIT Vrms Vrms %FSR
Gain mismatch channel-to-channel Minimum resistance load
Output d.c. level
AVDD/2
Notes: Ratio output level with 1kHz full scale input, output level with zeros into digital input, measured weighted over 20Hz 20kHz bandwidth. performance measurements done with 20kHz pass filter, where noted A-weight filter. Failure such filter will result higher THD+N lower Dynamic Range readings than found Electrical Characteristics. pass filter removes band noise; although audible affect dynamic specification values. decoupled with 10uF 0.1uF capacitors (smaller values result reduced performance). Power down occurs 1.5µs after MCLK stopped. Signal-to-noise ratio (dB) measure difference level between full scale output output with signal applied. Auto-zero Automute function employed achieving these results). Dynamic range (dB) measure difference between highest lowest portions signal. Normally THD+N measurement 60dB below full scale. measured signal then corrected adding 60dB (e.g. THD+N -60dB= -32dB, 92dB). THD+N (dB) THD+N ratio, values, (Noise Distortion)/Signal. Stop band attenuation (dB) degree which frequency spectrum attenuated (outside audio band). Channel Separation (dB) Also known Cross-Talk. This measure amount channel isolated from other. Normally measured sending full scale signal down channel measuring other.
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WM8759 MASTER CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
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Figure Master Clock Timing Requirements Test Conditions +25oC, 48kHz, MCLK 256fs unless otherwise stated. PARAMETER System Clock Timing Information
MCLK Master clock pulse width high MCLK Master clock pulse width MCLK Master clock cycle time MCLK Duty cycle Time from MCLK stopping power down.
SYMBOL tMCLKH tMCLKL tMCLKY
TEST CONDITIONS
40:60
UNIT
60:40
DIGITAL AUDIO INTERFACE
tBCH BCKIN tBCY tBCL
LRCIN tLRH tLRSU
Figure Digital Audio Data Timing Test Conditions +25oC, 48kHz, MCLK 256fs unless otherwise stated. PARAMETER BCKIN cycle time BCKIN pulse width high BCKIN pulse width LRCIN set-up time BCKIN rising edge LRCIN hold time from BCKIN rising edge set-up time BCKIN rising edge hold time from BCKIN rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH TEST CONDITIONS UNIT
Audio Data Input Timing Information
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WM8759
DEVICE GENERAL INTRODUCTION
WM8759 high performance with integrated headphone output buffer, designed digital consumer audio applications. range features make ideally suited portable players, players other consumer audio equipment. WM8759 complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo output smoothing filters. fully compatible ideal partner range industry standard microprocessors, controllers DSPs. novel multi sigma-delta design used, utilising 128x oversampling rate, optimise signal noise performance offer increased clock jitter tolerance. `high-rate' operation, oversampling ratio system clocks 128fs 192fs) Control internal functionality device provided hardware control (pin programmed). Operation using master clocks 256fs, 384fs, 512fs 768fs provided, selection between clock rates being automatically controlled. Sample rates (fs) from less than 8kHz 96kHz allowed, provided appropriate system clock input. Support also provided 192kHz using master clock 128fs 192fs. audio data interface supports 16-bit right justified 16-24-bit (Philips left justified, delayed) interface formats. interface also supported, enhancing interface options user. Split analog digital 2.7-5.5V supply used, output amplitude scaling with absolute analog supply level. supply voltage operation current consumption combined with count small package make WM8759 attractive many consumer applications. power down mode provided, allowing power consumption minimised. device packaged small 14-pin SOIC.
CIRCUIT WM8759 designed allow playback 24-bit audio similar data with high resolution noise distortion. Sample rates 192kHz used, with much lower sample rates being acceptable provided that ratio sample rate (LRCIN) master clock (MCLK) maintained required rates. DACs WM8759 implemented using sigma-delta oversampled conversion techniques. These require that samples digitally filtered interpolated generate samples much higher rate than 192kHz input rate. This sample stream then digitally modulated generate digital pulse stream that then converted analogue signals switched capacitor DAC. advantage this technique that linearised using noise shaping techniques, allowing 24-bit resolution using non-critical analogue components. further advantage that high sample rate output means that smoothing filters output need only have fairly crude characteristics order remove characteristic steps, images output DAC. prevent generation unwanted tones dithering used digital modulator along with higher order modulator. multi-bit switched capacitor technique used reduces sensitivity clock jitter, dramatically reduces band noise compared switched current single techniques used other implementations. voltage used reference DACs. Therefore amplitude signals outputs will scale with amplitude voltage pin. external reference could used drive into desired, with value typically about midrail ideal optimum performance.
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WM8759
Pre-Production outputs DACs buffered device buffer amplifiers capable driving loads either line level headphone level impedance. advanced multi-bit used WM8759 produces less band noise than single traditional sigma delta DACs, most applications where line level output required, post filter required. Typically coupling capacitor setting resistor ground only components required output chip.
CLOCKING SCHEMES
typical digital audio system there only central clock source producing reference clock which audio data processing synchronised. This clock often referred audio system's Master Clock. external master clock applied directly through MCLK input with configuration necessary sample rate selection. Note that WM8759, MCLK used derive clocks path. path consists sampling clock, digital filter clock digital audio interface timing. system where there number possible sources reference clock recommended that clock source with lowest jitter used optimise performance DAC. device powered down stopping MCLK. this state power consumption substantially reduced.
DIGITAL AUDIO INTERFACE
Audio data applied internal filters Digital Audio Interface. Three interface formats supported: Right Justified mode mode mode
formats send first. data format selected with FORMAT pin. When FORMAT LOW, right justified data format selected word lengths 16-bits used. When FORMAT HIGH, format selected word length value 24-bits used. word length shorter than 24-bits used, unused bits should padded with zeros). LRCIN BCKINs less duration, compatible format selected. Early Late clock formats supported, selected state FORMAT pin. `Packed' mode (i.e. only clocks LRCIN period) operation also supported both (16-24 bits) right justified formats, bit). `packed' format 16-bit word length applied BCKINS LRCIN half period), device auto-detects this mode switches 16-bit data length.
MODE
WM8759 supports word lengths 16-24 bits mode. mode, digital audio interface receives data input. Audio Data time multiplexed with LRCIN indicating whether left right channel present. LRCIN also used timing reference indicate beginning data words. modes, minimum number BCKINs LRCIN period times selected word length. LRCIN must high minimum word length BCKINs minimum word length BCKINs. mark space ratio LRCIN acceptable provided above requirements met. mode, sampled second rising edge BCKIN following LRCIN transition. LRCIN during left samples high during right samples.
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WM8759
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
BCKIN BCKIN
Figure Mode Timing Diagram
RIGHT JUSTIFIED MODE
WM8759 supports word lengths 16-bits right justified mode. right justified mode, digital audio interface receives data input. Audio Data time multiplexed with LRCIN indicating whether left right channel present. LRCIN also used timing reference indicate beginning data words. right justified mode, minimum number BCKINs LRCIN period times selected word length. LRCIN must high minimum word length BCKINs minimum word length BCKINs. mark space ratio LRCIN acceptable provided above requirements met. right justified mode, sampled rising edge BCKIN preceding LRCIN transition. LRCIN high during left samples during right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
Figure Right Justified Mode Timing Diagram
MODE
DSP/PCM mode, left channel available either (mode (mode rising edge BCLK (selectable LRP) following rising edge LRC. Right channel data immediately follows left channel data. Depending word length, BCLK frequency sample rate, there unused BCLK cycles between right channel data next sample. device master mode, output will resemble frame pulse shown Figure Figure device slave mode, Figure Figure possible length frame pulse less than 1/fs, providing falling edge frame pulse occurs greater than BCLK period before rising edge next frame pulse.
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WM8759
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Figure DSP/PCM Mode Audio Interface (mode LRP=0, Master)
Figure DSP/PCM Mode Audio Interface (mode LRP=1, Master)
Figure DSP/PCM Mode Audio Interface (mode LRP=0, Slave)
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WM8759
Figure DSP/PCM Mode Audio Interface (mode LRP=0, Slave)
AUDIO DATA SAMPLING RATES
master clock WM8759 supports audio sampling rates from 128fs 768fs, where audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz 192kHz. master clock used operate digital filters noise shaping circuits. WM8759 master clock detection circuit that automatically determines relation between master clock frequency sampling rate within master clocks). there greater than clocks error, interface shuts down mutes output. master clock should synchronised with LRCIN, although WM8759 tolerant phase differences jitter this clock. SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz MASTER CLOCK FREQUENCY (MHZ) (MCLK) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9344 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable
Table Master Clock Frequencies Versus Sampling Rate
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WM8759 HARDWARE CONTROL MODES
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WM8759 hardware programmable providing user with options select input audio data format, de-emphasis mute.
ENABLE OPERATION
(ENABLE) controls operation chip. ENABLE device held power state. this held high device powered ensure correct operation essential that there high transition ENABLE after digital supplies have come This achieved providing ENABLE signal from external controller chip means simple network ENABLE pin. "Recommended External Components" "Application Information" section this datasheet. Note that ENABLE should used mute temporarily silence (between tracks example). ENABLE intended used mute control allow entry into power mode. Disabling device ENABLE effect powering down voltage pin. Repeated enabling/disabling device cause audible pops output.
HIGH PERFORMANCE MODE
rising edge ENABLE, DEEMPH sampled. device powers normally. high device goes into high performance high power consumption state. Once ENABLE high, DEEMPH controls selection de-emphasis filter.
INPUT AUDIO FORMAT SELECTION
FORMAT (pin controls data input format. FORMAT Table Input Audio Format Selection Notes: 16-24 mode, data from 16-24 bits more supported provided that LRCIN high minimum data width BCKINs minimum data width BCKINs, unless Note data widths greater than bits, LSB's will truncated most significant bits will used internal processing. exactly BCKIN cycles occur both high period LRCIN WM8759 will assume data 16-bit accept data accordingly. INPUT DATA MODE right justified 16-24
INPUT FORMAT SELECTION
FORMAT LRCIN DUTY CYCLE (MSB-first, right justified) format (Philips serial data protocol) LRCIN BCKIN Less Duration format `late' mode format `early' mode
Table Interface Formats
DE-EMPHASIS CONTROL
DEEMPH (pin input control selection de-emphasis filtering applied. DEEMPH Table De-emphasis Control DE-EMPHASIS
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WM8759
DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Edge Passband Ripple Stopband Attenuation Table Digital Filter Characteristics SYMBOL TEST CONDITIONS -3dB 0.444fs 0.555fs 0.487fs ±0.05 UNIT
FILTER RESPONSES
0.15
Response (dB)
Response (dB)
0.05 -0.05 -0.1
-100
-0.15 -0.2 Frequency (Fs) 0.05 0.15 0.25 Frequency (Fs) 0.35 0.45
-120
Figure Digital Filter Frequency Response -44.1, 96kHz
Figure Digital Filter Ripple -44.1, 96kHz
-0.2
Response (dB)
Response (dB)
-0.4
-0.6
-0.8 Frequency (Fs) 0.05 0.15 0.25 Frequency (Fs) 0.35 0.45
Figure Digital Filter Frequency Response -192kHz
Figure Digital Filter Ripple -192kHz
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WM8759
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DIGITAL DE-EMPHASIS CHARACTERISTICS
Response (dB)
Response (dB)
-0.5 -1.5
-2.5 Frequency (kHz) Frequency (kHz)
Figure De-Emphasis Frequency Response (32kHz)
Figure De-Emphasis Error (32kHz)
Response (dB)
Response (dB)
-0.1 -0.2
-0.3 Frequency (kHz) -0.4 Frequency (kHz)
Figure De-Emphasis Frequency Response (44.1kHz)
Figure De-Emphasis Error (44.1kHz)
Response (dB)
Response (dB)
-0.2 -0.4
-0.6 -0.8
Frequency (kHz)
Frequency (kHz)
Figure De-Emphasis Frequency Response (48kHz)
Figure De-Emphasis Error (48kHz)
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WM8759
APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS
Figure External Component Diagram application where ENABLE directly from rather than dedicated control line, resistor capacitor used ENABLE introduce short delay High transition ENABLE. This will ensure goes high after power supplies have time settle (see "ENABLE Operation" "Hardware Control Modes" section datasheet). However, ENABLE signal being provided from external controller chip rather than directly, will required.
POWER UP/DOWN SEQUENCE
POWER UP/DOWN SEQUENCE
click free operation, WM8759 should powered down specific sequence. Power-up: Power AVDD DVDD wait settle Turn clocks data (MCLK, BCLK, LRCLK, SDATA) Switch ENABLE from high
Power-down: Switch Enable from high Remove clocks data Power down AVDD DVDD
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WM8759 LAYOUT RECOMMENDATIONS
Pre-Production
Care should taken layout that WM8759 mounted following notes will help this respect: supply device should noise free possible. This accomplished large degree with 10uF bulk capacitor placed locally device 0.1uF high frequency decoupling capacitor placed close possible. best place 0.1uF capacitor directly between pins device same layer minimize track inductance thus improve device decoupling effectiveness. should noise free possible. This provides decoupling chip reference circuits thus noise present this will directly coupled device outputs. similar manner decoupling described above, this should decoupled with 10uF bulk capacitor local device 0.1uF capacitor close possible. Separate analogue digital track routing from each other. device split into analogue (pins digital (pins pins sections that allow routing these signals easily separated. physically separating analogue digital signals, crosstalk from minimized. unbroken solid plane. achieve best performance from device, advisable have either plane layer multilayer dedicate side layer plane. double sided implementations best route many signals possible device mounted side board, with opposite side acting plane. plane greatly reduces electrical emissions from minimizes crosstalk between signals.
evaluation board available WM8759 that demonstrates above techniques excellent performance achievable from device. This ordered User manual downloaded from Wolfson site www.wolfsonmicro.com
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WM8759
PACKAGE DRAWING
SOIC 3.9mm Wide Body DM001.C
SEATING PLANE
0.10 (0.004)
Symbols REF:
Dimensions (MM) 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.55 8.75 3.80 4.00 1.27 5.80 6.20 0.25 0.50 0.40 1.27 JEDEC.95, MS-012
Dimensions (Inches) 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3367 0.3444 0.1497 0.1574 0.05 0.2284 0.2440 0.0099 0.0196 0.0160 0.0500
NOTES: LINEAR DIMENSIONS MILLIMETERS (INCHES). THIS DRAWING SUBJECT CHANGE WITHOUT NOTICE. BODY DIMENSIONS INCLUDE MOLD FLASH PROTRUSION, EXCEED 0.25MM (0.010IN). MEETS JEDEC.95 MS-012, VARIATION REFER THIS SPECIFICATION FURTHER DETAILS.
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WM8759
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IMPORTANT NOTICE
Wolfson Microelectronics ("Wolfson") products services sold subject Wolfson's terms conditions sale, delivery payment supplied time order acknowledgement.
Wolfson warrants performance products specifications effect date shipment. Wolfson reserves right make changes products specifications discontinue product service without notice. Customers should therefore obtain latest version relevant information from Wolfson verify that information current.
Testing other quality control techniques utilised extent Wolfson deems necessary support warranty. Specific testing parameters each device necessarily performed unless required regulation.
order minimise risks associated with customer applications, customer must adequate design operating safeguards minimise inherent procedural hazards. Wolfson liable applications assistance customer product design. customer solely responsible selection Wolfson products. Wolfson liable such selection circuitry other than circuitry entirely embodied Wolfson product.
Wolfson's products intended life support systems, appliances, nuclear systems systems where malfunction reasonably expected result personal injury, death severe property environmental damage. products customer such purposes customer's risk.
Wolfson does grant licence (express implied) under patent right, copyright, mask work right other intellectual property right Wolfson covering relating combination, machine, process which products services might used. provision publication third party's products services does constitute Wolfson's approval, licence, warranty endorsement thereof. third party trade marks contained this document belong respective third party owner.
Reproduction information from Wolfson datasheets permissible only reproduction without alteration accompanied associated copyright, proprietary other notices (including this notice) conditions. Wolfson liable unauthorised alteration such information reliance placed thereon.
representations made, warranties given, and/or liabilities accepted person which differ from those contained this datasheet Wolfson's standard terms conditions sale, delivery payment made, given and/or accepted that person's risk. Wolfson liable such representations, warranties liabilities reliance placed thereon person.
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June 2006

WM8759

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