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W78E58 W78C58


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W78E58 8-BIT MICROCONTROLLER
W78E58 8-bit microcontroller that functionally compatible with W78C58, except that mask replaced flash EEPROM with size facilitate programming verification, flash EEPROM inside W78E58 allows program memory programmed read electronically. Once code confirmed, user protect code security. W78E58 microcontroller supplies wider frequency range than most 8-bit microcontrollers market. functionally compatible with industry-standard 80C52 microcontroller series, except that extra 4-bit bit-addressable port(Port additional external interrupts INT2 INT3 W78E58 contains four 8-bit bi-directional bit-addressable ports, three 16-bit timer/counters, serial port. These peripherals supported eight-source, two-level interrupt capability. There bytes flash EEPROM application programs. W78E58 microcontroller power reduction modes, idle mode power-down mode, both which software selectable. idle mode turns processor clock allows continued peripheral operation. power-down mode stops crystal oscillator minimum power consumption. external clock stopped time state without affecting processor.
8-bit CMOS microcontroller Fully static design standby current full supply voltage DC-40 operation bytes on-chip scratchpad electrically erasable/programmable EPROM program memory address space data memory address space Four 8-bit bidirectional ports extra 4-bit bit-addressable port, additional INT2 INT3 (available 44-pin PLCC/QFP package) Three 16-bit timer/counters full duplex serial port Boolean processor Eight-source, two-level interrupt capability Built-in power management Code protection mechanism Packages: W78E58-16/24/40 PLCC W78E58P-16/24/40 W78E58F-16/24/40 TQFP W78E58M-16/24/40 Publication Release Date: November 1997 Revision
W78E58
CONFIGURATIONS
40-Pin (W78E58)
P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 P3.4 P3.5 P3.6 P3.7 XTAL2 XTAL1 P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, P0.7, PSEN P2.7, P2.6, P2.5, P2.4, P2.3, P2.2, P2.1, P2.0,
44-Pin PLCC (W78E58P)
44-Pin QFP/TQFP (W78E58F/W78E58M)
P1.5 P1.6 P1.7 RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 P3.4 P3.5
P0.4, P0.5, P0.6, P0.7, P4.1 PSEN P2.7, P2.6, P2.5,
P1.5 P1.6 P1.7 RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 P3.4 P3.5
P0.4, P0.5, P0.6, P0.7, P4.1 PSEN P2.7, P2.6, P2.5,
W78E58
DESCRIPTION
W78E58 operating modes, normal flash. normal mode, W78E58 corresponds W78C58. flash mode, user (the maker flash EEPROM writer) access flash EEPROM.
P0.7-P0.0 Port Bits
MODE Normal Flash DESCRIPTION Port Bits through Port bidirectional port. This port also provides multiplexed order address/data during accesses external memory. This port provides data during access flash EEPROM.
P1.7-P1.0 Port Bits
MODE Normal DESCRIPTION Port Bits through Port bidirectional port with internal pull-ups. Pins P1.0 P1.1 also serve (Timer external input) T2EX (Timer capture/reload trigger), respectively. This port provides low-order address during access flash EEPROM.
Flash
P2.7-P2.0 Port Bits
MODE Normal Flash DESCRIPTION Port Bits through Port bidirectional port with internal pull-ups. This port also provides upper address bits accesses external memory. This port provides high-order address during access flash EEPROM.
P3.7-P3.0 Port Bits
MODE Normal Flash DESCRIPTION Port Bits through Port bidirectional port with internal pull-ups. bits have alternate functions. P3.3-P3.0 P3.7-P3.6 flash mode configuration pins, Input. P3.3-P3.0 P3.7-P3.6 configured select execute flash operations. details, Flash Operations.
P4.3-P4.0 Port Bits (available 44-pin PLCC/QFP package)
MODE Normal DESCRIPTION Another bit-addressable bidirectional port P4.3 P4.2 alternative function pins. used general pins external interrupt input sources INT2 INT3
Publication Release Date: November 1997 Revision
W78E58
Flash function this mode.
EA/VPP
MODE Normal DESCRIPTION
External Access, Input, active low.
This forces processor execute program from external ROM. When internal flash EEPROM accessed W78C58, this should kept high. Flash VPP, Program Power supply pin, Input. This accepts high voltage (12V) needed programming flash EEPROM.
MODE Normal RST, Reset, Input, active high. This resets processor. must kept high least machine cycles order recognized processor. Flash Flash mode configuration pin, Input, active high. used configure flash operations. details, Flash Operations. DESCRIPTION
MODE Normal DESCRIPTION ALE, Address Latch Enable, Output, active high. used enable address latch that separates address from data Port runs 1/6th oscillator frequency. single pulse skipped during external data memory accesses. goes high impedance state with weak pull-up during reset state. Flash mode configuration pin, Input, active low. used configure flash operations. details, Flash Operations.
Flash
PSEN
MODE Normal DESCRIPTION PSEN Program Store Enable, Output, active low. This enables external onto Port address/data during fetch MOVC operations. PSEN goes high impedance state with weak pull-up during reset state Flash Flash mode configuration pin, Input, active high. PSEN used configure flash operations. details, Flash Operations.
XTAL1
MODE DESCRIPTION
W78E58
Normal Flash Crystal This crystal oscillator input. This driven external clock. Connect VSS.
XTAL2
MODE Normal Flash function this mode. DESCRIPTION Crystal This crystal oscillator output. inversion XTAL1.
VSS,
Power Supplies. These chip ground positive supplies.
Publication Release Date: November 1997 Revision
W78E58
BLOCK DIAGRAM
P1.0 P1.7
Port
Port Latch
INT2 Interrupt INT3 Timer Timer Timer UART
Port Latch Port
P0.0 P0.7
DPTR Stack Pointer Temp Reg.
Incrementor
Addr. Reg.
P3.0 P3.7
Port
Port Latch Instruction Decoder Sequencer
Address
bytes Port
Clock Controller
Port Latch
P2.0 P2.7
P4.0 P4.3
Port
Port Latch
Oscillator
Reset Block
Power Control
XTAL1 XTAL2 PSEN
W78E58
FUNCTIONAL DESCRIPTION
W78E58 architecture consists core controller surrounded various registers, five general purpose ports, bytes RAM, three timer/counters, serial port. processor supports different opcodes references both program address space data storage space.
Timers
Timers each consist 8-bit data registers. These called Timer Timer Timer TCON TMOD registers provide control functions timers T2CON register provides control functions Timer RCAP2H RCAP2L used reload/capture registers Timer operations Timer Timer same W78C51. Timer special feature W78E58: 16-bit timer/counter that configured controlled T2CON register. Like Timers Timer operate either external event counter internal timer, depending setting C/T2 T2CON. Timer three operating modes: capture, autoreload, baud rate generator. clock speed capture auto-reload mode same that Timers
Clock
W78E58 designed used with either crystal oscillator external clock. Internally, clock divided before used. This makes W78E58 relatively insensitive duty cycle variations clock.
Crystal Oscillator
W78E58 incorporates built-in crystal oscillator. make oscillator work, crystal must connected across pins XTAL1 XTAL2. addition, load capacitor must connected from each ground, resistor must also connected from XTAL1 XTAL2 provide bias when crystal frequency above MHz.
External Clock
external clock should connected XTAL1. XTAL2 should left unconnected. XTAL1 input CMOS-type input, required crystal oscillator. result, external clock signal should have input level greater than volts.
Power Management
Idle Mode idle mode entered setting PCON register. idle mode, internal clock processor stopped. peripherals interrupt logic continue clocked. processor will exit idle mode when either interrupt reset occurs. Power-down Mode When PCON register set, processor enters power-down mode. this mode clocks stopped, including oscillator. only exit power-down mode reset.
Publication Release Date: November 1997 Revision
W78E58
Reset
external RESET signal sampled S5P2. take effect, must held high least machine cycles while oscillator running. internal trigger circuit reset line used deglitch reset line when W78E58 used with external network. reset logic also special glitch removal circuit that ignores glitches reset line. During reset, ports initialized FFH, stack pointer 07H, PCON (with exception 00H, other registers except SBUF 00H. SBUF reset.
Option Setting
Users write programs into W78E58 using Winbond proprietary writer. writer programs data into internal region reads data back verification. After confirming that program correct, user lock data that they longer read. Lock This used protect customer data W78E58. turned after programmer finishes programming verify sequence. Once this logic flash data accessed again. MOVC Execute This used restrict region accessible MOVC instruction. prevent program from being downloaded using this instruction program needs jump outside data. When this logic MOVC instruction external program memory space will able access code external memory, will able access code internal memory. MOVC instruction internal program memory space will always able access code both internal external memory. this logic there restrictions MOVC instruction.
Defined Peripheral
order more suitable I/O, extra 4-bit bit-addressable port external interrupt INT2 INT3 been added either PLCC package. description follows: INT2/INT3 additional external interrupts, INT2 INT3 whose functions similar those external interrupt standard 80C52. functions/status these interrupts determined/shown bits XICON (External Interrupt Control) register. XICON register bit-addressable standard register standard 80C52. address 0C0H. set/clear bits XICON register, "SETB (/CLR) bit" instruction. example, "SETB 0C2H" sets XICON. ***XICON external interrupt control (C0H)
PX3: External interrupt priority high
W78E58
EX3: External interrupt enable IE3: set/cleared automatically hardware when interrupt detected/serviced IT3: External interrupt falling-edge/low-level triggered when this set/cleared software PX2: External interrupt priority high EX2: External interrupt enable IE2: set/cleared automatically hardware when interrupt detected/serviced IT2: External interrupt falling-edge/low-level triggered when this set/cleared software Eight-source interrupt informations: INTERRUPT SOURCE External Interrupt Timer/Counter External Interrupt Timer/Counter Serial Port Timer/Counter External Interrupt External Interrupt PORT4 Another bit-addressable port also available only bits (P4<3:0>) used. This port address located 0D8H with same function that port except P4.3 P4.2 alternative function pins. used general pins external interrupt input sources INT2 INT3 Example: SETB P4.0 P4.1 0D8H Output data through P4.0-P4.3. Read status Accumulator. P4.0 Clear P4.1 #0AH VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL (highest) (lowest) ENABLE REQUIRED SETTINGS IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6 INTERRUPT TYPE EDGE/LEVEL TCON.0 TCON.2 XICON.0 XICON.3
Reduce Emission
Because large on-chip flash EEPROM, when program running internal space, will unused. transition will cause noise, turned reduce Publication Release Date: November 1997 Revision
W78E58
emission useless. Turning signal transition only requires setting AUXR SFR, which located 08Eh. When turned off, will reactivated when program accesses external ROM/RAM data jumps execute external code. signal will turn again after been completely accessed program returns internal code space. AUXR register, when set, disables output. ***AUXR Auxiliary register (8EH)
Turn output.
Power-off Flag
***PCON Power control (87H) SMOD SMOD:
Double baud rate bit. When baud rate doubled when serial port being used either modes POF: Power flag. hardware when power reset. cleared software determine chip reset warm boot cold boot. GF1, GF0: These bits general-purpose flag bits user. Power down mode bit. enter power down mode. IDL: Idle mode bit. enter idle mode. power-off flag located PCON.4. This when been applied part. used determine reset warm boot cold boot subsequently reset software.
Flash Operations
normal operation, W78E58 functionally compatible with W78C58. flash operating mode, flash EEPROM programmed verified repeatedly. Once code inside flash EEPROM confirmed, code protected. flash EEPROM operations described below. operations configured pins RST, ALE, PSEN, A9CTRL (P3.0), A13CTRL (P3.1), A14CTRL (P3.2), OECTRL (P3.3), (P3.6), (P3.7), (P1.0) these operations, (P2.7 P2.0, P1.7 P1.0) (P0.7 P0.0) serve address data bus, respectively. Read Operation This operation enables customers read their codes option bits. data will valid lock programmed low.
W78E58
Program Operation This operation used program data flash EEPROM option bits. Programming initiated when reaches (12.5V) level, low, high. Program Verify Operation data must checked after programming. This operation should performed after each byte programmed, will ensure substantial program margin.
OPERATION P3.0 CTRL) Read Program Program Verify Notes: During these operations, VIH, VIL, PSEN VIH. 12V, VDD, Vss. program verify operation should follow programming operaion. P3.1 (A13 CTRL) P3.2 (A14 CTRL) P3.3 CTRL) P3.6 P3.7 (VPP) (A15 Address Address Address Data Data Data NOTES
ABSOLUTE MAXIMUM RATINGS
PARAMETER Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VDD-VSS MIN. -0.3 -0.3 MAX. +7.0 +0.3 +150 UNIT
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2 PSEN EA/Vpp DATA P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2
EA/Vpp PSEN DATA
Programming Configuration
Programming Verification
Publication Release Date: November 1997 Revision
W78E58
CHARACTERISTICS
(VDD-VSS ±10%, 25°C, Fosc MHz, unless otherwise specified.)
PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current Input Current Input Leakage Current Logic Transition Current Input Voltage Input Voltage Input Voltage XTAL1[*4] Input High Voltage Input High Voltage Input High Voltage XTAL1 [*4] Output Voltage
SYM. IIDLE IPWDN IIN1 IIN2
SPECIFICATION MIN. MAX. +300
UNIT
TEST CONDITIONS
load 5.5V Idle mode 5.5V Power-down mode 5.5V 5.5V 5.5V 5.5V <VIN
[*4]
-500
-200
5.5V =2.0V
VIL1
4.5V
VIL2 VIL3 VIH1
+0.2
4.5V 4.5V 5.5V
VIH2 VIH3 VOL1
+0.2 +0.2 0.45
5.5V 5.5V 4.5V
W78E58
Characteristics, continued
PARAMETER Output Voltage ALE, PSEN [*3] Sink Current Sink Current ALE, PSEN Output High Voltage Output High Voltage ALE, PSEN [*3] Source Current Source Current ALE, PSEN
Notes:
SYM. VOL2
SPECIFICATION MIN. MAX. 0.45
UNIT
TEST CONDITIONS 4.5V +4mA
ISK1 ISK2
4.5V 0.45V 4.5V 0.45V
VOH1 VOH2
4.5V -100 4.5V -400
ISR1 ISR2
-120
-250
4.5V 2.4V 4.5V 2.4V
Schmitt trigger input. internal pull-low resistors about /PSEN tested external access mode. XTAL1 CMOS input. Pins source transition current when they being externally driven from transition current reaches maximum value when approximates
CHARACTERISTICS
specifications function particular process used manufacture part, ratings buffers, capacitive load, internal routing capacitance. Most specifications expressed terms multiple input clock periods (TCP), actual parts will usually experience less than variation. numbers below represent performance expected from micron CMOS process when using output buffers.
Clock Input Waveform
Publication Release Date: November 1997 Revision
W78E58
XTAL1
PARAMETER Operating Speed Clock Period Clock High Clock
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Notes: clock stopped indefinitely either state. specification used reference other specifications. There duty cycle requirements XTAL1 input.
Program Fetch Cycle
PARAMETER Address Valid Address Hold from PSEN PSEN Data Valid Data Hold after PSEN High Data Float after PSEN High Pulse Width PSEN Pulse Width
Notes: P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. Memory access time TCP. Data have been latched internally prior PSEN going high. (due buffer driving delay wire loading)
SYMBOL TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW
MIN.
TYP.
MAX.
UNIT
NOTES
Data Read Cycle
PARAMETER Data Valid SYMBOL TDAR TDDA MIN. TYP. MAX. UNIT NOTE
W78E58
TDDH TDDZ TDRD
Data Hold from High Data Float from High Pulse Width
Notes: Data memory access time TCP. (due buffer driving delay wire loading)
Data Write Cycle
PARAMETER Data Valid Data Hold from High Pulse Width SYMBOL TDAW TDAD TDWD TDWR MIN. TYP. MAX. UNIT
Note: (due buffer driving delay wire loading)
Port Access Cycle
PARAMETER Port Input Setup Port Input Hold from Port Output SYMBOL TPDS TPDH TPDA MIN. TYP. MAX. UNIT
Note: Ports read during S5P2, output data becomes available S6P2. timing data referenced ALE, since provides convenient reference.
Program Operation
PARAMETER Setup Time Data Setup Time Data Hold Time Address Setup Time Address Hold Time
Program Pulse Width Program Operation Program Pulse Width Program Operation
SYMBOL TVPS TPWP TOPWP TOCS TOCH
MIN.
TYP.
MAX.
UNIT
OECTRL Setup Time OECTRL Hold Time
Publication Release Date: November 1997 Revision
W78E58
TOES TDFP TOEV
Setup Time High Output Float
Data Valid from
PSEN must pull status.
Note: Flash data accessed only flash mode. must pull status, must pull status,
W78E58
TIMING WAVEFORMS
Program Fetch Cycle
XTAL1
TALW TAPL PSEN TPSW TAAS PORT TAAH PORT Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 TPDA TPDH, TPDZ
Data Read Cycle
XTAL1 PSEN PORT
A8-A15 A0-A7 DATA
PORT DDH,
Publication Release Date: November 1997 Revision
W78E58
Timing Waveforms, continued
Data Write Cycle
XTAL1 PSEN PORT PORT
A8-A15 A0-A7 DATA
TDAD
Port Access Cycle
XTAL1
TPDS PORT INPUT SAMPLE DATA
W78E58
Timing Waveforms, continued
Program Operation
Program (A15. P3.6 (CE) P3.3 (OECTRL) P3.7 (OE) (A7. TVPS Data
Program Verify
Read Verify
Address Stable TPWP TOCH TOES DOUT TDFP
Address Valid
Data
TOEV
Publication Release Date: November 1997 Revision
W78E58
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory Crystal
CRYSTAL
XTAL1
XTAL2 INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78E58
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN
AD413 AD514 AD617 AD718
74LS373
27512
Figure
CRYSTAL
6.8K 4.7K
Above table shows reference values crystal applications.
Note: components refer Figure
W78E58
Typical Application Circuits, continued
Expanded External Data Memory Oscillator
OSCILLATOR
XTAL1 XTAL2 INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78E58
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN
74LS373
20256
Figure
PACKAGE DIMENSIONS
40-pin
Symbol
Dimension inches
Dimension
Min.
Nom.
Max.
0.210
Min.
0.254
Nom.
Max.
5.334
0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 0.670 0.090
3.81 0.406 1.219 0.203
3.937 0.457 1.27 0.254 52.20
4.064 0.559 1.372 0.356 52.58 15.494 13.97 2.794 3.556
14.986 13.72 2.286 3.048 16.00
15.24 13.84 2.54 3.302
Notes:
16.51
17.01 2.286
Base Plane Seating Plane
Dimension Max. include mold flash burrs. Dimension does include interlead flash. Dimension include mold mismatch determined mold parting line. Dimension does include dambar protrusion/intrusion. Controlling dimension: Inches. General appearance spec. should based final visual inspection spec.
Publication Release Date: November 1997 Revision
W78E58
Package Dimensions, continued
44-pin PLCC
Symbol
Dimension inches
Dimension
Min.
0.020 0.145 0.026 0.016 0.008 0.648 0.648
Nom.
Max.
0.185
Min.
0.508
Nom.
Max.
4.699
Notes:
0.150 0.028 0.018 0.010 0.653 0.653
0.155 0.032 0.022 0.014 0.658 0.658 0.630 0.630 0.700 0.700 0.110 0.004
3.683 0.66 0.406 0.203 16.46 16.46
3.81 0.711 0.457 0.254 16.59 16.59
3.937 0.813 0.559 0.356 16.71 16.71
0.050 0.590 0.590 0.680 0.680 0.090 0.610 0.610 0.690 0.690 0.100
1.27 14.99 14.99 17.27 17.27 2.296
16.00 16.00 17.78 17.78 2.794 0.10
15.49 15.49 17.53 17.53 2.54
Seating Plane
Dimension include interlead flash. Dimension does include dambar protrusion/intrusion. Controlling dimension: Inches General appearance spec. should based final visual inspection spec.
44-pin
Dimension inch
Dimension
Symbol
Min. Nom. Max.
-0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 -0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 -0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003
Min. Nom.
-0.05 1.90 0.25 0.101 0.635 12.95 12.95 0.65 1.295 -0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2
Max.
-0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
Notes:
Detail
Seating Plane
Detail
Dimension include interlead flash. Dimension does include dambar protrusion/intrusion. Controlling dimension: Millimeter General appearance spec. should based final visual inspection spec.
W78E58
Timing Waveforms, continued
44-pin TQFP
Dimension inch
Dimension
Symbol
Min.
-0.002 0.037 0.0039 0.004 0.390 0.390 0.025 0.468 0.468 0.018
Nom.
-0.004 0.039 0.013 -0.394 0.394 0.031 0.472 0.472 0.024 0.039
Max.
0.047 0.006 0.041 0.015 0.008 0.398 0.398 0.036 0.476 0.476 0.030 -0.003
Min.
-0.05 0.95 0.22 0.090 0.635 11.90 11.90 0.45
Nom.
-0.10 1.00 0.32 -10.00 10.00 0.80 12.00 12.00 0.60 1.00
Max.
1.20 0.15 1.05 0.38 0.200 10.1 10.1 0.952 12.10 12.10 0.75 -0.08
Notes:
Seating Plane
Detail
Dimension include interlead flash. Dimension does include dambar protrusion/intrusion. Controlling dimension: Millimeter General appearance spec. should based final visual inspection spec.
Detail
Headquarters
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
803, World Trade Square, Tower Winbond Memory Lab. Creation III, Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 First Street, Jose, FAX: 852-27552064 FAX: 886-3-5792697 95134, U.S.A. http://www.winbond.com.tw/ TEL: 408-9436666 Voice Fax-on-demand: 886-2-27197006 FAX: 408-5441798
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: data specifications subject change without notice.
Publication Release Date: November 1997 Revision

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