VR4181A

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INTEGRATED CIRCUIT
µPD30181A, 30181AY
VR4181A 64-/32-BIT MICROPROCESSOR
DESCRIPTION
µPD30181A 30181AY (VR4181A), which high-performance 64-/32-bit microprocessors employing RISC (reduced instruction computer) architecture developed MIPS products Series microprocessors manufactured NEC. VR4181A includes VR4120core, ultra-low-power-consumption core featuring cache memory, high-speed product-sum operation unit, memory management unit. Other on-chip components include controller, CompactFlash controller, host/function controller, controller, SDRAM controller, controller, AC97/I audio interface, full-duplex asynchronous serial interface, IrDA interface, serial interface, keyboard interface, touch panel interface, real-time clock, converter, converter, other controllers interfaces required battery-driven mobile information devices, fixed compact information devices, navigation systems, compact embedded devices. Detailed function descriptions provided following user's manuals. sure read them before designing. VR4181A Hardware User's Manual (U16049E) VR4100 Series Architecture User's Manual (U15509E)
FEATURES
VR4120 core (64-bit RISC core) chip Pipeline clock: Conforms MIPS (except FPU, instructions) MIPS16 instruction sets Supports MACC DMACC high-speed product-sum operation instructions On-chip cache memory Capacity includes instruction cache data cache Employs writeback cache Physical addresses: bits Virtual addresses: bits On-chip double-entry Effective power management using four modes: Fullspeed, Standby, Suspend, Hibernate Employs high-performance internal system (Tbus) DRAM controller supporting SDRAMs External system interface supporting ROM, page ROM, flash memory, SRAM, devices, (ATA) devices, SyncFlashmemory type controller (supports panels) ExCA register-compatible CompactFlash interface slots) host controller (Rev1.1, OHCI Rev1.0) controller function (Rev1.1) controller AC97 audio interfaces channel each) Clocked serial interface channel) NS16550-compatible serial interface channels) IrDA (SIR) interface channel) interfaces channels, µPD30181AY only) controller channels) controller supporting chain mode channels) Keyboard scan interface (supports matrix) coordinate auto scan touch panel interface On-chip converter converter On-chip watchdog timer unit unit (total timer counter channels) On-chip clock generators Power supplies: core, block Package: 240-pin plastic FBGA
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Document U16277EJ1V0DS00 (1st edition) Date Published October 2002 CP(K) Printed Japan
mark
shows major revised points.
2002
1997
µPD30181A, 30181AY
APPLICATIONS
navigation systems Digital consumer devices (digital information home equipment) Battery-driven mobile information devices Controllers embedded devices
ORDERING INFORMATION
Part Number Package 240-pin plastic FBGA
Note
Interface None None chip chip
Internal Maximum Operating Frequency
µPD30181AF1-131-GA3 µPD30181AF1-131-GA3-A µPD30181AYF1-131-GA3 µPD30181AYF1-131-GA3-A
Note Lead-free product
Note
240-pin plastic FBGA 240-pin plastic FBGA 240-pin plastic FBGA
CONFIGURATION
240-pin plastic FBGA
Bottom view
view
Index mark
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(1/3)
Power Supply CLK48 SDCS2# SDCS3# MEMWR# PCS4# PCS1# IORD# DQM1/LBE1# UHDN UPON DQM3/LBE3# PCS3# ROMCS# PCS2# SYSDIR IOWR# DQM0/LBE0# Name Power Supply UHDP NMI# DQM2/LBE2# PCS0# SYSEN# IORDY UBE# CAS# RAS# VDD2 GND2 VDD2 GNDU VDDU GND3 VDD3 GND2 MEMRD# PWM1/KSCAN6/GPIO9 IOCS16# PWM0/KSCAN7/GPIO8 SDCLK SDCS1# VDD3 VDD3 GND3 GND2 VDD2 Name
Remark indicates active low.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2/3)
Power Supply VDD3 KPORT0/GPIO4 PWM2/KSCAN5/GPIO10 KPORT1/GPIO5 SDCS0# CKE0 GND3 GNDP CF1_DIR/KPORT4/GPIO39 KPORT2/GPIO6 CLKX1 TC0#/GPIO52 TC1#/GPIO53 VDDP KPORT3/GPIO7 CF1_EN#/KPORT5/GPIO38 CLKX2 SA10 A23/RP# A24/CKE1 GND2 VDDO GNDO KSCAN0/GPIO0 KSCAN3/GPIO3 RTCX2 A21/GPIO60 A22/GPIO61 GND3 VDD2 GND3 KSCAN1/GPIO1 KSCAN2/GPIO2 RTCX1 Name Power Supply A19/GPIO58 A20/GPIO59 VDD3 VDD3 SO/KSCAN9/GPIO21 SCK/KSCAN11/GPIO23 FRM/KSCAN8/GPIO20 CF1_VCCEN#/KSCAN4/GPIO37 A17/GPIO56 A18/GPIO57 VDD2 GND2 JTMS JTDO SI/KSCAN10/GPIO22 JTCK A15/GPIO54 A16/GPIO55 JTRST# CF0_IOIS16#/GPIO34 JTDI/RMODE# BKTGIO# GND2 VDD2 CF0_CD2#/GPIO36 CF0_CD1#/GPIO35 CF_WAIT#/GPIO33 DAK1# DRQ1# GNDAD VDD2 GND2 Name
Remark indicates active low.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(3/3)
Power Supply 3.3V GND2 GND3 CF0_CE2#/GPIO32 CF0_DIR/GPIO27 CF0_READY/GPIO29 CF0_CE1#/GPIO31 DRQ0# POWER RSTSW# GNDTP VDDTP VDDAD VDD3 GND3 DCD2#/SDATAIN/SDI SDA0/KPORT6/GPIO11 VPBIAS/GPO63 VPLCD/GPO62 VDD3 VDD2 GND3 CF_REG#/GPIO25 CF0_RESET/GPIO28 CF0_STSCHG#/GPIO30 RTCRST# POWERON DAK0# TPX1 AIN2 DCD0#/GPIO16 DSR0#/CTS1#/GPIO15 RTS2#/SYNC/WS/DIVMODE1Note DTR2#/SDATAOUT/SDO/DIVMODE0 TxD1/SDA1/GPIO13 ENAB/M/BMODE0Note FPD14/CF1_STSCHG#/GPIO50 FPD13/CF1_CE2#/GPIO49 FPD8/GPIO44 FPD0
Note
Name
Power Supply FPD2 I.C. (GND3)Note CF0_EN#/GPIO26 MPOWER AIN0 TPX0 TPY0
Name
TxD0/CLKSEL2Note RTS0#/GPIO19/CLKSEL1Note RxD2/IRDIN CTS2#/BITCLK/SCLK I.C. (GND3)Note SCL0/KPORT7/GPIO12 VSYNC/FLM/BMODE1Note FPD15/CF1_READY/GPIO51 FPD12/CF1_CE1#/GPIO48 FPD10/CF1_CD1#/GPIO46 FPD6/GPIO42 FPD4/GPIO40 CF1_RESET/DBUS32Note CF0_VCCEN#/GPIO24 TPY1 AIN1 AIN3 AOUT RxD0 CTS0#/GPIO18 DTR0#/RTS1#/GPIO17/CLKSEL0Note TxD2/IRDOUT/MIPS16ENNote DSR2#/SRESET# RxD1/SCL1/GPIO14 DCLK/SHCLK HSYNC/LOCLK/NWIREENNote FPD11/CF1_CD2#/GPIO47 FPD9/GPIO45 FPD7/GPIO43 FPD5/GPIO41 FPD3 FPD1
Notes These pins used mode settings. mode setting made according status these pins rising edge RTCRST# signal. pull-up/pull-down resistors statuses. sure connect these pins GND3. Remark indicates active low.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
INDENTIFICATION (1/2) A(24:0): AIN(3:0): AOUT: BITCLK: BKTGIO#: BMODE(1:0): CAS#: CF_REG#: CF_WAIT#: CF0_CD(2:1)#: CF0_CE(2:1)#: CF0_DIR: CF0_EN#: CF0_IOIS16#: CF0_READY: CF0_RESET: CF0_STSCHG#: CF0_VCCEN#: CF1_CD(2:1)#: CF1_CE(2:1)#: CF1_DIR: CF1_EN#: CF1_READY: CF1_RESET: CF1_STSCHG#: CF1_VCCEN#: CKE0: CKE1: CLK48: CLKSEL(2:0): CLKX(2:1): D(31:0): DAK(1:0)#: DBUS32: DCD0#, DCD2#: DCLK: DIVMODE(1:0): DQM(3:0): Address Analog data Input Analog data output AC97 clock N-wire break trigger Boot mode SDRAM column address strobe CompactFlash register memory access CompactFlash wait input CompactFlash card detect CompactFlash card enable CompactFlash data direction CompactFlash buffer enable CompactFlash bits CompactFlash ready CompactFlash reset CompactFlash status change CompactFlash enable CompactFlash card detect CompactFlash card enable CompactFlash data direction CompactFlash buffer enable CompactFlash ready CompactFlash reset CompactFlash status change CompactFlash enable SDRAM Clock enable SyncFlash memory clock enable clock input Pipeline clock select Clock input Data acknowledge data mode 16550 data carrier detect clock Divide-by mode SDRAM byte enable DRQ(1:0)#: request
DSR0#, DSR2#: 16550 data ready DTR0#, DTR2#: 16550 data terminal ready ENAB: FLM: FPD(15:0): FRM: GND2: GND3: GNDAD: GNDO: GNDP: GNDTP: GNDU: GPIO(61:0): GPO(63:62): HSYNC: I.C.: IOCS16#: IORD#: IORDY: IOWR#: IRDIN: IRDOUT: JTCK: JTDI: JTDO: JTMS: JTRST#: KPORT(7:0): KSCAN(11:0): LOCLK: LBE(3:0)#: MEMRD#: MEMWR#: MIPS16EN: MPOWER: NMI#: display enable first line clock display data frame input Internal ground ground converter ground Oscillator ground ground Touch panel ground transceiver ground General-purpose General-purpose output horizontal sync Internally connected 16-bit sizing read ready write IrDA data input IrDA data output N-wire clock N-wire data input N-wire data output N-wire mode select N-wire reset Scan input Scan output load clock System byte enable modulation clock Memory read Memory write MIPS16 enable Main power control maskable interrupt
CTS0#, CTS1#, CTS2#: 16550 clear send
Remark indicates active low.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
INDENTIFICATION (2/2) NWIREEN: PCS(4:0)#: POWER: POWERON: PWM(2:0): RAS#: RMODE#: ROMCS#: RP#: RSTSW#: RTCRST#: RTCX(2:1): RxD0, RxD1, RxD2: SA10: SCLK: SCL1, SCL0: SCK: SDA1, SDA0: SDATAIN: SDATAOUT: SDCLK: SDCS(3:2)#: SDCS(1:0)#: SDI: SDO: SHCLK: N-Wire enable Programmable chip select Power switch Power state Pulse width modulation SDRAM address strobe N-wire reset mode select Chip select SyncFlash memory reset/power-down Reset switch Real-time clock reset Real-time clock input 16550 receive data SDRAM address 10-bit continuous clock clock serial clock data AC97 serial codec data input AC97 serial codec data output SDRAM clock SyncFlash memory chip select SDRAM chip select serial codec data input serial codec data output shift clock data input Remark indicates active low.
SRESET#: SYNC: SYSDIR: SYSEN#: TC(1:0)#: TPX(1:0): TPY(1:0): UBE#: UDN: UDP: UHDN: UHDP: UOC: UPON: VDD2: VDD3: VDDAD: VDDO: VDDP: VDDTP: VDDU: VPBIAS: VPLCD: VSYNC: WE#:
data output AC97 reset AC97 synchronous clock System data direction System data enable Terminal counter Touch panel coordinate data Touch panel coordinate data Upper byte enable system function negative data function positive data host negative data host positive data host root port over current host root port power control Internal power supply power supply converter power supply Oscillator power supply power supply Touch panel power supply transceiver power supply Bias power control Logic power control vertical sync SDRAM write enable word select
TxD0, TxD1, TxD2: 16550 transmit data
RTS0#, RTS1#, RTS2#: 16550 data request send
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
INTERNAL BLOCK DIAGRAM EXAMPLE CONNECTION EXTERNAL BLOCKS
CompactFlash/ Communication Card STN/TFT Panel Color/Monochrome SDRAM/ SyncFlash ROM/Flash memory Devices HDD, CD-ROM Mouse Printer
32/16-bit
BluetoothBaseband Func. Control Host Control AC97 Control Sound Stereo CODEC RTC/ Timer Power Management Control
Control
SDRAM Control
Control
Card/IDE Control slots
In-circuit emulator N-Wire
Debug
VR4120 Core
Bridge
Interrupt Watchdog Control Timer
Bridge
Audio Input
32.768 18.432
Clock Generator
Scan
Control
GPIO MAX.
Serial (UART)
Serial (I2C)
Serial (CSI)
Touch Panel Control
Analog Control Touch Panel
VR4181A
Port Control Backlight Contrast
IrDA/ RS-232-C Driver, Bluetooth Baseband, etc.
Module, Serial EEPROMetc.
MCU, CODEC Control, etc.
Battery Monitor
CORE INTERNAL BLOCK DIAGRAM
Virtual address Internal data
Control Control Address/Data Address/Data
interface
Data cache
Instruction cache
Clock generator Internal clock
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
CONTENTS
FUNCTIONS
Functions Status Specific Status Circuit Types Recommended Connection Unused Pins. Circuits
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
FUNCTIONS
Remark indicates active low.
Functions
System interface signals (1/3)
Signal Name A(22:15) SA10 Function Address These pins used specify system addresses. They used access ROM, flash memory, SRAM, devices, Cards, (ATA) devices, general-purpose devices. Address SDRAM SyncFlash memory Instead connecting A10, connect this (SA10) address SDRAM SyncFlash memory. Address These pins used specify system addresses. They used access SDRAM, SyncFlash memory, ROM, flash memory, SRAM, devices, CompactFlash/PC Cards, (ATA) devices, general-purpose devices. Data These pins used transfer data VR4181A SDRAM, SyncFlash memory, ROM, flash memory, SRAM, devices, CompactFlash/PC Cards, (ATA) devices, general-purpose devices. Programmable chip select These pins active when VR4181A accesses ROM, flash memory, SRAM, general-purpose devices. They connected only devices that subject sizing IOCS16# pin. Boot chip select This active when VR4181A accesses boot flash memory. When BMODE(1:0) status RTCRST# signal been cleared, VR4181A fetches boot code from device connected ROMCS# activate this pin. System memory read This becomes active when VR4181A reads data from following devices. ROM, flash memory, SRAM, general-purpose devices controlled ROMCS# PCS# External memory space devices CompactFlash/PC Card memory space devices Alternate Function CKE1 GPIO(61:54)
A(14:0)
D(31:0)
PCS(4:0)#
ROMCS#
MEMRD#
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2/3)
Signal Name MEMWR# Function System memory write This becomes active when VR4181A writes following devices. ROM, flash memory, SRAM, general-purpose devices controlled ROMCS# PCS# External memory space devices CompactFlash/PC Card memory space devices System read This becomes active when VR4181A reads data from external space devices CompactFlash/PC Card ports. valid only when accessing external space. System write This becomes active when VR4181A writes data external space devices CompactFlash/PC Card ports. valid only when accessing external space. System channel ready This (IORDY) inactive relation read/write strobes from VR4181A order extend access time device connected system bus. active once device mode that supports access from VR4181A. used access device connected ROMCS# PCS# device connected external space. System sizing request this signal active when device connected system accesses data 16-bit width. sizing that uses this IOCS16# enabled only when accessing external space. System higher byte enable This becomes active during system access higher bytes 16-bit data valid. used device connected ROMCS# PCS# device connected external space uses 16-bit width. System byte enable LBE(3:0)# signal pins used 32-bit general-purpose devices shared DQM(3:0) signal pins SDRAM SyncFlash memory, function this changes based time division. When VR4181A accesses device that uses ROMCS# PCS# pin, LBE(3:0)# signals become valid only when SYSEN# signal level. This signal indicates data bus's valid byte lane. device connected ROMCS# PCS# 32-bit width, this used. When SYSEN# high level, this operates DQM(3:0) pins that referenced SDRAM. Alternate Function
IORD#
IOWR#
IORDY
IOCS16#
UBE#
LBE(3:0)#
DQM(3:0)
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(3/3)
Signal Name SYSDIRNote Function Data isolation buffer direction control This signal valid only when accessing devices other than SDRAM SyncFlash memory devices. signal high level during read cycles level during write cycles. Enables data isolation buffer connection This signal high level during SDRAM SyncFlash memory cycles level when accessing other devices. service request signal DRQ(1:0)# signals sampled rising edge TClock. sure hold this signal active level until request acknowledged. this signal inactive when using DRQ(1:0)# signals. Enables service request This signal goes active level when access target device occurs transfer. transfer completion signal (open drain) This signal driven active level when transfer completed. During transfer, this signal operates stop request input signal. Non-maskable interrupt input This interrupt request signal that cannot masked relation core. When VR4181A starts normally MPOWER signal high level, input from NMI# connected core ICU. While MPOWER signal level, input NMI# monitored source shutdowns. Alternate Function
SYSEN#Note
DRQ(1:0)#
DAK(1:0)#
TC(1:0)#
GPIO(53:52)
NMI#
Note SYSEN# SYSDIR signals buffer control signals used isolate SDRAM SyncFlash memory buses from other low-speed device buses. Isolating high-speed memory access paths from other devices reduces load system between VR4181A SDRAM SyncFlash memory. When using system isolation buffer, correspondence between SYSEN# SYSDIR signals data isolation status shown below.
SYSEN# SYSDIR Operation Enables connection data isolation buffer Write cycle ROM, flash memory, SRAM, device, CompactFlash/PC Card, other general-purpose device Hibernate mode Enables connection data isolation buffer Read cycle ROM, flash memory, SRAM, device, CompactFlash/PC Card, general-purpose device Disables connection data isolation buffer Read/write cycle SDRAM SyncFlash memory
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Memory interface signals
Signal Name SDCLK Function Operating clock SDRAM SyncFlash memory This signal also (via register settings) stop clock output when accessing SDRAM SyncFlash memory. Operating clock enable signal SyncFlash memory Operating clock enable signal SDRAM Chip select signal SyncFlash memory Chip select signal SDRAM address strobe signal SDRAM SyncFlash memory Column address strobe signal SDRAM SyncFlash memory Byte enable signal SDRAM SyncFlash memory DQM(3:0) signals SDRAM SyncFlash memory shares pins with LBE(3:0)# signals 32-bit general-purpose devices, function these pins change based time division. When SYSEN# signal high level, operates DQM(3:0) signals which referenced SDRAM. Write enable signal SDRAM SyncFlash memory SyncFlash memory initialization/power down signal LBE(3:0)# Alternate Function
CKE1 CKE0 SDCS(3:2)# SDCS(1:0)# RAS# CAS# DQM(3:0)
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Initialization interface signals
Signal Name POWER Function VR4181A activation request (power switch) signal When rising edge this signal detected Hibernate mode, activation factor occurs (the VR4181A restores Fullspeed mode). VR4181A reset signal This signal initializes internal statuses resettable devices except timer, PMU, GIU, PWMU channels VR4181A reset signal This signal initializes internal statuses resettable devices, including timer. When supplying power device first time, sure this signal active external circuits. VR4181A activation indication When activation factor been detected, this signal becomes active (high level) specified amount time. VR4181A operation progress indication When circuits operating, this signal becomes active (high level). Hibernate mode, inactive (low level). When this signal inactive, power supply stopped. Alternate Function
RSTSW#
RTCRST#
POWERON
MPOWER
Remarks Activation factors used restore from Hibernate mode Fullspeed mode. further description operation initialization interface signals, Hardware User's Manual. Clock interface signals
Signal Name RTCX(2:1) CLKX(2:1) Function 32.768 crystal resonator connection 18.432 crystal resonator connection Alternate Function
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
interface signals
Signal Name DCLK/SHCLK HSYNC/LOCLK VSYNC/FLM ENAB/M FPD15 Function clock (DCLK) TFT/shift clock (SHCLK) Horizontal sync signal TFT/load clock Vertical sync signal TFT/first line clock Display enable signal TFT/M clock display data Alternate Function NWIREEN BMODE1 BMODE0 CF1_READY, GPIO51 CF1_STSCHG#, GPIO50 CF1_CE(2:1)#, GPIO(49:48) CF1_CD(2:1)#, GPIO(47:46) GPIO(45:40) GPO63
FPD14
display data
FPD(13:12)
display data
FPD(11:10)
display data
FPD(9:4) FPD(3:0) VPBIAS
display data display data bias power control This signal used general-purpose output when using controller. logic power control This signal used general-purpose output when using controller.
VPLCD
GPO62
Caution connection between FPD(15:0) VR4181A panel data line corresponds panel data width, shown below.
VR4181A Panel Data Bits) Data line Data line Data line Data line Panel Data Bits) Data line Data line Data line Data line Data line Data line Data line Data line Panel Data Bits) Data line (B0) Data line (B1) Data line (B2) Data line (B3) Data line (G0) Data line (G1) Data line (G2) Data line (G3) Data line (R0) Data line (R1) Data line (R2) Data line (R3) Panel Data Bits) Data line (B0) Data line (B1) Data line (B2) Data line (B3) Data line (B4) Data line (G0) Data line (G1) Data line (G2) Data line (G3) Data line (G4) Data line (G5) Data line (R0) Data line (R1) Data line (R2) Data line (R3) Data line (R4)
FPD0 FPD1 FPD2 FPD3 FPD4 FPD5 FPD6 FPD7 FPD8 FPD9 FPD10 FPD11 FPD12 FPD13 FPD14 FPD15
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
CompactFlash/PC Card/IDE (ATA) interface signal
Signal Name CF1_CD(2:1)# Function CompactFlash/PC Card (slot detection signal Alternate Function FPD(11:10), GPIO(47:46) FPD(13:12), GPIO(49:48) FPD14, GPIO50 FPD15, GPIO51 DBUS32 KPORT4, GPIO39 KPORT5, GPIO38 KSCAN4, GPIO37 GPIO(36:35) GPIO34 GPIO33 GPIO(32:31) GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
CF1_CE(2:1)#
CompactFlash/PC Card (slot enable signal
CF1_STSCHG# CF1_READY CF1_RESET CF1_DIR
CompactFlash/PC Card (slot status change signal CompactFlash/PC Card (slot ready signal CompactFlash/PC Card (slot reset signal CompactFlash/PC Card (slot data direction control signal
CF1_EN#
CompactFlash/PC Card (slot buffer enable signal
CF1_VCCEN#
CompactFlash/PC Card (slot enable signal
CF0_CD(2:1)# CF0_IOIS16# CF_WAIT# CF0_CE(2:1)# CF0_STSCHG# CF0_READY CF0_RESET CF0_DIR CF0_EN# CF_REG# CF0_VCCEN#
CompactFlash/PC Card (slot detection signal CompactFlash/PC Card (slot 16-bit signal CompactFlash/PC Card (slots wait signal CompactFlash/PC Card (slot enable signal CompactFlash/PC Card (slot status change signal CompactFlash/PC Card (slot ready signal CompactFlash/PC Card (slot reset signal CompactFlash/PC Card (slot data direction control signal CompactFlash/PC Card (slot buffer enable signal CompactFlash/PC Card (slots register select signal CompactFlash/PC Card (slot enable signal
Cautions sure MEMRD#, MEMWR#, IORD#, IOWR# respectively CompactFlash/PC Card access strobe signals OE#, WE#, IORD#, IOWR#. CF0_EN#, CF1_EN#, CF0_DIR, CF1_DIR signals used control buffer that isolates CompactFlash/PC Card's from other device's buses. This isolation CompactFlash/PC Card's enables plug-in support. following table lists correspondence between CF0_EN#, CF1_EN#, CF0_DIR, CF1_DIR signals data isolation statuses when using data isolation buffer.
CF0_EN#, CF1_EN# CF0_DIR, CF1_DIR Operation
Enable connection data isolation buffer Write cycle CompactFlash/PC Card Enable connection data isolation buffer Read cycle CompactFlash/PC Card Disable connection data isolation buffer
(Undefined)
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(host/function) interface signals
Signal Name CLK48 UHDP clock MHz) host serial data signal sure connect resistor series impedance matching. host serial data signal sure connect resistor series impedance matching. host route power control signal host route overcurrent input signal function serial data signal sure connect resistor series impedance matching. function serial data signal sure connect resistor series impedance matching. Function Alternate Function
UHDN
UPON
AC97/I stereo audio interface signals
Signal Name BITCLK/SCLK Function clock input (12.288 MHz) AC97/input output clock (maximum frequency during input: 6.144 MHz). When used SCLK signal, this signal output VR4181A when I2SU master mode input from external source slave mode. Synchronous clock output AC97/input output word select signal When used signal, this signal output VR4181A when I2SU master mode input from external source slave mode. Serial data output signal AC97/serial data output signal Serial data input signal AC97/serial data input signal Reset signal AC97
Alternate Function CTS2#
SYNC/WS
RTS2#, DIVMODE1
SDATAOUT/SDO
DTR2#, DIVMODE0 DCD2# DSR2#
SDATAIN/SDI SRESET#
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Clocked serial interface signals
Signal Name Function Serial clock (maximum frequency input output: MHz) This signal output VR4181A master mode input from external source slave mode. Serial data input signal Alternate Function KSCAN11, GPIO23
KSCAN10, GPIO22 KSCAN9 GPIO21
Serial data output signal This signal high impedance when value FRMEN FRMMD CSIMODE register, signal high level. Serial frame signal This signal determines data direction (transmit/receive), used enable (low level) disable (high level) transfers.
KSCAN8, GPIO20
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(10) 16550 (UART) serial interface signals
Signal Name RxD0 TxD0 RTS0# Serial (channel receive data Serial (channel transmit data Serial (channel transmit request signal Function Alternate Function CLKSEL2 GPIO19, CLKSEL1 GPIO18 GPIO17, CLKSEL0 GPIO16 GPIO15
CTS0# DTR0#/RTS1#
Serial (channel transmit enable signal Serial (channel terminal ready signal/serial (channel transmit request signal Serial (channel carrier detection signal Serial (channel data ready signal/serial (channel transmit enable signal Serial (channel receive data Serial (channel transmit data Serial (channel receive data Serial (channel transmit data
DCD0# DSR0#/CTS1#
RxD1 TxD1 RxD2 TxD2
SCL1, GPIO14 SDA1, GPIO13 IRDIN IRDOUT, MIPS16EN SYNC, DIVMODE1 BITCLK, SCLK SDATAOUT, SDO, DIVMODE0 SDATAIN, SRESET#
RTS2#
Serial (channel transmit request signal
CTS2# DTR2#
Serial (channel transmit enable signal Serial (channel terminal ready signal
DCD2# DSR2#
Serial (channel carrier detection signal Serial (channel data ready signal
(11) IrDA interface signals
Signal Name IRDIN IRDOUT IrDA receive data input IrDA transmit data output Function Alternate Function RxD2 TxD2, MIPS16EN
(12) serial interface signals (µPD30181AY only)
Signal Name SCL1 SDA1 SCL0
Function Serial clock (open drain) (channel Serial data (open drain) (channel Serial clock (open drain) (channel Serial data (open drain) (channel
Alternate Function RxD1, GPIO14 TxD1, GPIO13 KPORT7, GPIO12 KPORT6, GPIO11
SDA0
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(13) interface signals
Signal Name PWM2 output (channel Function Alternate Function KSCAN5, GPIO10 KSCAN6, GPIO9 KSCAN7, GPIO8
PWM1 PWM0
output (channel output (channel
(14) Keyboard interface signals
Signal Name KPORT7 KPORT6 KPORT5 scan input data scan input data scan input data Function Alternate Function SCL0, GPIO12 SDA0, GPIO11 CF1_EN#, GPIO38 CF1_DIR, GPIO39 GPIO(7:4) SCK, GPIO23 GPIO22 GPIO21 FRM, GPIO20 PWM0, GPIO8 PWM1, GPIO9 PWM2, GPIO10 CF1_VCCEN#, GPIO37 GPIO(3:0)
KPORT4
scan input data
KPORT(3:0) KSCAN11 KSCAN10 KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4
scan input data scan output data scan output data scan output data scan output data scan output data scan output data scan output data scan output data
KSCAN(3:0)
scan output data
(15) Touch panel/analog interface signals
Signal Name TPX(1:0) Function Touch panel coordinate data This signal used detect coordinate touch panel location that been pressed when supply voltage applied coordinates coordinates. Touch panel coordinate data This signal used detect coordinate touch panel location that been pressed when supply voltage applied coordinates coordinates. General-purpose data input General-purpose data output Alternate Function
TPY(1:0)
AIN(3:0) AOUT
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(16) Debug interface signals
Signal Name JTCK JTMS N-Wire clock N-Wire mode select signal This signal selects N-Wire serial transfer mode. N-Wire input data/N-Wire reset mode select signal This functions alternately RMODE# JTDI. When JTRST# active functions RMODE#, when JTRST# inactive functions JTDI. RMODE# input When JTRST# active, this reset mode pin. initial value debug reset determined level this signal. debug reset reset processor, there types: debug cold reset debug soft reset. This serves same function Cold Reset input Soft Reset input from various target systems. Sets debug reset valid resets core Sets debug reset invalid does reset core JTDI input When JTRST# signal inactive, this operates N-Wire serial data input. N-Wire serial data output N-Wire reset signal N-Wire break trigger BKTGIO#: When used input setting When JTRST# inactive BKTGIO# used input setting, this event trigger/break request input pin. When break requests valid, setting BKTGIO# level stops execution user programs normal mode forcibly shifts processor debug mode. After BKTGIO# goes level debug mode, break requests retained until processor restored normal mode. Requests break forcibly shifts processor debug mode Retains current status processor BKTGIO#: When used output setting When JTRST# inactive BKTGIO# used output setting, this event trigger/break output pin. When processor operating normal mode event detected that meets conditions hardware breakpoint (instruction address breakpoint data access breakpoint), event trigger output from BKTGIO# level signal (one pulse) detection event reported external debugging tool. Finally, after event trigger output, detected events reported event trigger. When processor shifted debug mode, output continues level previously non-reported events reported. Hardware breakpoint detected processor shifted debug mode. processor normal mode. Function Alternate Function
JTDI/RMODE#
JTDO JTRST# BKTGIO#
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(17) General-purpose signals (1/2)
Signal Name GPO63 GPO62 GPIO(61:54) GPIO(53:52) GPIO51 GPIO50 GPIO(49:48) GPIO(47:46) GPIO(45:40) GPIO39 GPIO38 GPIO37 GPIO(36:35) GPIO34 GPIO33 GPIO(32:31) GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 General-purpose ports General-purpose output ports Function Alternate Function VPBIAS VPLCD A(22:15) TC(1:0)# FPD15, CF1_READY FPD14, CF1_STSCHG# FPD(13:12), CF1_CE(2:1)# FPD(11:10), CF1_CD(2:1)# FPD(9:4) CF1_DIR, KPORT4 CF1_EN#, KPORT5 CF1_VCCEN#, KSCAN4 CF0_CD(2:1)# CF0_IOIS16# CF_WAIT# CF0_CE(2:1)# CF0_STSCHG# CF0_READY CF0_RESET CF0_DIR CF0_EN# CF_REG# CF0_VCCEN# SCK, KSCAN11 KSCAN10 KSCAN9 FRM, KSCAN8 RTS0#/ CLKSEL1 CTS0#
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2/2)
Signal Name GPIO17 General-purpose ports Function Alternate Function DTR0#, RTS1#, CLKSEL0 DCD0# DSR0#, CTS1# RxD1, SCL1 TxD1, SDA1 SCL0, KPORT7 SDA0, KPORT6 PWM2, KSCAN5 PWM1, KSCAN6 PWM0, KSCAN7 KPORT(3:0) KSCAN(3:0)
GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO(7:4) GPIO(3:0)
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(18) Mode setting signals These signals used various modes. These signals sampled only when RTCRST# signal changed high level. other times, they used alternate-function pins. order disconnect pull-up pull-down resistor mode setting during normal operation, switch linked RTCRST# signal.
Signal Name BMODE1 BMODE0 Function Boot type setting BMODE(1:0) ROM/flash memory BMODE(1:0) SyncFlash memory BMODE(1:0) Setting prohibited N-Wire enable signal Disabled Enabled Boot width specification bits bits frequency core's pipeline reference clock (AClock) CLKSEL(2:0) 111: Setting prohibited (147.4 MHz) CLKSEL(2:0) 110: 131.1 CLKSEL(2:0) 101: 118.0 CLKSEL(2:0) 100: 98.3 CLKSEL(2:0) 011: 90.7 CLKSEL(2:0) 010: 84.1 CLKSEL(2:0) 001: 78.5 CLKSEL(2:0) 000: 73.7 division ratio AClock internal system reference clock (TClock) DIVMODE(1:0) AClock/2 (DIV2 mode) DIVMODE(1:0) AClock/3 (DIV3 mode) DIVMODE(1:0) Setting prohibited Enables MIPS16 instruction disabled enabled Alternate Function VSYNC, ENAB,
NWIREEN
HSYNC, LOCLK
DBUS32
CF1_RESET
CLKSEL2 CLKSEL1 CLKSEL0
TxD0 RTS0#, GPIO19 DTR0#, RTS1#, GPIO17
DIVMODE1
RTS2#, SYNC, DTR2#, SDO, SDATAOUT TxD2, IRDOUT
DIVMODE0
MIPS16EN
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(19) Dedicated VDD/GND signals
Signal Name VDD2 GND2 VDD3 GND3 VDDU GNDU VDDP GNDP VDDO GNDO VDDAD Power Supply Power supply internal logic internal logic Power supply buffers (except buffer transceiver) buffers (except buffer transceiver) Dedicated power supply transceiver Dedicated transceiver Dedicated power supply (analog unit) Dedicated (analog unit) Dedicated power supply oscillator Dedicated oscillator Dedicated power supply converters. voltage applied this becomes maximum voltage value converters' interface signals. Dedicated converters. voltage applied this becomes minimum voltage value converters' interface signals. Dedicated power supply touch panel interface Dedicated touch panel interface Function
GNDAD
VDDTP GNDTP
Caution VR4181A includes power supply systems, system system. When applying voltage, sure apply power supply system first. Apply voltage power supply system according status MPOWER pin.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Statuses Specific Status
(1/7)
Name (Signal Name) AlternateFunction Name (Alternate Signal Name) CKE1 GPIO(61:54) GPIO(53:52) During Reset After Reset After Reset RSTSW Watchdog Timer Suspend Mode Hibernate Mode During Shutdown HALTimer Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A(22:15) A(14:0) SA10 D(31:0) IORD# IOWR# IORDY IOCS16# UBE# PCS(4:0)# SYSDIR SYSEN# DRQ(1:0)# DAK(1:0)# TC(1:0)# NMI# ROMCS# MEMRD# MEMWR# SDCLK CKE1 CKE0 SDCS(3:2)# SDCS(1:0)# RAS#
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating
Operating Note
Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note
Notes status previous Fullspeed mode retained. Changes according setting SDRAMACT register GIU. When SDACT When SDACT Remarks level, High level, Hi-Z: High impedance When high impedance, buffer's input enable setting OFF. Leakage current will occur even when intermediate level applied.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2/7)
Name (Signal Name) AlternateFunction Name (Alternate Signal Name) During Reset After Reset After Reset RSTSW Watchdog Timer Suspend Mode Hibernate Mode During Shutdown HALTimer
CAS# DQM(3:0), LBE(3:0)# POWER RSTSW# RTCRST# POWERON MPOWER RTCX(2:1) CLKX(2:1) DCLK, SHCLK
Note Note Note Hi-Z
Hi-Z
Note Note Note Note Note
Hi-Z
HSYNC, LOCLK NWIREEN VSYNC, ENAB, FPD15 BMODE1 BMODE0 CF1_READY, GPIO51 CF1_STSCHG#, GPIO50 CF1_CE(2:1)#, GPIO(49:48) CF1_CD(2:1)#, GPIO(47:46) GPIO(45:40) GPO62 GPO63
FPD14
Hi-Z
Hi-Z
Note
Hi-Z
FPD(13:12)
Hi-Z
Hi-Z
Note
Hi-Z
FPD(11:10)
Hi-Z
Hi-Z
Note
Hi-Z
FPD(9:4) FPD(3:0) VPLCD VPBIAS
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z
Note Note Hi-Z Hi-Z
Hi-Z Hi-Z
Notes status previous Fullspeed mode retained. panel's voltage drops during Suspend mode, enter settings register stop output operations pin's value input level sampled when RTCRST# signal changed high level order enable disable N-Wire. input level sampled when RTCRST# signal changed high level order boot type. Remarks level, High level, Hi-Z: High impedance When high impedance, buffer's input enable setting OFF. Leakage current will occur even when intermediate level applied.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(3/7)
Name (Signal Name) AlternateFunction Name (Alternate Signal Name) FPD(11:10), GPIO(47:46) FPD(13:12) GPIO(49:48) FPD14, GPIO50 FPD15, GPIO51 DBUS32 KPORT4, GPIO39 KPORT5, GPIO38 KSCAN4, GPIO37 GPIO(36:35) GPIO34 GPIO33 GPIO(32:31) GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 During Reset After Reset After Reset RSTSW Watchdog Timer Suspend Mode Hibernate Mode During Shutdown HALTimer Hi-Z
CF1_CD(2:1)#
Hi-Z
Hi-Z
CF1_CE(2:1)#
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
CF1_STSCHG# CF1_READY CF1_RESET CF1_DIR
Hi-Z Hi-Z Note Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z
Note Note
Hi-Z Hi-Z Note Hi-Z
CF1_EN#
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
CF1_VCCEN#
Hi-Z
Hi-Z
Note
Hi-Z
CF0_CD(2:1)# CF0_IOIS16# CF_WAIT# CF0_CE(2:1)# CF0_STSCHG# CF0_READY CF0_RESET CF0_DIR CF0_EN# CF_REG# CF0_VCCEN# CLK48 UHDP UHDN UPON
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Note Hi-Z Hi-Z Hi-Z Hi-Z
Note Note Note Note Note Note Note Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Notes status previous Fullspeed mode retained. input level sampled when RTCRST# signal changed high level order boot width. registers used high impedance. Remarks level, High level, Hi-Z: High impedance When high impedance, buffer's input enable setting OFF. Leakage current will occur even when intermediate level applied.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(4/7)
Name (Signal Name) AlternateFunction Name (Alternate Signal Name) SCLK, CTS2# RTS2#, DIVMODE1 SDO, DTR2#, DIVMODE0 SDI, DCD2# DSR2# BITCLK, CTS2# SYNC, RTS2#, DIVMODE1 SDATAOUT, DTR2#, DIVMODE0 SDATAIN, DCD2# KSCAN11, GPIO23 KSCAN10, GPIO22 KSCAN9, GPIO21 KSCAN8, GPIO20 CLKSEL2 GPIO19, CLKSEL1 GPIO18 During Reset After Reset After Reset RSTSW Watchdog Timer Suspend Mode Hibernate Mode During Shutdown HALTimer Hi-Z Hi-Z Hi-Z
BITCLK SYNC
Hi-Z Hi-Z Note
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
SDATAOUT
Note
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDATAIN SRESET# SCLK
Hi-Z Hi-Z Hi-Z Note
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
Note
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
RxD0 TxD0 RTS0#
Hi-Z Note Note
Hi-Z Hi-Z Hi-Z
Note Note
Hi-Z
CTS0#
Hi-Z
Hi-Z
Hi-Z
Notes input level sampled when RTCRST# signal changed high level order division ratio core's pipeline reference clock (AClock) peripheral system bus's reference clock (TClock). status previous Fullspeed mode retained. input level sampled when RTCRST# signal changed high level order frequency core's pipeline reference clock (AClock). Remarks level, High level, Hi-Z: High impedance When high impedance, buffer's input enable setting OFF. Leakage current will occur even when intermediate level applied.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(5/7)
Name (Signal Name) AlternateFunction Name (Alternate Signal Name) RTS1#, GPIO17, CLKSEL0 GPIO16 CTS1#, GPIO15 SCL1, GPIO14 SDA1, GPIO13 DTR0#, GPIO17, CLKSEL0 DSR0#, GPIO15 IRDIN IRDOUT, MIPS16EN SYNC, DIVMODE1 SCLK, BITCLK SDO, SDATAOUT, DIVMODE0 SDI, SDATAIN SRESET# RxD2 TxD2, MIPS16EN During Reset After Reset After Reset RSTSW Watchdog Timer Suspend Mode Hibernate Mode During Shutdown HALTimer Hi-Z
DTR0#
Note
Hi-Z
Note
DCD0# DSR0# RxD1 TxD1 RTS1#
Hi-Z Hi-Z Note
Hi-Z Hi-Z Hi-Z
Note Note
Hi-Z Hi-Z Hi-Z Hi-Z
CTS1# RxD2 TxD2
Hi-Z Note
Hi-Z Hi-Z
Hi-Z
Hi-Z Note
Hi-Z Hi-Z Hi-Z
RTS2#
Note
Hi-Z
Note
Hi-Z
CTS2# DTR2#
Hi-Z Note
Hi-Z Hi-Z
Hi-Z
Note
Hi-Z Hi-Z
DCD2# DSR2# IRDIN IRDOUT
Hi-Z Hi-Z Hi-Z Note
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Note
Hi-Z Hi-Z Hi-Z Hi-Z
Notes input level sampled when RTCRST# signal changed high level order frequency core's pipeline reference clock (AClock). status previous Fullspeed mode retained. input level sampled when RTCRST# signal changed high level order whether MIPS16 instruction not. input level sampled when RTCRST# signal changed high level order division ratio core's pipeline reference clock (AClock) peripheral system bus's reference clock (TClock). Remarks level, High level, Hi-Z: High impedance When high impedance, buffer's input enable setting OFF. Leakage current will occur even when intermediate level applied.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(6/7)
Name (Signal Name) AlternateFunction Name (Alternate Signal Name) RxD1, GPIO14 TxD1, GPIO13 KPORT7, GPIO12 KPORT6, GPIO11 KSCAN5, GPIO10 KSCAN6, GPIO9 KSCAN7, GPIO8 SCL0, GPIO12 SDA0, GPIO11 CF1_EN#, GPIO38 CF1_DIR, GPIO39 GPIO(7:4) SCK, GPIO23 GPIO22 GPIO21 FRM, GPIO20 PWM0, GPIO8 PWM1, GPIO9 PWM2, GPIO10 CF1_VCCEN#, GPIO37 GPIO(3:0) During Reset After Reset After Reset RSTSW Watchdog Timer Suspend Mode Hibernate Mode During Shutdown HALTimer Hi-Z Hi-Z Hi-Z
SCL1Note SDA1Note SCL0
Note
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Note Note Note
SDA0Note
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
PWM2
Hi-Z
Hi-Z
Note
Hi-Z
PWM1
Hi-Z
Hi-Z
Note
Note
Note
PWM0
Hi-Z
Hi-Z
Note
Note
Note
KPORT7 KPORT6 KPORT5
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
KPORT4
Hi-Z
Hi-Z
Hi-Z
KPORT(3:0) KSCAN11 KSCAN10 KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Note Note Note Note Note Note Note Note
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
KSCAN(3:0) TPX(1:0) TPY(1:0) AIN(3:0) AOUT
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z
Note Note Note Note
Hi-Z Hi-Z
Notes µPD30181AY only status previous Fullspeed mode retained. Remarks level, High level, Hi-Z: High impedance When high impedance, buffer's input enable setting OFF. Leakage current will occur even when intermediate level applied.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(7/7)
Name (Signal Name) AlternateFunction Name (Alternate Signal Name) During Reset After Reset After Reset RSTSW Watchdog Timer Suspend Mode Hibernate Mode During Shutdown HALTimer Hi-Z Hi-Z Hi-Z
JTCKNote JTMSNote JTDI RMODE# JTDONote JTRST#
Note Note
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
VPBIAS VPLCD
Note
Hi-Z Hi-Z Hi-Z Hi-Z HI-Z Hi-Z Hi-Z
Note
Hi-Z Hi-Z Hi-Z HI-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note Note
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note Note
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note Note
BKTGIO# GPO63 GPO62
Note
GPIO(61:54) GPIO(53:0)
A(22:15) Note
Notes This status when N-Wire function been prohibit status setting NWIREEN pin. When SyncFlash memory been selected boot ROM, this used GPIO pin. registers used high impedance. other names alternate-function names. GPIO19 GPIO17 signals sampled CLKSEL(1:0) when RTCRST# signal changed high level order frequency core's pipeline reference clock (AClock). Caution After reset, GPIO pins input direction input disable status set. Input enable status software after reset. Accordingly, there need externally elements such pull-up pull-down resistors unused GPIO pins order determine signal status. However, GPIO(61:54), which shared with A(22:15), function GPIO pins only when SyncFlash memory been selected. registers advance. Remarks level, High level, Hi-Z: High impedance When high impedance, buffer's input enable setting OFF. Leakage current will occur even when intermediate level applied. status output pins Hibernate mode specified using software enter required settings internal
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Circuit Types Recommended Connection Unused Pins
(1/3)
Name A24/CKE1 A23/RP# A(22:15)/GPIO(61:54) A(14:0) SA10 D(31:0) IORD# IOWR# IORDY IOCS16# UBE# PCS(4:0)# SYSDIR SYSEN# DRQ(1:0)# DAK(1:0)# TC(1:0)#/GPIO(53:52) NMI# ROMCS# MEMRD# MEMWR# SDCLK CKE0 SDCS(3:0)# RAS# CAS# DQM(3:0)/LBE(3:0)# POWER RSTSW# RTCRST# POWERON MPOWER DCLK/SHCLK HSYNC/LOCLK/NWIREEN VSYNC/FLM/BMODE1
Note Note
Circuit Type
Recommended Connection Unused Pins Leave open Leave open Leave open Leave open Leave open Connect VDD3 GND3 resistor Leave open Leave open Connect VDD3 Connect VDD3 Leave open Leave open Leave open Leave open Connect VDD3 Leave open Leave open Connect VDD3 Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect VDD3 Connect VDD3 Leave open Leave open Leave open Connect VDD3 GND3 resistor Connect VDD3 GND3 resistor
Note signal level sampled when RTCRST# signal changed high level.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2/3)
Name ENAB/M/BMODE0Note FPD15/CF1_READY/GPIO51 FPD14/CF1_STSCHG#/GPIO50 FPD(9:4)/GPIO(45:40) FPD(3:0) VPLCD/GPO62 VPBIAS/GPO63 CF1_RESET/DBUS32
Note
Note
Circuit Type
Recommended Connection Unused Pins Connect VDD3 GND3 resistor Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect VDD3 GND3 resistor Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect VDD3 GND3 resistor Connect VDD3 GND3 resistor Leave open Connect VDD3 GND3 resistor Leave open Leave open Connect VDD3 Connect VDD3 GND3 resistor Connect VDD3 GND3 resistor
CF1_DIR/KPORT4/GPIO39 CF1_EN#/KPORT5/GPIO38 CF1_VCCEN#/KSCAN4/GPIO37 CF0_CD(2:1)#/GPIO(36:35) CF0_IOIS16#/GPIO34 CF_WAIT#/GPIO33 CF0_CE(2:1)#/GPIO(32:31) CF0_STSCHG#/GPIO30 CF0_READY/GPIO29 CF0_RESET/GPIO28 CF0_DIR/GPIO27 CF0_EN#/GPIO26 CF_REG#/GPIO25 CF0_VCCEN#/GPIO24 SCK/KSCAN11/GPIO23 SI/KSCAN10/GPIO22 SO/KSCAN9/GPIO21 FRM/KSCAN8/GPIO20 RxD2/IRDIN TxD2/IRDOUT/MIPS16ENNote RTS2#/SYNC/WS/DIVMODE1Note CTS2#/BITCLK/SCLK DTR2#/SDATAOUT/SDO/DIVMODE0 DCD2#/SDATAIN/SDI DSR2#/SRESET# RxD0 TxD0/CLKSEL2
Note
RTS0#/GPIO19/CLKSEL1
Note
Note signal level sampled when RTCRST# signal changed high level.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(3/3)
Name CTS0#/GPIO18 DTR0#/RTS1#/GPIO17/CLKSEL0Note DCD0#/GPIO16 DSR0#/CTS1#/GPIO15 RxD1/SCL1/GPIO14 TxD1/SDA1/GPIO13 SCL0/KPORT7/GPIO12 SDA0/KPORT6/GPIO11 PWM2/KSCAN5/GPIO10 PWM1/KSCAN6/GPIO9 PWM0/KSCAN7/GPIO8 KPORT(3:0)/GPIO(7:4) KSCAN(3:0)/GPIO(3:0) CLK48 UHDP UHDN UPON TPX(1:0) TPY0 TPY1 AIN(3:0) AOUT JTCK JTMS JTDI/RMODE# JTDO JTRST# BKTGIO# Circuit Type Recommended Connection Unused Pins Leave open Connect VDD3 GND3 resistor Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect GND3 Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open
Note signal level sampled when RTCRST# signal changed high level.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Circuits
Type
VDD3 Data P-ch IN/OUT
Type
VDDTP Data P-ch IN/OUT
Output disable
N-ch
Output disable P-ch
N-ch
Input enable
Vref
N-ch
Type
VDD3 Data P-ch IN/OUT Open drain Output disable
Input enable
N-ch
N-ch
Type
P-ch N-ch Vref
Input enable
Type
VDDTP Data P-ch IN/OUT
Type
Analog output voltage
Type
Output disable P-ch Vref N-ch N-ch
Data Output disable
-IN/OUT
+IN/OUT
Input enable
Remark Type slew-rate output Type Schmitt-triggered input, slew-rate output Type Differential
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol VDD25 VDD33 Input voltage Condition (VDD2, VDDP pins) (VDD3, VDDU, VDDTP, VDDAD, VDDO pins) VDD33 VDD33 Storage temperature Tstg Rating -0.5 +3.6 -0.5 +4.0 -0.5 +4.0 -0.5 VDD33 +125 Unit
Cautions short-circuit more output pins simultaneously. even above parameters exceeds absolute maximum ratings even momentarily, quality product degraded. absolute maximum ratings, therefore, specify value exceeding which product physically damaged. product well within these ratings. specifications conditions shown Characteristics Characteristics ranges normal operation quality assurance product. -1.5 input pulse less than Operating Conditions
Parameter Supply voltage Symbol VDD25 VDD33 Ambient temperature Oscillation start voltageNote Oscillation hold voltage Oscillation hold voltage
Note
Condition (VDD2, VDDP pins) (VDD3, VDDU, VDDTP, VDDAD, VDDO pins) When operating 131.1
MIN.
MAX.
Unit
VDDS VDDH1 VDDH2
Note
Notes This voltage which oscillation always started after power application, applied oscillators 32.768 18.432 MHz. This voltage which oscillation guaranteed voltage lowered from normal operation level, applied oscillator 32.768 kHz. This voltage which oscillation guaranteed voltage lowered from normal operation level, applied oscillator 18.432 MHz. Remark VR4181A types power supplies. power supply should turned first. Turn on/off power supply depending status MPOWER pin.
Capacitance +85°C, VDD33
Parameter Input capacitance capacitance capacitance
Note
Symbol CI_USB
Condition Unmeasured pins returned
MIN.
MAX.
Unit
Note
Notes Applies UHDP, UHDN, UDP, pins. Applies pins other than UHDP, UHDN, UDP, pins.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Characteristics +85°C, VDD25 VDD33 Pins circuit types
Parameter Output voltage, high Symbol Pins types Output voltage, Pins types Input voltage, high Pins types
Note Note
Conditions
Note
MIN.
Note
TYP.
MAX.
Unit
Note
0.8VDD33
Note
Note
(excluding GPIO
Note
VDD33
edge triggered interrupt), VIH1E Pins type
Note
Note
(GPIO edge
0.75VDD33 -0.3 -0.3
VDD33
triggered interrupt) Input voltage, Pins type
Note
(excluding GPIO
Note
0.25VDD33
edge triggered interrupt), VIL1E Pins type
Note
Note
(GPIO edge
triggered interrupt)
Notes Applies following pins. D(31:0), IORDY, IOCS16#, DRQ(1:0)#, TC(1:0)#/GPIO(53:52), NMI#, HSYNC/LOCLK/NWIREEN, ENAB/M/BMODE0, VSYNC/FLM/BMODE1, FPD15/CF1_READY/GPIO51, FPD14/CF1_STSCHG#/GPIO50, FPD(9:4)/GPIO(45:40), CLK48, JTCK, JTMS, JTDI/RMODE#, JTRST#, BKTGIO#, A(14:0), A23/RP#, A24/CKE1, CAS#, CKE0, DAK(1:0)#, DCLK/SHCLK, DQM(3:0), FPD(3:0), IORD#, JTDO, MEMRD#, MEMWR#, MPOWER, PCS(4:0)#, POWERON, RAS#, ROMCS#, SA10, SDCLK, SDCS(3:0)#, SYSDIR, SYSEN#, UBE#, UPON, VPBIAS/GPO63, VPLCD/GPO62, Applies TPX(1:0) TPY0 pins. Applies TPY1 pin. Applies following pins. FPD(9:4)/GPIO(45:40), FPD14/CF1_STSCHG#/GPIO50, FPD15/CF1_READY/GPIO51, TC(1:0)#/GPIO(53:52), A(22:15)/GPIO(61:54) Remark details circuits, refer Circuits
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Pins circuit types
Parameter Output voltage, high Symbol VOH2 VOH_USB Output voltage, VOL2 VOL_USB Input voltage, high VIH2 VIH_USB Input voltage, VIL2 VIL_USB Hysteresis voltageNote Output cross levelNote Differential input sensitivityNote Differential input common mode rangeNote External pull-up resistor External pull-down resistor External resistor impedance adjustmentNote VCRS_USB VDI_USB Conditions Pins type BNote Pins type GNote Pins type BNote Pins type Pins type
Note
MIN. 0.8VDD33
TYP.
MAX.
Unit
0.75VDD33 -0.3 single 0.17VDD33
Note
VDD33
Pins type GNote single Pins type
Note
Pins type
Note
Pins type BNote Pins type GNote Pins type GNote
VCM_USB
Pins type GNote
Pins type GNote Pins type
Note
1.425 14.25 20.9
1.575 15.75 23.1
Pins type GNote
Notes Applies following pins. POWER, RSTSW#, RTCRST#, CF1_RESET/DBUS32, RxD0, TxD0/CLKSEL2, RxD2/IRDIN, TxD2/IRDOUT/MIPS16EN, CTS2#/BITCLK/SCLK, DTR2#/SDATAOUT/SDO/DIVMODE0, RTS2#/SYNC/WS/DIVMODE1, DCD2#/SDATAIN/SDI, DSR2#/SRESET#, UOC, CF1_DIR/KPORT4/GPIO39, CF1_EN#/KPORT5/GPIO38, CF1_VCCEN#/KSCAN4/GPIO37, CF0_CD2#/GPIO36, CF0_CD1#/GPIO35, CF0_IOIS16#/GPIO34, CF_WAIT#/GPIO33, CF0_CE2#/GPIO32, CF0_CE1#/GPIO31, CF0_STSCHG#/GPIO30, CF0_READY/GPIO29, CF0_RESET/GPIO28, CF0_DIR/GPIO27, CF0_EN#/GPIO26, CF_REG#/GPIO25, CF0_VCCEN#/GPIO24, SCK/KSCAN11/GPIO23, SI/KSCAN10/GPIO22, SO/KSCAN9/GPIO21, FRM/KSCAN8/GPIO20, RTS0#/GPIO19/CLKSEL1, CTS0#/GPIO18, DTR0#/RTS1#/GPIO17/CLKSEL0, DCD0#/GPIO16, DSR0#/CTS1#/GPIO15, RxD1/SCL1/GPIO14, TxD1/SDA1/GPIO13, SCL0/KPORT7/GPIO12, SDA0/KPORT6/GPIO11, PWM(2:0)/KSCAN(5:7)/GPIO(10:8), KPORT(3:0)/GPIO(7:4), KSCAN(3:0)/GPIO(3:0) Applies UHDP, UHDN, UDP, pins Hysteresis voltage: Difference between minimum voltage which high level Schmitt input signal recognized when signal goes from high maximum voltage which level recognized when signal goes from high low. Precision tests have been performed. Only guaranteed design characteristics. recommended value Remark details circuits, refer Circuits.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Connection example external resistor When pulled down
UHDP, UHDN, UDP,
GNDU
When pulled
VDDU
UHDP, UHDN, UDP,
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Common
Parameter Power supply currentNote Symbol IDD25Note Conditions Fullspeed mode Fullspeed mode, program using cache operating, controller operating, clock supplied unit Fullspeed mode, program using cache operating, controller operating Fullspeed mode, program using cache operating, peripheral masters stopped, clocks unused units stopped Standby mode, peripheral master operating continuously Standby mode, peripheral masters stopped, clocks unused unit stopped Suspend mode Hibernate mode, VDD25 IDD33
Note
MIN.
TYP.
MAX.
Unit
Fullspeed mode
32-bit 16-bit
Standby mode, peripheral master operating continuously
32-bit 16-bit
Standby mode, peripheral masters stopped, clocks unused units stopped Suspend mode Hibernate mode, PWMU channel operating Hibernate mode, PWMU channel stopped IDDAD Input leakage current
Note Note
A/D, converters operating VDD33 VDD33, VDD33 VDD33,
Output leakage current
Notes Value when AClock 131.1 MHz, TClock 65.55 MHz, Div2 mode. IDD25 total current flowing VDD2 VDDP pins. IDD33 total current flowing VDD3, VDDU, VDDTP, VDDO pins. IDDAD current flowing VDDAD when Vref supplied converters. Excluding I.C. pin. Remarks Suspend mode, internal controller does operate because memory controller (MCU) clock controller (LCU) clock stopped. Each current value average value that flows under specified conditions. Design power supply that current under MAX. condition supplied stably that voltage drop ripple occur whole system). peripheral master indicates following peripheral units. LCU, DCU, IOPCIU, USBHU, USBFU, AC97U
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Data Retention Characteristics +85°C)
Parameter Data retention voltage Data retention high-level input voltage Symbol VDDDR3 VIHDR Conditions Hibernate mode, power supply Hibernate mode, RTCRST# MIN. 0.9VDDDR3 MAX. Unit
data retention voltage data retention high-level input voltage voltages that guarantee operation ElapsedTime counter data retention registers (using power supply) following peripheral units. These voltages apply data core (using power supply). PMU: RTC: GIU: PMUINTREG, PMUCNTREG, PMUWAITREG, PMUDIVREG ETIMELREG, ETIMEMREG, ETIMEHREG, ECMPLREG, ECMPMREG, ECMPHREG GPMODE0, GPMODE1, GPMODE2, GPMODE3, GPMODE4, GPMODE5, GPMODE6, GPMODE7, GPDATA0, GPDATA1, GPDATA2, GPDATA3, GPINEN0, GPINEN1, GPINEN2, GPINEN3, GPINTMSK0, GPINTMSK1, GPINTMSK2, GPINTMSK3, GPINTTYP0, GPINTTYP1, GPINTTYP2, GPINTTYP3, GPINTTYP4, GPINTTYP5, GPINTTYP6, GPINTTYP7, GPINTSTAT0, GPINTSTAT1, GPINTSTAT2, GPINTSTAT3, PINMODE, SDRAMACT, NVREG0, NVREG1, NVREG2, NVREG3 PWMU: PWM0ATSREG, PWM0IATSREG, PWM0CNTREG, PWM0ASTCREG, PWM0INTREG, PWM1CTRL, PWM1BUF
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Characteristics +85°C, VDD25 VDD33 test input test points D(31:0), IORDY, IOCS16#, DRQ(1:0)#, TC(1:0)#/GPIO(53:52), NMI#, HSYNC/LOCLK/NWIREEN, VSYNC/FLM/BMODE1, FPD15/CF1_READY/GPIO51, FPD14/CF1_STSCHG#/GPIO50, FPD(9:4)/GPIO(45:40), CLK48, JTCK, JTMS, JTDI/RMODE#, JTRST#, BKTGIO#, TPX(1:0), TPY(1:0)
VDD33 Input pins
Test points 0.25VDD33
0.25VDD33
A(22:15)/GPIO(61:54), POWER, RSTSW#, RTCRST#, CF1_RESET/DBUS32, RxD0, TxD0/CLKSEL2, RxD2/IRDIN, TxD2/IRDOUT/MIPS16EN, CTS2#/BITCLK/SCLK, DTR2#/SDATAOUT/SDO/DIVMODE0, RTS2#/SYNC/WS/DIVMODE1, DCD2#/SDATAIN/SDI, DSR2#/SRESET#, UOC, CF1_DIR/KPORT4/GPIO39, CF1_EN#/KPORT5/GPIO38, CF1_VCCEN#/KSCAN4/GPIO37, CF0_CD(2:1)#/GPIO(36:35), CF0_IOIS16#/GPIO34, CF_WAIT#/GPIO33, CF0_CE(2:1)#/GPIO(32:31), CF0_STSCHG#/GPIO30, CF0_READY/GPIO29, CF0_RESET/GPIO28, CF0_DIR/GPIO27, CF0_EN#/GPIO26, CF_REG#/GPIO25, CF0_VCCEN#/GPIO24, SCK/KSCAN11/GPIO23, SI/KSCAN10/GPIO22, SO/KSCAN9/GPIO21, FRM/KSCAN8/GPIO20, RTS0#/GPIO19/CLKSEL1, CTS0#/GPIO18, DTR0#/RTS1#/GPIO17/CLKSEL0, DCD0#/GPIO16, DSR0#/CTS1#/GPIO15, RxD1/SCL1/GPIO14, TxD1/SDA1/GPIO13, SCL0/KPORT7/GPIO12, SDA0/KPORT6/GPIO11, PWM(2:0)/KSCAN(5:7)/GPIO(10:8), KPORT(3:0)/GPIO(7:4), KSCAN(3:0)/GPIO(3:0)
VDD33 Input pins
0.75VDD33 Test points 0.25VDD33
0.75VDD33 0.25VDD33
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
test output test points
VDD33 output pins 0.5VDD33 Test points 0.5VDD33
Load condition
output pins
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Clock parameters
Parameter core operating frequency Symbol fAClock Conditions CLKSEL(2:0) CLKSEL(2:0) CLKSEL(2:0) CLKSEL(2:0) CLKSEL(2:0) CLKSEL(2:0) CLKSEL(2:0) CLKSEL(2:0) TClock, SDCLK frequency fTClock DIVMODE(1:0) DIVMODE(1:0) DIVMODE(1:0) DIVMODE(1:0) MasterOut frequency PCIClock frequency fMasterOut tPCIClock PCICLKDIV(1:0) PCICLKDIV(1:0) PCICLKDIV(1:0) PCICLKDIV(1:0) LClock frequency fLClock LCLKDIV(1:0) LCLKDIV(1:0) LCLKDIV(1:0) LCLKDIV(1:0) PClock frequency fPClock PCLKDIV(1:0) PCLKDIV(1:0) PCLKDIV(1:0) PCLKDIV(1:0) ECU_SysClock frequency
Note Note Note Note Note Note
MIN.
TYP. 147.4 131.1 118.0 98.3 90.7 84.1 78.5 73.7
MAX.
Unit
18.432 18.432 18.432 18.432
fAClock/1 fAClock/2 fAClock/3 fAClock/4 fTClock/4 fTClock/8 fTClock/4 fTClock/2 fTClock/1 fTClock/1 fTClock/2 fTClock/3 fTClock/4
65.55 65.55 65.55 65.55
32.78 32.78 32.78 32.78
Note
18.432 18.432 18.432 18.432
Note
fTClock/1 fTClock/2 fTClock/4 fTClock/8 fTClock/1 fTClock/2 fTClock/4 fTClock/8
32.78 32.78 32.78 32.78 32.78 32.78 32.78 32.78
fECU_SysClock ECUSYSCLKDIV(1:0) ECUSYSCLKDIV(1:0) ECUSYSCLKDIV(1:0) ECUSYSCLKDIV(1:0)
Note These values cannot current VR4181A. Remarks settings CLKSEL(2:0) DIVMODE(1:0) signals sampled when RTCRST# signal changes high level. PCICLKDIV(1:0): Bits CLKDIVCTRL register CCU. these bits before starting on-chip peripheral unit. LCLKDIV(1:0): Bits EXIBUCFG register EXIBU. these bits before setting timing parameters each register EXIBU. PCLKDIV(1:0): Bits CLKDIVCTRL register CCU. ECUSYSCLKDIV(1:0): Bits CLKDIVCTRL register CCU. these bits before starting ECU.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Reset parameters
Parameter reset input low-level width RSTSW reset input low-level width Symbol tWRSL tWRSWL Conditions Applies RTCRST# signal Applies RSTSW# signal MIN. MAX. Unit
Remark low-level width reset input MIN. value lower, reset sequence started.
RTCRST# (input) tWRSL
RSTSW# (input) tWRSWL
Initial setting parameters
Parameter Setup time RTCRST#) Hold time (from RTCRST#) Symbol Conditions MIN. 91.6 MAX. Unit
RTCRST# (input)
NWIREEN, BMODE(1:0), DBUS32, CLKSEL(2:0), MIPS16EN, DIVMODE(1:0) (input)
Hi-Z Normal operation
Remark circles indicate sampling timing.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
SDRAM, SyncFlash interface (MCU) parameters
Parameter SDCLK frequency SDCLK cycle SDCLK high-level width SDCLK low-level width Output delay time (from SDCLK) Data setup time Data hold time Symbol fSDCLK tSDCLK tSDCH tSDCL tSDDP tSDS tSDH 15.26 11.7 Conditions MIN. MAX. 65.55 Unit
tSDCLK tSDCL SDCLK (output) tSDDP A(14:11), SA10, A(9:0) (output) tSDCH
CKE(1:0), SDCS(3:0)#, DQM(3:0), RAS#, CAS#, (output) D(31:0) (write)
D(31:0) (read)
Hi-Z
Hi-Z
tSDS
tSDH
Remark circles indicate sampling timing.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
ROM, flash memory, SRAM, interface (EXIBU) parameters
Parameter TClock frequency TClock cycle LClock frequency LClock cycle Output delay time Data input setup time Data input hold time Data output float delay time Data output setup time (from command signal) IORDY input hold time IOCS16# input hold time DRQn# input inactive setup time tEXRDYH tEXCS16H tDRQNEG Symbol fTClock tTClock fLClock tLClock tEXD tEXS tEXH tEXZ tEXCL 30.52 15.26 32.78 Conditions MIN. MAX. 65.55 Unit
Remarks TClock generated dividing AClock accordance with setting DIVMODE(1:0) signals when RTCRST# signal changes high level. After releasing reset, division ratio TClock changed setting PMUDIVREG register. LClock generated dividing Tclock accordance with setting LCLKDIV(1:0) bits EXIBUCFG register EXIBU. MEMRD#, MEMWR#, IORD#, IOWR# signals called command signals external system interface.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Non-READY mode timing
CONSET+tEXD
CONWID+tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD
SYSDIR (output) tTClock +tEXD tTClock +tEXD Note
D(31:0) (read)
Note tEXZ
Hi-Z
Input tEXS tEXH
Hi-Z
tEXD D(31:0) (write) tEXCL
tEXD
Note Output Remarks CONSET, CONWID, CSOFF, BUSIDLE timing parameters that changed setting registers EXIBU. Each timing parameter defined number LClock cycles. circles indicate sampling timing.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Page access timing (CONSET CSOFF
CONWID+tEXD
SUBCWID SUBCWID SUBCWID +tEXD +tEXD +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) SYSEN# (output) SYSDIR (output) tTClock +tEXD
tEXD
tEXD
D(31:0) (read)
Output tEXZ
Note
Note
Note
Note
tEXS tEXH D(31:0) (write)
tEXS tEXH
tEXS tEXH
tEXS tEXH
tEXD
tEXD
tEXD
tEXD
tEXD
Note Input Remarks CONWID SUBCWID timing parameters that changed setting registers EXIBU. Each timing parameter defined number LClock cycles. circles indicate sampling timing. broken lines indicate high impedance.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
READY mode timing (RDYSYN
CONSET +tEXD
RMINWID +tEXD
CONOFF +tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD
SYSDIR (output) tTClock +tEXD tTClock +tEXD D(31:0) (read) Note tEXZ tEXS tEXD D(31:0) (write) tEXCL tEXH tEXD Hi-Z Input Hi-Z Note
IORDY (input)
2tTClock+tLClock+tEXD
tEXRDYH
Note Output Remarks CONSET, CSOFF, RMINWID, CONOFF, BUSIDLE timing parameters that changed setting registers EXIBU. Each timing parameter defined number LClock cycles. circles indicate sampling timing.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
External space access (READY mode) timing (RDYSYN
IOCS16SET CONSET RMINWID CONOFF +tEXD +tEXD +tEXD +tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) SYSEN# (output)
tEXD
tEXD
tEXD
SYSDIR (output) tTClock +tEXD tTClock +tEXD Note
D(15:0) (read)
Note tEXZ
Hi-Z
Input
Hi-Z
Hi-Z
tEXS tEXD D(15:0) (write) tEXCL
tEXH tEXD
IORDY (input)
2tTClock+tLClock+tEXD IOCS16# (input)
tEXRDYH
tLClock+tEXD
tEXCS16H
Note Output Remarks IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, BUSIDLE timing parameters that changed setting registers EXIBU. Each timing parameter defined number LClock cycles. circles indicate sampling timing.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
transfer timing
CONSET+tEXD
CONWID+tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD
SYSDIR (output) DRQn# (input) DAKn# (output) Hi-Z Hi-Z tTClock +tEXD tDRQNEG
tTClock +tEXD
D(31:0) (read)
Note tEXZ
Input tEXS tEXH
Note
tEXD D(31:0) (write) tEXCL
tEXD
Note Output Remarks CONSET, CONWID, CSOFF, BUSIDLE timing parameters that changed setting registers EXIBU. Each timing parameter defined number LClock cycles. circles indicate sampling timing.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
CompactFlash/PC Card/ATA (IDE) interface (ECU) parameters
Parameter TClock frequency TClock cycle LClock frequency LClock cycle ECU_SysClock frequency ECU_SysClock cycle Output delay time (EXIBU) Output delay time (ECU) Data input setup time Data input hold time Data output float delay time Data output setup time command signal) CF_WAIT# input hold time CF0_IOIS16# input hold time tECURDYH tECUCS16H Symbol fTClock tTClock fLClock tLClock fECU_SysClock tECU_SysClock tEXD tECUD tEXS tEXH tEXZ tEXCL 30.52 30.52 32.78 15.26 32.78 Conditions MIN. MAX. 65.55 Unit
Remarks TClock generated dividing AClock accordance with setting DIVMODE(1:0) signals when RTCRST# signal changes high level. After releasing reset, division ratio TClock changed setting PMUDIVREG register. LClock generated dividing TClock accordance with setting LCLKDIV(1:0) bits EXIBUCFG register EXIBU. ECU_SysClock generated dividing TClock accordance with setting ECUSYSCLKDIV(1:0) bits CLKDIVCTRL register CCU. MEMRD#, MEMWR#, IORD#, IOWR# signals called command signals external system interface. Relationship between cycle type ECUWAIT
Cycle Number Wait Cycles 16-bit cycle (IOnWT 16-bit cycle(IOnWT 8-bit cycle (Wn_IOWS 8-bit cycle (Wn_IOWS 16-bit memory cycle (ZWSEN M16W(1:0) 16-bit memory cycle (ZWSEN M16W(1:0) 8-bit memory cycle (ZWSEN 8-bit memory cycle (ZWSEN tECU_SysClock tECU_SysClock MIN. tECU_SysClock tECU_SysClock tECU_SysClock tECU_SysClock ECUWAIT Value (ns) MAX.
Remarks IOnWT, Wn_IOWS, ZWSEN, M16W(1:0) bits register ECU.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
External space access (READY mode) timing (RDYSYN
IOCS16SET CONSET RMINWID ECUWAIT +tEXD +tEXD +tEXD +tECUD
CONOFF +tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output) CFn_CE(2:1)#, CF_REG# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD tEXD tTClock +tECUD tTClock +tECUD
SYSDIR (output) tTClock +tEXD CFn_EN# (output) tTClock +tECUD CFn_DIR (output) tTClock +tEXD Note tECUD tECUD tTClock +tECUD
D(15:0) (read)
Note tEXZ
Hi-Z
Input
Hi-Z
Hi-Z
tEXD D(15:0) (write) tEXCL CF_WAIT# (input) CF0_IOIS16# (input) tLClock+tECUD
tEXS
tEXH tEXD
tECURDYH
tECUCS16H
Note Output Remarks IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, BUSIDLE timing parameters that changed setting registers EXIBU. Each timing parameter defined number LClock cycles. circles indicate sampling timing.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
interface (USBHU, USBFU) parameters
Parameter Rise time
Note
Symbol tR_FUSB tR_LUSB
Conditions Fullspeed Mbps) mode speed (1.5 Mbps) mode Fullspeed Mbps) mode speed (1.5 Mbps) mode Fullspeed Mbps) mode speed (1.5 Mbps) mode
MIN.
MAX.
Unit
Fall time
Note
tF_FUSB tF_LUSB
Vp-p output potential width
Notes
tRFM_FUSB tRFM_LUSB
Notes Precision tests have been performed. Only guaranteed design characteristics. Indicated following expressions. tRFM_FUSB tR_FUSB/tF_FUSB tRFM_LUSB tR_LUSB/tF_LUSB
UHDP, UHDN UDP, (I/O)
tR_FUSB tR_LUSB
tF_FUSB tF_LUSB
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
AC97 interface (AC97U) parameters
Parameter BITCLK frequency BITCLK cycle BITCLK high-level width BITCLK low-level width SYNC frequency SYNC cycle SYNC high-level width SYNC low-level width SDATAIN input setup time BITCLK) SDATAIN input hold time BITCLK) SDATAOUT output delay time BITCLK) tSDATD tSDATH Symbol fBITCLK tBITCLK tBITCLKH tBITCLKL fSYNC tSYNC tSYNCH tSYNCL tSDATS Conditions MIN. TYP. 12.288 81.4 40.7 40.7 20.8 19.5 MAX. Unit
tBITCLK tBITCLKH BITCLK (input) tSDATS SDATAIN (input) tSDATD SDATAOUT (output) tSDATD tSDATH tBITCLKL
tSYNC tSYNCH SYNC (output) tSYNCL
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
interface (I2SU) parameters
Parameter SCLK frequency SCLK cycle SCLK high-/low-level width input setup time SCLK) input hold time (from SCLK) output delay time (from SCLK) delay time (from SCLK) Symbol fSCLK tSCLK tSCLKHL tSDIS tSDIH tSDOD tWSD tSCLK/2 tSCLK/2 Conditions MIN. MAX. 6.114 Unit
tSCLK tSCLKHL SCLK (I/O) tWSD (I/O) tSDIS (input) tSDOD (output) tSDOD tSDIH tSCLKHL
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(10) Serial interface (SIU) parameters
Parameter TxD0, TxD1, TxD2 output pulse width RxD0, RxD1, RxD2 input pulse width IRDOUT high-level output pulse width Symbol tTXD tRXD tIRDOUT Conditions MIN. (9/16) (3/16) IRDIN input pulse width tIRDIN (3/16) MAX. Unit
Remark data transfer cycle determined divisor baud rate generator SIUDLL SIUDLM registers.
Baud Rate (bps) 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 128000 144000 192000 230400 288000 384000 576000 1152000 Divisor (DLM(7:0)||DLL(7:0)) 23040 15360 10473 8565 7680 3840 1920 20000.00 13333.33 9090.91 7434.94 6666.67 3333.33 1666.67 833.33 555.56 500.00 416.67 277.78 208.33 138.89 104.17 52.08 26.04 17.36 8.68 7.81 6.94 5.21 4.34 3.47 2.60 1.74 0.868 (µs)
Remark Baud rate (18.432 MHz/16)/(value SIUDLM SIUDLL register)
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
TxDn
(output)
tTXD RxDn
(input)
tRXD IRDOUT
(output)
tIRDOUT IRDIN
(input)
tIRDIN
Remark
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(11) interface (I2CU) parameters (µPD30181AY only)
Parameter
Symbol
Condition
Normal Mode MIN. MAX.
High-Speed Mode MIN. MAX.
Unit
SCLn frequency Start condition hold time SCLn low-level width SCLn high-level width Rise time Fall time Data setup time Data retention time Repeat start setup time Stop condition setup time release time
fSCL tHD:STA tLOW tHIGH tSU:DAT tHD:DAT tSU:STA tSU:STO tBUF
0.25
SDAn (I/O)
tSU:STA
tSU:STO tHD:STA SCLn (I/O) tLOW tHIGH tSU:DAT tHD:DAT
tBUF
Remark
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(12) Clocked serial interface (CSI) parameters
Parameter frequency cycle high-/low-level width input setup time edge
Note
Symbol fSCK tSCK tSCKHL tSIS tSIH tSOD
Condition
MIN.
MAX. 4.608
Unit
tSCK/2 tSCK/2
input hold time (from edge output delay time (from edge
Note
Note
Note edge used differs depending settings CKMD CKPOL bits CSIMODE register.
tSCK tSCKHL (I/O) tSIS (input) tSOD (output) tSIH tSCKHL
Remark This diagram shows timing when using rising edge (CKMD CKPOL CKMD CKPOL
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(13) interface (LCU) parameters
Parameter DCLK/SHCLK frequency DCLK/SHCLK cycle DCLK/SHCLK high-/low-level width Output delay time (from DCLK/SHCLK edge
Note
Symbol fDCLK tDCLK tDCLKHL tLCDD
Condition
MIN.
MAX. 32.775
Unit
tDCLK/2 Applies HSYNC/LOCLK, VSYNC/FLM, ENAB/M, FPD(15: signals tDCLK/2
Note DCLK/SHCLK edge used differs depending setting SCLKPOL LCDCTRLREG register.
tDCLK tDCLKHL DCLK/SHCLK (output) tLCDD HSYNC/LOCLK, VSYNC/FLM, ENAB/M, FPD(15:0) (output) tDCLKHL
Remark This diagram shows timing when using DCLK/SHCLK rising edge (SCLKPOL
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(14) GPIO interface (GIU) parameters
Parameter GPIO input level width Symbol tGPIN1 Condition Restoring from Hibernate mode when level trigger selected. tGPIN2 Interrupt input when level trigger selected. GPIO input rise time
Note
MIN.
MAX.
Unit
(tTClock
tGPINR tGPINR2
GPIO(61:40) pins GPIO pins other than above GPIO(61:40) pins GPIO pins other than above
GPIO input fall time
Note
tGPINF tGPINF2
Note Precision tests have been performed. Only guaranteed design characteristics.
GPIO input level width
tGPIN1, tGPIN2
GPIOn (input)
Remark
GPIO input rise/fall time
tGPINF, tGPINF2 tGPINR, tGPINR2
GPIOn (input)
Remark
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(15) parameters
Parameter NMI# input low-level width Symbol tNMI Condition MIN. MAX. Unit
NMI# (input) tNMI
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Converter Characteristics +85°C, VDD25 VDD33
Parameter Zero-scale error Full-scale error
Notes
Symbol
Condition
MIN.
TYP. ±4.0 ±5.0 ±3.0 ±3.0
MAX.
Unit
Notes
Integral linearity error
Notes
VIAN
Note
Differential linearity error Analog input voltage
Note
Notes
-0.3 1.53 When input capacitance
VDDAD
Analog input equivalent resistance
RAIN CAIN REXOUT
Analog input equivalent capacitance
Note
Analog signal source allowable output impedance
Note
Notes Applies TPX(1:0), TPY(1:0), AIN(3:0) pins. Excluding quantization error.
Remark LSB:
Least significant
VDDAD: Voltage supplied VDDAD
converter input equivalent circuit
VR4181A
REXOUT
AINn
RAIN
CAIN
Remark
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Converter Characteristics +85°C, VDD25 VDD33
Parameter Integral linearity error
Notes
Symbol RSTOUT
Condition
MIN.
TYP. ±3.0 ±3.0 1110
MAX.
Unit
Differential linearity error String unit resistor
Notes
String output equivalent resistor
Notes Applies AOUT pin. Excluding quantization error. Remark LSB: Least significant Cautions output impedance converter large latch current from AOUT pin. load input impedance small, insert buffer amplifier between load AOUT pin. Make wiring between buffer amplifier load short possible. wiring long, processing required such enclosing wiring with ground pattern. output voltage converter changes steps, output signal from converter after passing through pass filter. converter output equivalent circuit
VR4181A VDDAD 1023
Series resistor string
selector
RSTOUT AOUT
GNDAD
Remark series resistor string connected between reference voltage converter (VDDAD) (GNDAD) converter. make 1024 equivalent voltage steps between pins, this circuit consists 1023 equivalent unit resistors (RST) resistors with resistance half RST. equivalent output impedance AOUT value calculated adding RSTOUT total value corresponding selected voltage step.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
PACKAGE DRAWING
240-PIN PLASTIC FBGA (16x16)
INDEX MARK
(UNIT:mm) ITEM DIMENSIONS 16.00±0.10 16.00±0.10 0.20 1.48±0.10 0.35±0.06 1.13 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.20 1.20 P240F1-80-GA3
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
RECOMMENDED SOLDERING CONDITIONS
µPD30181A 30181AY should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Table 4-1. Soldering Conditions Surface-Mount Type µPD30181AF1-131-GA3: 240-pin plastic FBGA
µPD30181AYF1-131-GA3: 240-pin plastic FBGA
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: seconds less (210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Symbol IR35-203-2
Note After opening pack, store 25°C less less allowable storage period. µPD30181AF1-131-GA3-A
Note
240-pin plastic FBGA 240-pin plastic FBGA
µPD30181AYF1-131-GA3-A
Note
soldering methods conditions, contact sales representative. Note Lead-free product
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. Reference document Electrical Characteristics Microcomputer (U15170J)
Note
Note This document number that Japanese version. documents indicated this publication include preliminary versions. However, preliminary versions marked such. EEPROM, VR4120, VR4181A, Series, VR4100 Series trademarks Corporation. MIPS registered trademark MIPS Technologies, Inc. United States. SyncFlash trademark Micron Technology, Inc. Bluetooth trademark Bluetooth SIG, Inc.
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Filiale Italiana Milano, Italy Tel: 02-66 Fax: 02-66 Branch Netherlands Eindhoven, Netherlands Tel: 040-244 Fax: 040-244
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
Branch Sweden Taeby, Sweden Tel: 08-63 Electronics (Europe) GmbH Fax: 08-63 Duesseldorf, Germany United Kingdom Branch Tel: 0211-65 Milton Keynes, Fax: 0211-65 Tel: 01908-691-133 Fax: 01908-670-290 Sucursal Madrid, Spain Tel: 091-504 Fax: 091-504 Succursale France Tel: 01-30-67 Fax: 01-30-67
Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
J02.4
Data Sheet U16277EJ1V0DS
µ3'$
Exporting this product equipment that includes this product require governmental license from U.S.A. some countries because this product utilizes technologies limited export control regulations U.S.A.
information this document current July, 2002. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

VR4181A

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