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VR4120

Catalog Datasheet Type PDF Document Tags
Abstract: Features VR4121 VR4121 VR4122 VR4122 CPU Core VR4120 VR4120A Max. Pipeline Clock 168 MHz 180 MHz , ultra-low-power-consuming VR4120 CPU core based on advanced 0.18 µm technology. The VR4120 CPU offers excellent performance , integrated, low-cost system on a chip. Features · · · · · · · VR4120 CPU CORE MIPS I, II, III , Driver 2 CLK PLL FIR/SI RTC SIU 7 Host Bridge VR4120 Core 180 MHz ICU DCHE , VR4120 core with a 64-bit architecture able to execute MIPS I, II, II or 16-bit MIPS 16 instruction sets ... Original
datasheet

4 pages,
42.48 Kb

VRC4173 VR4121 VR4100 U14327EJ1V0UM00 U14327E VR4122 VR4120 VR4122 abstract
datasheet frame
Abstract: µPD98453 PD98453 PRELIMINARY Network Processor Features · Includes high performance MIPS based 64-bit RISC processor VR4120 TM · Supports operation conforming to the USB Communication Device Class Specification · Can perform RTOS and network middleware (M/W) on · Can directly , > VR4120 core UTOPIA Level 2 I/F AD USB USB ATM Ethernet , ) VR4120 is a trademark of NEC Corporation. Ethernet is a trademark of XEROX Corporation USA. The export ... Original
datasheet

2 pages,
34.13 Kb

VR4120 s14250ej1v0pf00 pots telephone 10 M7A transistor M7A M7A transistor adsl splitter circuit diagram PD98453 IEEE802 PD98453 abstract
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Abstract: , nicknamed Korva, is a MIPS based 64-bit VR4120 RISC CPU controller for networking applications. The device , high-performance MIPS compatible 64-bit VR4120 RISC processor core · Supported by RTOS and network middleware · , Controller SDRAM USB Controller JTAG Boundary Scan PROM Flash CPU Core VR4120 ® Communication U n l i m i t e d Functional Block Description Main CPU The VR4120TM RISC , /PMD ATU-C POTS Splitter ADSL AFE ADSL Line ADSL TC/PMD Mux/ Demux CPU VR4120 ... Original
datasheet

4 pages,
64.03 Kb

VR4120 VR4100 U14948 RTOS-98501-VXWORKS NEC VR4100 adsl splitter dslam circuit diagram ATM25 NEC emma ATM-25 adsl modem board nec emma jtag PD98501 PD98501 abstract
datasheet frame
Abstract: , low-cost system on a chip. The microprocessor uses the ultra-low-power-consuming VR4120TM CPU core based on advanced 0.18-micron technology. The VR4120 CPU has an optimized five-stage pipeline, 32-KB 32-KB , DSU Serial Interface Unit Interrupt Control Unit VR4120 Core 150/180 MHz N-Wire /JTAG , Interrupt Control Memory Control DMA Control Interval Timer /RTC VR4120 CPU Core Power , process V R 4121 VR4120 168 MHz Instruction: 16 KB Data: 8 KB 210 Dhrystone MIPS MIPS I, II, III ... Original
datasheet

4 pages,
74.18 Kb

VR4122 VR4121 VR4120 VR4100 MIPS32 MIPS16 MIPS data bus VRC4173 VR4122TM PD30122 VR4120TM 32-KB 16-KB VR4121TM VR4122TM abstract
datasheet frame
Abstract: first processor that uses the ultra-low power consumption VR4120TM CPU core based on advanced 0.25 µm , systems. Features · · · · · · · · VR4120 MIPS RISC CPU core MIPS I, II, III and MIPS 16 , Real-Time Clock General-Purpose I/O Unit Graphics Controller Direct Memory Access Unit VR4120 , Driver Functional Block Description CPU The VR4121 VR4121 CPU is a powerful VR4120 core with a 64-bit , Bus Control Unit The bus control unit (BCU) transfers data between the VR4120 core and on-chip ... Original
datasheet

4 pages,
53.41 Kb

VRC4172 VR4120 VR4111 NEC AMC EDO RAM VR4121 VR4121 mips VR4121 abstract
datasheet frame
Abstract: processor that uses the ultra-low power consumption VR4120TM CPU core based on advanced 0.25 µm technology. , · · · · VR4120 MIPS RISC CPU core MIPS I, II, III and MIPS 16 instruction set Performance up , Direct Memory Access Unit VR4120 CPU 131 MHz, 168 MHz 16 Kbytes Instruction Cache 8 Kbytes Data , VR4120 core with a 64-bit architecture that executes 32-bit MIPS I, II, III or 16-bit MIPS 16 , between the VR4120 core and on-chip peripherals. It controls external circuits, such as the LCD and ... Original
datasheet

4 pages,
57.58 Kb

FPBGA NEC 1999 VRC4171A VR4111 VR4121 VR4120 VR4121 mips VR4121 abstract
datasheet frame
Abstract: VR4120TM CPU core based on advanced 0.25-micron technology. The VR4120 CPU has an optimized five-stage , Real-Time Clock LCD Controller VR4120 CPU (131, 168 MHz) 16K Instruction Cache 8K Data Cache , Conv. VR4120 168 MHz IR LED Clock Generator Touch Panel Control A/D Converter GPIO , 200 mW 224-pin FPBGA V R 4121 VR4120 168 MHz Instruction: 16KB/Data: 8KB 224 Dhrystone MIPS ... Original
datasheet

4 pages,
52.86 Kb

1683C VR4121 mips VR4111 VR4120 VR4121 VR4102 mips16 instruction set VR4111 modem MIPS16 VR4111 modem VR4121 VR4121TM PD30121 VR4120TM 16-KB VR4121TM abstract
datasheet frame
Abstract: Laki Communication Controller µPD98503 PD98503 Product Letter Description Laki is a new member of NEC's high performance Communication Controller product family. It is based on the VR4120 64-bit RISC CPU core, a member of the industry standard MIPS CPU family. With its 16 Kbytes instruction and 8 , suite. Features · Includes high performance MIPS based 64-bit RISC processor VR4120A running at , (Europe) GmbH, Printed in Germany, November 2000 Document No. S15149EE1V0PL00 S15149EE1V0PL00 VR Series and VR4120 are ... Original
datasheet

2 pages,
32.16 Kb

VR4120 PD98503 PD98503 abstract
datasheet frame
Abstract: Controller) is a high-performance access network processor featuring single-chip integration of the VR4120 , Sections 1 to 5 below describe these functional blocks. и On-chip VR4120 advanced 64-bit MIPS(r , controller VR4120 RISC processor core N-wire PROM/Flash SDRAM 3.3V MII System controller , Use of 0.25-...m CMOS process technology и 2.5-V or 3.3-V supply voltage и 500-pin tape BGA 1. VR4120 RISC processor core block The VR4120 core advanced 64-bit RISC processor supports a real-time OS and ... Original
datasheet

6 pages,
70.02 Kb

nec prom adsl hybrid filter D9845 PD98451/ PD98452/ PD98453 PD98451/ abstract
datasheet frame
Abstract: / Real-Time Clock VR4120 CPU Core Power Management GPIO /LED Serial Interface D/A , www.necel.com © 1999 NEC Electronics Inc. NEC, VR Series, VR4100 VR4100, VR4111 VR4111, VR4120, VR4121 VR4121, VR4122 VR4122, and VRC4173 VRC4173 ... Original
datasheet

4 pages,
103.53 Kb

AC97 UC1H usb vrc VR4100 VR4111 VR4120 VR4121 VR4122 nec vr series VRC4173 VRC4173TM VR4122TM VRC4173TM abstract
datasheet frame
Abstract: Communication Controller Markham µPD98502 PD98502 Product Letter Description Markham (µPD98502 PD98502) is a new member of NEC's high performance Communication Controller product family which is characterised by a variety of integrated communication interfaces. The chip is based on the VR4120 64-bit RISC CPU core, a member of the industry standard MIPS CPU family. With its 16 Kbyte instruction cache and , 2001 Document No. S15619EE1V0PL00 S15619EE1V0PL00 VR Series and VR4120 are trademarks of NEC Corporation. MIPS is a ... Original
datasheet

2 pages,
35.94 Kb

VR4120 NEC SRAM PD98502 PD98502 abstract
datasheet frame

Datasheet Content (non pdf)

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VR4121 VR4121 VR4121 VR4121 Low power consumption Device Int. Bus [Bit] Ext. Bus [Bit] No. of Instructions Core ROM [kB] ROM Type Cache [kB] Max. Clock [MHz] Speed Versions DMips Tmin [°C] Tmax [°C] I/O LCD ADC DAC DMA ch INT ch ext VDD [V] Power cons. [mW] UART Peripherals Timer Channels Total Watchdog Pack1 PWM Companionchip I-Cache D-Cache Cache Architecture uPD30121 uPD30121 uPD30121 uPD30121 32 32 MIPS III (no FP) + MIPS16 MIPS16 MIPS16 MIPS16 VR4120 0 NA 16/8 167 131/168 193 0 70 50 NO 8*10bit 1
www.datasheetarchive.com/files/nec/micros/series/vr4121.htm
NEC 16/09/1999 12.35 Kb HTM vr4121.htm
VR4122 VR4122 VR4122 VR4122 Low power consumption Device Int. Bus [Bit] Ext. Bus [Bit] No. of Instructions Core ROM [kB] ROM Type Cache [kB] Max. Clock [MHz] Speed Versions DMips Tmin [°C] Tmax [°C] I/O ADC DAC DMA ch INT ch ext VDD [V] Power cons. [mW] UART Peripherals Timer Channels Total Watchdog Pack1 Companionchip I-Cache D-Cache Cache Architecture uPD30122 uPD30122 uPD30122 uPD30122 32 32 MIPS III (no FP) + MIPS16 MIPS16 MIPS16 MIPS16 VR4120 0 NA 32/16 180 168/180 207 -10 70 _ NO NO 4 _ 3.3/1.8 350 2
www.datasheetarchive.com/files/nec/micros/series/vr4122.htm
NEC 16/09/1999 9.4 Kb HTM vr4122.htm
(VR4120 equivalent) Internal 64-bit data processing Optimized 6-stage pipeline
www.datasheetarchive.com/files/nec/micros/product/upd30121.htm
NEC 18/12/1998 15.11 Kb HTM upd30121.htm
No abstract text available
www.datasheetarchive.com/download/42652172-393173ZC/mplabalc30v2_05.tgz
Microchip 09/11/2006 11568.47 Kb TGZ mplabalc30v2_05.tgz
No abstract text available
www.datasheetarchive.com/download/42652172-393173ZC/mplabalc30v2_05.tgz
Microchip 09/11/2006 11568.47 Kb TGZ mplabalc30v2_05.tgz
No abstract text available
www.datasheetarchive.com/download/42652172-393173ZC/mplabalc30v2_05.tgz
Microchip 09/11/2006 11568.47 Kb TGZ mplabalc30v2_05.tgz
No abstract text available
www.datasheetarchive.com/download/42652172-393173ZC/mplabalc30v2_05.tgz
Microchip 09/11/2006 11568.47 Kb TGZ mplabalc30v2_05.tgz
No abstract text available
www.datasheetarchive.com/download/42652172-393173ZC/mplabalc30v2_05.tgz
Microchip 09/11/2006 11568.47 Kb TGZ mplabalc30v2_05.tgz
No abstract text available
www.datasheetarchive.com/download/42652172-393173ZC/mplabalc30v2_05.tgz
Microchip 09/11/2006 11568.47 Kb TGZ mplabalc30v2_05.tgz
No abstract text available
www.datasheetarchive.com/download/79262054-393174ZC/mplabc30v2_05.tgz
Microchip 09/11/2006 27045.95 Kb TGZ mplabc30v2_05.tgz