V53C404H
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V53C404H - V53C404H
V53C404H FAST PAGE MODE CMOS DYNAMIC
PRELIMINARY V53C404H
Max. Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
Features
4-bit organization access time: power dissipation Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh Refresh Interval V53C404H 1,024 cycles/16 Available 26/20-pin Single Power Supply Interface Fast Page Mode operation
Description
V53C404H 1,048,576 highperformance CMOS dynamic random access memory. V53C404H offers Page mode operation. address, input capacitances reduced quarter when DRAM used construct same memory density. V53C404H symmetric address accepts 1,024 cycle 16ms interval. inputs compatible. Fast Page Mode operation allows random access 1,024 bits, within page, with cycle times short 23ns. These features make V53C404H ideally suited wide variety high performance computer systems peripheral applications.
Device Usage Chart
Operating Temperature Range Package Outline Access Time (ns) Power Std. Temperature Mark Blank
V53C404H Rev. April 1996
V53C404H
FAMILY
DEVICE
SPEED TEMP. RAC) PWR. BLANK (0°C 70°C) BLANK (NORMAL)
(SOJ)
Description
Pkg.
Count
26/20
26/20 Lead Package CONFIGURATION View
I/O1 I/O2 I/O4 I/O3
Names
A0-A9 I/O0-I/O4 Address Inputs Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output Supply Supply Connect
V53C404H Rev. April 1996
Absolute Maximum Ratings*
Ambient Temperature Under Bias -10°C +80°C Storage Temperature (plastic) -55°C +125°C Voltage Relative -1.0 +7.0 Data Output Current Power Dissipation.
*Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
V53C404H
Capacitance*
25°C, 10%, Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, Data Input/Output Typ. Max. Unit
Note: Capacitance sampled 100% tested
Block Diagram
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
DATA COLUMN DECODERS
Y0-Y9
BUFFER
SENSE AMPLIFIERS
1024
REFRESH COUNTER
ADDRESS BUFFERS PREDECODERS
DECODERS
1024
MEMORY ARRAY
V53C404H Rev. April 1996
Operating Characteristics (1-2)
70°C, 10%, unless otherwise specified. V53C404H Symbol Parameter Access Time Min.
V53C404H
Typ.
Max.
Unit
Test Conditions
Notes
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Supply Current, Operating
VOUT RAS,
ICC1
RAS, other inputs (min.)
ICC2
Supply Current, Standby Supply Current, RAS-Only Refresh
ICC3
(min.)
ICC4
Supply Current, Page Mode Operation
Minimum Cycle
ICC5
Supply Current, Standby, Output Enabled other inputs Supply Current, CMOS Standby
RAS=VIH CAS=V
ICC6
VCC- other inputs -5.0
Input Voltage Input High Voltage Output Voltage Output High Voltage
VCC+1
V53C404H Rev. April 1996
Characteristics
70°C, ±10%, unless otherwise noted Test conditions, input pulse levels
JEDEC Symbol tRL1RH1 tRL2RL2 tRH2RL2 tRL1CH1 tCL1CH1 tRL1CL1 tWH2CL2 tAVRL2 tRL1AX tAVCL2 tCL1AX Symbol tRAS tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH Parameter Pulse Width Read Write Cycle Time Precharge Time Hold Time Pulse Width Delay Read Command Setup Time Address Setup Time Address Hold Time Column Address Setup Time Column Address Hold Time Hold Time (Read Cycle) Precharge Time Read Command Hold Time Referenced Read Command Hold Time Referenced Hold Time Referenced Access Time from Access Time from Access Time from Access Time from Column Address Low-Z Output High-Z Output
V53C404H
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Notes
tCL1RH1(R) tRSH tCH2RL2 tCH2WX tCRP tRCH
tRH2WX
tRRH
tOEL1RH2 tGL1QV tCL1QV tRL1QV tAVQV tCL1QX tCH2QZ tRL1AX tRL1AV
tROH tOAC tCAC tRAC tCAA tRAD
Column Address Hold Time from Column Address Delay Time
tCL1RH1(W) tRSH tWL1CH1 tWL1CL2 tCL1WH1 tWL1WH1 tCWL tWCS tWCH
Hold Time Write Cycle Write Command Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width
V53C404H Rev. April 1996
Characteristics (Cont'd)
JEDEC Symbol tRL1WH1 tWL1RH1 tDVWL2 tWL1DX tWL1GL2 tGH2DX tRL2RL2 (RMW) tRL1RH1 (RMW) tCL1WL2 tRL1WL2 tCL1CH1 tAVWL2 tCL2CL2 tCH2CL2 tAVRH1 tCH2QV tRL1DX tCL1RL2 tRH2CL2 tRL1CH1 tCL2CL2 (RMW) tCWD tRWD tCRW tAWD tCAR tCAP tDHR tCSR tRPC tCHR tPCM tREF tRRW Read-Modify-Write Cycle Pulse Width Delay Delay ReadModify-Write Cycle Pulse Width (RMW) Col. Address Delay Fast Page Mode Read Write Cycle Time Precharge Time Column Address Setup Time Access Time from Column Precharge Data Hold Time Referenced Setup Time CAS-beforeRAS Refresh Precharge Time Hold Time CAS-beforeRAS Refresh Fast Page Mode Read-ModifyWrite Cycle Time Transition Time (Rise Fall) Refresh Interval (512 Cycles) Symbol tWCR tRWL tWOH tOED tRWC Parameter Write Command Hold Time from
V53C404H
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Notes
Write Command Lead Time Data Setup Time Data Hold Time Write Hold Time Data Delay Time Read-Modify-Write Cycle Time
V53C404H Rev. April 1996
Notes:
V53C404H
dependent output loading when device output selected. Specified (max.) measured with output open. dependent upon number address transitions. Specified (max.) measured with maximum transitions address cycle Fast Page Mode. Specified (min.) steady state operating. During transitions, (min.) undershoot -1.0 period exceed parameters measured with (min.) (max.) VDD. tRCD (max.) specified reference only. Operation within tRCD (max.) limits insures that tRAC (max.) tCAA (max.) met. tRCD greater than specified tRCD (max.), access time controlled tCAA tCAC. Either tRRH tRCH must satisified Read Cycle occur. Measured with load equivalent inputs Access time determined longest tCAA, tCAC tCAP. Assumes that tRAD tRAD (max.). tRAD greater than tRAD (max.), tRAC will increase amount that tRAD exceeds tRAD (max.). Assumes that tRCD tRCD (max.). tRCD greater than (max.), tRAC will increase amount that tRCD exceeds tRCD (max.). Assumes that tRAD tRAD (max.). Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only. tRAD greater than specified tRAD (max.) limit, access time controlled tCAA tCAC. tWCS, tRWD tAWD tCWD restrictive operating parameters. tWCS (min.) must satisfied Early Write Cycle. referenced latter occurrence measured between (min.) (max.). AC-measurements assume Assumes three-state test load Thevenin equivalent). initial pause RAS-containing cycles required when exiting extended period bias without clocks. extended period time without clocks defined that exceeds specified Refresh Interval.
V53C404H Rev. April 1996
Waveforms Read Cycle
(13) ADDRESS ADDRESS (24) (10) (11) (R)(12) (23)
V53C404H
(13)
COLUMN ADDRESS (44) (14) (15)
(16) (20) (17) (18) (22) VALID DATA-OUT (21)
4092
(19)
(22)
Waveforms Early Write Cycle
(13) ADDRESS ADDRESS (24) (26) (30) (31) (46) (32) (33) VALID DATA-IN HIGH-Z
4092
(23)
(W)(25)
(13)
(44) (11) (10)
COLUMN ADDRESS (28) (29) (27)
Don't Care
Undefined
V53C404H Rev. April 1996
Waveforms OE-Controlled Write Cycle
(13) (24) (44) (11) (10) (W)(12) (23)
V53C404H
(13)
ADDRESS
ADDRESS
COLUMN ADDRESS (26) (31) (29)
(34) (35) (33) (32) VALID DATA-IN
4092
Waveforms Read-Modify-Write Cycle
(36) tRRW (37) (13) ADDRESS ADDRESS (24) (39) (35) (18) (19) (21)
Don't Care Undefined
(23)
(W)(25) (40) (10) COLUMN ADDRESS (41) (38) (31) (26)
(13)
(11)
(29)
(20) (17)
(33) (22) (32)
VALID DATA-OUT
VALID DATA-IN
4092
V53C404H Rev. April 1996
Waveforms Page Mode Read Cycle
(23) (13) (10) (11) COLUMN ADDRESS (14) (11) (20) (17) (19) (18) (21) (18) (44) (11) COLUMN ADDRESS (42) (43) (R)(12) (13)
V53C404H
ADDRESS
(10) ADDRESS
COLUMN ADDRESS
(14)
(45) (20) (17) (15)
(18)
(22) (22) (22) VALID DATA
(22) VALID DATA VALID DATA
4092
Waveforms Page Mode Write Cycle
(23) (13) ADDRESS (24) (27) (29)
COLUMN ADDRESS
(42) (43)
(W)(25)
(13)
(10)
COLUMN ADDRESS
(11)
(11)
(10)
(44) (11)
COLUMN ADDRESS
(26)
(28)
(27)
(26)
(28) (29)
(27)
(26) (31) (28) (29)
(32) (33)
VALID DATA
(32)
(33)
VALID DATA
(32)
(33)
VALID DATA
OPEN
OPEN 4092
Don't Care
V53C404H Rev. April 1996
Undefined
Waveforms Page Mode Read-Write Cycle
V53C404H
(50)
(W)(25) (13)
(43)
(24) (10) (10)
COLUMN ADDRESS
(11)
COLUMN ADDRESS
(11)
(10)
(44) (11)
COLUMN ADDRESS
ADDRESS
(39) (38)
(26)
(38) (26)
(38) (31) (26)
(20) (17)
(41)
(41) (29) (17)
(41) (17) (29) (29)
(35) (18) (19)
(20)
(43)
(35) (18) (33)
(43) (20)
(22)
(22)
(32) I/OH I/OL (21)
(33) (32)
(35) (18) (22) (33) (32)
4092
Waveforms RAS-Only Refresh Cycle
(13) ADDRESS NOTE:
4092
Don't care
Don't Care
Undefined
V53C404H Rev. April 1996
Waveforms CAS-before-RAS Refresh Counter Test Cycle
(47) UCAS, LCAS READ CYCLE (16) (17) (21) WRITE CYCLE
(32)
V53C404H
(49)
(43)
(W)(25)
ADDRESS
(15) (14)
(22) (22) (31) (26)
(27)
(28)
(33)
4092
Waveforms CAS-before-RAS Refresh Cycle
(43) (47) (22) NOTE: Don't care
Don't Care Undefined
4092
(48) (49)
V53C404H Rev. April 1996
Waveforms Hidden Refresh Cycle (Read)
(13) UCAS, LCAS ADDRESS (20) (17) (18) (21) (19) VALID DATA (22) (22)
V53C404H
(23)
(R)(12)
(49)
(13)
(24) (10) (11)
COLUMN ADDRESS
(15)
4092
Waveforms Hidden Refresh Cycle (Write)
(13) UCAS, LCAS ADDRESS (32) (33)
VALID DATA-IN
(23)
(12)
(49)
(13)
(24) (10) (11)
COLUMN ADDRESS
(27)
(28)
(46)
Don't Care
4092
Undefined
V53C404H Rev. April 1996
Functional Description
V53C404H CMOS dynamic optimized high data bandwidth, power applications. functionally similar traditional dynamic RAM. V53C404H reads writes data multiplexing 20-bit address into 10-bit 10-bit column address. address latched Address Strobe (RAS). column address "flows through" internal address buffer latched Column Address Strobe (CAS). Because access time primarily dependent valid column address rather than precise time that edge occurs, delay time from little effect access time.
V53C404H
Extended Data Output Page Mode
Fast Page Mode operation permits 1024 columns within selected device randomly accessed high data rate. Maintaining while performing successive cycles retains address internally eliminates need reapply each cycle. column address buffer acts transparent flow-through latch while high. Thus, access begins from occurrence valid column address rather than from falling edge CAS, eliminating tASC from critical timing path. latches address into column address buffer. During Fast Page Mode operation, Read, Write, ReadModify-Write Read-Write-Read cycles possible random addresses within row. Following initial entry cycle into Hyper Page Mode, access tCAA tCAP controlled. column address valid prior rising edge CAS, access time referenced rising edge specified CAP. column address valid after rising edge, access timed from occurrence valid address specified CAA. both cases, falling edge latches address enables output. Fast Page Mode provides sustained data rate applications that require high bandwidth such bit-mapped graphics highspeed signal processing. following equation used calculate maximum data rate: 1024 Data Rate 1023
Memory Cycle
memory cycle initiated bringing low. memory cycle, once initiated, must ended aborted before minimum tRAS time expired. This ensures proper device operation data integrity. cycle must initiated until minimum precharge time tRP/t elapsed.
Read Cycle
Read cycle performed holding Write Enable (WE) signal High during RAS/CAS operation. column address must held minimum specified tAR. Data becomes valid only when tOAC, tRAC, tCAA tCAC satisifed. result, access time dependent timing relationships between these parameters. example, access time limited tCAA when tRAC, tCAC tOAC satisfied.
Write Cycle
Write Cycle performed taking during operation. column address latched CAS. Write Cycle controlled controlled depending whether falls later. Consequently, input data must valid before falling edge CAS, whichever occurs last. CAScontrolled Write Cycle, when leading edge occurs prior transition, data pins will High-Z state beginning Write function. Ending Write with will maintain output High-Z state. controlled Write Cycle, must high state tOED must satisfied.
Data Output Operation
V53C404H Input/Output controlled CAS, RAS. transition enables transfer data from selected address Memory Array. high transition disables data transfer latches output data output enabled. After memory cycle initiated with transition, transition level enables internal path. high transition high level disables path output driver enabled. transition while high effect data path output drivers. output drivers, when otherwise
V53C404H Rev. April 1996
enabled, disabled holding high. signal effect data stored output latches. level also disable output drivers when low. During Write cycle, goes time relationship that would normally cause outputs active, necessary disable output drivers prior transition allow Data Setup Time (tDS) satisfied.
V53C404H
Table V53C404H Data Output
Operation Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles Fast Page Mode Read Fast Page Mode Write Cycle (Early Write) Fast Page Mode ReadModify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
State
Data from Addressed Memory Cell High-Z Controlled. High High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains previous cycle High-Z
Power-On
After application supply, initial pause required followed minimum initialization cycles (any combination cycles containing clock). Eight initialization cycles required after extended periods bias without clocks (greater than Refresh Interval). During Power-On, current requirement V53C8256H dependent input levels CAS. during Power-On, device will into active cycle will exhibit current transients. recommended that track with held valid during Power-On avoid current surges.
V53C404H Rev. April 1996
Package Diagram 26/20-Pin
V53C404H
0.332/0.342 0.296/0.304 0.667/0.683 0.125/0.135
0.082/0.093 0.018 Typ. 0.025 Min. 0.255/0.275
0.028 Typ.
0.05 Typ.
Unit: Inch
4/96 Copyright 1996, MOSEL VITELIC Inc. Printed U.S.A.
information this document subject change without notice. MOSEL VITELIC makes commitment update keep current information contained this document. part this document copied reproduced form means without prior written consent MOSEL VITELIC.
MOSEL VITELIC subjects products normal quality control sampling techniques which intended provide assurance high quality products suitable usual commercial applications. MOSEL VITELIC does testing appropriate provide 100% product quality assurance does assume liability consequential incidental arising from products. such products used applications which personal injury might occur from failure, purchaser must quality assurance testing appropriate such applications.
V53C404H Rev. April 1996
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