V53C404D
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V53C404D - V53C404D
V53C404D HIGH PERFORMANCE, POWER FAST PAGE MODE CMOS DYNAMIC
V53C404D
HIGH PERFORMANCE V53C404D
Max. Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
Features
Description
V53C404D high speed 1,048,576x4 CMOS dynamic random access memory. V53C404D offers combination features: Fast Page Mode high data bandwidth, fast usable speed, CMOS standby current. inputs outputs compatible. Input output capacitances significantly lowered allow increased system performance. Fast Page Mode operation allows random access 1024 (x4) bits within with cycle times short Because static circuitry, clock critical timing path. flow-through column address latches allow address pipelining while relaxing many critical system timing requirements fast usable speed. These features make V53C404D ideally suited main memories, graphics, digital signal processing high performance computing systems.
4-bit organization access time: 60,70,80,100 power dissipation V53C404D-10 Operating Current max. Standby Current max. CMOS Standby Current V53C404D max. Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability Refresh Interval V53C404D 1024 cycles/16ms On-chip substrate bias generator Fast Page Mode sustained data rate greater than Available 26/20 package (300 mil)
Device Usage Chart
Operating Temperature Range Package Outline Access Time (ns) Power Std. Temperature Mark Blank
V53C404D Rev. August 1995
V53C404D
FAMILY
DEVICE (SOJ)
SPEED
TEMP. PWR. BLANK (0°C 70°C) BLANK (NORMAL)
Description
Pkg.
Count
26/20
(100
26/20 Lead Package CONFIGURATION
View
I/O1 I/O2 I/O4 I/O3
Names
A0-A9 I/O1-I/O Address Inputs Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output Supply Supply Connect
V53C404BK
Absolute Maximum Ratings*
Ambient Temperature Under Bias -10°C +80°C Storage Temperature (plastic) -55°C +125°C Voltage Relative -1.0 +7.0 Data Output Current Power Dissipation
*Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
Capacitance*
25°C, 10%,
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, Data Input/Output Typ. Max. Unit
Note: Capacitance sampled 100% tested
V53C404D Rev. August 1995
Block Diagram
V53C404D
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
DATA COLUMN DECODERS
BUFFER
SENSE AMPLIFIERS
1024
REFRESH COUNTER
ADDRESS BUFFERS PREDECODERS
DECODER
1024
MEMORY ARRAY
1486
V53C404D Rev. August 1995
Operating Characteristics (1-2)
70°C, 10%, unless otherwise specified. V53C404D Symbol Parameter
IDD1 Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Supply Current, Operating IDD2 IDD3 Supply Current, Standby Supply Current, RAS-Only Refresh IDD4 Supply Current, Fast Page Mode Operation IDD5 IDD6 Supply Current, Standby, Output Enabled Supply Current, CMOS Standby
V53C404D
Access Time
Min.
Max.
Unit Test Conditions
VOUT RAS, (min.)
Notes
RAS, other inputs (min.)
Minimum Cycle
RAS=VIH, CAS=VIL other inputs VDD- 0.2V other inputs
L-Version
IDD7 Battery Back-up Data Retention Current (Only V53C404DL) Input Voltage Input High Voltage Output Voltage Output High Voltage -1.0
CAS-Before-RAS Refresh cycle CMOS clock levels
VDD+1
V53C404D Rev. August 1995
Characteristics
70°C, ±10%, unless otherwise noted Test Conditions, input pulse levels
V53C404D
Notes
JEDEC Symbol
tRL1RH1 tRL2RL tRH2RL2 tRL1CH1 tCL1CH1 tRL1CL1 tWH2CL2 tAVRL2 tRL1AX tAVCL2 tCL1AX tCL1RH1(R) tCH2RL2 tCH2WX
Symbol
tRAS tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH(R) tCRP tRCH
Parameter
Pulse Width Read Write Cycle Time Precharge Time Hold Time Pulse Width Delay Read Command Setup Time Address Setup Time Address Hold Time Column Address Setup Time Column Address Hold Time Hold Time (Read Cycle) Precharge Time Read Command Hold Time (Referenced CAS) Read Command Hold Time (Referenced RAS) Hold Time Referenced Access Time from Access Time from Access Time from Access Time from Column Address Low-Z Output Low-Z Output
Min. Max. Min. Max. Min. Max. Min. Max. Unit
100K 100K 100K 100K
tRH2WX
tRRH
tOEL1RH2 tGL1QV tCL1QV tRL1QV tAVQV tCL1QX tCH2QZ
tROH tOAC tCAC tRAC tCAA
6,8,9 6,7,10
V53C404D Rev. August 1995
Characteristics (Cont'd.)
V53C404D
Notes
JEDEC Symbol
RL1AX RL1AV CL1RH1(W) WL1CH1 WL1CL2 CL1WH1 WL1WH1 RL1WH1 WL1RH1 DVWL2 WL1DX WLG1GL2 GH2DX RL2RL2 (RMW) RL1RH1 (RMW) CL1WL2 RL1WL2
Symbol
RSH(W) tCWL
Parameter
Column Address Hold Time from Column Address Delay Time Hold Time Write Cycle Write Command Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width Write Command Hold Time from Write Command Lead Time Data Setup Time Data Hold Time Write Hold Time Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle Pulse Width Delay Delay Read-Modify-Write Cycle Pulse Width (RMW) Column Address Delay Fast Page Mode Read Write Cycle Time Precharge Time Column Address Setup Time Access Time from Column Precharge
Min. Max. Min. Max. Min. Max. Min. Max. Unit
12,13
CL1CH1 AVWL2 CL2CL2 CH2CL2 AVRH1 CH2QV
V53C404D Rev. August 1995
Characteristics (Cont'd.)
V53C404D
Notes
JEDEC Symbol
tRL1DX2 tCL1RL2
Symbol
tDHR tCSR
Parameter
Data Hold Time Referenced Setup Time CAS-before-RAS Refresh Precharge Time Hold Time CAS-before-RAS Refresh Fast Page Mode ReadModify-Write Cycle Time precharge time (CAS-Before-RAS Refresh cycle) Hold Time from (CAS-Before-RAS Refresh Cycle) set-up Time (Test Mode) hold Time (Test Mode) Transition Time (Rise Fall) Refresh Interval (1024 Cycles) Refresh Interval Power Version Precharge Delay Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRH2CL2 tRL1CH1
tRPC tCHR
tCL2CL2 (RMW)
tPCM
tWH2RL2
tWRP
tRL1WL2
tWRH
tWL1RL2 tRL1WH1
tWSR tWHR tREF tREF tCPWD
V53C404D Rev. August 1995
Notes:
V53C404D
dependent output loading when device output selected. Specified (max.) measured with output open. dependent upon number address transitions. Specified (max.) measured with maximum transitions address cycle Fast Page Mode. Specified (min.) steady state operating. During transitions, (min.) undershoot -1.0 period exceed parameters measured with (min.) (max.) VDD. tRCD (max.) specified reference only. Operation within tRCD (max.) limits insures that tRAC (max.) tCAA (max.) met. tRCD greater than specified tRCD (max.), access time controlled tCAA tCAC. Either tRRH tRCH must satisified Read Cycle occur. Measured with load equivalent inputs Access time determined longest tCAA, tCAC tCAP. Assumes that tRAD tRAD (max.). tRAD greater than tRAD (max.), tRAC will increase amount that tRAD exceeds tRAD (max.). Assumes that tRCD tRCD (max.). tRCD greater than tRCD (max.), tRAC will increase amount that tRCD exceeds tRCD (max.). Assumes that tRAD tRAD (max.). Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only. tRAD greater than specified (max.) limit, access time controlled tCAA tCAC. tWCS, tRWD, tAWD tCWD restrictive operating parameters. tWCS (min.) must satisfied Early Write Cycle. referenced latter occurrence measured between (min.) (max.). AC-measurements assume Assumes three-state test load Thevenin equivalent). initial pause RAS-containing cycles required when exiting extended period bias without clocks. extended period time without clocks defined that exceeds specified Refresh Interval.
V53C404D Rev. August 1995
Waveforms Read Cycle
(13) ADDRESS ADDRESS (24) (10) COLUMN ADDRESS (44) (20) (18) (19) (21) (22) VALID DATA-OUT (17) (16) (15) (11) (R)(12) (23)
V53C404D
(13)
(14)
(22)
Waveforms Early Write Cycle
(13) ADDRESS ADDRESS (24) (26) (30) (31) (46) (32) (33) VALID DATA-IN HIGH-Z
(23)
(W)(25)
(13)
(44) (11) (10)
COLUMN ADDRESS (28) (29) (27)
V53C404D Rev. August 1995
Waveforms OE-Controlled Write Cycle
(13) (24) (44) (11) (10) (W)(12) (23)
V53C404D
(13)
ADDRESS
ADDRESS
COLUMN ADDRESS (26) (31) (29)
(34) (35) (33) (32) VALID DATA-IN
Waveforms Read-Modify-Write Cycle
(36) tRRW (37) (13) ADDRESS ADDRESS (24) (39) (35) (18) (19) (21)
V53C404D Rev. August 1995
(23)
(W)(25) (40) (10) COLUMN ADDRESS (41) (38) (31) (26)
(13)
(11)
(29)
(20) (17)
(33) (22) (32)
VALID DATA-OUT
VALID DATA-IN
Waveforms Fast Page Mode Read Cycle
(13) (10) (11) COLUMN ADDRESS COLUMN ADDRESS (14) (11) COLUMN ADDRESS (44) (42) (43) (R)(12) (23)
V53C404D
(13)
ADDRESS
(10) ADDRESS
(11)
(14)
(20) (17) (45) (17) (20) (17) (15)
(22) (19) (18) (21) (18) (22) (21) VALID DATA (21) (22) (22) VALID DATA VALID DATA
(18)
(22) (22)
Waveforms Fast Page Mode Write Cycle
(23) (13) ADDRESS (24) (27) (29) (32)
VALID DATA COLUMN ADDRESS
(42) (43)
(W)(25) (13)
(44) (10) (11)
COLUMN ADDRESS
(10) (11)
COLUMN ADDRESS
(11)
(26) (27) (28)
(26) (27) (28) (29)
(26) (31) (28) (29)
(32) (33)
OPEN VALID DATA
(32) (33)
VALID DATA
(33)
OPEN
V53C404D Rev. August 1995
Waveforms Fast Page Mode Read-Write Cycle
V53C404D
(50) (43)
(W)(25) (13)
(24) (10) (10) (11)
COLUMN ADDRESS COLUMN ADDRESS
(44) (10) (11)
COLUMN ADDRESS
(11)
ADDRESS
(39) (38)
CPWD (58) (38) (26) (26)
(38) (31) (26)
(41) (20) (17)
(41) (29) (17)
(41) (29) (17) (29)
(43) (35) (18) (19) (20) (35) (18) (22)
(43) (20) (35) (18) (22) (33) (32)
(22) (33) (33) (32)
(32) I/OH I/OL (21)
(21)
(21)
Waveforms RAS-Only Refresh Cycle
(13) ADDRESS NOTE:
DATA-IN ADD.
Don't care
V53C404D Rev. August 1995
Waveforms CAS-before-RAS Refresh Cycle
(43) (47) (51) (52) (48) (49)
V53C404D
(22)
NOTE: Don't care
1486
Waveforms Hidden Refresh Cycle (Read)
(13) ADDRESS (20) (17) (18) (21) (19) VALID DATA
1486
(23)
(R)(12)
(49)
(13)
(24) (10)
COLUMN ADDRESS
(51) (11)
(52)
(15)
(22) (22)
V53C404D Rev. August 1995
Waveforms Hidden Refresh Cycle (Write)
(13) ADDRESS (32) (33)
VALID DATA-IN
V53C404D
(23)
(12) (51) (24) (10) (11)
COLUMN ADDRESS
(49)
(13)
(52)
(27)
(28) (29)
(46)
1486
Test Mode Initiation Cycle
tRAS tCSR (47) (43) tCHR (49)
tWSR (53)
tWHR (54)
(22)
1486
V53C404D Rev. August 1995
Waveforms CAS-before-RAS Refresh Counter Test Cycle
(47) READ CYCLE (51) (21) WRITE CYCLE
(32)
V53C404D
(49)
(43)
(W)(25)
(10) (11)
ADDRESS
COLUMN ADDRESS
(52)
(15) (14)
(16) (17)
(22) (22) DOUT (31) (26)
(52)
(27)
(28)
(51)
(33)
1579
V53C404D Rev. August 1995
Functional Description
V53C404D CMOS dynamic optimized high data bandwidth, power applications. functionally similar traditional dynamic RAM. V53C404D reads writes data multiplexing 20-bit address into 10-bit 10-bit column address. address latched Address Strobe (RAS). column address "flows through" internal address buffer latched Column Address Strobe (CAS). Because access time primarily dependent valid column address rather than precise time that edge occurs, delay time from little effect access time.
V53C404D
Ending Write with will maintain output High-Z state. controlled Write Cycle, must high state tOED must satisfied.
Refresh Cycle
retain data, 1024 Refresh Cycles required each period. There ways refresh memory: clocking each 1024 addresses through with least once every Read, Write, Read-Modify-Write RAS-only cycle refreshes addressed row. Using CAS-before-RAS Refresh Cycle. makes transition from high after previous cycle before falls, CAS-beforeRAS refresh activated. V53C404D uses output internal 10-bit counter source addresses ignore external address inputs. CAS-before-RAS "refresh-only" mode data access device selection allowed. Thus, output remains High-Z state during cycle. CAS-before-RAS counter test mode provided ensure reliable operation internal refresh counter.
Memory Cycle
memory cycle initiated bringing low. memory cycle, once initiated, must ended aborted before minimum time expired. This ensures proper device operation data integrity. cycle must initiated until minimum precharge time tRP/tCP elapsed.
Read Cycle
Read cycle performed holding Write Enable (WE) signal High during RAS/CAS operation. column address must held minimum specified tAR. Data becomes valid only when tOAC tRAC tCAA tCAC satisifed. result, access time dependent timing relationships between these parameters. example, access time limited when tCAC tOAC satisfied.
Data Retention Mode
V53C404D offers CMOS standby mode that entered causing clock swing between valid "extra high" within VDD. While clock "extra high" level, V53C404 power consumption reduced IDD6 level. Overall consumption when operating this mode calculated follows: (IDD1) (tRX-tRC) (IDD6) Where: Refresh Cycle Time Refresh Interval 1024
Write Cycle
Write Cycle performed taking during operation. column address latched CAS. Write Cycle controlled controlled depending whether falls later. Consequently, input data must valid before falling edge CAS, whichever occurs last. CAS-controlled Write Cycle, when leading edge occurs prior transition, data pins will High-Z state beginning Write function.
V53C404D Rev. August 1995
Fast Page Mode Operation
Fast Page Mode operation permits 1024 columns within selected device randomly accessed high data rate. Maintaining while performing successive cycles retains address internally eliminates need reapply each cycle. column address buffer acts transparent flow-through latch while high. Thus, access begins from occurrence valid column address rather than from falling edge CAS, eliminating tASC from critical timing path. latches address into column address buffer acts output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write Read-Write-Read cycles possible random addresses within row. Following initial entry cycle into Fast Page Mode, access tCAA tCAP controlled. column address valid prior rising edge CAS, access time referenced rising edge specified tCAP. column address valid after rising edge, access timed from occurrence valid address specified tCAA. both cases, falling edge latches address enables output. Fast Page Mode provides sustained data rate applications that require high data rates such bit-mapped graphics high-speed signal processing. following equation used calculate maximum data rate: Data Rate 1024 1023
V53C404D
high. signal effect data stored output latches. level also disable output drivers when low. During Write cycle, goes time relationship that would normally cause outputs active, necessary disable output drivers prior transition allow Data Setup Time (tDS) satisfied.
Power-On
After application supply, initial pause required followed minimum initialization cycles (any combination cycles containing clock). Eight initialization cycles required after extended periods bias without clocks (greater than Refresh Interval). During Power-On, current requirement V53C404D dependent input levels CAS. during Power-On, device will into active cycle will exhibit current transients. recommended that track with held valid during Power-On avoid current surges.
Table V53C404D Data Output
Operation Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles Fast Page Mode Read Fast Page Mode Write Cycle (Early Write) Fast Page Mode ReadModify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
State
Data from Addressed Memory Cell High-Z Controlled. High High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains previous cycle High-Z
Data Output Operation
V53C404D Input/Output controlled CAS, RAS. transition enables transfer data from selected address Memory Array. high transition disables data transfer latches output data output enabled. After memory cycle initiated with transition, transition level enables internal path. high transition high level disables path output driver enabled. transition while high effect data path output drivers. output drivers, when otherwise enabled, disabled holding
V53C404D Rev. August 1995
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