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Spartan-6 FPGA Memory Controller
UG388 (v2.3) August 2010
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Revision History
following table shows revision history this document.
Date 05/28/09 08/18/09 Version Initial Xilinx release. Removed references per-bit deskew calibration. Chapter Added XC6SLX75 XC6SLX75T devices CPG196, CSG484, FG(G)900 packages Table 1-2, page Chapter Figure 2-2, page changed Configuration 128-bit bidirectional. Added note regarding board design requirements under Table 2-9, page Chapter Updated first paragraph Supported Memory Devices, page Added note Clocking, page Added subsection Additional Board Design Requirements, page Chapter Moved Note from Figure 4-1, page below figure. Added Note about calibration logic. Appendix Updated JEDEC specification links Memory Standards, page Revision
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Date 12/02/09
Version
Revision Moved Chapter "Getting Started," Chapter "Debugging Designs," UG416, Spartan-6 FPGA Memory Interface Solutions User Guide. Changed introduction About This Guide, page Chapter Revised Note Table 1-1, page refer data sheet specific values. Added Note Table 1-2, page Chapter Table 2-3, changed description values C_MC_CALIBRATION_MODE attribute page Appended sentences exception page Chapter Replaced text regarding speed calibration clock, calib_clk, page Chapter Rephrased Note under Figure 4-1, page third paragraph after Notes page removed sentence about calibration logic. Added note after first paragraph Calibration, page Removed portion sentence about calibration logic first paragraph Phase Centering, page Added paragraph above Figure 4-13, page Added note page before Table 4-5. Revised document hyperlinks. Chapter Features Benefits section, added bullet input termination automatic calibration section. Table 1-1, added parameters Data Rate Minimum column updated table note Table 1-2, revised table note Chapter Table 2-2, added "THREEQUARTERS" possible value Memory Drive Strength attribute, modified description Memory Burst Length attribute, indicating that DDR3 always Clock, Reset, Calibration Signals section, added calibration heading name, introductory text, caption Table 2-4. Table 2-4, changed signal name BUFPLL BUFPLL_MCB, changed signal name sys_rst async_rst, added signals mcb_drp_clk calib_done. Memory Device Interface section, modified descriptive text related pins. Added clarifying text Note (page relating unused pins from active reverting general-purpose I/O. Table 2-9, modified descriptions signals. Chapter Table 3-1, removed memory devices MT41K128M8xx-25 MT41K256M4xx-25. Clocking section, added text related MIG/EDK generation clocking infrastructure. Clarified text related location externally driven PLL. Revised text related calibration clock. Figure 3-3, changed signal name from calib_clk mcb_drp_clk. Changed first sentence after Figure 3-3. Changed first sentence about calibration related clock page Under Figure 3-4, added clarifying text related using bank1 pins pins. Additional Board Design Requirements section page clarified requirements pull-down resistors RESET, CKE, signals. Added Simultaneous Switching Output Considerations section. Chapter Phase Input Termination section, added clarifying text related input termination pins. Addressing section, added clarifying text related offsetting starting address location using write data mask inputs. Added Read Latency Suspend sections. Appendix Updated JEDEC URLs.
01/05/10 03/04/10
2.0.1
UG388 (v2.3) August 2010
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Spartan-6 FPGA Memory Controller
Date 06/14/10
Version
Revision XCN10024, Performance JTAG Revision Code Spartan-6 LX16 LX45 FPGAs, addresses these changes: Chapter Added important note about Standard Extended performance modes. Chapter Table 2-4, included BUFPLL_MCB block name pll_lock description changed clock frequency example sysclk_2x description. Chapter Clocking, removed LOCKED pll_lock from block Wrapper blocks, respectively, changed clock frequency examples second fourth paragraphs under Figure page
08/09/10
Chapter Table 1-1, changed minimum data rate value LPDDR indicated that speed-grade devices support table note Added table note Table 1-3. Chapter Table 2-4, added italicized sentence calib_done signal description. Table 2-5, Table 2-6, Table 2-7, added sentence about reset being required recover pX_cmd_error, pX_wr_error, pX_rd_error descriptions, respectively. Chapter Added BUFG Figure 3-3. Added sentences about preferred location first paragraph under Figure 3-3. Added sentences about driving MCBs both sides device second paragraph under Figure 3-3. Added Modifying Clock Setup section. Added fourth bullet about VREF Additional Board Design Requirements. Chapter second last paragraph Phase Input Termination, replaced sentence about VREF source still being provided different standards when calibrated input termination desired with sentence about LPDDR memory requiring VREF Added sentence about resulting input termination last paragraph Phase Input Termination page Appendix Removed obsolete link.
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UG388 (v2.3) August 2010
Table Contents
Revision History
Preface: About This Guide
Guide Contents Additional Documentation Additional Support Resources
Chapter Memory Controller Block Overview
Scope Introduction Features Benefits Block Diagram Performance Device Family Support Supported Memory Configurations. Software Tool Support
Chapter Functional Description
Architecture Overview Port Configurations
Selecting Port Configuration
Arbitration Programmability Interface Details
User (Fabric Side) Interface Clock, Reset, Calibration Signals Command Path Write Datapath Read Datapath Self-Refresh Signals Memory Device Interface
Chapter Designing with
Design Flow
CORE Generator Tool
Supported Memory Devices Simulation Resource Utilization. Clocking
Modifying Clock Setup
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Migration Banking. Layout Considerations
General Guidelines Data, Data Mask, Data Strobe Guidelines Address, Control, Clock Guidelines Additional Board Design Requirements Simultaneous Switching Output Considerations
Chapter Operation
Startup Sequence Calibration
Phase Input Termination Phase Centering Phase Continuous Tuning
Instructions Addressing Command Path Timing. Write Path Timing Read Path Timing Memory Transactions
Simple Write Simple Read
Read Latency Self Refresh Suspend
Suspend Mode without DRAM Data Retention Suspend Mode with DRAM Data Retention Additional Suspend Mode Requirements
Byte Address Memory Address Conversion Transaction Ordering Coherency
Appendix References
Memory Standards Layout Signal Integrity
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Preface
About This Guide
This document describes Spartan®-6 FPGA memory controller block (MCB). Complete up-to-date documentation Spartan-6 family FPGAs available Xilinx website implement based memory interface, supported design tool flows must followed: Memory Interface Generator (MIG) traditional (non-embedded) FPGA designs, refer UG416, Spartan-6 FPGA Memory Interface Solutions User Guide information implementing based memory interface using tool within CORE Generatorsoftware. This document also contains information debugging interfaces. Embedded Development (EDK) embedded designs, refer DS643, Multi-Port Memory Controller (MPMC) details used implement MPMC within environment.
Guide Contents
This manual contains following chapters: Chapter Memory Controller Block Overview, introduces Spartan-6 FPGA MCB. Chapter Functional Description, describes architecture, signal interface, possible configurations MCB. Chapter Designing with MCB, provides details incorporate into Spartan-6 design, with specifics customize block given application. Chapter Operation, explains functions various operational modes: startup, calibration, refresh, precharge, standard read/write transactions, etc. Appendix References, contains links additional documentation relevant memory interface design.
Additional Documentation
following documents also available download Spartan-6 Family Overview This overview outlines features product selection Spartan-6 family.
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Preface: About This Guide
Spartan-6 FPGA Data Sheet: Switching Characteristics This data sheet contains Switching Characteristic specifications Spartan-6 family.
Spartan-6 FPGA Packaging Pinouts Product Specification This specification includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications.
Spartan-6 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters configuration interfaces (serial parallel), multi-bitstream management, bitstream encryption, boundary-scan JTAG configuration, reconfiguration techniques.
Spartan-6 FPGA SelectIO Resources User Guide This guide describes SelectIOresources available Spartan-6 devices. Spartan-6 FPGA Clocking Resources User Guide This guide describes clocking resources available Spartan-6 devices, including DCMs PLLs.
Spartan-6 FPGA Block Resources User Guide This guide describes Spartan-6 device block capabilities. Spartan-6 FPGA Configurable Logic Block User Guide This guide describes capabilities configurable logic blocks (CLBs) available Spartan-6 devices.
Spartan-6 FPGA Transceivers User Guide This guide describes transceivers available Spartan-6 FPGAs. Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes architecture DSP48A1 slice Spartan-6 FPGAs provides configuration examples.
Spartan-6 FPGA Planning Design Guide This guide provides information design Spartan-6 devices, with focus strategies making design decisions interface level.
Spartan-6 FPGA Power Management User Guide This guide provides information various hardware methods power management Spartan-6 devices, primarily focusing suspend mode.
Additional Support Resources
find additional documentation, Xilinx website search Answer Database silicon, software, questions answers, create technical support WebCase, Xilinx website http://www.xilinx.com/support.
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Chapter
Memory Controller Block Overview
Scope
This chapter provides overview Spartan®-6 FPGA memory controller block (MCB). contains these sections: Introduction Features Benefits Block Diagram Performance Device Family Support Supported Memory Configurations Software Tool Support
Introduction
dedicated embedded block multi-port memory controller that greatly simplifies task interfacing Spartan-6 devices most popular memory standards. provides significantly higher performance, reduced power consumption, faster development times than equivalent implementations. embedded block implementation conserves valuable FPGA resources allows user focus more unique features FPGA design.
Features Benefits
features benefits Spartan-6 FPGA memory controller block are: DDR, DDR2, DDR3, LPDDR (Mobile DDR) memory standards support Mb/s (400 double data rate) performance four cores single Spartan-6 device. Each core supports: 4-bit, 8-bit, 16-bit single component memory interface Memory densities 12.8 Gb/s aggregate bandwidth ports depending configuration 32-, 64-, 128-bit data options Bidirectional (R/W) unidirectional only only) port options
Configurable dedicated multi-port user interface FPGA logic
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Chapter Memory Controller Block Overview
Memory Bank Management eight memory banks open simultaneously greater controller efficiency Predictable timing power Guaranteed performance Simplified board design Predefined I/Os used interface become general-purpose I/Os (see page details). Programmable drive strength On-Die Termination (ODT) latency Self refresh (including partial array) Refresh interval Write recovery time Adjusts (strobe) (data) timing relationship optimal read performance Embedded controller physical interface (PHY), providing:
Predefined pinouts (I/O locations) each
Common memory device options attributes support
Automatic delay calibration memory strobe read data inputs
Optional automatic calibration FPGA on-chip input termination optimal signal integrity Supported Xilinx® CORE Generatorand Embedded Development (EDK) design tools Memory Interface Generator (MIG) tool within CORE Generator software simplifies design flow Embedded designs also access multi-port memory controller (MPMC) tool
Block Diagram
block diagram Figure shows major architectural components core. Throughout this document, described provided user memory tools within CORE Generator software environment. These tools typically produce top-level "wrapper" files that incorporate embedded block memory controller primitive necessary soft logic port mapping required deliver complete solution. example, Figure 1-1, physical interface uses capabilities general block (IOB) implement external interface memory. General clock network resources also used.
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Block Diagram
X-Ref Target Figure
Spartan-6 FPGA Wrapper FIFO FIFO FIFO FIFO FIFO FIFO User Logic Clocking Network Memory Dedicated Routing DDR2 DDR3 LPDDR 32-Bit Bidirectional 32-Bit Bidirectional 32-Bit Unidirectional 32-Bit Unidirectional 32-Bit Unidirectional 32-Bit Unidirectional Calibration Logic Arbiter Controller
Datapath
UG388_c1_01_050409
Figure 1-1:
Spartan-6 FPGA Memory Controller Block Wrapper View)
single data rate (SDR) user interface inside FPGA configured ports, with each port consisting command interface read and/or write data interface. 32-bit bidirectional four 32-bit unidirectional hardware-based ports inside grouped create five different port configurations. Other major components include: Arbiter Determines which port currently priority accessing memory device. Controller Primary control block that converts simple requests made user interface into necessary instructions sequences required communicate with memory. Datapath Handles flow write read data between memory device user logic. Physical Interface (PHY) Converts controller instructions into actual timing relationships signaling necessary communicate with memory device. Calibration Logic Calibrates optimal performance reliability.
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Chapter Memory Controller Block Overview
Performance
dedicated cores Spartan-6 devices enable significantly higher performance levels than equivalent solutions implemented FPGA logic. Because memory bandwidth often bottleneck overall system performance, cores were specifically engineered users looking maximize memory performance low-cost, low-power FPGA device. Each core supports memory interface data rates total memory bandwidth specifications shown Table 1-1. Peak bandwidth single memory interface calculated three supported interface widths. Note: supports Standard Extended performance modes depending selected VCCINT operating conditions. Peak data rates shown Table represent maximum performance when using VCCINT range Extended performance mode. Refer Table (Recommended Operating Conditions) Performance Characteristics section DS162, Spartan-6 FPGA Data Sheet: Switching Characteristics VCCINT operating conditions performance specifications Standard Extended modes. Table 1-1: Memory Interface Data Rates Peak Bandwidth Each
Data Rate: Mb/s (MHz Clock) Minimum DDR2 DDR3 LPDDR
Notes:
maximum data rate shown does apply speed grades. Refer DS162, Spartan-6 FPGA Data Sheet: Switching Characteristics, performance speed grade. speed-grade devices support MCB. minimum frequency requirement dictated minimum frequency specification memory standard. Memory Standards Appendix links relevant JEDEC specifications.
Peak Bandwidth Interface (Gb/s) 4-Bit Gb/s Gb/s Gb/s Gb/s 8-Bit Gb/s Gb/s Gb/s Gb/s 16-Bit Gb/s 12.8 Gb/s 12.8 Gb/s Gb/s
Memory Type
Maximum(1) Mb/s (200 MHz) Mb/s (400 MHz) Mb/s (400 MHz) Mb/s (200 MHz)
Mb/s(2) (83.3 MHz) Mb/s(2) (125 MHz) Mb/s(2) (303 MHz) Mb/s(2) MHz)
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Device Family Support
Device Family Support
number MCBs available given Spartan-6 device determined density range that device falls within. smallest device (XC6SLX4) contains MCBs, midrange density devices contain MCBs, largest devices contain four MCBs. Table shows number MCBs supported each device/package combination. Note: designed interface single memory component. Multiple
component interfaces single (for example, memories interfacing mode) supported.
Table 1-2:
Device
Support Device Package Combination
Package TQG144 CPG196 CSG225 2(1) 2(1) 2(2) 2(2) 2(2) 2(2) 2(2) 2(2) 2(2) 2(2) 2(2) 2(2) 2(2) 2(2) FT(G)256 CSG324 FG(G)484 CSG484 FG(G)676 FG(G)900
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T XC6SLX150T
Notes:
devices CSG225 package, MCBs support only memory interface width options, meaning LPDDR devices cannot supported. addition, there only address bits available this package, which limits maximum memory density DDR2 DDR3. devices with four MCBs, only MCBs bonded FGG484 CSG484 packages.
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Chapter Memory Controller Block Overview
Supported Memory Configurations
Spartan-6 FPGA supports wide range common memory types, configurations, densities, shown Table 1-3. Table 1-3: Supported Memory Configurations
Width bits)
Notes:
supports single-die, memory components (when available from memory suppliers) dual-die, memory components.
Memory Density
Memory Type LPDDR DDR2 DDR3
Gb(1)
Software Tool Support
Spartan-6 FPGA supported standard software tool flows like other soft embedded blocks offered Xilinx. conventional (i.e., non-embedded) FPGA designs, integrated into design using Memory Interface Generator (MIG) tool, available CORE Generator tool. tool used generate memory interfaces Xilinx FPGAs. produces necessary design files, user constraints files (UCFs), script files simulation implementation memory solutions offered Xilinx. Getting Started chapter UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, contains detailed step-by-step instructions tool implement memory interfaces based MCB. embedded designs (e.g., MicroBlazeprocessor designs), configurator found Xilinx Platform Studio tool within environment used specify memory interface characteristics. this flow, serves underlying hardware implementation MPMC block, available library. addition setting controller memory attributes, tool generates necessary soft bridges bus, Xilinx Cache Link (XCL), LocalLink (LL), other specified interface connecting peripherals resulting memory controller ports.
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Chapter
Functional Description
This chapter provides detailed functional description Spartan®-6 FPGA MCB. contains following sections: Architecture Overview Port Configurations Arbitration Programmability Interface Details
Architecture Overview
provides simple, reliable means interfacing single component memory device. User Interface removes complexities memory interfacing that more engineering resources directed unique aspects FPGA design. operate speeds considerably faster than comparable "soft" solution implemented FPGA logic. With data rates Mb/s, more than doubles performance prior generation low-cost FPGA memory interface solutions, allowing higher levels bandwidth and/or narrower memory buses. This provides significant benefit conserving valuable FPGA logic resources that otherwise required communicate with memory device. Figure expands block diagram introduced Chapter show major signals associated with User Interface internal FPGA well signals connected external memory device. While User Interface configured support ports, simplicity, Figure shows only signals single bidirectional port.
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Chapter Functional Description
X-Ref Target Figure
Spartan-6 FPGA Wrapper
p0_cmd_clk p0_cmd_en p0_cmd_bl p0_cmd_instr p0_cmd_addr p0_cmd_full p0_cmd_empty
Memory
p0_rd_clk p0_rd_en p0_rd_data p0_rd_empty p0_rd_full p0_rd_overflow p0_rd_count p0_rd_error p0_wr_clk p0_wr_en p0_wr_data p0_wr_mask p0_wr_empty p0_wr_full p0_wr_underrun p0_wr_count p0_wr_error
FIFO FIFO FIFO FIFO FIFO FIFO
Arbiter
Controller
mcbx_dram_clk mcbx_dram_clk_n mcbx_dram_cke mcbx_dram_ras_n mcbx_dram_cas_n mcbx_dram_we_n mcbx_dram_odt mcbx_dram_ddr3_rst mcbx_dram_ba mcbx_dram_addr mcbx_dram_dq mcbx_dram_dqs mcbx_dram_dqs_n mcbx_dram_udm mcbx_dram_ldm
Dedicated Routing
Clock Network
32-Bit Bidirectional 32-Bit Bidirectional 32-Bit Unidirectional 32-Bit Unidirectional 32-Bit Unidirectional 32-Bit Unidirectional
Datapath
Spartan-6 FPGA Memory Controller Block
UG388_c3_01_050409
Figure 2-1:
Architecture with Major Internal Signals
There three basic types ports that established User Interface: Read port (unidirectional) Write port (unidirectional) Read Write port (bidirectional)
Each port contains command path datapath. unidirectional port, command path paired with single read-only single write-only datapath. However, bidirectional port, single command path shared both read write datapaths associated with that port. FIFOs used User Interface command path datapath queue memory requests manage transfer from user clock domain memory controller clock domain. command path signals port used issue requests command FIFOs. command FIFOs have user-programmable depth four. They store instruction type (read, write, refresh, etc.), address, burst length associated with requested memory transaction. command path also includes full empty status flag outputs from command FIFOs, indicating whether requests accepted. There command FIFOs available hardware; port configuration determines many accessible User Interface (see Port Configurations). more details command path signals, refer Interface Details, page
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Port Configurations
datapath, underlying hardware contains 32-bit ports, which inherently bidirectional. other four ports inherently unidirectional combined create bidirectional ports well. There five possible port configurations that combine these hardware ports implement desired User Interface (see Port Configurations). width read write data word fields User Interface naturally determined chosen configuration. datapath FIFOs deep, allowing burst lengths data words from given start address. addition data word field, write path FIFOs contain mask fields that allow optional masking write data byte basis. Full, empty, underrun, count, error outputs indicate current status write data FIFOs. read data FIFOs have similar status outputs. more details read write datapath signals, refer Interface Details, page arbiter inside uses time slot based arbitration mechanism determine which ports User Interface currently access memory. There also methods allowing some ports greater priority, thus frequent access memory, discussed Arbitration. Bank management logic allows eight memory banks open simultaneously, allowing controller maintain high efficiency levels when accessing data spread across multiple banks. addition, read write requests memory include optional auto-precharge automatically close bank upon completion transaction improve efficiency random data accesses within bank. does perform reordering transactions.
Port Configurations
five possible port configurations User Interface shown Figure 2-2. Configuration user ports essentially directly underlying physical hardware ports. other configurations, diagram shows physical ports concatenated create different user port combinations. shown Figure 2-2, tool always sequentially numbers ports User Interface starting from regardless underlying physical port numbers. five port configurations, command path, write datapath, read datapath within given port have separate clocks therefore connected independent clock domains. However, recommended that paths related given port kept single clock domain simplify interface requirements.
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Chapter Functional Description
X-Ref Target Figure
Configuration
32-Bit Bidirectional 32-Bit Unidirectional
Configuration Configuration
32-Bit Bidirectional 64-Bit Bidirectional 32-Bit Bidirectional
Configuration
64-Bit Bidirectional
Configuration
128-Bit Bidirectional
User Port
32-Bit
User Port
32-Bit
User Port
64-Bit
User Port
64-Bit
User Port
32-Bit
User Port
32-Bit
User Port
32-Bit
User Port User Port
32-Bit
User Port
32-Bit
128-Bit
User Port
32-Bit
User Port
64-Bit
User Port
32-Bit
User Port
32-Bit
User Port
32-Bit
User Port
32-Bit
UG388_c3_02_072809
Figure 2-2:
Possible Port Configurations User Interface
Selecting Port Configuration
tool CORE Generatortool provides simple graphical interface setting number type ports required specific application. designs that require less than full width functionality User Interface, unused ports simply disabled through interface. event that additional ports required beyond ports provided MCB, port bridges with additional arbitration mechanisms implemented FPGA logic expand port capabilities.
Arbitration
arbiter inside uses time slot based arbitration mechanism determine which port User Interface currently access memory. There time slots arbitration table shown Table 2-1. Each time slot corresponds single memory clock cycle. order port priority given time slot determined port numbers entered into Priority through columns moving from left right across table. Table shows case where User Interface configured maximum ports. configured have fewer than ports, arbitration table automatically adjusts have priority columns only selected number ports.
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Arbitration
Table 2-1:
Time Slot
Arbitration Table with Round Robin Configuration
Priority Priority Priority Priority Priority Priority
During given clock cycle, arbiter determines which port service that time slot. moves left right across priority columns find first port that that command pending command FIFO. That port then serviced with execution pending command, arbiter moves next time slot following clock cycle. port command pending that row, action occurs that time slot clock cycle lost. order port priorities arbitration table fully programmable. tool provides default round-robin scheme illustrated Table 2-1, where ports given highest priority available time slots. However, tool also provides custom option where user define arbitration table. This allows some ports given greater overall access memory device. However, care should exercised when using this option ensure that assigned priorities prevent active ports from receiving access memory device. possible configure User Interface have five ports (two 32-bit bidirectional ports three 32-bit unidirectional ports, with 32-bit unidirectional port disabled). this case, arbitration table reduced time slots. When number time slots evenly divisible number ports, each port ensured receive equal access memory device, desired.
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Chapter Functional Description
Programmability
highly configurable through memory device controller attributes, allowing support multiple memory standards configurations. tool within CORE Generator tool Configurator Xilinx Platform Studio tool within environment provide simple means configuring attributes implement desired memory interface (for example, "Getting Started" chapter UG416, Spartan-6 FPGA Memory Interface Solutions User Guide). Table Table list memory device controller attributes, respectively, supported MCB. specific parameter names, possible values, descriptions associated with each attributes provided. general, tool Configurator tools responsible setting parameter values, values should modified directly. Memory timing parameters taken from vendor data sheets, automatically assigned tools when supported device selected. Timing parameters specified when creating custom device (see "Setting Controller Options" section Spartan-6 FPGA Memory Interface Solutions User Guide). Table 2-2: Memory Device Attributes
Parameter Name(s) C_MEM_TYPE Description Possible Values This attribute sets memory standard implemented MCB. Possible values: DDR, DDR2, DDR3, LPDDR. Memory Data Width Memory Address Width C_NUM_DQ_PINS C_MEM_ADDR_WIDTH This attribute sets width bus. Possible values: "4", "8", "16". This attribute sets memory address width (the total number address bits). Possible values: Based device selection tool. Memory Bank Address Width C_MEM_BANKADDR_WIDTH This attribute sets number bank address bits. Possible values: Based device selection tool. Memory Column Address Width C_MEM_NUM_COL_BITS This attribute sets number column address bits. Possible values: Based device selection tool. Memory Burst Length C_MEM_BURST_LEN This attribute sets memory burst length used. tool determines value based memory standard, port configuration, interface width. DDR3 will always Possible values: "4", "8".
Memory Attributes Memory Type
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Programmability
Table 2-2:
Memory Device Attributes (Cont'd)
Parameter Name(s) DDR, DDR2, LPDDR: C_MEM_CAS_LATENCY DDR3: C_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_CAS_WR_LATENCY Description Possible Values This attribute sets latency (the delay clock cycles between READ command first output data) memory. DDR3 separate Read Write latency values. Possible values: depending memory type.
Memory Attributes Memory Latency
Partial Array Self-Refresh Size Memory Drive Strength
C_MEM_MOBILE_PA_SR
LPDDR: This attribute sets array size self-refresh operation. Possible values: LPDDR: Full, Half This attribute sets output drive strength memory device. Possible values: DDR/DDR2: "FULL", "REDUCED" DDR3: "DIV6" (RZQ/6), "DIV7" (RZQ/7) LPDDR: "FULL", "THREEQUARTERS", "HALF", "QUARTER"
DDR, DDR2: C_MEM_DDR1_2_ODS DDR3: C_MEM_DDR3_ODS LPDDR: C_MEM_MDDR_ODS
Memory Termination Value (ODT)
DDR2: C_MEM_DDR2_RTT DDR3: C_MEM_DDR3_RTT
This attribute sets on-die termination resistance memory device. Possible values: DDR2: "OFF", "50OHMS", "75OHMS", "150OHMS" DDR3: "OFF", "DIV2" (RZQ/2), "DIV4" (RZQ/4), "DIV6" (RZQ/6), "DIV8" (RZQ/8), "DIV12" (RZQ/12)
Note:
Memory Differential Enable C_MEM_DDR2_DIFF_DQS_EN Enables differential strobe use. This attribute always enabled DDR3; "YES" DDR2 frequencies above MHz. Possible values: DDR2: "YES", "NO" Memory Auto Self Refresh C_MEM_DDR3_AUTO_SR DDR3 only: Auto self-refresh allows memory determine best refresh interval based device temperature. auto selfrefresh used, operating temperature range must indicated using hightemperature self-refresh register. Possible values: "ENABLED", "MANUAL" Memory High Temperature Self Refresh C_MEM_DDR2_3_HIGH_TEMP_SR DDR2 DDR3: Memory high-temperature self-refresh mode decrease refresh interval time. Possible values: DDR2/DDR3: "NORMAL" (0-85°C), "EXTENDED" 85°C)
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Chapter Functional Description
Table 2-2:
Memory Device Attributes (Cont'd)
Parameter Name(s) C_MEM_DDR3_DYN_WRT_ODT Description Possible Values DDR3: Determines value dynamic output driver termination. Possible values: DDR3: "OFF", "DIV2" (RZQ/2), "DIV4" (RZQ/4)
Memory Attributes Memory Dynamic Output Driver Termination
Memory tRAS Value
C_MEM_TRAS
Minimum Active Precharge period memory. Possible values picoseconds): Based device selection tool.
Memory tRCD Value
C_MEM_TRCD
Minimum Active Read Write command delay memory. Possible values picoseconds): Based device selection tool.
Memory tREFI Value
C_MEM_TREFI
Average Periodic Refresh Interval memory. This attribute rate which refreshes memory, self-refresh interval. Possible values picoseconds): Based device selection tool.
Memory tRFC Value
C_MEM_TRFC
Minimum Auto-Refresh Active AutoRefresh command period memory. Possible values picoseconds): Based device selection tool.
Memory Value
C_MEM_TRP
Minimum Precharge command period memory. Possible values picoseconds): Based device selection tool.
Memory Value
C_MEM_TWR
Minimum Write Recovery time memory. Possible values picoseconds): Based device selection tool.
Memory tRTP Value
C_MEM_TRTP
Minimum Read Precharge command delay memory. Typically, this parameter only found DDR2 DDR3 devices. Possible values picoseconds): Based device selection tool.
Memory tWTR Value
C_MEM_TWTR
Minimum Write Read command delay memory. Possible values picoseconds): Based device selection tool.
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Programmability
Table 2-3:
Controller Attributes
Parameter Name(s) C_MEMCLK_PERIOD Description Possible Values This attribute converts memory timing parameters between clock cycles picoseconds. Possible values picoseconds): Based frequency selection tool.
Controller Attributes Controller Clock Period
Controller Port Configuration
C_PORT_CONFIG
This attribute sets port configuration User Interface. determines port direction Bidirectional, Unidirectional Write, Unidirectional Read) data width (32, bits). Possible Values: "B32_B32_W32_W32_W32_W32" "B32_B32_W32_W32_W32_R32" "B32_B32_W32_W32_R32_W32" "B32_B32_W32_W32_R32_R32" "B32_B32_W32_R32_W32_W32" "B32_B32_W32_R32_W32_R32" "B32_B32_W32_R32_R32_W32" "B32_B32_W32_R32_R32_R32" "B32_B32_R32_W32_W32_W32" "B32_B32_R32_W32_W32_R32" "B32_B32_R32_W32_R32_W32" "B32_B32_R32_W32_R32_R32" "B32_B32_R32_R32_W32_W32" "B32_B32_R32_R32_W32_R32" "B32_B32_R32_R32_R32_W32" "B32_B32_R32_R32_R32_R32" "B32_B32_B32_B32" "B64_B32_B32" "B64_B64" "B128"
Port Data Width (Ports
C_P0_DATA_PORT_SIZE C_P1_DATA_PORT_SIZE
Ports User Interface vary data width depending port configuration selected (Ports through available, always bits wide). These parameters Port data width. Possible Values: "32", "64", "128" This attribute sets number mask bits Ports depending data width determined port configuration. Possible Values: "4", "8", "16"
Port Data Mask Width (Ports
C_P0_MASK_SIZE C_P1_MASK_SIZE
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Chapter Functional Description
Table 2-3:
Controller Attributes (Cont'd)
Parameter Name(s) C_PORT_ENABLE Description Possible Values This six-bit value determines which underlying 32-bit hardware ports used given port configuration. Possible Values: example, 6'b001111 ports enabled
Controller Attributes Controller Port Enable
Address Mapping Order
C_MEM_ADDR_ORDER
This attribute determines byte address presented User Interface maps physical memory bank, row, column address bits. This attribute based system addressing scheme. This value should take most advantage open bank management capabilities. Possible Values: "BANK_ROW_COLUMN", "ROW_BANK_COLUMN"
Arbitration Time Slot Count
C_ARB_NUM_TIME_SLOTS
This attribute sets number time slots arbitration table. Most port configurations have time slots, port configurations with active ports have time slots arbitration table ensure equal arbitration. Possible Values: "12", "10" These 6-digit octal (18-bit) values port priority each time slot. Possible Values: example, C_ARB_TIME_SLOT0 18'o012345 (sets Port with highest priority down Port with lowest priority).
Arbitration Time Slot Values
C_ARB_TIME_SLOT[0:11]
Controller Calibration Bypass (Simulation)
C_MC_CALIB_BYPASS
Directs tool simulation files skip controller calibration sequence faster simulation.
Note: This parameter simulation only.
Possible Values: "YES", "NO" Reserved Calibration Address Space C_MC_CALIBRATION_RA C_MC_CALIBRATION_BA C_MC_CALIBRATION_CA Defines starting row, bank, column address reserved calibration. This attribute used training pattern data during recalibration avoid overwrite application data. Possible Values (any valid address okay): Examples: C_MC_CALIBRATION_RA 15'h0000 C_MC_CALIBRATION_BA 3'h0 C_MC_CALIBRATION_CA 12'h000
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Interface Details
Table 2-3:
Controller Attributes (Cont'd)
Parameter Name(s) C_MC_CALIBRATION_MODE Description Possible Values This attribute determines whether executes precise alignment real-time voltage/temperature compensation strobe (recommended) simply uses fixed ratio period offset into data window. Possible Values: "CALIBRATION" (precise alignment with voltage/temperature compensation), "NOCALIBRATION" (fixed offset delay)
Controller Attributes Calibration Mode
Offset Delay Value
C_MC_CALIBRATION_DELAY
This attribute sets fixed offset delay ratio period when C_MC_CALIBRATION_MODE CALIBRATION". Possible Values: "QUARTER", "HALF", "THREEQUARTER", "FULL"
Interface Details
shown architecture block diagram Figure 2-1, page basic interfaces: internal User Interface FPGA logic external interface memory device predefined pins. following subsections discuss details signals related these interfaces. rest this document, descriptions refer interface wrapper delivered CORE Generator tool flows, interface underlying memory controller block primitive.
User (Fabric Side) Interface
User Interface contains necessary signals user logic FPGA logic interact with command path datapath ports. also includes general clock reset signals well signals related calibration, debug, self-refresh operation. User Interface configured have anywhere from ports shown Port Configurations, page
Clock, Reset, Calibration Signals
Table shows clock, reset, calibration related signals User Interface. Table 2-4: Clock, Reset, Calbration Signals
Direction Input Description Main system reset MCB. This active-High signal indicates completion phases calibration during start-up sequence MCB. Transactions should submitted until this signal goes High indicate that calibration completed. Calibration Chapter more information.
Signal Name async_rst
calib_done
Output
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Chapter Functional Description
Table 2-4:
Clock, Reset, Calbration Signals (Cont'd)
Direction Description This clock synchronizes soft calibration module sysclk_2x domain. must generated same sysclk_2x ensure that phase-synchronized that domain. Clocking Chapter more information. clock enable strobe from BUFPLL_MCB. This signal pulses High every other clock cycle sysclk_2x. used double data rate transfers blocks. clock enable strobe from BUFPLL_MCB. This signal pulses High every other clock cycle sysclk_2x_180. used double data rate transfers blocks. Lock signal from BUFPLL_MCB block. Main system clock MCB. This signal generated Spartan-6 FPGA block rebuffered BUFPLL_MCB driver clock network. operates times memory clock frequency (for example, memory interface). This input phase-shifted clock with same frequency sysclk_2x. generated same PLL/BUFPLL_MCB resources.
Signal Name
mcb_drp_clk
Input
pll_ce_0
Input
pll_ce_90 pll_lock
Input Input
sysclk_2x
Input
sysclk_2x_180
Input
Command Path
Table defines signals related command path User Interface. port signal names have prefix where represents port number (for example, port signals prefixed with port with forth). Table 2-5: Command Path Signals
Direction Description Byte start address current transaction. Addresses must aligned port size: pX_cmd_addr[29:0] Input 32-bit ports: Lower bits must 64-bit ports: Lower three bits must 128-bit ports: Lower four bits must Burst length number user words current transaction. Burst length encoded representing user words (for example, 6'b00011 burst length transaction). user word width equals port width (for example, burst length 64-bit port transfers 64-bit user words bits total). User clock Command FIFO. FIFO signals captured rising edge this clock. This active-High empty flag Command FIFO indicates commands queued FIFO, although there might commands flight.
Signal Name
pX_cmd_bl[5:0]
Input
pX_cmd_clk
Input
pX_cmd_empty
Output
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Interface Details
Table 2-5:
Command Path Signals (Cont'd)
Direction Input Description This active-High signal write-enable signal Command FIFO. This signal covered more detail Chapter This output indicates Command Port error occurred because FIFO pointers were unsynchronized. reset required recover from this condition. This active-High output full flag Command FIFO. indicates FIFO cannot accept more commands blocks writes Command FIFO. Command code current instruction. represents READ/WRITE select, Auto Precharge enable, represents Refresh, which always takes priority: Write: 3'b000
Signal Name pX_cmd_en
pX_cmd_error
Output
pX_cmd_full
Output
pX_cmd_instr[2:0]
Input
Read: 3'b001 Write with Auto Precharge: 3'b010 Read with Auto Precharge: 3'b011 Refresh: 3'b1xx This signal covered more detail Chapter
Write Datapath
Table shows signals related write datapath User Interface. port signal names have prefix where represents port number (for example, port signals prefixed with port with forth). Table 2-6: Write Datapath Signals
Signal Name pX_wr_clk Direction Input Description This signal user clock Write Data FIFO. Count value Write Data FIFO. This output indicates many user words FIFO (from 64). count value indicates FIFO empty. This signal longer latency than pX_wr_empty flag. Therefore, FIFO could empty experience underrun even when count Write Data value loaded into Write Data FIFO sent memory. PX_SIZE bits, depending port configuration. This active-High signal empty flag Write Data FIFO. indicates there valid data FIFO.
pX_wr_count[6:0]
Output
pX_wr_data[PX_SIZE-1:0]
Input
pX_wr_empty
Output
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Chapter Functional Description
Table 2-6:
Write Datapath Signals (Cont'd)
Signal Name Direction Description This active-High signal write enable Write Data FIFO. indicates that value pX_wr_data valid loading into FIFO. Data loaded rising edge pX_wr_clk when pX_wr_en pX_wr_full This signal indicates Write Data FIFO error occurred because FIFO pointers were unsynchronized. reset required recover from this condition. This active-High signal full flag Write Data FIFO. When this signal high, prevents data from being loaded into FIFO. Data mask bits Write Data. This mask loaded into FIFO coincident with associated Write Data (pX_wr_data). mask associated with each byte data. When pX_wr_mask High, corresponding byte data masked (that written memory). This active-High signal underrun flag. indicates there enough data Write Data FIFO complete transaction. last valid data word written continuously finish burst. prevent underrun, make sure there enough data FIFO when issuing Write instruction Command FIFO. sys_rst signal must asserted reset this flag recover from this condition.
pX_wr_en
Input
pX_wr_error
Output
pX_wr_full
Output
pX_wr_mask[PX_MASKSIZE-1:0]
Input
pX_wr_underrun
Output
Read Datapath
Table shows signals related read datapath User Interface. port signal names have prefix where represents port number (for example, port signals prefixed with port with forth). Table 2-7: Read Datapath Signals
Direction Input Description This input user clock Read Data FIFO. This active-High signal read enable Read Data FIFO. Read Data clocked FIFO rising edge pX_rd_clk when pX_rd_en pX_rd_empty
Signal Name pX_rd_clk
pX_rd_en
Input
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Interface Details
Table 2-7:
Read Datapath Signals (Cont'd)
Direction Description Read Data value returning from memory. This signal driven output Read Data FIFO into FPGA logic. PX_SIZE bits, depending port configuration. This active-High signal full flag Read Data FIFO. When High, this signal prevents additional data returning from memory from being loaded into FIFO. This active-High signal empty flag Read Data FIFO. indicates there valid data FIFO. Count value Read Data FIFO. This signal indicates many user words FIFO (from 64). count value indicates FIFO empty. This signal longer latency than pX_rd_full flag. Therefore, FIFO could full experience overflow even when count less than This active-High signal overflow flag. indicates that data lost Read Data continuing return from memory after Read Data FIFO full. prevent overflow:
Signal Name
pX_rd_data[PX_SIZE-1:0]
Output
pX_rd_full
Output
pX_rd_empty
Output
pX_rd_count[6:0]
Output
pX_rd_overflow
Output
Make sure there enough room store requested Read Data FIFO before issuing Read instruction Command FIFO. sure account transactions flight. sys_rst signal must asserted reset this flag recover from this condition. This signal indicates Read Data FIFO error occurred because FIFO pointers were unsynchronized. reset required recover from this condition.
pX_rd_error
Output
Self-Refresh Signals
Table shows self-refresh signals accessible through user interface. Self-refresh covered more detail Chapter Table 2-8: Self-Refresh Signals
Direction Description This input rising-edge sensitive. When asserted, requests memory device enter selfrefresh mode. signal must remain asserted until selfrefresh_mode signal goes active. This active-High signal indicates memory device self-refresh mode.
Signal Name
selfrefresh_enter
Input
selfrefresh_mode
Output
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Chapter Functional Description
Memory Device Interface
Memory Device Interface contains necessary signals communicate with external memory device. these signals (Table 2-9) have predefined locations Spartan-6 devices. UG385, Spartan-6 FPGA Packaging Pinouts Product Specification detailed pinout information each device/package combination. addition, soft calibration module generated requires allocation additional (RZQ) designs. required pin, location moved within bank. When Calibrated Input Termination selected tool, also generated with soft calibration module. location also moved must placed bonded (i.e., valid package pin) within bank. "Setting FPGA Options" section UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, more information pins. Note: predefined pins revert general-purpose I/Os when unused. addition,
unused pins from active also revert general-purpose I/Os. This includes higher order address bank address pins needed particular density device, data bits needed particular interface width, reset signals when needed memory standard, UDQS UDQS_n strobes interfaces. other interface pins required based designs. addition, there exceptions general-purpose recovery rules: Data mask pins paired such that only used, lost general I/O. data mask pins required designs support variable burst length requests user interface. Therefore, both unavailable general I/Os whenever used. Data strobe pins paired such that only used (single-ended strobe), DQS_n lost general I/O. same true UDQS UDQS_n.
Table 2-9:
Memory Device Interface Signals
Direction Description Address memory device. C_MEM_ADDR_WIDTH tool depending memory device configuration (the maximum value 15). Bank Address memory device. supports eight banks memory device. This signal active-Low column address strobe memory device. This active-High signal clock enable memory device. This output differential clock output) memory device. This output differential clock output) memory device. This signal DDR3 reset memory device. Bidirectional data memory device. C_NUM_DQ_PINS tool depending memory device configuration (valid values 16).
Signal Name mcbx_dram_addr [C_MEM_ADDR_WIDTH-1:0]
Output
mcbx_dram_ba[2:0]
Output
mcbx_dram_cas_n mcbx_dram_cke mcbx_dram_clk mcbx_dram_clk_n mcbx_dram_ddr3_rst
Output Output Output Output Output
mcbx_dram_dq [C_NUM_DQ_PINS-1:0]
Bidir
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Interface Details
Table 2-9:
Memory Device Interface Signals (Cont'd)
Direction Bidir Description Bidirectional data strobe DQ[7:0]. This signal input during Read transactions output during Write transactions. Bidirectional complementary data strobe DQ[7:0]. This signal input during Read transactions output during Write transactions. This output data mask lower data byte (DQ[7:0]) x16, configurations. This output on-die termination signal. supported DDR2 DDR3. This active-Low signal address strobe memory device. This output data mask upper data byte (DQ[15:8]) when interfacing device. Bidirectional data strobe DQ[15:8]. This signal input during Read transactions output during Write transactions. Bidirectional complementary data strobe DQ[15:8]. This signal input during Read transactions output during Write transactions. This signal active-Low write enable memory device. Required designs. When Calibrated Input Termination selected tool, should have resistor value from ground, where desired input termination value. other cases, should left no-connect pin. moved valid package within bank. Connect signal used with soft calibration module when Calibrated Input Termination selected. must placed valid package within bank, there should board trace attached this (i.e., connect). generated designs that Calibrated Input Termination.
Signal Name mcbx_dram_dqs
mcbx_dram_dqs_n
Bidir
mcbx_dram_ldm
Output
mcbx_dram_odt mcbx_dram_ras_n
Output Output
mcbx_dram_udm
Output
mcbx_dram_udqs
Bidir
mcbx_dram_udqs_n
Bidir
mcbx_dram_we_n
Output
Bidir
Bidir
Note: Refer Layout Considerations Chapter board design requirements related CS#, ODT, pins memory device.
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Chapter Functional Description
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Chapter
Designing with
This chapter provides detailed information design with Spartan®-6 FPGA MCB. contains these sections: Design Flow Supported Memory Devices Simulation Resource Utilization Clocking Migration Banking Layout Considerations
Design Flow
There supported design flows MCB: Non-embedded design flow Conventional FPGA design with Xilinx® ISE® tool flow tool used within CORE Generatortool designs Processor-based FPGA system design with tool flow Configurator Xilinx Platform Studio (XPS) used within environment designs
Embedded design flow
Both tool flows provide simple method developing reliable interface external memory devices. step-by-step driven flow allows based design configured parameterized meet precise needs application. tool flow actually "wrapper" levels: lower-level wrapper (mcb_raw_wrapper.v) top-level wrapper (for example, memc3_wrapper.v). lower-level wrapper incorporates necessary silicon blocks (MCB, I/O, etc.) soft logic (soft calibration module), required solution. also provides access signals associated with underlying hardware implementation User Interface ports calibration logic. top-level wrapper handles signal reassignment, tying lower-level wrapper signals, needed, passing down parameter values lower wrapper based user selections tool. top-level wrapper presents clean interface only those signals needed implement MCB-based design configured during tool flow. example, while lower-level wrapper always shows native 32-bit ports User Interface, top-level wrapper reassigns signals, ties unused ports, concatenates buses
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Chapter Designing with
present port interface user expects, such single 64-bit port. top-level wrapper that subsequently integrated into larger FPGA design. lower-level wrapper (mcb_raw_wrapper.v) documented throughout this User Guide. parameter signal lists Chapter example, described with respect this lower-level wrapper. This wrapper does change based choices made tool flow, whereas top-level wrapper customized result user selections. addition, embedded design flow (EDK) uses same lower-level wrapper foundation creating Multi-Port Memory Controller (MPMC) peripheral. configurator allows user necessary soft bridges lowerlevel wrapper create desired peripheral interfaces, such interface Xilinx Cache Link (XCL) interface Local Link (LL) interface Other Personality Interface Modules (PIMs) supported
Figure illustrates lower-level wrapper used both non-embedded (MIG) embedded (EDK) design flows.
X-Ref Target Figure
Top-level Wrapper (MIG) Lower-level Wrapper Port Grouping Signal
Ports
Top-level Wrapper (EDK)
Soft Bridges
Lower-level Wrapper
Ports
Top-level User Interface
Top-level User Interface
Soft Calibration Module
Soft Calibration Module
Non-embedded Design (MIG/CORE Generator Tool)
Figure 3-1:
Embedded Design (EDK XPS)
UG388_c4_01_050409
Common Lower-Level Wrapper Non-embedded Embedded Design
CORE Generator Tool
Figure shows high-level design flow integrating based memory interface into non-embedded (conventional) FPGA design. "Getting Started" chapter UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, provides detailed step-by-step guide Phase this design flow. Phase Phase outside scope this document, detailed instructions tool flow found elsewhere Xilinx Documentation Library.
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Supported Memory Devices
X-Ref Target Figure
Phase
Launch Tool from Inside CORE Generator Tool
Phase
Integrate Constraints into Overall Design Constraints File
Phase
Implement Design Synthesis, MAP,
Make selections FPGA/Memory Parameters Generate Files
Import Build Options into Tool Project
Perform Timing Simulation Completed Design
Perform Functional Simulation Example Design (optional)
Perform Functional Simulation with Design Integrated
Verify Design Hardware
UG388_c4_02_050409
Figure 3-2: Design Flow Non-embedded (Conventional) FPGA Applications
Supported Memory Devices
Table provides list memory devices verified operate with Xilinx hardware verification platform. These devices selected tool EDK) flow from drop-down list supported devices. Xilinx will devices drop-down supported device list future releases, these devices will receive "simulation only" verification. Additionally, custom devices created user tool; however, these have simulation hardware verification Xilinx. "Setting Controller Options" section UG416, Spartan-6 FPGA Memory Interface Solutions User Guide, more information. Table 3-1: Supported Memory Devices
Vendor Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Micron Part Number MT41J64M16xx-187E MT41J256M8xx-187E MT41J128M8xx-187E MT41J256M4xx-187E MT41J512M4xx-187E MT47H256M4xx-25E MT47H64M8xx-25E-IT MT47H128M8xx-25 MT47H128M16xx-3 MT47H256M4xx-3 MT47H16M16xx-3 MT47H32M16xx-37E MT47H32M8xx-37E Width Density
Standard DDR3 DDR3 DDR3 DDR3 DDR3 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2
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Chapter Designing with
Table 3-1:
Supported Memory Devices (Cont'd)
Vendor Micron Micron Micron Elpida Elpida Hynix Micron Micron Micron Micron Micron Micron Micron Micron Part Number MT47J64M16xx-3 MT47J256M4xx-37E MT47J128M8xx-3 EDE1116ACBG-8E EDE5116AJBG-8E HYB18TC512160B2F-2.5 MT46V32M16xx-5B-IT MT46V32M8xx-5B MT46V64M4xx-5B MT46H32M16xxxx-5 MT46H16M16xxxx-6-IT MT46H16M16xxxx-75-IT MT46H64M16xxxx-5L-IT MT46H64M16xxxx-6L-IT Width Density
Standard DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 LPDDR LPDDR LPDDR LPDDR LPDDR
Simulation
simulation model underlying contained within EDK) wrapper encrypted specified Verilog LRM-IEEE 1364-2005. This similar other offered Xilinx, such transceiver Integrated Endpoint blocks Express® designs. Xilinx supports following simulators this encryption methodology: ModelSim 6.4b above
encrypted model automatically compiled when usual COMPXLIB script run, provided appropriate version simulator available computer. When running simulation Verilog based design, following library must referenced: secureip. most simulators, this done using switch argument simulator, such secureip. Note: VHDL used design entry language, mixed-language license required ModelSim simulate designs that include MCB. more information simulating blocks using secureip methodology, UG626, Synthesis Simulation Design Guide.
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Resource Utilization
Resource Utilization
EDK) wrapper produced design flow incorporates device resources required implementation based memory interface. most part, wrapper files simply managing signal name reassignment connectivity between silicon resources (for example, block connections), thus consume measurable FPGA logic. However, soft calibration module contained within wrapper does consume small amount FPGA logic resources. addition, there specific clocking requirements (see Clocking) that result some general clocking resources. Table shows resource utilization associated with design, excluding logic required user design control User Interface ports. This table uses DDR3 interface with eight banks, differential strobes, data masking calculate maximum count. Other memory standards configurations fewer pins. Table 3-2: Resource Utilization Each Based Memory Interface
Memory Interface Width Resource Memory Controller Block (MCB) Predefined Pins: Address, Data, Control, etc. Soft Calibration Module Logic Block BUFPLL_MCB Buffer Slices Slices Slices
Clocking
This section describes clocking requirements implementing memory interface based MCB. EDK) tool automatically generates clocking infrastructure that fully complies with these requirements. requires three basic types clocks: system clocks determine operating frequency memory controller physical interface external memory device. Calibration clock determines operating frequency calibration logic. User clocks determine operating frequency User Interface ports. These clocks completely asynchronous system calibration clocks. Command Data Path FIFOs handle necessary clock domain transfer from User Interface internal controller logic.
Figure shows recommended clock distribution scheme system calibration clocks. MCBs located regions left right side device, must therefore driven clock network. clock network designed significantly higher frequencies than global clock network, allowing memory interfaces operate Mb/s. Note: CLKOUT0 CLKOUT1 only outputs that connected
BUFPLL_MCB driver. These connections must made exactly shown Figure 3-3.
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Chapter Designing with
X-Ref Target Figure
CLKB IBUFGDS CLKIN1
CLKOUT0 CLKOUT1
SERDESSTROBE0 PLLIN0 PLLIN1 IOCLK0 IOCLK1
Clock Network
Wrapper
pll_ce_0 sysclk_2x sysclk_2x_180 pll_ce_90
SERDESSTROBE1
BUFPLL_MCB
CLKOUT2 CLKFB CLKFB BUFG second same side device available)
mcb_drp_clk
UG388_c4_03_080310
Figure 3-3:
Recommended System Calibration Clock Distribution
create desired system clock frequency clock network, external clock source drives PLLs center column device. external clock frequency critical long synthesize desired system clocks from general, preferred location nearest center device that minimizes physical distance between BUFPLL_MCB block. This location strongly recommended larger devices with PLLs. generates system clock outputs, sysclk_2x sysclk_2x_180, that twice frequency desired memory clock (for example, Mb/s DDR2 interface with memory clock equal MHz, system clocks MHz) degrees phase from each other. Only clock lines available each side device drive clock network from PLLs. pair system clocks uses these clock lines connect MCBs left right side device. Thus devices with four MCBs, MCBs same side device must share same system clock pair therefore must same data rate, although memory standard implemented different. DCMs have access clock network cannot, therefore, used drive MCBs. also possible drive MCBs both sides device from single PLL. this case, BUFPLL_MCB blocks (one each side device) must driven shared PLL. When pair system clocks reaches clock network, they rebuffered BUFPLL_MCB driver. This driver also creates clock enable strobes required MCB: pll_ce_0 pll_ce_90. attributes BUFPLL_MCB primitive should follows create necessary clock enable strobe behavior MCBs: LOCK_SRC "LOCK_TO_0" DIVIDE
rebuffered full rate system clocks clocks) used layer interface create necessary double data rate (DDR) signaling pins (for example, clock used generate effective Mb/s signal I/O). divide-by-two circuit creates what traditionally considered memory clock frequency (for example, Mb/s interface). These clocks drive controller, arbiter, other single data rate (SDR) logic.
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Clocking
calibration related clock, mcb_drp_clk, must generated must phase-synchronized (i.e., phase) with sysclk_2x domain. calibration clock rate limited normal static timing analysis, with typical achievable frequency MHz. general, calibration clock frequency least should used allow complete calibration operations reasonable period time. user clocks associated with each User Interface ports (port number used given design, follows: pX_cmd_clk: Command FIFO user clock clocking Address, Instruction, Burst Length from FPGA logic into FIFO. pX_wr_clk: Write Data FIFO user clock loading write data from FPGA logic into FIFO preparation burst memory. pX_rd_clk: Read Data FIFO user clock clocking data returning from memory into FPGA logic.
user clocks completely asynchronous from system calibration clocks therefore they operate frequency dictated FPGA logic portion design. FIFOs inside handle necessary clock domain transfer. best utilization available memory bandwidth, user clocks should above frequency determined ratio User Interface external Memory Device interface. example: DDR3 Mb/s interface with memory clock memory device: result bits data transfer clock cycle bits each clock edge) User interface: user clock should above (16/64) While technically required, also highly recommended that three user clocks port (pX_cmd_clk, pX_wr_clk, pX_rd_clk) driven same clock source from FPGA logic avoid complex timing synchronization issues user design.
Modifying Clock Setup
default tool sets clocking infrastructure assuming that user input clock (CLKIN1 PLL) operating memory clock frequency. modify clocking setup create necessary clocks from different input clock frequency adjust user calibration clock frequencies, these parameters adjusted level example user design: Cx_CLKFBOUT_MULT Cx_DIVCLK_DIVIDE Cx_CLKOUT0_DIVIDE (for sysclk_2x) Cx_CLKOUT1_DIVIDE (for sysclk_2x_180) Cx_CLKOUT2_DIVIDE (for user clock) Cx_CLKOUT3_DIVIDE (for calibration clock)
where represents block number. There options determining correct values these parameters: Clocking Wizard found CORE Generator tool determine appropriate parameter settings based desired input output clock frequencies PLL. Choose Manual Selection PLL_BASE primitive
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Chapter Designing with
opening dialog page ensure that used. Only listed parameter values produced Clocking Wizard should transferred back into design. other output from Clocking Wizard needed. Clocking Wizard also determines resulting output jitter from specific configuration that used validate main system clocks against memory device input clock jitter requirements. Refer "PLL" chapter UG382, Spartan-6 FPGA Clocking Resources User Guide verify proper settings listed parameters desired input output clock frequencies PLL. This method requires better understanding aspects such keeping operating frequency within specified limits.
Migration Banking
located left side (for devices with MCBs) lower-left side (for devices with four MCBs) device most flexible design with most situations (see Figure 3-4). predefined pins this location have fewest number "multipurpose" functions, while MCBs right side device tend have pins with more shared functionality.
X-Ref Target Figure
Devices
Figure 3-4:
Four Devices
UG388_c4_04_050409
MCB3 Preferred Location Migration Flexibility
example, some bank pins shared with Byte-wide Peripheral Interface (BPI) pins that used configure Spartan-6 device from parallel flash device. These dual-purpose pins used interface, both. Thus, necessary consider what other components will system, they will interface Spartan-6 device when planning interfaces. MCBs both sides device have pins that shared with global clock (GCLK) pins pins, overall left lower left) side fewest restrictions related usage. addition, possible migrate between Spartan-6 family members same package type (for example, migrate from LX16 device LX25 device same CSG324 package) while maintaining same predefined locations. This applies locations. general, particular device migrate down least device density same package type. Refer Spartan-6 Family Overview more details available devices package types.
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Layout Considerations
Layout Considerations
This section lists layout considerations, which should reviewed before beginning board design based memory interface. Spartan-6 FPGA Designer's Guide should also consulted information regarding proper device decoupling, overall power distribution system design, other general guidelines. Additional references layout signal integrity analysis memory interfaces found Appendix References. trace length calculations assume average electrical delay inch signal trace.
General Guidelines
Only internal layers should used route memory interface signals between FPGA memory devices. Breakout vias connect component balls excluded from this requirement. bottom layer routing considered routing external termination resistors used) when placed fly-by mode after memory component. Memory interfaces without external terminations should have maximum vias. Memory interfaces with external terminations should have maximum three vias. Once signal broken internal signal layer, must complete routing that layer. Terminating signal permits final routing component connection bottom layer board. layer hopping allowed. Overall trace length should minimized. Traces should inches less. Trace widths should mils. Trace spacing should three times trace width. Signals must routed over splits voids. Routing differential pairs adjacent noisy signal lines high-speed switching devices such clock chips should avoided. spacing between differential clocks/strobes other signals same layer should mil. spacing should maintained when using serpentine routing length matching. Differential clocks/strobes routed differential signals. clock pairs must routed same layer with layer changes hops after initial breakout. Series terminations used) should close FPGA possible. Parallel terminations used) should close DRAM possible. Parallel termination resistors should placed bottom layer island. Board designers should ensure that clock lines routed differentially correct trace widths clearances maintained achieve target differential impedance. Routing signals differentially reduces flight time clocks when compared single-ended signals. Because this, most DDR2 design guides recommend that clock signals routed same length longer than address, control, command signals compensate this timing variation.
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Chapter Designing with
Data, Data Mask, Data Strobe Guidelines
Data (DQ), Data Mask (DM), Data Strobe (DQS) signals should receive highest priority (that routed first), because they highest speed signals. signals should routed data group (per byte). Each group should have similar loading routing maintain timing signal integrity. provided spacing should between data group other signals. signals should isolated from other signals avoid crosstalk. There should maximum electrical delay (±150 mil) between DQ/DM associated strobe. data group should referenced GROUND plane. swapping memory interface permitted facilitate layout. Swapping should only done within data group. DQS_N trace lengths should matched (±10 mil). Memory terminations external terminations used) should placed after associated memory component fly-by fashion. 16-bit devices, LDQS/LDQS_N UDQS/UDQS_N trace lengths should matched within electrical delay (±150 mil).
Address, Control, Clock Guidelines
When data groups have been routed, next highest priority differential clock CK_N). clock should routed first because address control trace length matching must referenced differential clock trace length, which might need adjusted layout task proceeds. CK_N trace lengths must matched (±10 mil). trace lengths must matched (±250 mil) maximize setup hold margins. There must maximum electrical delay (±300 mil) between address/control signals associated CK_N differential clock FPGA output. Address control signals referenced POWER plane GROUND plane next this group signals stack-up. avoid crosstalk, address command signals should kept different routing layer from DQS, Differential clock terminations external terminations used) must located close possible load, after clock pads PCB. trace lengths used trace length matching must exclude CLINE length trace from memory ball terminating resistor. Memory terminations should placed external terminations used) after associated memory component fly-by fashion.
Additional Board Design Requirements
addition layout guidelines detailed this section, these board design requirements must implemented:
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Layout Considerations
active-Low Chip Select (CS#) target memory device should connected ground board. Because only supports connections single memory component, does provide signal control input. Contact your memory vendor more information, needed. DDR3 memory devices, RESET signals should each have resistor ground ensure that these signals during memory initialization. DDR2 memory devices, signals should each have resistor ground ensure that these signals during memory initialization. HSWAPEN Spartan-6 device grounded during configuration, internal pull-ups VCCO enabled device pins until configuration completes, including VREF pins associated with usage. VREF level generated from resistor divider, temporary internal pull-ups might elevate level VREF pins during device configuration. designer should ensure that held reset until VREF level returned stable level avoid calibration operation with invalid VREF more information, "Configuration" section "I/O Clock Planning" chapter UG393, Spartan-6 FPGA Design Planning Guide.
Simultaneous Switching Output Considerations
noted Block Diagram Chapter utilizes general blocks (IOBs) associated with predefined locations create external interface memory device. tool automatically configures these locations implement required standard selected memory type (e.g., SSTL18 DDR2, SSTL15 DDR3). Hardware characterization based memory interfaces indicates there Simultaneous Switching Output (SSO) related restrictions when using predefined locations their maximum extent (i.e., maximum number data address pins interface). Refer DS162, Spartan-6 FPGA Data Sheet: Switching Characteristics UG361, Spartan-6 FPGA SelectIO Resources User Guide more information characteristics. When placing signals remaining pins bank, recommended that they used follows: Single-ended output with drive strength, unterminated standards LVCMOS LVCMOS
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Chapter Designing with
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Chapter
Operation
This chapter provides detailed information operation Spartan®-6 FPGA MCB. contains these sections: Startup Sequence Calibration Instructions Addressing Command Path Timing Write Path Timing Read Path Timing Memory Transactions Self Refresh Suspend Byte Address Memory Address Conversion Transaction Ordering Coherency
Startup Sequence
Figure shows startup procedure MCB. After FPGA been fully configured providing system clocks locked, number initialization calibration steps automatically performed prepare normal operation.
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Chapter Operation
X-Ref Target Figure
FPGA Configuration Lock
Phase Calibration Centering
Phase Calibration Input Termination
Normal Operation Begins
Phase Calibration Continuous Tuning
Memory Device Mode Registers Loaded
UG388_c5_01_021910
Figure 4-1: Notes relevant Figure 4-1:
Startup Sequence
soft calibration module implements some aspects Phases calibration. hard calibration logic does perform individual per-bit deskew data bus. Follow guidelines Layout Considerations, page ensure that DQ/DQS board traces properly length matched.
first major operation Phase calibration. this step, soft calibration module measures value external resistor determine desired on-chip Input Termination value several pre-defined pins (e.g., bus). This only occurs user selects Calibrated Input Termination option flow (see "Setting FPGA Options" section UG416, Spartan-6 FPGA Memory Interface Solutions User Guide). Otherwise approximate uncalibrated on-chip termination external termination assumed, this startup step skipped. second major step startup sequence load memory device mode registers with desired parameters. After memory device been configured, Phase calibration occurs. This phase adds delay input path strobes entering FPGA. goal shift strobes into center what becomes Read Data capture window. Once operations startup sequence have completed, enters normal operation. Commands Data loaded into User Interface FIFOs while startup sequence progress, commands executed until calibration completes block enters normal operation. During normal operation, soft calibration module continuously monitors delay values IDELAY element used delay input paths (for more information IDELAY, Spartan-6 FPGA SelectIOResources User Guide). intent measure change delay value voltage temperature variations during operation. shift delay value detected, delay count strobe input paths adjusted keep them centered Read Data capture window. update IDELAY values done during memory REFRESH operations avoid impacting normal data operations controller efficiency. Phase calibration known continuous tuning. Calibration more details phases calibration.
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Calibration
Calibration
achieve optimum signal integrity maximum timing margin (hence, highest performance) memory interface, automatically performs several forms calibration briefly outlined Startup Sequence, page hard calibration logic soft calibration module generated tool EDK) work together implement reliable flexible calibration scheme. Each phase calibration discussed greater detail below. Note: descriptions calibration phases this section assume that C_MC_CALIBRATION_MODE attribute "CALIBRATION" described Table 2-2, page
Phase Input Termination
On-chip termination reduces component count improves signal integrity moving termination close endpoint signal transmission possible. interfaces allow "Calibrated Input Termination" selected pre-defined pins. This feature creates on-chip input termination pins that been calibrated based external resistor, making more precise than when using "Uncalibrated Input Termination" option. soft calibration module uses pins, ZIO, generated tool EDK) perform calibration input termination. required designs. When Calibrated Input Termination used, resistor must connected between ground with value that twice (2R) that desired input impedance (e.g., resistor achieve effective input termination). should left no-connect (NC) designs using Calibrated Input Termination. addition, must within same bank memory interface pins. only required designs using Calibrated Input Termination must no-connect (i.e., connected trace) assigned valid package (i.e., bonded I/O) location within bank. default locations pins found constraints files. soft calibration module relies VREF supply required SSTL standards perform necessary input termination calibration. LPDDR memory does calibrated input termination SSTL type standard therefore does require VREF Phase calibration effectively measures value external resistor programs blocks pins create split termination between VCCO GND. This scheme creates Thevenin equivalent termination VCCO with value shown Figure 4-2. resulting input termination dynamically disabled when driven output (e.g., data during Write transaction) enabled other times properly terminate incoming signals.
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Chapter Operation
X-Ref Target Figure
VCCO
VCCO
Split Termination Implemented
Thevenin Equivalent
UG388_c5_02_050109
Figure 4-2:
Calibrated Input Termination
Phase Centering
optimal performance maximum timing margin, strobe edges must centered Read Data capture window with respect input capture flip-flop. Phase calibration responsible this centering operation. memory device output pins transmit Read Data (DQ) strobes edgealigned FPGA input pins shown Figure 4-3. reliable operation, strobe must delayed with respect bits that captures Read Data away from transition region data bus. During this phase, delay count IDELAY block strobe input path incremented shift internal signal capture flip-flop into center what will become Read Data capture window shown Figure 4-3.
X-Ref Target Figure
External Pin)
External Pin)
Delay
Data
Data
Data
Data
Data
Data
Internal
Internal
IDELAY Shift
Data
Data
Data
Data
Data
Data
Before Phase
Figure 4-3:
After Phase
UG388_c5_03_080409
Phase Calibration Centering
Phase Continuous Tuning
Voltage temperature variations during operation cause changes IDELAY values. Because strobe delayed half period more than bits, uses significantly more IDELAY taps. Therefore, delay value IDELAY elements changes response voltage temperature drift, delay strobe input path sees disproportionate shift relative bits. compensate voltage temperature related shift strobes, Phase calibration runs continuously during normal operation. uses soft calibration module
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Calibration
continuously monitor delay values IDELAY elements used delay input paths. shift delay value detected, delay count strobe input paths adjusted keep them centered Read Data capture window. update IDELAY values done during memory REFRESH operations avoid impacting normal data operations controller efficiency.
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Chapter Operation
Instructions
Table provides detailed descriptions memory instructions implemented MCB. load instruction into Command FIFO User Interface port, 3-bit code instruction clocked into pX_cmd_instr[2:0] inputs rising edge pX_cmd_clk.
Table 4-1:
Instructions Implemented
Code [2:0] Description Memory Write. Writes number data words specified pX_cmd_bl[5:0] memory device beginning byte address specified pX_cmd_addr[29:0]. Prior issuing this instruction, sufficient data must loaded into Write Data FIFO complete transaction. Otherwise data "underrun' condition occurs. This instruction valid write only bidirectional ports. Memory Read. Reads number data words specified pX_cmd_bl[5:0] from memory device beginning byte address specified pX_cmd_addr[29:0]. Prior issuing this instruction, Read Data FIFO must have enough space complete transaction. Otherwise data "overflow" condition occurs. This instruction valid read only bidirectional ports. Memory Write with Auto Precharge. This instruction same Write instruction with auto precharge appended after burst completion. Auto precharge closes DRAM bank where transaction ended. This improve latency applications with more random access patterns that tend jump between rows same bank. Note: looks ahead subsequent transactions. auto precharge skipped following transaction same accessed current transaction. Memory Read with Auto Precharge. This instruction same Read instruction with auto precharge appended after burst completion. Auto precharge closes DRAM bank where transaction ended. This improve latency applications with more random access patterns that tend jump between rows same bank. Note: looks ahead subsequent transactions. auto precharge skipped following transaction same accessed current transaction. Memory Refresh. Prompts issue refresh command memory device. Resets tREFI counter allowing data stream uninterrupted full refresh cycle. This instruction should only used highly customized dataflow structures. general, automatically issues refresh commands own, which periodically results increased latency transactions.
Instruction
Write
Read
Write with Auto Precharge
Read with Auto Precharge
Refresh
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Addressing
Addressing
From User Interface perspective, provides simple sequential byte addressing scheme into physical DRAM. fact that DRAMs store data fixed segments abstracted this scheme, allowing simple SRAM-like address interface. details bank, row, column address bits mapped byte address, refer Byte Address Memory Address Conversion, page Table shows byte address presented User Interface must aligned port width. Depending number bytes port width, certain number address bits must ensure that consecutive addresses fall data word boundaries. write data mask inputs (pX_wr_mask) User Interface used offset starting address byte location. example, begin writing byte address 0x01 when using 32-bit (4-byte) User Interface, byte address presented command port User Interface should 0x00 meet requirements Table 4-2, least significant mask should such that only bytes address 0x01 higher actually written. Table 4-2: Address Requirements Byte Address Alignment
Bytes Data Word Address Requirement pX_cmd_addr[1:0] 2'b00 pX_cmd_addr[2:0] 3'b000 pX_cmd_addr[3:0] 4'b0000
Port Width bits bits bits
also important understand addressing relationship when 32-bit 64-bit ports used together User Interface (see Port Configurations, page 17). 32-bit ports memory appears aligned 4-byte boundaries, while 64-bit ports memory appears aligned 8-byte boundaries. Table shows data words 32bit port into address space single data word 64-bit port. Table 4-3: 32-bit 64-bit Port Address Relationship
32-bit Port Address 0x00 0x04 0x08 0x0C Data [31:0] 0x00 [31:0] [31:0] 0x08 [31:0] [63:32] [63:32] [31:0] Address 64-bit Port Data [31:0]
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Chapter Operation
Command Path Timing
command path User Interface uses simple 4-deep FIFO structure hold pending commands. instruction type, address, burst length requested transaction loaded into this Command FIFO. full flag (pX_cmd_full) signal from command FIFO must command accepted into FIFO when pX_cmd_en asserted during rising edge pX_cmd_clk. Otherwise, command ignored. Figure Figure demonstrate protocol loading command into FIFO.
X-Ref Target Figure
26,520ns p0_cmd_clk p0_cmd_en p0_cmd_instr[2:0] p0_cmd_bl[5:0]
26,530ns
26,540ns
26,550ns
26,560ns
26,570ns
26,580ns
26,590ns
p0_cmd_byte_addr[29:0] 00D6E3FC p0_cmd_empty p0_cmd_full
005AD3FD
cmd_empty deasserted with write first position FIFO registered configured edge when cmd_en asserted. Write user words from byte address 0x005AD3F0.
Write with Auto Precharge user word byte address 0x00EE16FFC.
UG388_c5_05_051409
Figure 4-4:
X-Ref Target Figure
Command Path Timing (Write)
27,050ns 27,060ns 27,070ns
p0_cmd_clk p0_cmd_en p0_cmd_instr[2:0] p0_cmd_bl[5:0] p0_cmd_byte_addr[29:0] p0_cmd_ba[2:0] p0_cmd_ra[14:0] p0_cmd_ca[11:0] p0_cmd_empty p0_cmd_full 00B2D3FC 2CB4 1EADBEEC 2B6F
Read user words from byte address 0x00B2D3FC.
UG388_c5_06_051409
Figure 4-5:
Command Path Timing (Read)
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Write Path Timing
Write Path Timing
write path User Interface uses simple 64-deep FIFO structure hold data preparation Write transaction memory. Similar Command FIFO, full flag (pX_wr_full) from Write Data FIFO must data accepted into FIFO when pX_wr_en asserted during rising edge pX_wr_clk. Otherwise, data ignored. full flag Low, pX_wr_data captured into FIFO rising edge pX_wr_clk. every clock cycle that pX_wr_en asserted, there must valid data pX_wr_data bus. Figure demonstrates protocol loading data into Write Data FIFO.
X-Ref Target Figure
247,100,000ps
247,120,000ps
247.140,000ps
247,160,000ps
247,180,000ps
247,200,000ps
pX_wr_clk pX_wr_en pX_wr_mask[3:0] pX_wr_data[31:0] pX_wr_empty pX_wr_full pX_wr_underrun pX_wr_count[6:0]
0000 C0C0 C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7C7C7
user_empty deasserted with write first position FIFO registered configured edge written FIFO.
deasserted with last data. written FIFO. Count should reflect total number cycles which asserted.
Latency from MemC side read pointer user interface count flexible.
Count jump undefined increments.
UG388_c5_07_051409
Figure 4-6: Write Path Timing pX_wr_underrun signal indicates user that memory controller attempted send more data than present write data FIFO that data which intended memory never reached memory. This condition must avoided guarantee reliable operation. avoid underrun condition, user must guarantee that necessary data available write data FIFO accommodate transaction before committing that transaction command FIFO. count signal (pX_wr_count) provides count number entries FIFO. asynchronicity FIFOs MCB, count signal longer latency than empty full flags. Therefore, this should only used intermediate references watermarks. count will transition immediately with respect FIFO operations committed user. However, take longer operations committed controller apparent count signals than full empty signals. Thus Write Data FIFO FIFO filling, count always reports least many entries FIFO. example, user written eight words into FIFO, count might report eight even though somewhere during process writing FIFO, controller could have started pulling data FIFO. Additionally, controller continues transmit data memory, count could still showing entries FIFO even though FIFO already empty. Write Data FIFO, perfectly suitable count signal almost full flag because FIFO will never full count reporting less than full. However, very important other methods ensure underrun conditions occur.
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Chapter Operation
Read Path Timing
read path User Interface uses simple 64-deep FIFO structure hold data returning from Read transaction. empty flag (pX_rd_empty) from Read Data FIFO used data valid indicator. Whenever pX_rd_empty deasserted, there valid data present pX_rd_data bus. transfer data into FPGA logic from Read Data FIFO, pX_rd_en signal must asserted rising edge pX_rd_clk. pX_rd_data transitions rising edge pX_rd_clk. pX_rd_en signal remain asserted times pX_rd_empty signal used data valid indicator, desired. Figure demonstrates protocol loading data Read Data FIFO.
X-Ref Target Figure
247,320,000ps
247.340,000ps
247,360,000ps
247,380,000ps
pX_rd_clk pX_rd_en pX_rd_data[31:0] XXXX> 03020100 pX_rd_empty pX_rd_full pX_rd_overflow pX_rd_count[6:0]
user_empty deasserted with write first data FIFO coincident with configured edge. Transistions controller side clock domain allow additional latency.
131> 232> 333> 434> 535> 636> 737> XXXXX
Count jump undefined increments.
Count data presented configured edge. Count must through decode logic.
user_empty asserted with read last data FIFO.
presented transparently before first
UG388_c5_08_051409
Figure 4-7:
Read Path Timing
pX_rd_overflow signal indicates user that memory returned more data than fits into read data FIFO that data lost. This condition must avoided guarantee reliable operation. avoid overflow condition, user must guarantee that there enough space read data FIFO accommodate transaction before committing that transaction command FIFO. count signal (pX_rd_count) provides count number entries FIFO. asynchronicity FIFOs MCB, count signal longer latency than empty full flags. Therefore, this should only used intermediate references watermarks. count will transition immediately with respect FIFO operations committed user; however, takes longer operations committed controller apparent count signals than full empty signals. Thus Read Data FIFO FIFO emptying, count always reports less than equal number entries that actually FIFO. example, FIFO contains eight words, count might report eight even though somewhere during process reading from FIFO, controller could have started pushing more data into FIFO. Additionally, controller continues push data into FIFO, count could showing fewer entries FIFO even though FIFO already full even overflowed. Read Data FIFO, count must used with caution there will likely more data FIFO than count reporting, especially flight transactions. Count used almost empty flag, only throttle read datapath pipelines, throttle commands into command FIFO.
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Memory Transactions
Memory Transactions
Executing Write Read transaction requires proper sequencing between command data paths. following subsections demonstrate protocols issuing simple Write simple Read transactions.
Simple Write
implement Write transaction, Write Data FIFO first must loaded with sufficient data complete request dictated burst length value that entered into Command FIFO. Otherwise, underrun condition occurs when transaction tries execute. Figure shows most basic protocol loading Write Data FIFO. data presented pX_wr_data bus, pX_wr_en activated such that data written into FIFO rising edge pX_wr_clk. pX_wr_empty pX_wr_count values reflect fact that data been loaded into FIFO. this example, total three data words bits each) loaded into FIFO.
X-Ref Target Figure
860ns
870ns
880ns
890ns
p0_wr_clk p0_wr_en p0_wr_count[6:0] p0_wr_full p0_wr_data[31:0] 00000000 0C255418 p0_wr_empty
Write data into data path prior asserting write enable. Data written into FIFO positive edge wr_clk where write enable present. Subsequent writes update count immediately data being pulled FIFO. From empty state, empty flag deasserted cycle after data written into FIFO synchronization register, count begins update.
UG388_c5_09_051409
AE82E2D5
62F5AEC5
FB324838
Figure 4-8:
Loading Write Data FIFO
Figure shows protocol entering Write request into Command FIFO after data been loaded into Write Data FIFO. pX_cmd_bl value (b'10 burst length consistent with number data words loaded. When Write request loaded into Command FIFO, automatically executes transaction memory device when arbiter services this port.
X-Ref Target Figure
830ns
840ns
850ns
860ns
870ns
880ns
p0_cmd_clk p0_cmd_en p0_cmd_instr[2:0] p0_cmd_bl[5:0] p0_cmd_addr[29:0]
0000 1DE7 12E1
Write command with instruction, burst length, starting address.
Command address written into FIFO positive edge cmd_clk where cmd_en present.
UG388_c5_10_051409
Figure 4-9:
Entering Write Request into Command FIFO
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Chapter Operation
Simple Read
implement Read transaction, Read Data FIFO must have enough space complete request dictated burst length value that entered into Command FIFO. Otherwise, overflow condition occurs when transaction tries execute. Figure 4-10 shows protocol entering Read request into Command FIFO. pX_cmd_bl value specifies number data words requested from memory. When Read request loaded into Command FIFO, automatically executes transaction when arbiter services this port.
X-Ref Target Figure 4-10
3452ns
3456ns
3460ns
3464ns
3468ns
3472ns
p0_cmd_clk p0_cmd_en p0_cmd_instr[2:0] p0_cmd_bl[5:0] p0_cmd_addr[29:0] 0706 p0_cmd_full p0_cmd_empty
Read command with instruction, burst length, starting address. Command address written into FIFO positive edge cmd_clk where cmd_en present.
UG388_c5_11_051409
39D2
Figure 4-10:
Entering Read Request into Command FIFO
Figure 4-11 shows requested data returning from memory being loaded into Read Data FIFO. data then presented pX_rd_data access FPGA logic. pX_rd_empty pX_rd_count values indicate that data been loaded into FIFO.
X-Ref Target Figure 4-11
2170ns
2180ns
2190ns
dqs[0] dq[7:0] p0_rd_clk p0_rd_en p0_rd_count[6:0] p0_rd_full p0_rd_data[31:0] 20352035 p0_rd_empty
Data read from memory. First valid data word available rd_data bus. Empty deasserts count reflects data FIFO.
UG388_c5_12_051409
20355BE8
747F5BE8
1B693F36
Figure 4-11: Read Data Returning from Memory Device
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Read Latency
transfer data into FPGA logic from Read Data FIFO, pX_rd_en signal activated during rising edge pX_rd_clk shown Figure 4-12. pX_rd_count value updates accordingly.
X-Ref Target Figure 4-12
2190ns
2200ns
2210ns
dqs[0] dq[7:0] p0_rd_clk p0_rd_en p0_rd_count[6:0] p0_rd_full p0_rd_data[31:0] p0_rd_empty
First valid data word available rd_data bus. Count updates reflect data written into FIFO. Rd_en pops data FIFO count decrements.
UG388_c5_13_051409
1B693F36
8822C810
Figure 4-12:
Transferring Read Data into FPGA Logic
Read Latency
Read latency defined number memory clock cycles from when READ command written Command Path FIFO User Interface when corresponding first data word available Read Data Path FIFOs. When benchmarking read latencies, important specify exact conditions under which measurement occurs. Read latency varies based conditions, such Number commands already FIFO pipeline before READ command issued Whether ACTIVATE command needs issued open bank/row Whether PRECHARGE command needs issued close previously opened bank Specific timing parameters memory, such tRAS tRCD conjunction with clock frequency State arbiter multi-port designs Memory device latency Board-level chip-level (for both memory FPGA) propagation delays
Table shows read latencies different situations memory clock frequencies. first scenario, read occurs that already open memory device, meaning precharge activate commands required prior accessing requested data. second scenario, read occurs address location (bank/row conflict). This requires precharge close previously open row, followed activation row, which increases read latency. Both scenarios Table assume single port User Interface with other commands pending (i.e., idle prior read request) memory device with latency equal
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Chapter Operation
Table 4-4:
Read Latency
Read Latency (Memory Clock Cycles)
Read Latency Scenario
MEMCLK MEMCLK (667 Mb/s) (800 Mb/s)
Read from Open Outbound Command Path Memory Latency (CL) Inbound Read Datapath Total Latency Cycles (Time Read from Outbound Command Path Precharge/Activate Memory Latency (CL) Inbound Read Datapath Total Latency Cycles (Time 12.5 Cycles 12.5 Cycles 12.5 Cycles 12.5 Cycles
Self Refresh
self-refresh interface mechanism which user request that memory enter exit self-refresh mode. Self refresh only supported LPDDR, DDR2, DDR3 memories. Self refresh allows memory conserve power while retaining data when memory does need actively transmitting data. self-refresh interface uses simple protocol enter exit self-refresh mode. single mode status (selfrefresh_mode) indicates whether memory currently self-refresh mode. asynchronous selfresh_enter signal sampled core clock, which often running speeds much faster than User Interface clocks. enter self-refresh mode, selfrefresh_enter signal asserted until selfrefresh_mode goes High (see Figure 4-13). selfrefresh_enter signal must remain High stay self-refresh mode. exit mode, selfrefresh_enter signal deactivated (see Figure 4-14). selfrefresh_mode signal then goes indicating that self-refresh mode been exited. selfresh_enter signal must maintained steady state condition because glitch line interpreted request. general, these signals should registered user before going guarantee that these signals only switch when desired. Spartan-6 device into suspend mode while external memory self-refresh mode further reduce system power consumption. However, Spartan-6 device cannot reconfigured while memory device self-refresh mode. Reconfiguring causes loss state MCB, preventing proper exiting from self-refresh mode.
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Suspend
X-Ref Target Figure 4-13
3140ns
3150ns
3160ns
3170ns
3180ns
3190ns
3200ns
3210ns
sysclk90 usrclk selfrefresh_enter selfrefresh_mode
UG388_c5_14_050709
Figure 4-13:
X-Ref Target Figure 4-14
Entering Self-Refresh Mode
3300ns
3400ns
3500ns
3600ns
3700ns
3800ns
sysclk90 usrclk selfrefresh_enter selfrefresh_mode
UG388_c5_15_050709
Figure 4-14:
Exiting Self-Refresh Mode
Suspend
This section describes recommended methods using Suspend Mode capabilities Spartan-6 devices with designs containing MCB-based interface.
Suspend Mode without DRAM Data Retention
cases where important retain data stored DRAM device, Suspend simply brought active-High state enter suspend mode. Prior bringing Suspend High, should placed reset bringing async_rst active-High state. While suspend mode, held reset. When Suspend brought exit suspend mode, held reset until PLL_LOCK signal goes active, indicating stable clock source MCB. then exits reset initializes DRAM using same startup sequence that occurs during initial power-up system reset MCB. DRAM data should considered invalid when exiting suspend mode this scenario.
Suspend Mode with DRAM Data Retention
cases where DRAM data must retained, SUSPEND_SYNC primitive must used combination with Self Refresh interface implement suspend mode properly. SUSPEND_SYNC primitive used ensure that puts DRAM device into self-refresh mode (see Self Refresh section) retain state prior putting FPGA into suspend mode. Figure 4-15 shows SUSPEND_SYNC primitive connected Suspend logic interface implement suspend mode with DRAM data retention. timing diagram Figure 4-16 illustrates signal relationships required successfully take FPGA into suspend mode this scenario.
Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
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Chapter Operation
X-Ref Target Figure 4-15
SUSPEND_SYNC
Suspend
(MIG Wrapper)
selfrefresh_enter selfrefresh_mode
Suspend Logic
SREQ SACK
UG388_c4_15_021610
Figure 4-15: SUSPEND_SYNC Connections
X-Ref Target Figure 4-16
SUSPEND SREQ selfrefresh_enter selfrefresh_mode SACK PLL_lock
UG388_c4_16_021910
Figure 4-16:
Suspend Mode Timing Diagram
response active-High Suspend pin, SUSPEND_SYNC primitive sends suspend request (SREQ) signal indicate desire enter suspend mode. SREQ signal connected directly selfrefresh_enter input top-level EDK) wrapper, from which routed soft calibration module. soft calibration module completes current operations before forwarding self-refresh request from there memory device. Once successfully placed DRAM device self-refresh mode, selfrefresh_mode output goes High. This signal directly connected suspend acknowledge (SACK) input SUSPEND_SYNC primitive, indicating that FPGA placed suspend mode. PLL_lock signal lost when Suspend occurs. When Suspend goes exit suspend mode, SREQ therefore selfrefresh_enter signals inactive, FPGA emerges from Suspend state. PLL_lock signal initially tries lock onto incoming clock again. However, because selfrefresh_mode signal active, this PLL_lock condition does cause system reset normally would. When achieves lock, soft calibration module forwards request leave self-refresh mode from there memory device. When DRAM device successfully exited self-refresh mode, selfrefresh_mode signal returns state, normal operation resume with loss DRAM data.
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Byte Address Memory Address Conversion
Additional Suspend Mode Requirements
While Spartan-6 device suspend mode, some critical signals driving DRAM device must maintained known state. When using suspend mode with memory devices that support self-refresh mode, output Spartan-6 device should have constraint added retain last state during Suspend state. statement like following should added user constraints file (UCF):
"mcbx_dram_cke" SUSPEND="drive_last_value";
This ensures that DRAM device executes self-refresh mode properly. addition, DDR3, reset signal DRAM should have similar constraint added file follows:
"mcbx_dram_reset_n" SUSPEND="drive_last_value";
This prevents unintentional reset DRAM device during suspend mode.
Byte Address Memory Address Conversion
From User Interface perspective, provides simple sequential byte addressing scheme into physical DRAM. fact that DRAMs store data fixed segments abstracted this scheme, allowing simple SRAM-like address interface. automatically converts User Interface byte address into necessary row, bank, column address signals required particular memory device configuration. complete abstraction physical memory addressing details, manages automatic bank crossing transparent User Interface. memory standard, width, density affect User Interface byte address bits respective row, bank, column address bits. Memory device selection tool results passing necessary parameters that create proper address assignments. Table 4-5, page shows assignments made based given memory device configuration. These mappings based JEDEC standard addressing schemes. shown Table 4-5, memory width (x4, x16) affects mapping byte address physical address. devices, column address always external address create byte-aligned addressing into memory device (User Interface maps column address Because devices native byte addressing, uses direct mapping byte address physical address (User Interface maps directly column address devices, mapping shifted create address alignment two-byte boundary (User Interface maps column address supports general schemes mapping User Interface byte address memory interface physical address: ROW_BANK_COLUMN BANK_ROW_COLUMN. Port Configuration page tool allows selection scheme most suited particular application (see "Creating Design" section UG416, Spartan-6 FPGA Memory Interface Solutions User Guide). Table shows mapping only ROW_BANK_COLUMN addressing. BANK_ROW_COLUMN addressing, position Bank address groups switched such that Bank address bits position with respect User Interface byte address. Column address mappings remain unchanged. ROW_BANK_COLUMN addressing scheme means that transaction occurring over sequential address space (for example, long data burst), automatically opens same next bank DRAM device continue transaction when existing reached. This reduces overhead caused closing
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Chapter Operation
down current (Precharge command) opening another same bank (Activate command) continue transaction. ROW_BANK_COLUMN addressing scheme well suited applications that require bursting large data packets sequential address locations where efficiency gained striping data across multiple banks. contrast, BANK_ROW_COLUMN addressing means that crossing boundary results closing that opening another within same bank. Bank address bits reside position User Interface byte address used switch between major address spaces that reside different banks. example, microprocessor microcontroller based application that tends have shorter, more random transactions block memory period time then jump another block (that bank) might prefer this address mapping scheme. specifics application determine whether ROW_BANK_COLUMN BANK_ROW_COLUMN should chosen address scheme. Note: When referring Table 4-5, user must ensure that requirements listed Table 4-2, page followed preserve proper data word boundaries.
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Spartan-6 FPGA Memory Controller UG388 (v2.3) August 2010
Byte Address Memory Ad
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