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PRACTICAL CONSIDERATIONS HIGH PERFORMANCE MOSFET, IGBT GATE DRIVE CIRCUITS BILL ANDREYCAK
INTRODUCTION switchmode power supply industry's trend towards higher conversion frequencies justified dramatic improvement obtaining higher power densities. these frequencies pushed towards beyond megahertz, Mosfet transition periods become significant portion total switching period. Losses associated with overlap switch voltage current only degrade overall power supply efficiency, warrant consideration from both thermal packaging standpoint. A/though brief, each Mosfet switching transitions further reduced driven from from high speed, high current totem-pole driver designed exclusively this application. This paper will highlight three such devices; UC1708 UC1710 high current Mosfet driver ICs, UC1711 high speed driver. Other Mosfet driver typical application circuits featured UNITRODE Application Note
U-118. EFFECTIVE GATE CAPACITANCE
Mosfet input capacitance (Ciss) frequently misused load represented power mosfet gate driver reality, effective input capacitance Mosfet (Ceff) much higher, must derived from manufacturers' published total gate charge (Qg) information. Even specified maximum values gate charge parameter accurately reflect driver's instantaneous loads during given switching transition. Fortunately, manufacturers provide curve gate-tosource voltage (Vgs) versus total gate charge their datasheets. This will segmented into four time intervals interest switching transition. Each these will analyzed determine effective gate capacitance driver requirements optimal performance. Inadequate gate drive generally result
adjusting gate charge numbers accordingly. Both turn-on turn-off trasnsitions shown with respective drain currents drain-to-source voltages.
Gate voltage time
TOTAL GATE CHARGE (Qg)
First, typical high power Mosfet "Gate Charge versus Gate-to-Source Voltage" curve will examined. IRFP460 device been selected this curve applicable most other devices
INTERVAL t0-t1 time required bring gate voltage from zero threshold Vgs(th) expressed delay time. Both voltage across switching device current through uneffected during this interval. INTERVAL t2-t3
Beginning time drain-to-source voltage starts fall which introduces "Miller" capacitance effects (Cgd) from drain Mosfet gate. result noticeable plateau gate voltage waveform from time until while charge equal admitted. here that most drive circuits taxed their limits. interval concludes time when drain voltage approaches minimum. INTERVAL t3-t4 During this final interval interest gate voltage rises from plateau prior region final drive voltage. This increasing gate voltage decreases Rds(on), Mosfet drain-to-source resistance. Bringing gate voltage above volts, however, little effect further reducing Rds(on).
INTERVAL t1-t2 This period starts time when gate voltage reached Vgs(th) drain current begins flow. Current continues rise until essentially reaching final value time While this occurred, gate source voltage also been increasing. drain-to-source voltage remains unchanged Vds(off). Power Mosfet wasted simultaneous overlap voltage current.
SUMMARY INTERVAL WAVEFORMS DRIVER LIMITATIONS INTERVAL to-t1 t1-t2 t2-t3 t3-t4 Vgs(t) 0-threshold thrs-plateau V(plateau) rising TURN-OFF WAVEFORMS Gate voltage time
Vds(t) Vds(off) Vds(off) falling lon*Rds(t)
DRIVER LIMITATIONS Slew rate (dv/dt) Slew rate (dv/dt) Peak current l(max) Peak dv/dt
rising lon(dc) lon(dc)
INTERVAL t4-t3 beginning turn-off cycle described delay from final drive voltage (Vgs(on)) plateau region. Both drain voltage current waveforms remain unchanged while devices effective resistance (Rds(on)) increases gate voltage decreases. INTERVAL t3-t2 Once plateau reached time gate voltage remains constant until time Gate charge Miller effect being removed, amount equal Qgd. drain voltage rises state amplitude, Vds(off), while drain current continues flow equals l(on). This lossy transition ends time INTERVAL t2-t1 Once Miller charge completely removed, gate voltage reduced from plateau threshold voltage causing drain current fall from l(on) zero. Transition power loss ends time when gate threshold crossed.
Figure intervals during turn-off basically same those described turn-on, however sequence corresponding waveforms reversed.
INTERVAL This brief period little interest turn-off sequence since device time
SUMMARY INTERVAL WAVEFORMS DRIVER LIMITATIONS INTERVAL t4-t3 t3-t2 t2-t1 t1-t0 Vgs(t) falling V(plateau) Vplat-thrsh thrsh-0
Transition Power Loss
Vds(t) Ion" Rds(t) falling Vds(off) Vds(off)
DRIVER LIMITATIONS Peak dv/dt Peak Current (max) Slew rate (dv/dt) Slew rate (dv/dt)
Ion(dc) lon(dc) falling
Ploss This relationship displays need fast transitions switching frequency, significant concern megaHertz. Minimization transition power loss achieved with high current drivers.
During each turn-on turn-off sequences power lost switching device's simultaneous overlap drain source voltage drain current. Since both voltage current externally controlled application, driver only reduce power losses making transition times brief possible. Minimization these losses simply requires competent driver able provide high peak currents with high voltage slew rates. review prior transition waveforms indicates that power lost between times While serves pivot point which waveform rising falling, equations show irrelavent power loss equation. purpose brevity, waveform interest approximated triangle while other waveform constant. duration between times defined transition time, t(tran), with conversion period t(period) During intervals from l(on) Vds(off) t(2-1) Ploss t(period)
Vds(off) l(on) *t(3-2)
Each division transition interval associated gate charge which derived from manufacturers datasheets. Since there three basic shapes curve, interval from lumped together with that period. most large geometries, amount charge span negligible anyway. This simplification allows easy calculation effective gate capacitance each interval along with quantifying peak current required traverse given amount time. Charge represented product capacitance multiplied voltage, current multiplied time. effective gate capacitance determined dividing required gate charge (Qg) gate voltage during given interval. Likewise, current necessary force transition within specified time obtained dividing gate charge desired time. (effective) delta delta
Ploss t(period) Combining equations with t(tran) t3-1 results loss Vds(off) l(on) t(trans) Ploss t(period) Since these loses incurred twice percycle, first turn-on then again turn-off, result doubling power loss.
Ig(required) delta t(transition)
UC1710 "MILLER KILLER"
High peak gate drive currents desirable paralleled applications, typical high power switching section power factor correction stage. Dubbed "the Miller Killer", UC1710 boasts guaranteed peak output current. This hefty driver current minimizes parasitic "Miller" effects which would otherwise result poor transi-
tion performance. Higher currents possible with this driver, however limiting factor soon becomes parasitic series inductance package layout interconnection nH/inch. type arrangement board layout absolute MUST realize this device's full potential. 1710 BLOCK DIAGRAM 1708 BLOCK DIAGRAM
UC1708 unique blend high speed attributes UC1711 along with higher peak current capability UC1710. This dual noninverting driver accepts positive TTL/CMOS logic from control circuits provides peak outputs from each totem pole. Propagation delays under nanoseconds while rise fall times typically nanoseconds into nanoFarads. output stage design float" version which incorporates self biasing technique hold outputs during undervoltage lockout, even with removed. package, device features remote ENABLE SHUTDOWN function addition seperate signal power grounds. ENABLE function places device current standby mode SHUTDOWN circuitry high speed logic directly outputs.
UC1710 "no-load" rise fall times nanoseconds less) which change significantly with loads under nanoFarads. It's also specified into load capacitance nanoFarads, roughly equivalent what represented three paralleled "size devices. Propagation delays brief with typical values specified nanoseconds from either input percent change output voltage.
UC1708 1710 1711 PERFORMANCE COMPARISON TABLE PARAMETER Propagation Delay t(plh) input output Raise time t(tlh) rise Propagation Delay t(phl) input output Fall Time t(thl) fall LOAD
Optimization driver this type application difficult. general, MOSFET driver output stage designed switch fast manufacturer's process will allow.
Using table above, driver output slew rates average current delivered calculated. figures compared lower power opamps comparators gain perspective relative speed these high performance drivers. UC1708 delivers output slew rates (dv/dt) order volts microsecond, average load currents under amp, depending load. high speed UC1711 exhibits similar characteristics under loaded conditions, achieve load slew rate over 1700 volts microsecond nearly volts nanosecond. higher power applications, UC1710 "Miller Killer" will produce average current amps slew rates volts microsecond. With lighter loads will deliver average current amps slew rate approximately volts microsecond. most applications, UC1710 will easily outperform "homebrew" discrete mosfet transistor totem pole drive techniques. Each device this generation MOSFET drivers significantly more responsive than earlier counterparts given application whether it's higher speed (UC1711), higher peak current (UC1710) combination both (UC1708).
There numerous tradeoffs involved design these drivers beyond obvious choices number outputs peak current capability. Crossconduction defined conduction current through both totem pole transistors simultaneously from ground. unproductive loss output stage which results unnecessary heating driver wasted power. Cross conduction result turning transistor before opposing fully off, compromise often necessary minimize input output propagation delays. interesting observation that cross-conduction less concern with large capacitive loads (FETs) than with unloaded lightly loaded driver outputs. capacitive load will reduce slew output stage, slowing down dv/dt. This causes portion cross conduction current flow from load, rather than from input supply through driver's opposite output transistor. power loss associated with drivers inherent cross-conduction unchanged with large capacitive loads, however caused "shoot-through" supply current.
previously demonstrated, ideal MOSFET gate drive unique blend both high speed switching high peak current capability. Initially, high speed required bring gate voltage from zero plateau, current low. Once plateau intersected, driver voltage fairly constant, must switch modes. Instantly, driver current snaps maximum charge injected overcome FET's Miller effects. Finally, combination both high slew rate high current needed complete gate drive cycle. turn-off this sequence reversed, first demanding both high slew rate high current simultaneously. This followed plateau region which limited only maximum driver current. Finally, there high speed discharge gate zero volts.
There variety applications MOSFET drivers each with unique speed peak current requirements. Most general purpose drivers feature peak totem-pole outputs which deliver rise fall times approximately nanoseconds into nanoFarad. Propagation delays neighborhood nanoseconds, making these devices quite adaptable numerous power supply motor control applications. These specifications used comparison those series higher speed higher current devices, specifically, UC1708, UC1710 UC1711 power MOSFET drivers. Each member this group "third" generation driver features significant performance improvements over their predecessors with parameter optimized specific applications.
MOSFET DRIVER FEATURE PERFORMANCE OVERVIEW TABLE
Feature Number outputs Peak output current (per output) Noninverting input-output logic Inverting input-output logic Maximum supply voltage Typical supply current (1.) Remote Enable Shutdown Input Seperate grounds, signal power Seperate pins package package TO-220 package
Note Typical plus current measured 200KHZ, duty cycle load Note Using device's other input Note Package dependent
UC1711 BLOCK DIAGRAM
power supply industry's trend towards higher power densities thrust switching frequencies well beyond megaHertz many medium power systems. With microsecond total conversion period, less, switching transitions should order tens nanoseconds yield high efficiency. Additionally, propagation delays from driver input output should around nanoseconds quick response.
UC1711 device features typical propagation delays three nanoseconds load, depending transition. Coupled with dual peak totem-pole outputs, this device optimized high frequency drive applications. Schottky transistor construction only fast, radiation tolerant well.
GATE DRIVE POWER CONSIDERATIONS
gate power utilized charging discharging capacitor frequency P(cap) Substituting gate charge capacitance multiplied voltage (Q=C*V) this equation results P(gate) gate power required verses size switching frequencies tabulated some common applications Table Table transforms this power into driver input current nominal volt bias.
Perhaps most popular misconception power supply industry that gates require power from auxiliary supply that both turn-on turn-off miraculously power free. Another fallacy that driver consumes measured supply current, ICc, none used transition gates. Obviously, both these statements false. reality, power required gate itself quite substantial high frequency applications. Calculation this begins listing specified total gate charge device,
GATE POWER (mW) SWITCHING FREQUENCY SIZE
SWITCHING FREQUENCY (kHz) SIZE SIZE SIZE SIZE SIZE SIZE SIZE Table
SUPPLY CURRENT (mA) SWITCHING FREQUENCY SIZE
SWITCHING FREQUENCY (kHz) SIZE SIZE SIZE SIZE SIZE SIZE
driver output stage modelled resistance respective auxiliary supply rail driving ideal capacitor. power used charge discharge MOSFET gate capacitor completely transferred into heat driver. This gate power loss adds driver's power loss resulting driver power dissipation equal it's input voltage, Vcc, multiplied gate driver currents, ICC. This calculated determined empirically measuring driver input voltage current.
This term then added ambient temperature yield resulting junction temperature, driver thermally attached heatsink "cold plate", then thermal impedance from device junction it's package case, theta (Ojc), used determine thermal rise. Likewise, this thermal rise added heatsink temperature determine junction temperature. either case, maximum junction temperature (tj(max)) should determined checked against device's absolute maximum specification. Average supply currents each three drivers interest varies primarily with switching frelisting each driver quency. Rather than independently, rough approximation milliamps will used driver current, regardless specific device utilized switching frequency. addition, typical supply voltage volts results power dissipation driver itself milliwatts. calculated gate power Table been added estimated 300mW device power formulate Table driver total power dissipation. This particular interest selecting driver package pin, TO-220, etc.) heat sink determination specific maximum junction temperature, rise. Typical junction temperature rises frequency size package, recommendations shown table
Proper package selection and/or device heatsinking only method available insure safe operating junction temperature, IC's specified graded various junction temperature ranges, priced accordingly. precaution, should noted that using device outside tested temperature range result poor performance, parameters which outside their specifications, quite possibly operation all.
junction temperature driver obtained first calculating device's thermal rise above ambient temperature. This obtained multiplying average input power (Vin*lin) device's thermal impedance air, theta (Oja).
AVERAGE POWER DISSIPATION (mW) FREQUENCY SIZE
SWITCHING FREQUENCY (kHz) SIZE SIZE SIZE SIZE SIZE SIZE SIZE Table
1MEG 1.3w 2.4W 3.1w
SWITCHING FREQUENCY (kHz) Table
P(diss) 500mW DIL, rise DIL, rise DIL, rise P(diss) 500mW (using heatsink) DIL, rise DIL, rise P(diss) 500mW TO-220 recommended
SIZE SIZE SIZE SIZE SIZE SIZE
HIGH POWER APPLICATIONS
Most high power applications require "monster" MOSFETs several large FETs parallel each switch. Generally, these medium frequency applications (less than 200kHz) where obtaining Rds(on) primary concern minimize switch loss. uncommon find two, three even four large devices used parallel, although some these combinations unlikely from cost versus performance standpoint. MOSFET ARRANGEMENT SIZE SIZE SIZE SIZE 3XSlZE4(1) SIZE Rds(on) effective 0.85 0.40 0.27 0.425 0.283 0.213 Qg(nC) total
Table seven displays individual device characteristics several popular parallel arrangements. Listed descending order Rds(on) room temperature total gate charge required. This will ultimately used determine gate drive current Table total power dissipation Table driver recommendation Table various applications.
PARALLELED MOSFET CHARACTERISTICS TABLE
MOSFET ARRANGEMENT SIZE SIZE SIZE SIZE SIZE SIZE
Rds(on) effective 0.200 0.135 0.133 0.100 0.090 0.068
Consider another selection Consider "Monster"
AVERAGE SUPPLY CURRENT (mA) FREQUENCY SELECTION
SWITCHING FREQUENCY (kHz) ARRANGEMENT SIZE SIZE SIZE SIZE mohm
*Includes 25mA driver supply current
POWER DISSIPATION (mW) FREQUENCY APPLICATION SWITCHING FREQUENCY (kHz) ARRANGEMENT SIZE SIZE SIZE SIZE mohm Table 1.2W 1.0W 1.1W 1.7W
1.2W 1.7W 2.1W
Includes 300mW driver dissipation
DRIVER PACKAGE SELECTION GUIDE Selection Guide rise PLCC with heatsink. TO-220. TO-220 with heatsink ARRANGEMENT SIZE SIZE SIZE SIZE mohm Table UC1710 DRIVER PERFORMANCE Although capacitive nature, "Miller" effects demands driver differ significantly than true capacitor load previously described. Table shows typical response UC1710 "Miller Killer" driving single APT5025BN (size device paralleled MOSFET combinations reference. SWITCHING FREQUENCY (kHz)
UC1710 RISE, FALL DELAY TIMES LOADS TEST CONDITIONS LOAD APT5025 APT5025 THREE APT5025
PERFORMANCE COMPARISONS "HOMEBREW" TOTEM-POLES INTEGRATED CIRCUIT DRIVERS
input drive waveform above Vgs(th) device below that device. technique minimize cross conduction peak current some resistance between FETs. While this does minimize "shoot-through" current, also limits peak current available load. This somewhat defeats purpose using MOSFETs first place deliver high currents. resistor serves additional purpose damping gate drive oscillations during transitions. practical application, resistors used place with center-tap connecting gate, load shown figure
prior lack "off-the-shelf" high current high speed drivers prompted many design their gate drive circuits. Traditionally, NPN-PNP emitter follower arrangement been used lower frequency applications shown Figure
Figure higher speed applications, channel pair used shown figure circuit configured with channel upper side switch simplify auxiliary bias. Otherwise, gate drive potential volts above auxiliary bias would required. Unfortunately, this configuration drawbacks First, leads inverting logic flow from driver input output, complicating matters especially during power-up power-down sequences. Without clever undervoltage lockout circuit main power switch will tend auxiliary supply voltage raised lowered while OFF. Cross conduction both FETs unavoidable with this configuration difference between gate threshold voltages each device. Both channel devices cross conducting while their
performance circuit figure evaluated compared that UC1710 driver into nanoFarad load. size three type size channel device were connected series with one-half resistors limit shoot-through current. These FETs were driven from UC1711 dual driver which deliver peak gate drive currents rapid transitions. results this test shown figure
Driver Performance into 30nF load
Lines: solid=UC3710, dashed=discrete Figure VERT: 5V/DIV: HORIZ: nS/DIV
test results indicate very similar performance into this load from either technique. Obviously, "homebrew" approach utilizes total three devices comparison single UC1710 driver obtain essentially same high speed performance. Additionally, cost channel alone exceed price UC1710 device,
mention difference board real estate. final note, discrete approach required over milliamps more supply current than single UC1710 driver increase supply current twenty percent. Results this test shown figures
RISE FALL TRANSITION PERFORMANCE INTO RISE TIMES (Fig 11.) FALL TIMES (Fig 12.)
PHOTO SCALES (BOTH): VERT=2V/DIV, HORIZ=10 nS/DIV LINES: SOLID UC3710; DASHED DISCRETE CIRCUIT FIGURE
POWER DEVICES IGBTs MCTs: While existing generations
power MOSFETs continue enchanced lower RDS(on) faster recovery internal diodes, alternative devices have also been introduced. Among most popular, viable high voltage high power applications IGBTs (Insulated Gate Bipolar transistors) MCTs (MOS Controlled Thyristors). Although frequently drawn structure, IGBT actually resembles bipolar transistor with internal device control base drive. Indicative description, essentially structure also utilitzing drive stage. Both devices offer significant cost advantages over MOSFETs given power capability.
MOSFET, IGBT Gate Drives: There
numerous reasons driving MOSFET gate
negative potential during device's state. Degradation gate turn-on threshold over time especially following high levels irradiation amongst most common. However, with IGBTs, important concern ability keep device following turnoff with high drain current flowing. larger IGBT's with ratings Amps, inductive effects caused device's package alone "kick" effective gate-to-emitter voltage positive several Volts even with gate shorted emitter package terminals Actually, this result high current flowing emitter lead (package) inductance which less than 1nH. corresponding voltage drop changes polarity turn off, thus pulling emitter below gate, ground. high enough, fast turn will followed parasitic turn-on
switch, potential destruction semiconductor. Applying correct amplitude negative gate voltage insure proper operation under these high current turn-off conditions. Also, negative bias protects against turn-on from high dv/dt related changes that could couple into gate through "Miller" capacitance.
capability. Recently introduced parts boast maximum ratings megawatt, ideal large industrial motor drives high power distribution-even substation level. These devices essentially controlled SCRs intended frequency switchmode conversion. They will most likely replace high power discrete transistors, Darlingtons SCRs because their higher efficiency lower cost. Gate Charge Effective Capacitance with Negative Bias: While several MOSFET IGBT manufacturers recommend negative gate voltages device's state, publish curves information about gate charge characteristics when gate below zero Volts. This complicates gate drive circuit design each IGBT, MOSFET switch must evaluated user over ranges operation conditions. test fixture shown Figure used provide empirical generalizations devices interest. switched constant current source/sink been configured using simple dual op-amp drive "constant" device under test (DUT). Gate voltage versus time monitored which provides exact gate charge requirements given device. application specific requirements also accommodated modifying test circuit with external circuitry. Negative Gate Charge Empirical Data: Several MOSFET, IGBT gate charge measurements were taken establish general characteristics with negative gate charge effective capacitance during this third quadrant operation calculated compared first quadrant specifications from manufacturers data sheets. Figure demonstrates general relationships gate charges comparison. Both IGBT have similar negative bias gate charge requirements with applied positive bias. MOSFET, however, exhibits slightly reduced gate charge negative bias region, somewhere between percent positive bias charge. MOSFET's more significant "Miller" effect first quadrant responsible this since higher effective capacitance during plateau region does occur with negative bias.
Figure IGBT Diagrams Unlike power MOSFET switches, IGBT transconductance continues increase with gate voltage. While most MOSFET devices peak with about Volts gate, IGBT performance steadily improves suggested Volt maximum gate voltage. Typically, most IGBT manufacturers recommend negative drive voltage between -15V. Generally, most convenient derive negative voltage equal amplitude positive supply rail, ±15V common. gate charge required IGBT (for given voltage current rating) noticeably less than that MOSFET. Part this better utilization silicon which allows IGBT considerably smaller than counterpart. Additionally, IGBT (being bipolar transistor) does suffer from severe "Miller" effects devices, easing drive requirements given application. However, because their advantages, most available IGBTs have fairly high gate charge demands simply because their greater power handling capability. contrast, MCTs (MOS Controlled Thyristors) exhibit highest silicon utilization level among power switching devices. While relatively market, these devices quickly gaining acceptance very high power (above several kilowatts) applications because their high voltage (1000V) high current 1000A)
Figure Gate Charge Test Circuit Total Gate Power Negative Drive Voltage Applications: previously presented gate power equations still apply, however they must modified include additional charge requirements negative supply sake simplicity, voltage. multiplication factor used recalculation exact figures. When identical amplitudes positive negative supply voltages used, example ±15V, then gate power utilized simply multiplied factor two. This completes process IGBTs MCTs. total MOSFET gate charge, other hand, should only multiplied factor 1.75 accommodate reduced negative bias demands. Additionally, negative supply voltage different than positive rail voltage used, example then scaling factor must adjusted accordingly. this case, total gate power would (-5/-15) 1.33 times initial 0-15V gate power IGBTs MCTs. negative drive voltage scaling factor (-5/15) would multiplied index MOSFET were used instead IGBT MCT. This would result 1.23 1.25 times increase over initial (0-15V) gate power demand.
Figure Gate Charge Comparison High Transition
Figure Gate Drive Comparison High Transition
cessfully conquer challenges obtaining rapid transitions MOSFET gate drive circuits.
need higher speed higher current driver become increasingly apparent power conversion switching frequencies pushed towards beyond megaHertz. Likewise, quest higher overall efficiencies resulted creation large, even "monster" size MOSFET geometries. These industry trends have stimulated development innovative MOSFET driver ones which would significantly outperform their predecessors, including discrete versions. generation high speed high current MOSFET drivers been presented. Each optimized unique blend these attributes, UC1708, UC1710 UC1711 devices sucHIGH CURRENT DRIVER CIRCUITS
UNITRODE Application Note U-118, "New Driver IC's Optimize High Speed Power MOSFET Switching Characteristics", UNITRODE LINEAR DATABOOK, INTERNATIONAL RECTIFIER Application Notes AN-937, AN-947 Datasheets, I.R. HEXFET Power MOSFET Designers Manual HDB-4 ADVANCED POWER TECHNOLOGY Databook 1989
High Speed Power Driver (Single ended) 1.5A High
TotemPole Output Speed MOSFET Compatible Quiescent Current Cost Package
Dual High Current MOSFET Compatible Output Driver
Dual Uncommitted High Current MOSFET Compatible Output Driver Dual Non-Inverting Power Driver
Dual, 1.5A Totem Pole Outputs Parallel Push-Pull Conversion (1706Series) Internal Overlap Protection Analog, Latched Shutdown High-Speed, Power MOSFET Compatible Thermal Shutdown Protection Operation Quiescent Current Peak Current Totem Pole Output Operation Rise Fall Times Propagation Delays Thermal Shutdown Under-Voltage Protection High-Speed, Power MOSFET Compatible Efficient High Frequency Operation Low-Cross-Conduction Current Spike Enable Shutdown Functions Wide Input Voltage Range Protection 1.5A Source/Sink Drive Compatible with 0026 40ns Rise Fall into 1000pF Quiescent Current Peak Current Capability 40ns Rise Fall Times 40ns Delay Times (1Nf) Saturation Voltage 25nS Rise Fall into 1000pF 15nS Propagation Delay 1.5Amp Source Sink Output Drive Operation with Supply High-Speed Schottky Process 8-PIN Mini-DIP Package Radiation Hard Fully Isolated Drive High Voltage 100% Duty Cycle 600kHz Carrier Capability Local Current Limiting Feature
Dual High Speed Driver
High CurrentSpeed Driver
Dual Ultra High Speed Driver
UC3724 UC3725 (PAIR)
Isolated High Side Drive N-Channel Power MOSFET Gates
CORPORATION CONTINENTAL BLVD. MERRIMACK, 03054 TEL. (603) 424-2410 (603) 424-3460
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