TXC-02020 TXC-02021 STS-1

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Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 (44-Pin) ARTE: TXC-02021 (68-Pin) DATA SHEET Preliminary FEATURES
Single device line interface STS-1 Single power supply Meets `crossconnect frame' mask requirements Adaptive equalization cable Input dynamic range 1.0V) Meets approved DS3/STS-1 jitter requirements Selectable B3ZS line encoding/decoding Line terminal side insertion Full loopback capability Coding Violation Excessive Zeros monitors Loss signal detection (per T1/M1 Spec) On-device line buffer/filter optional line build-out bypass Power-down mode Available plastic package sizes: 44-pin (ART) 68-pin with Extended features (ARTE) Meets ANSI Standard T1.102-1993
Advanced DS3/STS-1 Receiver/Transmitter (ART) device performs receive transmit line interface functions required transmission (44.736 Mbit/s) STS-1 (51.840 Mbit/s) signals across coaxial interface. operates from single supply with minimum number (passive) external components. Performance monitoring, loopbacks, generation B3ZS encoding/decoding functions included. single-device solution interfacing STS-1 signals STS-X crossconnect frames, meets applicable ANSI, BellCore, interconnections specifications wide range system applications. ARTE (Extended features) version nine additional input output pins.
PRELIMINARY information documents contain information products sampling, pre-production early production phases product life cycle. Characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
APPLICATIONS
Multiplexers DSX/STSX performance monitoring cross connects Fiber optic microwave radio terminals High speed DS3/STS-1 transmission application
LINE SIDE
TERMINAL SIDE
Line Inputs
Frame
ARTE
Terminal Outputs
Line Outputs
Advanced DS3/STS-1 Receiver/Transmitter
Terminal Inputs
Control Inputs
Status/Performance Monitors
Document Number: TXC-02020-MB March 1995
U.S. Patent 5,119,326 U.S. and/or foreign patents issued pending Copyright 1995 TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
TranSwitch Corporation
Progress Drive Shelton, 06484 Tel: 203-929-8810 Fax: 203-926-9453
PRELIMINARY
TABLE CONTENTS
ARTE
SECTION PAGE Block Diagram Block Diagram Description Diagrams Descriptions Absolute Maximum Ratings Thermal Characteristics Power Requirements Input, Output Parameters Timing Characteristics Operation .20-32 Receiver Input Requirements Interfering Tone Tolerance Receiver Output Specifications Transmitter Specifications Loopback Control Signal Arbitration Power-Down Mode Jitter Transfer Jitter Generation Jitter Tolerance Physical Design Packaging Ordering Information Related Products Standards Documentation Sources List Data Sheet Changes
LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 9.1. Figure 9.2. Figure 9.3. Figure 9.4. Figure 10a. Figure 10b. Figure Figure 12a. Figure 12b. Figure Figure ARTE Block Diagram Diagram PLCC Package ARTE Diagram PLCC Package Interface Isolated Pulse Mask Interface Isolated Pulse Mask Equations STS-1 Interface Isolated Pulse Mask Equations STS-1 Interface Diagram Mask Receiver CLKO Data Output Timing Receiver CLKO Data Output Timing Transmitter Input Timing Coding Violation Pulse Excessive Zeros Pulse Examples B3ZS Coding Examples Idealized Transmit Input Output Data Jitter Transfer Test Arrangement Jitter Generation Test Arrangement ARTE Input Jitter Tolerance ARTE Input Jitter Tolerance STS-1 Interference Margin Test Configuration External Components, Connections Power/Ground Single-Ended Receive Termination 44-Pin Plastic Leaded Chip Carrier ARTE 68-Pin Plastic Leaded Chip Carrier
TXC-02020-MB March 1995
PRELIMINARY
BLOCK DIAGRAM
Line Side
EYEP* EYEN* EXZ* RAIS
ARTE
Terminal Side
PRBS Analyzer
RECEIVE
Adaptive Equalizer/
Clock Recovery
BIST RXDIS*
B3ZS Decoder
CLKO DLOS ALOS*
Detector Auxiliary Loopback Control Loopback Controls
Control
RP/RD CLKO
TEST1*
TRLBK LNLBK TP/TD
(Thick dashed lines show parts loopback paths)
REFCK
Generator
Control
CLKI RZTXIN
DOUT DO1* DO2*
Output Control
B3ZS Encoder TRANSMIT
PRBS Generator
B3ZSDIS
TEST0*
DSXDIS TPLLC TAIS ZERO
*Note: nine signal terminations denoted with asterisk provided 68-pin extended feature ARTE (TXCversion ART. These terminations provided 44-pin (TXC-02020) device.
Figure ARTE Block Diagram
BLOCK DIAGRAM Receiver Functions Adaptive Equalizer/AGC block receiver used recover CMOS level rail data from bipolar B3ZS encoded input pulses. dynamic range volts) which allows device used applications where input signal attenuated beyond level pulse template (such bridging repeaters protection switches). Adaptive equalization included restore integrity signal after been attenuated frequency-dependent loss feet coaxial cable. equalized AGC'd differential signals provided outputs EYEP EYEN pins. Differential inputs provided allow optimum performance device noisy environments. Alternatively, single ended operation used less critical environments where transformer desired (the input signal coupled capacitor). When differential mode used, voltage measured between maximum magnitude volts. single-ended operation, voltage measured (DI2) relative bias voltage (DI1) maximum +1.0 volts. larger input levels, step-down transformer resistive attenuation should used. -3TXC-02020-MB March 1995
PRELIMINARY
ARTE
PLL-based Clock Recovery block used recover CMOS level clock from equalized sliced input pulses. filters internal. B3ZS Decoder block decodes B3ZS encoded line signal detects coding errors excessive zeros incoming data stream. active-high pulse generated output whenever input signal violates B3ZS encoding sequence bipolar violations. active-low pulse generated output when string three more zeros detected, remains until detected. B3ZSDIS control input used disable this function. Control block multiplexes appropriate signals Receiver Terminal Side outputs. output data formats include: B3ZS decoded outputs recovered from line (RP/RD contains recovered data; held low). Encoded outputs from Clock Recovery block (RP/RD contains positive data; contains negative data). This mode allows external device such Framer perform B3ZS encoding/decoding functions. B3ZSDIS enables this mode. Loopback signals from Transmitter terminal side inputs when TRLBK low. format signals when RAIS low. Outputs CLKO CLKO provide true inverted clocks above formats. RXDIS signal forces RP/RD outputs state. Detector block generates active outputs which indicate absence line side input signal(s). DLOS output goes when string consecutive zeros occurs line. This output reset when detected density range 33%) pulses. ALOS output goes high when density greater than goes when density below 28%. Between ALOS output toggle between active inactive states. Transmitter Functions Control block multiplexes appropriate signals transmitter. selectable formats include: Unencoded input data (TP/TD contains data, must grounded). B3ZS encoded input data (TP/TD contains positive data, contains negative data). B3ZSDIS enables this mode. B3ZS encoded input data (TP/TD contains positive data, contains negative data). This mode enabled RZTXIN. Loopback signals from B3ZS Decoder when LNLBK low. format signals when TAIS low. PRBS Generator output when TEST0 low. CLKI input clock above formats. When RZTXIN low, CLKI signal ignored. B3ZS Encoder block encodes input data compliant with ANSI Specification T1.102A. Figure gives examples B3ZS encoding. B3ZSDIS control used disable this block. B3ZSDIS must when RZTXIN low. Output Control block contains appropriate formatting circuitry required transform B3ZSencoded data into pulses that meet requirements STS-1 line rates. internal line driver included which enables drive these signals directly into load output cable. DSXDIS input determines which output types enabled. DOUT single-ended output which meets DS3/STS-1 templates. internal transversal filter used create this output. Outputs rectangular pulses representing level-translated versions input digital signals. external
TXC-02020-MB March 1995
PRELIMINARY
ARTE
transformer required translate these signals appropriate polarity. When DSXDIS high DOUT output enabled. When DSXDIS DO1/DO2 outputs enabled. Figure shows idealized transmitter waveforms both output modes. external capacitor connected from TPLLC Analog Ground required internal used calibrate transversal filter circuit (see Figure 12a). Input ZERO improves DOUT pulse shape short cable. Loopbacks Insertion Loopback Controls block enables input signals looped back both line terminal sides device. When TRLBK (Terminal Loopback) TP/TD, CLKI inputs directly looped back RP/RD, CLKO pins Control Block. When LNLBK DI1/DI2 signals looped back DOUT DO1/DO2 outputs Adaptive Eq/AGC, Clock Recovery, B3ZS Decoder, Control, Loopback Controls, Control, B3ZS Encoder, Output Control blocks. These loopbacks operated independently simultaneously. should noted that, when TRLBK active, DLOS, ALOS output signals will still respond line input data signals applied pins DI2. Generator block generates alarm indication signal (AIS) compliant with Bellcore Specification TR191 line terminal sides device (selected with TAIS RAIS). STS-1 operation inputs device must contain correct overhead required path sectionalization; i.e., this block generates format only. will override loopback commands. ARTE device, TEST1 will loop back terminal input data through encoder, auxiliary loopback control, clock recovery decoder blocks, described below. When TXAIS active same time TEST1 will loop through this path. Testability PRBS Generator PRBS Analyzer blocks (PRBS means Pseudo-Random Binary Sequence) used provide internal BIST function ART. When TEST0 output PRBS generator driven through Control, B3ZS Encoder, Output Control blocks DOUT output. This output looped back Receiver inputs external capacitor. PRBS Analyzer monitors output Control block. output signals conform correct 215-1 pattern BIST output will high. Note that PRBS Analyzer always functions, regardless state TEST0 pin; whenever valid 215-1 pattern (this pattern contain significant number errors still valid) appears receiver outputs BIST will high. Since this function sends signals through data path blocks device particularly useful manufacturing test. This test must with B3ZSDIS held high. TEST1 enables auxiliary terminal side loopback primarily intended during device test. Signals from Transmitter inputs routed through Control, B3ZS Encoder, Auxiliary Loopback Control, Clock Recovery, B3ZS Decoder, Control blocks Receiver outputs. Input Reference Clock input CMOS level clock STS-1 rate must applied REFCK input operate. This will typically supplied local oscillator board. tolerance required operation when generator used. generate valid pattern tolerance required.
TXC-02020-MB March 1995
PRELIMINARY
Functional Differences Between 68-Pin (ARTE) 44-Pin (ART) Versions
ARTE
68-pin version (ARTE) features terminations 44-pin version (ART), plus following nine additional terminations (Extended features): RXDIS ALOS EYEP EYEN TEST0 TEST1 Transmit output rectangular positive pulse Transmit output rectangular negative pulse Receive output disable Analog loss signal indicator Positive pattern monitor Negative pattern monitor Enables internal built-in self test (BIST) function Enables terminal side loopback from TP/TD signals receiver outputs Excessive zeros received pattern
DIAGRAMS
AGNDRX B3ZSDIS AVDDRX AVDDRX REFCK DLOS
RAIS
BIST
AGNDRX AVDDRX AGNDRX AVDDTPLL TPLLC AGNDTPLL AVDDTX DOUT AGNDTX
DVDD RP/RD CLKO CLKO DGND DGND DVDD TP/TD CLKI
44-Pin PLCC Diagram (Top View)
AVDDTX
DSXDIS
RZTXIN
ZERO
LNLBK
TRLBK
TAIS
AGNDTX
Figure Diagram PLCC Package
AGNDTX
AVDDTX
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PRELIMINARY
ARTE
AGNDRX
B3ZSDIS
AVDDRX
AVDDRX
REFCK
TEST0
EYEN
DLOS
EYEP
ALOS
RAIS
BIST
AGNDRX AVDDRX AGNDRX AVDDTPLL TPLLC AGNDTPLL AVDDTX AVDDTX DOUT AGNDTX AGNDTX
DVDD RXDIS RP/RD CLKO CLKO DGND DGND DVDD TP/TD CLKI
ARTE 68-Pin PLCC Diagram (Top View)
DSXDIS
RZTXIN
TEST1
DVDD
ZERO
LNLBK
TRLBK
TAIS
AVDDTX
AGNDTX
Figure ARTE Diagram PLCC Package
AGNDTX
AVDDTX
TXC-02020-MB March 1995
PRELIMINARY
DESCRIPTIONS
Power Supply Ground Symbol ARTE (44-Pin) (68-Pin) I/O/P* Type Name/Function
ARTE
AVDDTX
Analog Transmit: Volt Supply
AVDDRX
Analog Receive: Volt Supply
AVDDTPLL DVDD
Analog Transmit PLL: Volt Supply Digital VDD: Volt Supply
AGNDTX
Analog Ground Transmit: Volts Reference
AGNDRX
Analog Ground Receive: Volts Reference
AGNDTPLL DGND
Analog Ground Transmit PLL: Volts Reference Digital Ground: Volts Reference
*Note: Input; Output; Power
Receive Interface Symbol ARTE (44-Pin) (68-Pin) I/O/P Type Name/Function
Analog Analog
Data Data Line Side Inputs. single ended operation must coupled ground capacitor. differential operation both inputs tied directly transformer. Positive Pattern Monitor: Monitors noninverted AGC'd equalized output from Adaptive EQ/AGC block. Negative Pattern Monitor: Monitors inverted AGC'd equalized output from Adaptive EQ/AGC block.
EYEP
Analog
EYEN
Analog
*See Input, Output Parameters section below Type definitions.
TXC-02020-MB March 1995
PRELIMINARY
Symbol ARTE (44-Pin) (68-Pin) I/O/P Type Name/Function
ARTE
DLOS
CMOS CMOS CMOS
Excessive Zeros: when three more consecutive zeros occur input data stream. Coding Violation: High when incoming data violates B3ZS code bipolar violations. Digital LOS: when consecutive zeros appear incoming data stream. Cleared when ones pulse density range 33%) pulses. Analog LOS: when pulse density pulses. Cleared when pulse density pulses. ALOS toggle between active inactive when between 33%. Receiver Positive/Data: Generates B3ZS decoded NRZ, combined data (B3ZSDIS high) positive rail data (B3ZSDIS low). Held when RXDIS low. Receiver Negative: Generates negative rail data when B3ZSDIS low. Held when B3ZSDIS high and/or when RXDIS low. Receiver Clock Out: Receiver output clock. Receiver Clock Inverted: Receiver inverted output clock. Built-In Self Test Output: High when valid unframed 215-1 PRBS pattern detected.
ALOS
CMOS
RP/RD
CMOS
CMOS
CLKO CLKO BIST
CMOS CMOS CMOS
*Note: TRLBK (active), this output signal responds input pins.
Transmit Interface Symbol ARTE (44-Pin) (68-Pin) I/O/P Type Name/Function
TP/TD
CMOS
Transmitter Positive/Data: Input unencoded NRZ, combined data (B3ZSDIS high) positive rail data (B3ZSDIS low). Transmitter Negative: Input negative rail data when B3ZSDIS low. Must tied when B3ZSDIS high. Transmitter Input Clock: Transmitter clock input. Transmit Capacitor: Capacitor transversal filter calibration (see Figure 12a). Data Positive: Rectangular positive pulse output enabled when DSXDIS low. High impedance when DSXDIS high.
TXC-02020-MB March 1995
CMOS
CLKI TPLLC
CMOS Analog Analog
PRELIMINARY
Symbol ARTE (44-Pin) (68-Pin) I/O/P Type Name/Function
ARTE
Analog
Data Negative: Rectangular negative pulse output enabled when DSXDIS low. High impedance when DSXDIS high. Data Out: filtered single-ended output enabled when DSXDIS high. with impedance when DSXDIS low.
DOUT
Analog
Control/Reference Pins (All control pins enabled when low) Symbol ARTE (44-Pin) (68-Pin) I/O/P Type Name/Function
RAIS RXDIS TRLBK
TTLp TTLp TTLp
Receive Enable: Enables generation receiver outputs. (See Note Receive Output Disable: Forces RP/RD state. Terminal Loopback Enable: Enables loopback from transmitter inputs receiver outputs Control block, Loopback Controls block Control block. Line Loopback Enable: Enables loopback from DI1/DI2 inputs DOUT DO1/DO2 outputs Adaptive Eq/AGC, Clock Recovery, B3ZS Decoder, Control, Loopback Controls, Control, B3ZS Encoder Output Control blocks. Transmit Input Enable: When accepts B3ZS encoded return-to-zero pulses (properly timed) transmitter TP/TD inputs. CLKI B3ZSDIS inputs must tied this mode. B3ZS Codec Disable: Disables internal B3ZS Encoder Decoder functions. Transmit Zero Cable Enable: Improves DOUT output mask short cable lengths feet). Transmit Enable: Enables generation transmitter outputs. (See Note Transmit Output Disable: Disables DOUT output enables DO1/DO2 outputs.
LNLBK
TTLp
RZTXIN
TTLp
B3ZSDIS ZERO TAIS DSXDIS
TTLp TTLp TTLp TTLp
Note defined valid M-frame with proper subframe structure. data payload 1010 sequence starting with after each overhead bit. Overhead bits follows: F0=0, F1=1, M0=0, M1=1; C-bits X-bits P-bits valid parity.
TXC-02020-MB March 1995
PRELIMINARY
Symbol ARTE (44-Pin) (68-Pin) I/O/P Type Name/Function
ARTE
TEST0
TTLp
Test Enables internal BIST function (unframed 215-1 PRBS generator). This function described Block Diagram Description, Testability section. Test Enables terminal side loopback from TP/TD signals receiver outputs Control, B3ZS encoder, Clock Recovery, B3ZS Decoder, Control blocks. This loopback should enabled only unencoded input data. Reference Clock Input: Input reference clock system frequency required device operation, namely 44.736 applications 51.840 STS-1 applications. Required tolerance when generation required otherwise.
TEST1
TTLp
REFCK
CMOS
Connects Symbol ARTE (44-Pin) (68-Pin) I/O/P Type Name/Function
Connect. pins connected, even another pin, must left floating. device damaged pins connected.
TXC-02020-MB March 1995
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
Parameter Supply voltage input voltage Continuous power dissipation Ambient operating temperature Operating junction temperature Storage temperature range Symbol -0.3 -0.3 +7.0
ARTE
Unit
*Note: Operating conditions exceeding those listed Absolute Maximum Ratings cause permanent failure. Exposure absolute maximum ratings extended periods impair device reliability.
THERMAL CHARACTERISTICS
Parameter Thermal resistance: junction ambient, PLCC Thermal resistance: junction ambient, PLCC -Typ -Unit
oC/W oC/W
Test Conditions
POWER REQUIREMENTS
Parameter 4.75 0.95 5.25 Unit Outputs terminated Inputs switching, VDD=5.25 Test Conditions
TXC-02020-MB March 1995
PRELIMINARY
INPUT, OUTPUT PARAMETERS
Input Parameters TTLp Parameter Input Capacitance
Note: input pads have internal pull-up resistor.
ARTE
Unit
Test Conditions
5.25V 5.25V
Input Parameters CMOS Parameter Input Capacitance (VDD (VDD Unit 5.25V 5.25V Test Conditions
Output Parameters CMOS Parameter tRISE tFALL Unit Test Conditions source sink 4.75V 4.75V CLOAD CLOAD
TXC-02020-MB March 1995
PRELIMINARY
TIMING CHARACTERISTICS
Line Side Timing Characteristics
ARTE
line side signal characteristics designed that output meets requirements ANSI standard T1.102-1993. When terminated into test load using 734A coaxial cable device will meet STS-1 interface isolated pulse masks defined below Figures through cable distance feet. pulse measurement made using Hewlett Packard HP54502A oscilloscope equivalent) average mode, which described instruction manual this instrument. input ART/ARTE device pseudo-random binary sequence (PRBS) signal. pulse sequences output also meets STS-1 interface diagram mask shown Figure
NORMALIZED AMPLITUDE
MAXIMUM*
-0.8 -0.4 +0.4
MINIMUM*
+0.8
+1.2
+1.6
TIME, UNIT INTERVALS (UI)**
Note: curves shown approximate representations equations Figure corresponding STS-1 curves (not shown) would slightly different, indicated equations Figure **Note: (System Clock Frequency)
Figure Interface Isolated Pulse Mask
TXC-02020-MB March 1995
PRELIMINARY
ARTE
CURVE MAXIMUM (UPPER) CURVE
TIME UNIT INTERVALS -0.85 -0.68 -0.68 0.36 0.36 -0.85 -0.36 -0.36 0.36 0.36
NORMALIZED AMPLITUDE 0.03
+0.03 0.34
0.08 0.407e -1.84(T-0.36) 0.03 0.03 0.18 0.03
MINIMUM (LOWER) CURVE
Figure Interface Isolated Pulse Mask Equations
CURVE MAXIMUM (UPPER) CURVE
TIME UNIT INTERVALS -0.85 -0.68 -0.68 0.26 0.26 -0.85 -0.38 -0.38 0.36 0.36
NORMALIZED AMPLITUDE 0.03 +0.03 0.34 0.61e -2.4(T-0.26)
MINIMUM (LOWER) CURVE
0.03
0.03 0.18
0.03
Figure STS-1 Interface Isolated Pulse Mask Equations
TXC-02020-MB March 1995
PRELIMINARY
ARTE
0.75 NORMALIZED AMPLITUDE 0.25 -0.25
-0.5 -0.75
-0.5 -0.25 0.25
TIME UNIT INTERVALS (UI)
*Note: (System Clock Frequency)
Outer region corner points Point Time -0.5 -0.261 -0.136 -0.028 0.094 0.187 0.31 Amplitude 0.426 0.904 1.03 1.03 0.883 0.723 0.566 0.426 Point
Inner region corner points Time -0.245 -0.187 -0.104 -0.017 0.077 0.18 -0.054 Amplitude 0.214 0.455 0.67 0.67 0.581 0.14 0.16
Note Both inner outer regions symmetric about zero amplitude axis.
Figure STS-1 Interface Diagram Mask
TXC-02020-MB March 1995
PRELIMINARY
ARTE
Timing Diagrams Detailed timing diagrams illustrated Figures through with values timing intervals following each figure. output times measured with maximum load capacitance. Timing parameters measured (VOH VOL)/2 (VIH VIL)/2 applicable.
tCYC CLKO tPWH
RP/RD/RN
Parameter CLKO, output clock period CLKO, STS-1 output clock period Output clock duty cycle, tPWH/tCYC RP/RD/RN data output delay after CLKO
Symbol tCYC tCYC -tOD
22.353 19.290
Unit
Figure Receiver CLKO Data Output Timing
tCYC CLKO
tPWH
RP/RD/RN
Parameter CLKO, output clock period CLKO, STS-1 output clock period Output clock duty cycle, tPWH/tCYC RP/RD/RN data output delay after CLKO
Symbol tCYC tCYC -tOD
22.353 19.290
Unit
0.75
Figure Receiver CLKO Data Output Timing
TXC-02020-MB March 1995
PRELIMINARY
ARTE
tCYC CLKI TP/TD/TN DON'T CARE
tPWH DON'T CARE
Parameter CLKI, input clock period CLKI, STS-1 input clock period Input clock duty cycle, tPWH/tCYC TP/TD/TN data stable CLKI setup time CLKI TP/TD/TN data stable hold time
Symbol tCYC tCYC -tSU
22.353 19.290
Unit
Figure Transmitter Input Timing
tPWH
Parameter pulse width pulse high time delay from occurrence violation
*Note: (System Clock Frequency)
Symbol tPWH
Unit*
Figure Coding Violation Pulse
TXC-02020-MB March 1995
PRELIMINARY
ARTE
tPWL
Parameter pulse width pulse time delay from occurrence violation
*Note: (System Clock Frequency)
Symbol tPWL
Unit*
Figure Excessive Zeros Pulse
TXC-02020-MB March 1995
PRELIMINARY
OPERATION
Receiver Input Requirements
ARTE
Parameter Interface Cable Rate: STS-1 Line Code Input Signal Amplitude: Single-Ended Input Differential Input Cable Length Input Return Loss: STS-1 Input Resistance Signal-to-Noise Tolerance Input Jitter Tolerance Signal Coupling 44.736 Mbit/s 51.840 Mbit/s B3ZS
Value AT&T 728A/734A coaxial equivalent)
(measured relative other used bias, DI2) (magnitude differential amplitude between DI2) feet 22.368 with external resistor, effect external transformer excluded) 25.920 with external resistor, effect external transformer excluded) greater than either value produced adjacent pulses data stream ±10% peak pulse amplitude, whichever greater. defined Figures 10b: "ART ARTE Input Jitter Tolerance"* input signal must coupled transformer capacitor.
*Note: Refer Operation-Jitter Tolerance section below.
Interfering Tone Tolerance will properly recover clock present error-free output receive terminal side interface* presence sinusoidal interfering tone signal following line rates: Interfering Tone Tolerance Data Rate (Mbit/s) 51.84 44.736 Tone Frequency (MHz) 25.97 22.4 Maximum Tone Level
*Note: Figure "Interference Margin Test Configuration"
TXC-02020-MB March 1995
PRELIMINARY
Receiver Output Specifications Parameter Clock Recovery Jitter Peaking Clock Recovery pull-in time Sequences Reported Coding Violations maximum Value
ARTE
BOV, 00V, three more consecutive zeros (excessive zeros)
TXC-02020-MB March 1995
PRELIMINARY
Transmitter Specifications
ARTE
Note: output load assumed these specifications. Measurements made transmitter unless otherwise noted.
Parameter DO1/DO2 Output Characteristics: Amplitude Pulse Width Rise Time Overshoot/Undershoot Output Power Output Power Pulse Imbalance Pulse Symmetry DOUT Output Characteristics, ZERO high: Pulse Shape (DS3) Pulse Shape (STS-1) Amplitude Output jitter DOUT Output Characteristics, ZERO low: Pulse Shape (DS3) Pulse Shape (STS-1) Amplitude Pulse Shape (DS3) defined Figure ANSI TI.404-19XX, TIE1.2/93-004, with cable defined Figure 4-10 TR-TSY-000253, with output cable ±0.67 Volts ±10% DS3; +0.8 STS-1 defined Figure TR-TSY-000499
*Note: (System Clock Frequency)
Value
±1.75 volts ±10% ±10%* ±1.5 Between -1.8 +5.7 all-ones pattern measured 3kHz band centered system frequency. Between -4.7 +3.6 signal measured through low-pass filter with cutoff with cable lengths between feet. Ratio positive negative pulse amplitudes: 1.10. Output power system frequency below level system frequency
defined Figure ANSI TI.404-19XX, TIE1.2/93-004 defined Figure 4-10 TA-NWT-000253, Issue October 1993 ±0.81 Volts ±10% DS3-X; +0.95 STS-1 0.05 maximum with jitter-free input clock CLKI
TXC-02020-MB March 1995
PRELIMINARY
ARTE
B3ZS PATTERNS
B3ZS
B3ZS
B3ZS
indicates even number pulses since last violation (V). indicates number pulses since last violation (V). inserted pulse, intentional violation alternating plus minus pulses used 1's. inserted pulse that follows normal alternating Bipolar coding scheme (i.e., polarity opposite preceding pulse). Note: Three consecutive zeros replaced with 00V; substitution choice made that number pulses between inserted violation pulses (V's) odd; note that sequential violations opposite polarity charge transmission medium zero.
Figure 9.1. Examples B3ZS Coding
TXC-02020-MB March 1995
PRELIMINARY
ARTE
TXCABLE
CLKI TP/TD
DOUT
Unencoded Data TP/TD CLKI
pulse
DSXDIS low; ARTE only
TXCABLE (Bipolar signal)
DSXDIS low;
DOUT
VDD/2 VDD/2 VDD/2
DSXDIS high;
TXCABLE (Bipolar signal)
DSXDIS high;
Encoded Data
TP/TD
DO1, DO2, DOUT, CLKI TXCABLE same unencoded case. Figure 9.2. Examples Idealized Transmit Input Output Data
TXC-02020-MB March 1995
PRELIMINARY
Loopback Control Signal Arbitration
ARTE
TEST1
RAIS
TAIS
LNLBK
TRLBK
Terminal Output Normal Normal Term Loopback Term Loopback Normal Term Loopback Term Loopback*
Line Output Normal Normal Line Loopback Normal Line Loopback Line Loopback Normal
Through clock recovery block terminal data only, ARTE device. Notes: Don't Care. TEST1 input provided only ARTE device.
Power-Down Mode order reduce current required when either transmitter receiver used, following power pins tied ground:
44-Pin Package:
Receiver-Only Operation: AVDDTX pins Transmitter-Only Operation: AVDDRX pins
68-Pin Package:
Receiver-Only Operation: AVDDTX pins Transmitter-Only Operation: AVDDRX pins
Current reduction Power Down-Mode follows: Receiver-Only Operation: reduced approximately Transmitter-Only Operation: reduced approximately
Note: Power must provided AVDDTPLL three operational modes (Receiver Transmitter, Receiver-Only, Transmitter-Only). Refer Figure associated Note power supply connections.
TXC-02020-MB March 1995
PRELIMINARY
ARTE
Jitter Transfer Transfer jitter through individual unit digital equipment characterized relationship between applied input jitter resulting output jitter function frequency. DS3, Bellcore Technical Reference TR-TSY-000499, Issue December 1989 further describes defines jitter transfer. STS-1, Bellcore Technical Reference TR-NWT-000253, Issue December 1991 further describes defines jitter transfer. looped back configuration (through receive path externally looped back through transmit path), absence applied input jitter amount jitter introduced ARTE devices maximum 0.065 Unit Intervals (UIs, where System Clock Frequency) peak-to-peak jitter over jitter frequency range (filter with high-pass low-pass MHz). test arrangement illustrated Figure recommended performance jitter transfer test. This test made adding jitter line side data inputs (DI1 DI2) measuring jitter terminal side receiver clock output (CLKO). Intrinsic test equipment jitter must substracted from measurement. receiver outputs (RP/RD, CLKO) looped back transmitter inputs (TP/TD, CLKI) using cables. transmitter activated ensure that there crosstalk between transmitter receiver. ART/ARTE
Signal Generator*
CLKO
Jitter Analyzer*
Termination
Hewlett Packard HP3784A Digital Transmission Analyzer, equivalent.
Figure 9.3. Jitter Transfer Test Arrangement Jitter Generation Jitter generation process whereby jitter appears output port individual unit digital equipment absence applied input jitter. DS3, Bellcore Technical Reference TR-TSY-000499, Issue December 1989 specifies maximum jitter generation peak-to-peak output terminal receiver Category equipment. STS-1, Bellcore Technical Reference TR-NWT-000253, Issue December 1991 specifies maximum jitter generation peak-to-peak maximum output terminal receiver Category equipment.
TXC-02020-MB March 1995
PRELIMINARY
ARTE
test arrangement illustrated Figure recommended performance jitter generation test. This test made adding jitter inputs receiver, looping receiver outputs transmitter inputs with cables, then measuring jitter output transmitter. jitter filter used. Intrinsic test equipment jitter must subtracted from measurement. DS3/STS-1 jitter generation within ARTE devices 0.145 peak-to-peak maximum frequencies specified standards referenced above. ART/ARTE
Signal Generator*
Jitter Analyzer*
Hewlett Packard HP3784A Digital Transmission Analyzer, equivalent.
Figure 9.4. Jitter Generation Test Arrangement Jitter Tolerance DS3: Input jitter tolerance maximum amplitude sinusoidal jitter given jitter frequency, which, when modulating signal equipment port, results more than errored seconds cumulative, where these errored seconds integrated over successive 30-second measurement intervals, jitter amplitude increased each succeeding measurement interval. Requirements input jitter tolerance specified terms compliance with jitter mask, which represents combination points. Each point corresponds minimum amplitude sinusoidal jitter given jitter frequency which, when modulating signal equipment input port, results fewer errored seconds 30-second measurement interval. Bellcore Technical Reference TR-TSY-000499, Issue December 1989 specifies minimum requirement mask Category equipment. mask shown Figure 10a. Jitter tolerance within ARTE meets exceeds performance requirements. Figure presents Bellcore minimum jitter tolerance requirement mask measured performance. STS-1: STS-1, jitter tolerance specified Bellcore Technical Reference TR-NWT-000253. minimum requirement mask shown Figure 10b. Jitter tolerance within ARTE meets exceeds performance requirements. Figure presents Bellcore STS-1 minimum jitter tolerance requirement mask measured STS-1 performance.
TXC-02020-MB March 1995
PRELIMINARY
ARTE
Sinusoidal Input Jitter Amplitude (UI, Peak-Peak) 50kHz
Measured* dB/decade Minimum Required
maximum measurement limit test equipment.
2.3K
300K
Jitter Frequency (Hz)
Figure 10a. ARTE Input Jitter Tolerance
Sinusoidal Input Jitter Amplitude (UI, Peak-Peak) 50kHz Minimum Required
Measured*
maximum measurement limit test equipment.
0.15 2,000 20,000 Jitter Frequency (Hz, Scale)
Figure 10b. ARTE Input Jitter Tolerance STS-1
Sine Wave Generator
Passive Combiner
Line DS3/STS-1 Digital Transmission Test Line feet
ARTE
Figure Interference Margin Test Configuration
TXC-02020-MB March 1995
PRELIMINARY
Physical Design
ARTE
High-frequency design techniques must employed layout printed circuit board which ARTE device mounted. summary special design requirements provided below. More details available TranSwitch Application Note AN-406, Guidelines ART/ARTE Printed Circuit Board Layout, Document TXC-02020-AN1. following guidelines suggestions should adhered successful board design. STS-1 frequencies important high-frequency layout techniques. techniques discussed below bare minimum that should used. possible 'solid' ground plane. However, impossible have ground that truly solid physical limitations. Therefore recommended that star ground star power distribution scheme used. `Solid' this instance means that impedance from point plane board ground connection should low. This very important regards location analog ART/ARTE device since severely degraded drops these planes. solid, impedance plane feasible, then grounds should divided into following regions: Analog Receiver ground, AGNDRX Analog Transmitter ground, AGNDTX Analog ground, AGNDTPLL digital ground, DGND Board Logic ground
These ground regions should connected star pattern. other words, each region should have separate path common connection point. connection point should close possible point where ground comes onto board. Under circumstances should ground region connected common point through trace. trace impedance high frequencies; short. Ground currents through trace impedance will cause voltage noise. wide path connection point possible. solid power plane. Break power plane into regions. power regions should mirror images ground regions minimize capacitive noise coupling. power ground planes placed adjacent layers there will additional noise reduction capacitive coupling. example, six-layer board could ferrite beads used analog power lines, recommended, there will narrowing power plane ferrite bead. beads used, wide path possible back common connecting point. should noted that using beads cause large reduction transceiver. effect highly board dependent easily predictable. Figures show recommended ground power connections ART. passive components should connected indicated ground planes. Connecting components wrong plane will inject noise signal into that part transceiver. long trace connect components ground either solid regionalized ground plane; short trace possible. decoupling capacitors should placed close feasible their associated chip pins same board side chip. Placing capacitors other side board will have measurable impact device performance. Again, should pointed that board trace impedance, short. other passive components should also placed close possible their associated pins. Placement critical since they monitoring purposes only.
TXC-02020-MB March 1995
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ARTE
notes bottom Figure give external component values types, listing various powers grounds, other general notes. General Comments board trace high frequencies zero-impedance metal interconnection. distributed network. values parasitic components determined trace geometry (width height) surrounding material. trace with given geometry will have different impedance outside board layer from same trace placed instead internal layer. Large branches main trace will change impedance branch point effect impedances parallel, branch lengths should kept minimum (less than quarter wavelength). This very important clock lines where load/source impedance mismatches cause severe ringing, which leads timing problems. clock buffers reduce difficulty distributing clock with many loads. relays used switch transceivers out, shielded variety minimize crosstalk, especially from power used energize relay. Match impedance board traces transmitter outputs receiver inputs transmission line impedance ohms transformer used) minimize reflections. Physically separate analog signal lines from digital lines. Route differential receiver lines side side make coupled noise common-mode. Avoid ninety-degree corners board lands; keep lands straight short possible. terminating (i.e., series-damping) resistors digital signals lines where appropriate (i.e., line longer than quarter wavelength highest signal frequency importance, reflections will start causing problems). above comments guidelines only. High-frequency board layout difficult must done with care. board layout will reduce transceiver cause timing problems with board logic, perhaps point requiring complete board redesign.
TXC-02020-MB March 1995
PRELIMINARY
ARTE
Ferrite Bead 6.3v
Ferrite Bead 6.3v
Ferrite Bead (Notes 6.3v
0.01 DVDD
0.01 AVDDRX
0.01 (Note AVDDTPLL AVDDTX
Line Inputs
37.5, 37.5,
(Note EYEP* EYEN*
T1** Differential Input Termination (Notes
0.01 TEST0* TEST1* BIST REFCK RZTXIN RXDIS* LNLBK TRLBK TAIS RAIS B3ZSDIS DSXDIS ZERO DO1* RP/RD CLKO CLKO TP/TD CLKI Receiver Outputs
Testability
ARTE
0.01 TPLLC (Note
Reference Clock
Terminal Side Line Side
Control Signals
Transmitter Inputs
T3**(Note Output Output T2**
DLOS ALOS* EXZ* Status/Perf. Monitor Signals
DO2* DOUT AGNDTX DGND AGNDRX Note AGNDTPLL (Note next page numbered Notes.
Note: capacitor values microfarads, resistor values ohms.
Figure 12a. External Components, Connections Power/Ground
TXC-02020-MB March 1995
PRELIMINARY
ARTE
0.01µf Line Inputs 0.1µf
Figure 12b. Single-Ended Receive Termination
NOTES: *The nine device signal terminations marked with asterisks provided ARTE ART. **T1, Coilcraft WB1010 Transformers equivalent. optional. only required ARTE square wave transmit output used (DO1, DO2). replaced with resistor with corresponding slight increase input return loss. only required ARTE monitoring purposes, device operation. Differential Input Termination line inputs replaced circuit Figure single-end operation. Fair Rite #2743002111 equivalent should used each ferrite bead Locate ferrite bead/capacitor decoupling close possible ARTE. Locate capacitor close possible ferrite bead, place individual 0.01 capacitor close possible each voltage ART/ARTE. Power Connections Transmit PLL. Connect AVDDTPLL, AGNDTPLL TPLLC follows: Mode Receive Transmit Receive Transmit AVDDTPLL AVDDRX AVDDRX AVDDTX AGNDTPLL TPLLC
GD=Digital Ground; GRX=Analog Receive Ground; GTX=Analog Transmit Ground.
TXC-02020-MB March 1995
PRELIMINARY
PACKAGING
ARTE
available 44-pin plastic leaded chip carrier (ART) also with extended features 68-pin plastic leaded chip carrier (ARTE). Both packages suitable socket surface mounting. dimensions shown inches nominal values unless otherwise indicated.
0.170 0.075 0.653 0.500 0.149 0.690
0.017 typ.
TRANSWITCH
0.050 typ.
VIEW
BOTTOM VIEW
Figure 44-Pin Plastic Leaded Chip Carrier
0.990 0.953 0.800
0.075
0.170 0.050 typ. 0.149
TRANSWITCH
0.017 typ.
VIEW
BOTTOM VIEW
Figure ARTE 68-Pin Plastic Leaded Chip Carrier
TXC-02020-MB March 1995
PRELIMINARY
ORDERING INFORMATION
Part Number: ARTE Part Number: TXC-02020-AIPL TXC-02021-AIPL
ARTE
44-pin plastic leaded device carrier 68-pin plastic leaded device carrier
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TXC-02020-MB March 1995
PRELIMINARY
STANDARDS DOCUMENTATION SOURCES
ARTE
Telecommunication technical standards reference documentation obtained from following organizations: ANSI (U.S.A.): American National Standards Institute (ANSI) West 42nd Street York, York 10036 Tel: 212-642-4900 Fax: 212-302-1286 Bellcore (U.S.A.): Bellcore Attention Customer Relations Corporate Place, 184A Piscataway, 08854-4156 Tel: 800-521-2673 U.S.A. Canada only) Tel: 908-699-5800 Fax: 908-336-2559 908-336-2692 ITU-T (International): Publication Services International Telecommunication Union (ITU) Telecommunication Standardization Bureau Contact: Sales Service Department Place Nations 1211 Geneve Switzerland Tel: 41-22-730-5285 41-22-730-5111 Fax: 41-22-730-5194 (Japan): Standard Publishing Group Telecommunications Technology Committee Floor, Hamamatsucho Suzuki Building, 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 81-3-3432-1551 Fax: 81-3-3432-1553
TXC-02020-MB March 1995
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LIST DATA SHEET CHANGES
ARTE
This change list identifies those areas within this updated ARTE Data Sheet that have technical differences relative previous superseded ARTE Data Sheet: Updated ARTE Data Sheet: Superseded ARTE Data Sheet: Edition March 1995 Edition November 1994
page numbers indicated below this updated data sheet include changes relative superseded data sheet.
Page Number Updated Data Sheet 26-27
Summary Change Changed edition number date. Updated Table Contents List Figures. Modified Figure Added Auxiliary Loopback Control block. Modified Control block. Modified second paragraph. Added text second fourth paragraphs "Transmitter Functions" subsection. Added text both paragraphs "Loopbacks Insertion" subsection added third paragraph. Modified last paragraph Testability subsection. Made minor changes Name/Function column Added note explain output signal responds TRLBK low. Added information transmit output pulse measurement. Added Figure 9.1. Added Figure 9.2. Modified Loopback Control Signal Arbitration section. Added description jitter transfer test arrangement jitter generation test arrangement, including Figures 9.4. Deleted note from Physical Design section. Changed information Bellcore ITU. Updated List Data Sheet Changes. Added Documentation Update Registration Form.
TXC-02020-MB March 1995
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NOTES
ARTE
TranSwitch reserves right make changes product(s) circuit(s) described herein without notice. liability assumed result their application. TranSwitch assumes liability TranSwitch applications assistance, customer product design, software performance, infringement patents services described herein. does TranSwitch warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right TranSwitch covering relating combination, machine, process which such semiconductor products services might used.
PRELIMINARY information documents contain information products sampling, preproduction early production phases product life cycle. Characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product. TXC-02020-MB March 1995
TranSwitch VLSI: Powering Communication Innovation
TranSwitch Corporation Progress Drive Shelton, 06484 Tel: 203-929-8810 Fax: 203-926-9453
PRELIMINARY
DOCUMENTATION UPDATE REGISTRATION FORM
ARTE
would like added database customers have registered receive updated documentation this device becomes available, please provide your name address below, mail this page Mary Koch TranSwitch. Mary will ensure that relevant Product Information Sheets, Data Sheets, Application Notes Technical Bulletins sent you. Please print type information requested below, attach business card. Name: Title: Company: Dept./Mailstop: Street: City/State/Zip: located outside U.S.A., please Postal Code: Country:
Telephone:_ Ext.: Fax: E-Mail: Purchasing Dept. Location:
Please describe briefly your intended application this device, indicate whether would care have TranSwitch applications engineer contact provide assistance:
also interested receiving updated documentation other TranSwitch device types, please list them below rather than submitting separate registration forms:
Please this page Mary Koch (203) 926-9453 fold, tape mail (see other side)
TXC-02020-MB March 1995
TranSwitch VLSI: Powering Communication Innovation
(Fold back this line second, then tape closed, stamp mail.)
First Class Postage Required
TranSwitch Corporation Attention: Mary Koch Progress Drive Shelton, 06484 U.S.A.
(Fold back this line first.)
Please complete registration form this back cover sheet, mail wish receive updated documentation this TranSwitch product becomes available.
TranSwitch Corporation Progress Drive Shelton, 06484 Tel: 203-929-8810 Fax: 203-926-9453

TXC-02020 TXC-02021 STS-1

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