TPS65950

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TPS65950
Integrated Power Management/Audio Codec Silicon Revision
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Literature Number: SWCS032C October 2008 Revised October 2009
TPS65950
SWCS032C OCTOBER 2008 REVISED OCTOBER 2009 www.ti.com
Contents
Features TPS65950 Block Diagram Terminal Description Corner Balls Ball Characteristics Signal Description Electrical Characteristics Absolute Maximum Ratings Minimum Voltages Associated Currents Recommended Operating Conditions Digital Electrical Characteristics Power Module Power Providers 4.1.1 VDD1 dc-dc Regulator 4.1.1.1 VDD1 dc-dc Regulator Characteristics 4.1.1.2 External Components Application Schematic 4.1.2 VDD2 dc-dc Regulator 4.1.2.1 VDD2 dc-dc Regulator Characteristics 4.1.2.2 External Components Application Schematic 4.1.3 dc-dc Regulator 4.1.3.1 dc-dc Regulator Characteristics 4.1.3.2 External Components Application Schematic 4.1.4 VDAC Regulator 4.1.5 VPLL1 Regulator 4.1.6 VPLL2 Regulator 4.1.7 VMMC1 Regulator 4.1.8 VMMC2 Regulator 4.1.9 VSIM Regulator 4.1.10 VAUX1 Regulator 4.1.11 VAUX2 Regulator 4.1.12 VAUX3 Regulator 4.1.13 VAUX4 Regulator 4.1.14 Internal LDOs 4.1.15 4.1.16 Short-Circuit Protection Scheme Power References Power Control 4.3.1 Backup Battery Charger 4.3.2 Battery Monitoring Threshold Detection 4.3.2.1 Power On/Power Backup Conditions 4.3.3 VRRTC Regulator Power Consumption Power Management 4.5.1 Boot Modes
Introduction
Contents
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
www.ti.com SWCS032C OCTOBER 2008 REVISED OCTOBER 2009
4.5.2
Process Modes 4.5.2.1 C027.0 Mode
4.5.3
4.5.2.2 C021.M Mode Power-On Sequence 4.5.3.1 Timings Before Sequence_Start
4.5.3.2 OMAP2 Power-On Sequence 4.5.3.3 OMAP3 Power-On Sequence 4.5.3.4 Power Slave_C021_Generic Mode 4.5.4 Power-Off Sequence 4.5.4.1 Power-Off Sequence Master Modes Real-Time Clock Embedded Power Controller 5.1.1 Backup Battery Audio/Voice Module Audio/Voice Downlink (RX) Module 6.1.1 Earphone Output 6.1.1.1 Earphone Output Characteristics 6.1.1.2 External Components Application Schematic 6.1.2 Stereo Hands-Free 6.1.2.1 Stereo Hands-Free Output Characteristics 6.1.2.2 External Components Application Schematic 6.1.3 Headset 6.1.3.1 Headset Output Characteristics 6.1.3.2 External Components Application Schematic 6.1.4 Headset Pop-Noise Attenuation 6.1.5 Predriver External Class-D Amplifier 6.1.5.1 Predriver Output Characteristics 6.1.5.2 External Components Application Schematic 6.1.6 Vibrator H-Bridge 6.1.6.1 Vibrator H-Bridge Output Characteristics 6.1.6.2 External Components Application Schematic 6.1.7 Carkit Output 6.1.8 Digital Audio Filter Module 6.1.9 Digital Voice Filter Module 6.1.9.1 Voice Downlink Filter (Sampling Frequency kHz) 6.1.9.2 Voice Downlink Filter (Sampling Frequency kHz) 6.1.10 Boost Stage Audio/Voice Uplink (TX) Module 6.2.1 Microphone Bias Module 6.2.1.1 Analog Microphone Bias Module Characteristics 6.2.1.2 External Components Application Schematic 6.2.1.3 Digital Microphone Bias Module Characteristics 6.2.1.4 Silicon Microphone Characteristics 6.2.2 Stereo Differential Input 6.2.3 Headset Differential Input 6.2.4 Radio/Auxiliary Stereo Input 6.2.4.1 External Components
Contents
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
SWCS032C OCTOBER 2008 REVISED OCTOBER 2009 www.ti.com
6.2.7 Microphone Amplification Stage 6.2.8 Carkit Input 6.2.9 Digital Audio Filter Module 6.2.10 Digital Voice Filter Module 6.2.10.1 Voice Uplink Filter (Sampling Frequency kHz) 6.2.10.2 Voice Uplink Filter (Sampling Frequency kHz) Transceiver Features Transceiver 7.2.1 MCPC Carkit Port Timing 7.2.2 USB-CEA Carkit Port Timing 7.2.3 Port Timing 7.2.4 Electrical Characteristics 7.2.4.1 Tolerance 7.2.4.2 LS/FS Single-Ended Receivers 7.2.4.3 LS/FS Differential Receiver 7.2.4.4 LS/FS Differential Transmitter 7.2.4.5 Differential Receiver 7.2.4.6 Differential Transmitter 7.2.4.7 CEA/MCPC/UART Driver 7.2.4.8 Pullup/Pulldown Resistors 7.2.4.9 DPLL Electrical Characteristics 7.2.4.10 Power Consumption 7.2.5 Electrical Characteristics 7.2.5.1 VBUS Electrical 7.2.5.2 Electrical Battery Interface General Description 8.1.1 Battery Charger Interface Overview 8.1.2 Battery Backup Overview Typical Application Schematics 8.2.1 Functional Configurations 8.2.2 In-Rush Current Limitation Schematic 8.2.3 Configuration With Used Electrical Characteristics 8.3.1 Main Charge 8.3.2 Precharge 8.3.3 Constant Voltage Mode Charge Sequence Timing Diagram Charger Type MADC General Description Main Electrical Characteristics Channel Voltage Input Range 9.3.1 Sequence Conversion Time (Real-Time Nonaborted Asynchronous)
6.2.5 6.2.6 Interface Digital Microphones Uplink Characteristics
Contents
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
www.ti.com SWCS032C OCTOBER 2008 REVISED OCTOBER 2009
10.1 General Description Keyboard 11.1 Keyboard Connection Clock Specifications 12.1 Features 12.2 Input Clock Specifications 12.2.1 Clock Source Requirements 12.2.2 High-Frequency Input Clock 12.2.3 32-kHz Input Clock 12.2.3.1 External Crystal Description 12.2.3.2 External Clock Description 12.3 Output Clock Specifications 12.3.1 32KCLKOUT Output Clock 12.3.2 HFCLKOUT Output Clock 12.3.3 Output Clock Stabilization Time Timing Requirements Switching Characteristics 13.1 Timing Parameters 13.2 Target Frequencies 13.3 Timing 13.4 Audio Interface: TDM/I2S Protocol 13.4.1 Right- Left-Justified Data Format 13.4.2 Data Format 13.5 Voice/Bluetooth Interfaces 13.6 JTAG Interfaces Debouncing Time External Components TPS65950 Package 16.1 TPS65950 Standard Package Symbols 16.2 Package Thermal Resistance Characteristics 16.3 Mechanical Data 16.4 Specifications Glossary
Drivers
Copyright 2008-2009, Texas Instruments Incorporated
Contents
TPS65950
SWCS032C OCTOBER 2008 REVISED OCTOBER 2009 www.ti.com
List Figures
4-10 4-11 4-12 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32
TPS65950 Block Diagram PBGA Bottom View Power Provider Block Diagram VDD1 dc-dc Regulator Efficiency VDD1 dc-dc Application Schematic VDD2 dc-dc Regulator Efficiency VDD2 dc-dc Application Schematic dc-dc Regulator Efficiency Active Mode dc-dc Application Schematic Timings Before Sequence Start
Timings-OMAP2 Power-On Sequence Timings-OMAP3 Power-On Sequence Timings-Power Slave_C021_Generic Model Power-Off Sequence Master Modes Audio/Voice Module Block Diagram Earphone Amplifier Earphone Speaker Stereo Hands-Free Amplifiers
Headset Amplifier Headset 4-Wire Stereo Jack Without External FET. Headset 4-Wire Stereo Jack With External Headset 5-Wire Stereo Jack Headset 4-Wire Stereo Jack Optimized Headset Pop-Noise Cancellation Diagram Predriver External Class Vibrator H-Bridge Carkit Output Downlink Path Characteristics Digital Audio Filter Downlink Path Characteristics Digital Voice Filter Downlink Path Characteristics Voice Downlink Frequency Response With Voice Downlink Frequency Response With Analog Digital Microphone Multiplexing Analog Microphone Pseudodifferential Analog Microphone Differential Digital Microphone Bias Module Block Diagram Digital Microphone Bias Module Timing Diagram Silicon Microphone Module Audio Auxiliary Input Example Interface Circuitry Uplink Amplifier Carkit Input Uplink Path Characteristics Digital Audio Filter Uplink Path Characteristics Digital Audio Filter Uplink Path Characteristics Voice Uplink Frequency Response With (Frequency Range Voice Uplink Frequency Response With (Frequency Range 3000 3600
Stereo Hands-Free
List Figures
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
www.ti.com SWCS032C OCTOBER 2008 REVISED OCTOBER 2009
6-33 6-34 10-1 11-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 13-1 13-2 13-3 13-4 13-5 13-6 13-7 14-1 16-1 16-2 16-3
Voice Uplink Frequency Response With (Frequency Range Voice Uplink Frequency Response With (Frequency Range 6200 7000 Overview System Application Schematic. MCPC UART Handshake Mode Data Flow MCPC UART Handshake Mode Timings USB-CEA Carkit UART Data Flow USB-CEA Carkit UART Timing Parameters Interface-Transmit Receive Modes (ULPI 8-Bit) Typical Application Schematics Typical Application Schematic (In-Rush Current Limitation) Typical Application Schematic (BCI Used) Automatic Charge Sequence Timing Diagram Conversion Sequence General Timing Diagram
Driver Block Diagram Keyboard Connection Clock Overview HFCLKIN Clock Distribution Example Wired-OR Clock Request. HFCLKIN Squared Input Clock 32-kHz Oscillator Block Diagram Master Mode With Crystal 32-kHz Crystal Input 32-kHz Oscillator Block Diagram Without Crystal Option 32-kHz Oscillator Block Diagram Without Crystal Option 32-kHz Oscillator Bypass Mode Block Diagram Without Crystal Option 32-kHz Square- Sine-Wave Input Clock 32.768-kHz Clock Output Block Diagram 32KCLKOUT Output Clock HFCLKOUT Output Clock 32KCLKOUT HFCLKOUT Clock Stabilization Time HFCLKOUT Behavior Interface-Transmit Receive Slave Mode Interface-I2S Master Mode. Interface-I2S Slave Mode Interface-TDM Master Mode Voice/BT Interface-Master Mode (Mode Voice Interface-Slave Mode (Mode JTAG Interface Timing Debouncing Sequence Chronogram Example Printed Device Reference TPS65950 Mechanical Package View Ball Size
Copyright 2008-2009, Texas Instruments Incorporated
List Figures
TPS65950
SWCS032C OCTOBER 2008 REVISED OCTOBER 2009 www.ti.com
List Tables
4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 6-10 6-11 6-12 6-13 6-14
Ball Characteristics Signal Description Absolute Maximum Ratings VBAT Required VBAT Ball Associated Maximum Current
Summary Power Providers VDD1 dc-dc Regulator Characteristics VDD2 dc-dc Regulator Characteristics dc-dc Regulator Characteristics. VDAC Regulator Characteristics VPLL1 Regulator Characteristics VPLL2 Regulator Characteristics VMMC1 Regulator Characteristics. VMMC2 Regulator Characteristics. VSIM Regulator Characteristics VAUX1 Regulator Characteristics VAUX2 Regulator Characteristics VAUX3 Regulator Characteristics VAUX4 Regulator Characteristics Output Load Conditions Characteristics Voltage Reference Characteristics Backup Battery Charger Characteristics Battery Threshold Levels VRRTC Regulator Characteristics Power Consumption Regulator States Depending Cases BOOT Mode Description C027.0 Mode Description C021.M Mode Description System States Earphone Amplifier Output Characteristics Stereo Hands-Free Output Characteristics Headset Output Characteristics Output Characteristics Headset 4-Wire Stereo Jack Without External FET. Output Characteristics Headset 4-Wire Stereo Jack With External Output Characteristics Headset 5-Wire Stereo Jack Headset Pop-Noise Characteristics Predriver Output Characteristics Vibrator H-Bridge Output Characteristics MCPC USB-CEA Carkit Audio Downlink Electrical Characteristics Digital Audio Filter Electrical Characteristics Digital Voice Filter Electrical Characteristics With Digital Voice Filter Electrical Characteristics With Boost Electrical Characteristics Versus Frequency 22.05 kHz)
Recommended Operating Maximum Ratings Digital Electrical Characteristics
List Tables
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
www.ti.com SWCS032C OCTOBER 2008 REVISED OCTOBER 2009
6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 10-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10
Boost Electrical Characteristics Versus Frequency kHz) Analog Microphone Bias Module Characteristics Characteristics Analog Microphone Bias Module With Bias Resistor Digital Microphone Bias Module Characteristics Digital Microphone Bias Module Characteristics Silicon Microphone Module Characteristics
MCPC USB-CEA Carkit Audio Uplink Electrical Characteristics Digital Audio Filter Electrical Characteristics Digital Voice Filter Electrical Characteristics With Digital Voice Filter Electrical Characteristics With MCPC UART Handshake Mode Timings USB-CEA Carkit Interface Timing Parameters USB-CEA Carkit UART Timing Parameters Interface Timing Requirement Parameters Interface Switching Requirement Parameters 5V-Tolerant Electrical Summary LS/FS Single-Ended Receivers LS/FS Differential Receiver LS/FS Differential Transmitter Differential Receiver Differential Transmitter CEA/MCPC/UART Driver Pullup/Pulldown Resistors DPLL Electrical Characteristics Power Consumption. VBUS Electrical. Electrical
Uplink Amplifier Characteristics Main Charge Electrical Characteristics VBAT 0.22 unless otherwise specified
Precharge Electrical Characteristics 0.22 unless otherwise specified Mode Electrical Characteristics
Precharge Detection Characteristics Main Charge Current Limit Indication Electrical Characteristics Analog Input Voltage Range
Sequence Conversion Timing Characteristics Electrical Characteristics TPS65950 Input Clock Source Requirements HFCLKIN Input Clock Electrical Characteristics HFCLKIN Square Input Clock Timing Requirements With Slicer Bypass Crystal Electrical Characteristics
Base Oscillator Switching Characteristics 32-kHz Crystal Input Clock Timing Requirements 32-kHz Input Square- Sine-Wave Clock Source Electrical Characteristics 32-kHz Square-Wave Input Clock Source Timing Requirements 32KCLKOUT Output Clock Electrical Characteristics 32KCLKOUT Output Clock Switching Characteristics
List Tables
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
SWCS032C OCTOBER 2008 REVISED OCTOBER 2009 www.ti.com
12-11 12-12 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 14-1 15-1 16-1 16-2
HFCLKOUT Output Clock Electrical Characteristics HFCLKOUT Output Clock Switching Characteristics Timing Parameters
TPS65950 Interface Target Frequencies Interface Timing Requirements Interface Switching Requirements Interface-Timing Requirements. Interface-Switching Characteristics Interface Master Mode Timing Requirements Interface Master Mode Switching Characteristics
Voice Interface Timing Requirements (Mode Voice Interface Switching Characteristics (Mode JTAG Interface Timing Requirements. JTAG Interface Switching Characteristics Debouncing Time TPS65950 External Components TPS65950 Nomenclature Description TPS65950 Thermal Resistance Characteristics
List Tables
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
www.ti.com SWCS032C OCTOBER 2008 REVISED OCTOBER 2009
Integrated Power Management/Audio Codec
Check Samples: TPS65950
Introduction
TPS65950 device highly integrated power-management audio coder/decoder (codec) integrated circuit (IC) that supports power peripheral requirements OMAPapplication processors. device contains power management, audio codec, universal serial (USB) high-speed (HS) transceiver, ac/USB charger, light-emitting diode (LED) drivers, analog-to-digital converter (ADC), real-time clock (RTC), embedded power control. power portion device contains three buck converters, controllable dedicated SmartReflexclass-3 interface, multiple low-dropout (LDO) regulators, embedded power controller (EPC) manage power-sequencing requirements OMAP, backup module. powered backup battery when main supply present, device contains coin-cell charger recharge backup battery needed. module provides on-the-go (OTG) transceiver suitable direct connection OMAP universal transceiver macrocell interface (UTMI) interface (ULPI) with integrated charge pump (CP) full support carkit Consumer Electronics Association (CEA)-936A specification. Li-ion battery charger supports charging from chargers, host devices, chargers, carkits. type charger detected automatically device, which provides hardware-controlled linear charging with chargers, chargers, carkits, addition software-controlled charging charger types. audio codec device includes five digital-to-analog converters (DACs) ADCs provide multiple voice channels stereo downlink channels that support standard audio sample rates through several inter-IC sound (I2STM)/time division multiplexing (TDM) format interfaces. audio output stages device include stereo headset amplifiers, integrated class-D amplifiers providing stereo differential outputs, predrivers line outputs, earpiece amplifier. input audio stages include three differential microphone inputs, stereo line inputs, interface digital micrphones. Automatic programmable gain control available with necessary digital filtering, side-tone functions, pop-noise reduction. device also provides auxiliary modules, including drivers, ADC, keypad interface, general-purpose inputs/outputs (GPIOs). driver power circuits illuminate panel provide user indicators. drivers also provide pulse width modulation (PWM) circuits control illumination levels LEDs. monitors signals entering device, such supply charging voltages, multiple additional external inputs system use. keypad interface implements built-in scanning algorithm decode hardware-based presses reduce software use, with multiple additional GPIOs that used interrupts when they configured inputs. This TPS65950 Data Manual describes electrical mechanical specifications TPS65950. covers following topics: TPS65950 terminals: Assignment, multiplexing, electrical characteristics, functional description (see Section Terminal Description) Electrical characteristic requirements: Maximum recommended operating conditions, digital input/output (I/O) characteristics (see Section Electrical Characteristics) Power module, including power provider, power references, power control, power consumption, power management with sequences (see Section Power Module) (see Section Real-Time Clock Embedded Power Controller) Audio/voice module with electrical characteristics application schematics downlink
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
SWCS032C OCTOBER 2008 REVISED OCTOBER 2009 www.ti.com
uplink paths (see Section Audio/Voice Module) Battery charger interface (see Section Battery Interface) Various modules: Monitoring analog-to-digital conversion (MADC), drivers, keyboard (see Section MADC, Section Drivers, Section Keyboard) Clock specifications: Clock slicer, input output clocks (see Section Clock Specifications) Timing requirements switching characteristics timings) interfaces (see Section Timing Requirements Switching Characteristics) Deboucing time (see Section Debouncing Time) External components application schematics (see Section External Components) Thermal resistance characteristics, device nomenclature, mechanical data about available packaging (see Section TPS65950 Package) Glossary acronyms abbreviations used this data manual (see Section Glossary)
Features
TPS65950 following features: Power: Three efficient stepdown converters external linear LDOs clocks peripherals SmartReflex dynamic voltage management Audio: Voice codec 15-bit linear codec kHz) Differential input main submicrophones Differential headset microphone input Auxiliary/FM input (mono stereo) Differential speaker headset drivers (external predrivers class stereo class-D drivers Pulse code modulation (PCM) interfaces Bluetooth® interface Automatic level control (ALC) Digital analog mixing 16-bit linear audio stereo (96, 44.1, kHz, derivatives) 16-bit linear audio stereo (48, 44.1, kHz, derivatives) Digital microphone inputs Carkit Charger: Li-ion, Li-on polymer, cobalt-nickel-manganese charger Supports charging with ac-regulated charger (maximum host devices, Mobile Computing Promotion Consortium (MCPC) devices, chargers, carkit chargers (maximum Backup battery charger USB: OTG-compliant transceivers 12-bit ULPI power supply (5-V VBUS) CEA-2011: transceiver interface specification
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Introduction Submit Documentation Feedback Product Folder Link(s): TPS65950
Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
www.ti.com SWCS032C OCTOBER 2008 REVISED OCTOBER 2009
CEA-936A: Mini-USB analog carkit interface specification MCPC ME-universal asynchronous receiver/transmitter (UART) GL-006 specification Additional features: driver circuit external LEDs 10-bit MADC with external inputs retention modules inter-integrated circuit (I2CTM) serial control Thermal shutdown hot-die detection Keypad interface External vibrator (vibrator) control GPIO devices 0.4-mm pitch, pin, package
TPS65950 Block Diagram
Figure block diagram TPS65950.
Copyright 2008-2009, Texas Instruments Incorporated
Introduction Submit Documentation Feedback Product Folder Link(s): TPS65950
TPS65950
SWCS032C OCTOBER 2008 REVISED OCTOBER 2009 www.ti.com
Device
Digital signal(s) Analog signal(s) Interface subchip(D)
Audio
Audio amplifiers amplifiers Analog volume control converters converters Differential vibrator Carkit preamplifiers
Digital interface
AUDIO analog
Analog digital bias
Clock generator
Clocks
Audio voice filters paths) Vibrator control
Bluetooth interface interface
TDM/I2S interface
In/Out GPIO GPIO Card Det1 Card Det2
Wrapper digital
AUDIO digital Audio subchip (A-D)
SIH_INT
Clocks
Clocks SIH_INT
Clocks
SIH_INT digital (ULPI/ registers interrupts MCPC carkit)
Analog carkit interfaces module USB2.0 transceiver
power supply precharge module
ULPI (12) UART(2) BERCLK
Shundan Felica Vibrator control Smart Reflex Power digital
Clocks
master slave
Slave wrapper MHz/32
SIH_INT
subchip (A-D)
BERDATA
Auxiliary subchip (A-D) Precharge loop Keypad digital Precharge Precharge status Main loop Main Main analog
Power analog Thermal monitor system
Clock slicer
oscillator BCITOP LEDTOP
Shifters
Power control (BBS-backup VRRTC-UVLO)
Power provider (LDOs-DCDCs)
Power references (Vref-Iref-BandGap)
digital MADC digital state-machine analog
MADC analog (SAR-Vref)
Power subchip (A-D)
MADCTOP
LedSync
StartADC 032-003
Figure 1-1. TPS65950 Block Diagram
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Copyright 2008-2009, Texas Instruments Incorporated
TPS65950
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Terminal Description
Figure shows ball locations 209-ball plastic ball grid array (PBGA) package used with Table locate signal names ball grid numbers.
032-088
Figure 2-1. PBGA Bottom View
Corner Balls
four corner balls (see following list) usable functional pins: Test TestV1 Test.RESET TestV2 eight corner adjacent balls are: RFID.EN UART1.TXD JTAG.TDI/BERDATA JTAG.CLK/BERCLK PCM.VFS PCM.VDX PCM.VDR PCM.VCK
Copyright 2008-2009, Texas Instruments Incorporated
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Ball Characteristics
Table describes terminal characteristics signals multiplexed each pin. following list describes column headings Table 2-1: Ball: Ball number(s) associated with each signal(s) Name: Names signals that multiplexed each ball A/D: Analog digital signal Type: Terminal type when particular signal multiplexed terminal Input Output Open drain Reference Level: Voltage applied cell (see power module battery charger interface [BCI] chapters values). PU/PD: Denotes presence internal pullup pulldown. Pullups pulldowns enabled disabled through software. Minimum value Typical value Maximum value Buffer Strength: Drive strength associated output buffer
Table 2-1. Ball Characteristics
Ball[1] JTAG.TDO GPIO1/CD2 JTAG.TMS GPIO2 Test1 GPIO15 Test2 GPIO6 PWM0 Test3 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 Name[2] ADCIN0 ADCIN1 ADCIN2 VCCS VBATS PCHGAC PCHGUSB VPRECH BCIAUTO ICTLUSB1 ICTLUSB2 ICTLAC1 ICTLAC2 VBAT GPIO0/CD1 Type[4] Power Power Reference Level RL[5] VINTANA1.OUT VINTANA1.OUT VINTANA2.OUT VBAT VACCHARGER VBAT VACCHARGER VBUS VPRECH VPRECH VBUS VCCS VACCHARGER VCCS VBAT IO_1P8 PU[6] Min[7] Typ[8] Max[9] PD[6] Buffer Strength (mA)[10]
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Table 2-1. Ball Characteristics (continued)
Ball[1] Name[2] GPIO7 VIBRA.SYNC PWM1 Test4 I2C.SR.SDA VMODE2 I2C.SR.SCL DIG.MIC.0 MIC.SUB.M DIG.MIC.1 HSMIC.P HSMIC.M VBAT.LEFT VBAT.LEFT IHF.LEFT.P IHF.LEFT.M GND.LEFT GND.LEFT Power Power Power Power VMIC2.OUT VINTANA2.OUT VINTANA2.OUT VBAT VBAT VBAT VBAT VMIC1.OUT MICBIAS2.OUT I2C.CNTL.SDA I2C.CNTL.SCL PCM.VCK PCM.VDR PCM.VDX PCM.VFS I2S.CLK I2S.SYNC I2S.DIN I2S.DOUT MIC.MAIN.P MIC.MAIN.M MIC.SUB.P IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 MICBIAS1.OUT MICBIAS1.OUT MICBIAS2.OUT IO_1P8 IO_1P8 START.ADC SYSEN CLKEN CLKEN2 CLKREQ INT1 INT2 NRESPWRON NRESWARM PWRON NSLEEP1 NSLEEP2 CLK256FS VMODE1 BOOT0 BOOT1 REGEN MSECURE VREF AGND Power Power IO_1P8 IO_1P8 IO_1P8 IO_1P8 VBAT VBAT VBAT IO_1P8 VREF OD/I IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 VBAT 7.35 Type[4] Reference Level RL[5] IO_1P8 IO_1P8 PU[6] Min[7] Typ[8] Max[9] PD[6] Buffer Strength (mA)[10]
avoid reflection this caused impedance mismatch, serial resistance (Rs) must added. Terminal Description Submit Documentation Feedback Product Folder Link(s): TPS65950
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Table 2-1. Ball Characteristics (continued)
Ball[1] VMID ADCIN7 VMIC1.OUT MICBIAS2.OUT VMIC2.OUT VHSMIC.OUT MICBIAS.GND Power Power Power Power Power Power Power OD/CMOS/I/O Power VINTANA2.OUT VINTANA2.OUT External IO_1P8 IO_1P8 VUSB.3P1 VINTANA2.OUT VUSB.3P1 VINTANA2.OUT VUSB.3P1 VINTANA2.OUT VUSB.3P1 VINTANA2.OUT VUSB.3P1 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 VBUS VBUS VBUS VBUS IO_1P8 IO_1P8 GPIO9 GPIO10 IO_1P8 IO_1P8 IO_1P8 Power Power VINTANA2.OUT VINTANA2.OUT AUXL AUXR MICBIAS1.OUT Power VINTANA2.OUT VINTANA2.OUT VINTANA2.OUT VINTANA2.OUT HSOR PreDriv.RIGHT Power VINTANA2.OUT VINTANA2.OUT VINTANA2.OUT Name[2] VBAT.RIGHT VBAT.RIGHT IHF.RIGHT.P IHF.RIGHT.M GND.RIGHT GND.RIGHT EAR.P EAR.M HSOL PreDriv.LEFT Type[4] Power Power Power Power Reference Level RL[5] VBAT VBAT VBAT VBAT VINTANA2.OUT VINTANA2.OUT VINTANA2.OUT VINTANA2.OUT PU[6] Min[7] Typ[8] Max[9] PD[6] Buffer Strength (mA)[10]
AVSS1 UART1.RXD RTSO/ CLK64K.OUT/ BERCLK.OUT ADCIN5 CTSI/ BERDATA.OUT ADCIN3 TXAF ADCIN4 RXAF ADCIN6 MANU 32KCLKOUT 32KXIN 32KXOUT HFCLKIN HFCLKOUT VBUS DP/UART3.RXD DN/UART3.TXD UCLK AVSS2 AVSS3 AVSS4 UART1.TXD GPIO8
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Table 2-1. Ball Characteristics (continued)
Ball[1] GPIO11 DATA0 UART4.TXD DATA1 UART4.RXD DATA2 UART4.RTSI DATA3 UART4.CTSO GPIO12 DATA4 GPIO14 DATA5 GPIO3 DATA6 GPIO4 DATA7 GPIO5 TEST.RESET TESTV1 TESTV2 TEST JTAG.TDI/ BERDATA JTAG.TCK/ BERCLK CP.IN CP.CAPP CP.CAPM CP.GND VBAT.USB VUSB.3P1 VAUX12S.IN VAUX1.OUT VAUX2.OUT VPLLA3R.IN VRTC.OUT VPLL1.OUT VSDI.CSI.OUT VAUX3.OUT VAUX4.IN VAUX4.OUT VMMC1.IN VMMC1.OUT VMMC2.IN VMMC2.OUT VSIM.OUT VINTUSB1P5. VINTUSB1P8. VDAC.IN VDAC.OUT VINT.IN VINTANA1.OUT Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power IO_1P8 VBAT VBAT VINTANA2.OUT IO_1P8 IO_1P8 IO_1P8 VBAT/VBUS CP.CAPP CP.CAPM VBAT VUSB.3P1 VBAT VAUX1.OUT VAUX2.OUT VBAT VRTC.OUT VPLL1.OUT VSDI.CSI.OUT VAUX3.OUT VBAT VAUX4.OUT VBAT VMMC1.OUT VBAT VMMC2.OUT VSIM.OUT VINTUSB1P5.OUT VINTUSB1P8.OUT VBAT VDAC.OUT VBAT VINTANA1.OUT IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 Name[2] Type[4] Reference Level RL[5] IO_1P8 PU[6] Min[7] Typ[8] Max[9] PD[6] Buffer Strength (mA)[10]
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Table 2-1. Ball Characteristics (continued)
Ball[1] Name[2] VINTANA2.OUT VINTANA2.OUT VINTDIG.OUT VDD1.IN VDD1.IN VDD1.IN VDD1.SW VDD1.SW VDD1.SW VDD1.FB VDD1.GND VDD1.GND VDD1.GND VDD2.IN VDD2.IN VDD2.FB VDD2.SW VDD2.SW VDD2.GND VDD2.GND VIO.IN VIO.IN VIO.FB VIO.SW VIO.SW VIO.GND VIO.GND BKBAT IO.1P8 Type[4] Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power VBAT VBAT VBACK IO_1P8 IO_1P8 LEDSYNC LEDA VIBRA.P LEDB VIBRA.M KPD.C0 KPD.C1 KPD.C2 KPD.C3 KPD.C4 KPD.C5 KPD.C6 KPD.C7 KPD.R0 KPD.R1 KPD.R2 KPD.R3 KPD.R4 KPD.R5 KPD.R6 KPD.R7 VBAT IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 VBAT VBAT IO_1P8 VBAT VBAT VBAT VBAT VBAT VBAT VBAT Reference Level RL[5] VINTANA2.OUT VINTANA2.OUT VINTDIG.OUT VBAT VBAT VBAT VBAT VBAT VBAT PU[6] Min[7] Typ[8] Max[9] PD[6] Buffer Strength (mA)[10]
DGND LEDGND GPIO13
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Table 2-1. Ball Characteristics (continued)
Ball[1] Name[2] GPIO16 BT.PCM.VDR DIG.MIC.CLK0 GPIO17 BT.PCM.VDX DIG.MIC.CLK1 RFID.EN Type[4] Reference Level RL[5] IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 IO_1P8 VMMC2.OUT PU[6] Min[7] Typ[8] Max[9] PD[6] Buffer Strength (mA)[10]
Signal Description
Table lists signals TPS65950; some signals available multiple pins. Table 2-2. Signal Description
Signal Name ADCIN0 Type
Module
Description
Ball
Configuration Default After Reset Released Signal Type Power Power
Internal Pull
Unused Features GND(3) GND(3) GND(3) Floating Floating Floating Floating VBAT Floating
Battery type Battery temperature General-purpose (GP) input Charge current sensing Charge device input voltage Charge current sensing precharge sense signal. Used also EEPROM precharge sense signal Precharge regulator output Linear charge specific boot mode power device control power device control power device control power device control Battery voltage sensing GPIO0/card detection JTAG test data output GPIO1/card detection JTAG test mode state GPIO2 Test1 used test mode only GPIO15 Test2 used test mode only GPIO6 Pulse width driver Test3 used test mode only (controlled JTAG) GPIO7 Vibrator on-off synchronization Pulse width driver Test4 used test mode only (controlled JTAG) conversion request
Power Power
ADCIN0 ADCIN1 ADCIN2 VCCS VBATS PCHGAC PCHGUSB VPRECH BCIAUTO ICTLUSB1 ICTLUSB2 ICTLAC1 ICTLAC2 VBAT GPIO0
ADCIN1 ADCIN2 VCCS VBATS PCHGAC PCHGUSB
Charger
VPRECH BCIAUTO ICTLUSB1 ICTLUSB2 ICTLAC1 ICTLAC2 VBAT GPIO0/CD1 JTAG.TDO GPIO1/CD2 JTAG.TMS GPIO2 Test1 GPIO15
GPIO1
Floating
GPIO2
Floating
GPIOs/ JTAG
Test2 GPIO6 PWM0 Test3 GPIO7 VIBRA.SYNC PWM1 Test4
GPIO15
Floating
GPIO6
Floating
GPIO7
Floating
START.
START.ADC
START.ADC
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Table 2-2. Signal Description (continued)
Module Signal Name SYSEN CLKEN CLKEN2 CLKREQ INT1 INT2 NRESPWRON NRESWARM PWRON NSLEEP1 NSLEEP2 CLK256FS VMODE1 BOOT0 BOOT1 REGEN MSECURE VREF VREF AGND SmartReflex
Description
Type
Ball
Configuration Default After Reset Released Signal Type
Internal Pull
Unused Features Floating Floating Floating Floating Floating Floating VBAT Floating
System enable output Clock enable Clock enable Clock request Output interrupt line Output interrupt line Output control NRESPWRON application processor Input, detect user action reset button Input, detect control command start stop system connected Sleep request from device Sleep request from device Control output Digital voltage scaling linked with VDD1 Boot Boot Enable signal external Security digital rights management Reference voltage Analog ground reference voltage connected SmartReflex data Digital voltage scaling linked with VDD2 SmartReflex data data clock Data clock (voice port) Data receive (voice port) Data transmit (voice port) Frame synchronization (voice port) Clock signal (audio port) Synchronization signal (audio port) Data receive (audio port) Data transmit (audio port) Main microphone left input Main microphone left input Main microphone right input Digital microphone input data Main microphone right input Digital microphone input data Headset microphone input Headset microphone input
OD/I
SYSEN CLKEN CLKEN2 CLKREQ INT1 INT2 NRESPWRON NRESWARM PWRON NSLEEP1 NSLEEP2 CLK256FS VMODE1 BOOT0 BOOT1 REGEN MSECURE VREF AGND Signal functional(4)
CONTROL
Power Power
Power Power
Floating Floating Floating
I2C.SR.SDA VMODE2 I2C.SR.SCL
VMODE2 I2C.CNTL.SDA I2C.CNTL.SCL PCM.VCK PCM.VDR PCM.VDX PCM.VFS I2S.CLK I2S.SYNC I2S.DIN I2S.DOUT MIC.MAIN.P MIC.MAIN.M MIC.SUB.P
Floating Floating Floating Floating Floating Floating
I2C.CNTL.SDA I2C.CNTL.SCL PCM.VCK
PCM.VDR PCM.VDX PCM.VFS I2S.CLK
I2S.SYNC I2S.DIN I2S.DOUT MIC.MAIN.P MIC.MAIN.M
ANA.MIC
MIC.SUB.P DIG.MIC.0 MIC.SUB.M DIG.MIC.1
MIC.SUB.M HSMIC.P HSMIC.M
Headset microphone
HSMIC.P HSMIC.M
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Table 2-2. Signal Description (continued)
Module Signal Name VBAT.LEFT VBAT.LEFT IHF.LEFT.P IHF.LEFT.M GND.LEFT GND.LEFT Hands-free VBAT.RIGHT VBAT.RIGHT GND.RIGHT GND.RIGHT IHF.RIGHT.P IHF.RIGHT.M EAR.P Earpiece EAR.M HSOL PreDriv.LEFT Headset VMID HSOR PreDriv.RIGHT ADCIN7 input AUXL AUXR MICBIAS1. VMIC1.OUT MICBIAS2. VMIC2.OUT VMIC BIAS VHSMIC.OUT MICBIAS.GND AVSS1 AVSS2 AVSS3 AVSS4 UART1.TXD Headset UART GPIO8 UART1.RXD Headset UART transmit data GPIO8 Headset universal asynchronous receiver/transmitter (UART) receive data/switch detection GPIO8 Floating Analog ground Power Description Type
Ball
Configuration Default After Reset Released Signal Type
Internal Pull
Unused Features VBAT VBAT Floating Floating VBAT VBAT Floating Floating Floating Floating Floating
Battery voltage input Battery voltage input Hands-free speaker output left Hands-free speaker output left Battery voltage input Battery voltage input Hands-free speaker output right Hands-free speaker output right Earpiece output differential output Earpiece output differential output Differential/single-ended headset left output Predriver output left external class-D amplifier Pseudo-ground headset output Differential/single-ended headset right output Predriver output right external class-D amplifier input Auxiliary audio input left Auxiliary audio input right Analog microphone bias Digital microphone power supply Analog microphone bias Digital microphone power supply Headset microphone bias Dedicated ground microphones
Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power
VBAT.LEFT VBAT.LEFT IHF.LEFT.P IHF.LEFT.M GND.LEFT GND.LEFT VBAT.RIGHT VBAT.RIGHT GND.RIGHT GND.RIGHT IHF.RIGHT.P IHF.RIGHT.M EAR.P EAR.M HSOL
Power Power Power Power Power Power Power Power
VMID
Power
Floating
HSOR
Floating
ADCIN7 AUXL AUXR MICBIAS1.OUT
Power
Floating
J4/J6/ J7/J8/E5
MICBIAS2.OUT VHSMIC.OUT MICBIAS.GND AVSS1 AVSS2 AVSS3 AVSS4 UART1.TXD
Power Power Power
Floating Floating
Power
Floating
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Table 2-2. Signal Description (continued)
Module Signal Name Description Type
Ball
Configuration Default After Reset Released Signal Type
Internal Pull
Unused Features
RTSO/ CLK64K.OUT/ BERCLK.OUT ADCIN5 CTSI/ BERDATA.OUT MCPC ADCIN3 TXAF ADCIN4 RXAF ADCIN6 MANU 32KCLKOUT 32KXIN Clock 32KXOUT HFCLKIN HFCLKOUT VBUS UART3.RXD UART3.TXD UCLK GPIO9 GPIO10 GPIO11 DATA0 UART4.TXD DATA1 UART4.RXD ULPI DATA2 UART4.RTSI DATA3 UART4.CTSO GPIO12 DATA4 GPIO14 DATA5 GPIO3 DATA6 GPIO4 DATA7 GPIO5
Ready-to-send output/ 64-kHz output clock/ error ratio (BER) clock test mode input Clear-to-send input/ BERDATAOUT test mode input
RTSO/ CLK64K.OUT/ BERCLK.OUT
Floating
CMOS/ TXAF CTSI/ BERDATA.OUT
input
input Manufacturer Buffered output 32-kHz digital clock Input 32-kHz oscillator Output 32-kHz oscillator Input digital sine) clock clock output VBUS power rail data P/USB carkit receive data/UART3 receive data data N/USB carkit transmit data/UART3 transmit data clock stop GPIO9 direction GPIO10 next GPIO11 Data0 UART4.TXD Data1 UART4.RXD Data2 UART4.RTSI Data3 UART4.CTSO GPIO12 Data4 GPIO14 Data5 GPIO3 Data6 GPIO4 Data7 GPIO5
Power
RXAF MANU 32KCLKOUT 32KXIN 32KXOUT HFCLKIN HFCLKOUT VBUS DP/UART3.RXD DN/UART3.TXD UCLK
Power
Floating Floating Floating Floating Floating Connected VRUSB3V1 Floating Floating
Floating
Floating
DATA0
Floating
DATA1
Floating
DATA2
Floating
DATA3
Floating
DATA4
Floating
DATA5
Floating
DATA6
Floating
DATA7
Floating
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Table 2-2. Signal Description (continued)
Module Signal Name Description Type
Ball
Configuration Default After Reset Released Signal Type
Internal Pull
Unused Features
Test.RESET TestV1 TestV2 Test Test JTAG.TDI/ BERDATA JTAG.TCK/ BERCLK CP.IN CP.CAPP CP.CAPM CP.GND VBAT.USB USB.LDO VAUX1 VAUX2 VPLLA3R VRTC VPLL1 VPLL2 VAUX3 VAUX4 VBAT.USB VUSB.3P1 VAUX12S.IN VAUX1.OUT VAUX2.OUT VPLLA3R.IN VRTC.OUT VPLL1.OUT VSDI.CSI.OUT VAUX3.OUT VAUX4.IN VAUX4.OUT VMMC1.IN VMMC1.OUT VMMC2.IN VMMC2.OUT VSIM.OUT VINTUSB1P5. VINTUSB1P8. VDAC.IN VDAC.OUT VINT VINTANA1 VINT.IN VINTANA1. VINTANA2. VINTANA2. VINTDIG.OUT
Reset device (except power state-machine) Analog test Analog test Selection between JTAG mode application mode JTAG/GPIOs (with JTAG.TDI/BERDATA JTAG.TCK/BERCLK input voltage flying capacitor flying capacitor ground LDOs (VINTUSB1P5, VINTUSB1P8, VUSB.3P1) VBAT output VAUX1/VAUX2/VSIM input voltage VAUX1 output voltage VAUX2 output voltage Input VPLL1, VPLL2, VAUX3, VRTC LDOs VRTC internal output (internal only) output voltage Output voltage regulator VAUX3 output voltage VAUX4 input voltage VAUX4 output voltage VMMC1 input voltage VMMC1 output voltage VMMC2 input voltage VMMC2 output voltage VSIM output voltage VINTUSB1P5 internal output (internal only) VINTUSB1P8 internal output (internal only) Input VDAC, VINTANA1, VINTANA2 LDOs Output voltage regulator Input VINTDIG VINTANA1 internal output (internal only) VINTANA2 internal output (internal only) VINTANA2 internal output (internal only) VINTDIG internal output (internal only)
Test.RESET TestV1 TestV2 Test JTAG.TDI/ BERDATA JTAG.TCK/ BERCLK CP.IN CP.CAPP CP.CAPM CP.GND VBAT.USB VUSB.3P1 VAUX12S.IN VAUX1.OUT VAUX2.OUT VPLLA3R.IN VRTC.OUT VPLL1.OUT VSDI.CSI.OUT VAUX3.OUT VAUX4.IN VAUX4.OUT VMMC1.IN VMMC1.OUT VMMC2.IN VMMC2.OUT VSIM.OUT VINTUSB1P5. VINTUSB1P8. VDAC.IN VDAC.OUT VINT.IN VINTANA1.OUT VINTANA2.OUT VINTANA2.OUT VINTDIG.OUT
Floating Floating Floating
Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power
Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power
VBAT Floating Floating VBAT VBAT Floating Floating VBAT Floating Floating Floating VBAT Floating VBAT Floating VBAT Floating Floating Floating Floating VBAT Floating VBAT
VMMC1
VMMC2 VSIM VINTUSB1 VINTUSB1 Video
VINTANA2
VINTDIG
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Table 2-2. Signal Description (continued)
Module Signal Name VDD1.IN VDD1.IN VDD1.IN VDD1.SW VDD1.SW VDD1.SW VDD1 VDD1.FB VDD1.GND VDD1.GND VDD1.GND VDD2.IN VDD2.IN VDD2.FB VDD2 VDD2.SW VDD2.SW VDD2.GND VDD2.GND VIO.IN VIO.IN VIO.FB VIO.SW VIO.SW VIO.GND VIO.GND Backup battery Digital Digital ground BKBAT IO.1P8 DGND Description Type
Ball
Configuration Default After Reset Released Signal Type
Internal Pull
Unused Features VBAT VBAT VBAT Floating Floating Floating VBAT VBAT Floating Floating VBAT VBAT Floating Floating
VDD1 dc-dc input voltage VDD1 dc-dc input voltage VDD1 dc-dc input voltage VDD1 dc-dc switch VDD1 dc-dc switch VDD1 dc-dc switch VDD1 dc-dc output voltage (feedback) VDD1 dc-dc ground VDD1 dc-dc ground VDD1 dc-dc ground VDD2 dc-dc input voltage VDD2 dc-dc input voltage VDD2 dc-dc output voltage (feedback) VDD2 dc-dc switch VDD2 dc-dc switch VDD2 dc-dc ground VDD2 dc-dc ground dc-dc input voltage dc-dc input voltage dc-dc output voltage (feedback) dc-dc switch dc-dc switch dc-dc ground dc-dc ground Backup battery TPS65950 input Digital ground
Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power
VDD1.IN VDD1.IN VDD1.IN VDD1.SW VDD1.SW VDD1.SW VDD1.FB VDD1.GND VDD1.GND VDD1.GND VDD2.IN VDD2.IN VDD2.FB VDD2.SW VDD2.SW VDD2.GND VDD2.GND VIO.IN VIO.IN VIO.FB VIO.SW VIO.SW VIO.GND VIO.GND BKBAT IO.1P8
Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power
DGND LEDGND GPIO13 Signal functional(4) Signal functional(4)
LEDGND GPIO13 LEDSYNC driver LEDA VIBRA.P LEDB VIBRA.M
driver ground GPIO13 synchronization input H-bridge vibrator H-bridge vibrator
Power
Floating
Floating
Floating
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Table 2-2. Signal Description (continued)
Module Signal Name KPD.C0 KPD.C1 KPD.C2 KPD.C3 KPD.C4 KPD.C5 KPD.C6 Keypad KPD.C7 KPD.R0 KPD.R1 KPD.R2 KPD.R3 KPD.R4 KPD.R5 KPD.R6 KPD.R7 GPIO16 BT.PCM.VDR Bluetooth/ digital microphone DIG.MIC.CLK0 GPIO17 BT.PCM.VDX DIG.MIC.CLK1 RFID RFID.EN Description Type
Ball
Configuration Default After Reset Released Signal Type
Internal Pull
Unused Features Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating
Keypad column Keypad column Keypad column Keypad column Keypad column Keypad column Keypad column Keypad column Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Bluetooth receive data GPIO16 Digital microphone clock GPIO17 Bluetooth transmit data Digital microphone clock Enable radio frequency identification (RFID) device
KPD.C0 KPD.C1 KPD.C2 KPD.C3 KPD.C4 KPD.C5 KPD.C6 KPD.C7 KPD.R0 KPD.R1 KPD.R2 KPD.R3 KPD.R4 KPD.R5 KPD.R6 KPD.R7
GPIO16
Floating
GPIO17
Floating
RFID.EN
Floating
Input; Output; Open drain This column provides connection when associated feature used connected. When there muxing, functions muxed used. even function used, Default Configuration column applies. Connection criteria: Analog pins: input: output: Floating (except VPRECH connected GND) input default: (except audio features input: capacitor ground with 100-nF typical value capacitor) Digital pins: input: (except keypad left floating) input pullup: Floating output: Floating pullup: Floating (not applicable): When associated feature mandatory good functioning TPS65950. VPRECH, VBATS, VCCS signals must connected each other with CPRECH capacitor (see Section 8.2.3, Configuration with Used). Signal functional indicates that signal presented after release reset.
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Electrical Characteristics
Absolute Maximum Ratings
Table lists absolute maximum ratings. Table 3-1. Absolute Maximum Ratings
Parameter Test Conditions Where supply represents voltage applied power supply associated with input 1.4W (Theta 11°C/W 2S2P board) 1.0*Supply Unit
Main battery supply voltage Voltage input Storage temperature range Ambient temperature range Junction temperature (TJ)
Junction temperature (TJ) parametric compliance product tolerate voltage spikes total duration milliseconds.
Minimum Voltages Associated Currents
Table lists VBAT minimum maximum currents VBAT ball. Table 3-2. VBAT Required VBAT Ball Associated Maximum Current
Category Module Maximum Current Specified (mA) 1.85 2.85 3.15 Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected 2.75 Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected +250 Output Voltage VBAT Minimum
VBAT name VDD_VPLLA3R_IN_6POV VPLL1 (LDO) VPLL2 (LDO)
Internal module supplied
VAUX3 (LDO) VDD1 core (DCDC) VDD2 core (DCDC) SYSPOR (power ref) PBIAS (power ref)
VBAT name VDD_VDAC_IN_6POV VDAC (LDO) VINTANA1 (LDO) Internal module supplied VINTANA2 (LDO) core (DCDC) VAUX4 core (LDO) VBAT name VDD_VAUXI2S_IN_6POV
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Table 3-2. VBAT Required VBAT Ball Associated Maximum Current (continued)
Category Module Maximum Current Specified (mA) Output Voltage VBAT Minimum
VAUX1 (LDO) Internal module supplied VAUX2 (LDO)
Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected
VSIM (LDO) VBAT name VDD_VMMC2_IN_6POV VMMC2 (LDO) Power_REGBATT VBAT name VDD_VMMC1_IN_6POV VMMC1 (LDO) Power_REGBATT VBAT name VDD_VINT_IN_6POV VINTDIG (LDO) Internal module supplied VRRTC (LDO) VBACKUP (LDO) VBAT name VDD_VAUX4_IN_6POV VAUX4 (LDO)
0.001 0.001
1.85 2.85 3.15
1.85 2.85 3.15
Maximum (2.7, output voltage selected
Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected Maximum (2.7, output voltage selected output voltage selected
1.85 2.85 3.15
Recommended Operating Conditions
Table lists recommended operating maximum ratings. Table 3-3. Recommended Operating Maximum Ratings
Parameter 2.7(1) Unit
Main battery supply voltage Backup battery supply voltage Ambient temperature range
minimum threshold battery which device will turn OFF. However, minimum voltage which device will power ±100 PWRON does have switch connected VBAT) considering battery plug device switch event. PWRON switch then minimum device turn
Digital Electrical Characteristics
Table describes digital electrical characteristics. Reference level voltage applied cell VOL: Low-level output voltage VOH: High-level output voltage VIL: Low-level input voltage VIH: High-level input voltage
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Table 3-4. Digital Electrical Characteristics
Name GPIO0/CD1 JTAG.TDO GPIO0/CD2 JTAG.TMS GPIO2 Test1 GPIO15 Test2 GPIO16 PWM0 Test3 GPIO17 VIBRA.SYNC PWM1 Test4 START.ADC SYSEN CLKEN CLKEN2 CLKREQ INT1 INT2 NRESPWRON NRESWARM PWRON NSLEEP1 NSLEEP2 CLK256FS VMODE1 BOOT0 BOOT1 REGEN MSECURE I2C.SR.SDA VMODE2 I2C.SR.SCL I2C.CNTL.SDA I2C.CNTL.SCL PCM.VCK PCM.VDR PCM.VDX PCM.VFS I2S.CLK I2S.SYNC I2S.DIN I2S.DOUT UART1.TXD GPIO8 UART1.RXD RTSO/CLD64K.OUT/ BERCLK.OUT CTSI/BERDATA.OUT MANU 32KCLKOUT 0.45 0.45 0.45 0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 0.032 33.0 33.0 33.0 33.0 33.0 33.0 0.45 RL-0.45 33.0 33.0 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 -0.5 -0.5 -0.5 -0.5 0.45 0.45 0.45 0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 VBAT RL+0.5 RL+0.5 RL+0.5 RL+0.5 12.288 3.25 3.25 10.0 100.0 100.0 100.0 33.0 33.0 33.0 33.0 29.0 33.0 10.0 33.0 100.0 33.0 33.0 33.0 33.0 33.0 29.0 33.0 29.4 10.0 29.4 10.0 16.7 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 16.3 33.3 33.3 33.3 33.3 33.3 16.7 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 16.3 33.3 33.3 33.3 33.3 33.3 0.45 RL-0.45 0.35xRL 0.65xRL 0.45 RL-0.45 0.35xRL 0.65xRL 0.45 RL-0.45 0.35xRL 0.65xRL 0.45 RL-0.45 0.35xRL 0.65xRL 0.45 RL-0.45 0.35xRL 0.65xRL 0.45 RL-0.45 0.35xRL 0.65xRL Freq (MHz) Load (pF) Rise Fall Time (ns) Output Mode Time (ns)
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Table 3-4. Digital Electrical Characteristics (continued)
Name HFCLKOUT UCLK GPIO9 GPIO10 GPIO11 DATA0 UART4.TXD DATA1 UART4.RXD DATA2 UART4.RTSI DATA3 UART4.CTSO GPIO12 DATA4 GPIO14 DATA5 GPIO3 DATA6 GPIO4 DATA7 GPIO5 Test.RESET Test JTAG.TDI/ BERDATA JTAG.TCK/ BERDATA GPIO13 LEDSYNC KPD.C0 KPD.C1 KPD.C2 KPD.C3 KPD.C4 KPD.C5 KPD.C6 KPD.C7 KPD.R0 KPD.R1 KPD.R2 KPD.R3 KPD.R4 KPD.R5 KPD.R6 KPD.R7 GPIO16 DIG.MIC.CLK0 BT.PCM.VDX GPIO17 DIG.MIC.CLK1 BT.PCM.VDX 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 0.033 29.0 29.0 29.0 29.0 29.0 29.0 29.0 29.0 3051.8 3051.8 3051.8 3051.8 3051.8 3051.8 3051.8 3051.8 33.3 41.7 100.0 33.3 41.7 100.0 29.0 29.0 29.0 29.0 29.0 29.0 29.0 29.0 3051.8 3051.8 3051.8 3051.8 3051.8 3051.8 3051.8 3051.8 33.3 41.7 100.0 33.3 41.7 100.0 0.45 RL-0.45 33.3 33.3 0.45 0.45 0.45 0.45 RL-0.45 RL-0.45 RL-0.45 RL-0.45 33.0 29.0 33.0 33.0 33.0 29.0 33.0 33.0 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 RL-0.45 0.45 0.45 RL-0.45 RL-0.45 Freq (MHz) 38.4 Load (pF) Rise Fall Time (ns) Output Mode Time (ns)
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Table 3-4. Digital Electrical Characteristics (continued)
Name RFID.EN Freq (MHz) Load (pF) Rise Fall Time (ns) Output Mode Time (ns)
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Power Module
This section describes electrical characteristics voltage regulators timing characteristics supplies digitally controlled TPS65950. Figure block diagram power provider.
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Main battery
VPLL1.OUT CVPLL1.OUT
VPLL1
1.0/1.2/1.3/1.8
VPLLA3R.IN
VINT.IN
VINTDIG
1.0/1.2/1.3/1.5
VINTDIG.OUT CVINTDIG.OUT
VPLL2 VPLL2.OUT 0.7/1.0/1.2/1.3/1.5/1.8/1.85
VPLLA3R.IN
CVPLL2.OUT
/2.5/2.6/2.8/2.85/3.0/3.15
VDAC.IN
VINTANA1
1.5V
VINTANA.OUT CVINTANA1.OUT
VMMC1.OUT CVMMC1.OUT
VMMC1
1.85/2.85 /3.0/3.15
VMMC1.IN
VDAC.IN
VINTANA2
2.5/2.75
VINTANA2.OUT CVINTANA2.OUT
VMMC2.OUT CVMMC2.OUT
VMMC2
1.0/1.2/1.3/1.5/1.8/1.85/ 2.5/2.6/2.8/2.85 /3.0/3.15
VMMC2.IN
VDAC.IN
VDAC
1.2/1.3/1.8
VDAC.OUT CVDAC.OUT
VAUX1.OUT CVAUX1.OUT
VAUX1
1.5/1.8/2.5/2.8/3.0
VAUX12S.IN
VSIM
VAUX12S.IN 1.0/1.2/1.3/ 1.8/2.8/3.0
VSIM.OUT CVSIM.OUT
VAUX2.OUT CVAUX2.OUT
VAUX2
1.3/1.5/1.7/1.8/1.9/2.0/ 2.1/2.2/2.3/2.4/2.5/2.8
VAUX12S.IN
VDD1.IN
VDD1.L
LVDD1
VDD1 (DC-DC)
1.45 1200
VDD1.OUT
VDD1.GND
CVDD1.OUT
VAUX3.OUT CVAUX3.OUT
VAUX3 1.5/1.8/2.5/2.8/3.0
VPLLA3R.IN VDD2.L
VDD2.IN
LVDD2
CVDD2.OUT
VAUX4
VDD2 (DC-DC)
VDD2.OUT
VDD2.GND
VAUX4.OUT CVAUX4.OUT
0.7/1.0/1.2/1.3/1.5/1.8/ 1.85/2.5/2.6/2.8/ 2.85/3.0/3.15
VAUX4.IN
VIO.L VUSB.3P1 CVUSB.3P1
LVIO
CVIO.OUT
VRUSB_3V1
VBAT.USB
VIO.IN
(DC-DC)
V/1.85
VIO.OUT
VIO.GND
VINTUSB1P8.OUT CVINTUSB1P8.OUT
VRUSB_1V8
1.81
VBAT.USB
VINTUSB1P5.OUT CVINTUSB1P5.OUT
VRUSB_1V5
1.525
VBAT.USB
032-002
Figure 4-1. Power Provider Block Diagram
NOTE component values, Table 15-1.
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Power Providers
Table lists power providers. Table 4-1. Summary Power Providers
Default Voltage Depending Boot Mode OMAP2 Mode 1.85 2.75 OMAP3 Mode 2.75
Name
Type
Voltage Range
Maximum Current 1200
VAUX1 VAUX2 VAUX3 VAUX4 VMMC1 VMMC2 VPLL1 VPLL2 VSIM VDAC VDD1 VDD2 VINTANA1 VINTANA2 VINTDIG USBCP VUSB1V5 VUSB1V8 VUSB3V1 VRRTC VBRTC
External External External External External External External External External External External External External Internal Internal Internal Internal Internal Internal Internal Internal Internal
SMPS SMPS SMPS
1.5, 1.8, 2.5, 2.8, 1.3, 1.5, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 1.5, 1.8, 2.5, 2.8, 0.7, 1.0, 1.2, 1.5, 1.8, 1.85, 2.5, 2.6, 2.8, 2.85, 3.0, 3.15 1.85, 2.85, 3.0, 3.15 1.0, 1.2, 1.3, 1.5, 1.8, 1.85, 2.5, 2.6, 2.8, 2.85, 3.0, 3.15 1.0, 1.2, 1.3, 1.8, 2.8, 0.7, 1.0, 1.2, 1.3, 1.5, 1.8, 1.85, 2.5, 2.6, 2.8, 2.85, 3.0, 3.15 1.0, 1.2, 1.3, 1.8, 2.8, 1.2, 1.3, 1.8, 1.85 1.45 2.5, 2.75 1.0, 1.2, 1.3,
significance boot mode, Section Power Management.
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4.1.1
4.1.1.1
VDD1 dc-dc Regulator
VDD1 dc-dc Regulator Characteristics
VDD1 dc-dc regulator stepdown dc-dc converter with configurable output voltage. programming output voltage characteristics dc-dc converter SmartReflex-compatible. regulator sleep mode reduce leakage (PFM) power-down mode when being used. Table lists characteristics regulator. Table 4-2. VDD1 dc-dc Regulator Characteristics
Parameter Input voltage range Output voltage Output voltage step Output accuracy Switching frequency Conversion efficiency (2), Figure active sleep modes sleep Output current Ground current (IQ) Active mode Sleep mode 30°C Sleep, unloaded Active, unloaded, switching Short-circuit current Load regulation Transient load regulation Line regulation Transient line regulation Startup time Recovery time Slew rate (rising falling) Output shunt resistor (pulldown) Value External coil Saturation current Value External capacitor Equivalent series resistance (ESR) switching frequency From sleep mode mode with constant load mVPP input, 10-s rise fall time 0.25 VMax IMax (IMax/2)+10 Maximum slew rate IMax/2/100 Covering 1.45-V range 1.45 mV/s Comments 12.5 1.45 Unit
Accuracy includes variations (line load regulations, line load transients, temperature, process). VBAT VDD1 MHz, LDCR Output voltage must discharge load current completely settle final value within Load current varies proportionally with output voltage. slew rate increasing decreasing voltages maximum load current Under current load condition step: Imax/2 (550 with ±20% external capacitor accuracy Imax/3 (367 with ±50% external capacitor accuracy
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Table connect VDD1/2 dc-dc converter when used. Figure shows efficiency VDD1 dc-dc regulator active sleep modes.
Output voltage VBAT
Effciency
0.0001
0.001
0.01 Iload
032-004
Figure 4-2. VDD1 dc-dc Regulator Efficiency 4.1.1.2 External Components Application Schematic
Figure application schematic with external components VDD1 dc-dc regulator.
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Device VDD1.IN (D14) VDD1.IN (E14) VDD1.IN (E15) VDD1.SW (C14) LVDD1 VDD1.SW (D15) VDD1.SW (D16) CVDD1.OUT VDD1.GND (B15) VDD1.GND (C15) VDD1.GND (C16)
032-005
Figure 4-3. VDD1 dc-dc Application Schematic
NOTE component values, Table 15-1.
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4.1.2
4.1.2.1
VDD2 dc-dc Regulator
VDD2 dc-dc Regulator Characteristics
VDD2 dc-dc regulator programmable output stepdown dc-dc converter with internal field effect transistor (FET). Like VDD1 regulator, VDD2 regulator placed sleep power-down mode SmartReflex-compatible. VDD2 regulator differs from VDD1 current load capability. Table lists characteristics regulator. Table 4-3. VDD2 dc-dc Regulator Characteristics
Parameter Input voltage range Output voltage Output voltage step Output accuracy Switching frequency Conversion efficiency sleep mode
Comments
12.5
Unit
Covering 0.6-V 1.45-V range, single programmable value. sleep Active mode Sleep mode 30°C Sleep, unloaded Active, unloaded, switching
mV/s
Figure active mode
Output current Ground current (IQ)
Short-circuit current Load regulation Transient load regulation Line regulation Transient line regulation Output shunt resistor (internal pulldown) Startup time Recovery time Slew rate (rising falling)
VMax IMax (IMax/2) Maximum slew rate IMax/2/100 mVPP input, 10-s rise fall time
0.25
From sleep mode mode with constant load Value Saturation current Value switching frequency
External coil
External capacitor
Accuracy includes variations (line load regulations, line load transients, temperature, process) VBAT VDD2 MHz, LDCR Output voltage must discharge load current completely settle final value within Load current varies proportionally with output voltage. slew rate increasing decreasing voltages maximum load current Under current load condition step: Imax/2 (300 with ±20% external capacitor accuracy Imax/3 (200 with ±50% external capacitor accuracy
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Table connect VDD2 dc-dc converter when used. Figure shows efficiency VDD2 dc-dc regulator active sleep modes.
Output voltage VBAT
Effciency
0.0001
0.001
0.01 Iload
032-006
Figure 4-4. VDD2 dc-dc Regulator Efficiency 4.1.2.2 External Components Application Schematic
Figure application schematic with external components VDD2 dc-dc regulator.
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Device VDD2.IN (D13) VDD2.IN (P14)
VDD2.SW (T13) VDD2.SW (R14)
LVDD2
CVDD2.OUT VDD2.GND (T14) VDD2.GND (R15)
032-007
Figure 4-5. VDD2 dc-dc Application Schematic
NOTE component values, Table 15-1.
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4.1.3
4.1.3.1
dc-dc Regulator
dc-dc Regulator Characteristics
I/Os memory dc-dc regulator 600-mA stepdown dc-dc converter (internal FET) with output voltage settings. supplies memories ports application first power providers switch power-up sequence. This dc-dc regulator placed sleep power-down mode; however, care must taken sequencing this power provider, because numerous electrostatic discharge (ESD) blocks connected this supply. Table lists characteristics regulator. Table 4-4. dc-dc Regulator Characteristics
Parameter Input voltage range Output voltage Output accuracy
Comments
1.85
Unit
0.25
Switching frequency Conversion efficiency sleep modes Figure active mode sleep Output current Ground current (IQ) mode Sleep mode 30°C Sleep, unloaded Active, unloaded, switching Load transient Line transient Start-up time Recovery time Output shunt resistor (internal pulldown) Value External coil Saturation current External capacitor Value switching frequency From sleep mode mode with constant load mVPP input rise fall time
This voltage tuned according platform transient requirements. accuracy includes variations (line load regulation, line load transient, temperature, process). accuracy accuracy only. VBAT MHz, LDCR Load transient also specified IOUTmax/2, this included accuracy.
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Figure shows efficiency dc-dc regulator active sleep modes.
Output voltage VBAT
Effciency
0.0001
0.001
0.01 Iload
032-008
Figure 4-6. dc-dc Regulator Efficiency Active Mode 4.1.3.2 External Components Application Schematic
Figure application schematic with external components dc-dc regulator.
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Device VIO.IN (R4) VIO.IN (P3)
VIO.SW (R3) VIO.SW (T4)
LVIO
CVIO.OUT VIO.GND (R2) VIO.GND (T3)
032-009
Figure 4-7. dc-dc Application Schematic
NOTE component values, Table 15-1.
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4.1.4
VDAC Regulator
VDAC programmable regulator high power-supply ripple rejection (PSRR), low-noise, linear regulator that powers host processor dual-video DAC. controllable with registers through powered down. Table lists characteristics regulator. Table 4-5. VDAC Regulator Characteristics
Parameter Test Conditions Connected from VDAC.OUT analog ground mode 1.164 1.261 1.746 1.236 1.339 1.854 nV/Hz Unit
Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics VOUT Input voltage Output voltage
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IMax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax
Output noise
Ground current
mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C
Dropout voltage Transient load regulation Transient line regulation
mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
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4.1.5
VPLL1 Regulator
VPLL1 programmable regulator high-PSRR, low-noise, linear regulator used host processor phase-locked loop (PLL) supply. Table lists characteristics regulator. Table 4-6. VPLL1 Regulator Characteristics
Parameter Test Conditions Connected from VPLL1.OUT analog ground mode low-power mode 0.97 1.164 1.261 1.746 2.716 2.91 1.03 1.236 1.339 1.854 2.884 3.090 Unit
Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics VOUT Input voltage Output voltage
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IMax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax
Ground current
mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C
Dropout voltage Transient load regulation Transient line regulation
mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
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4.1.6
VPLL2 Regulator
VPLL2 programmable regulator high-PSRR, low-noise, linear regulator used host processor supply. Table lists characteristics regulator. Table 4-7. VPLL2 Regulator Characteristics
Parameter Test Conditions Connected from VPLL2.OUT analog ground 0.672 0.97 1.164 1.261 1.455 1.746 1.795 2.425 2.522 2.716 2.765 2.91 3.05 1.85 2.85 3.15 0.728 1.03 1.236 1.339 1.545 1.854 1.906 2.575 2.678 2.884 2.936 3.09 3.245 Unit
Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics Input voltage
VOUT
Output voltage
mode low-power mode
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IMax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
Ground current
Dropout voltage Transient load regulation Transient line regulation
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4.1.7
VMMC1 Regulator
VMMC1 regulator programmable linear voltage converter that powers multimedia channel (MMC) slot. includes discharge resistor overcurrent (short -ircuit) protection. This regulator also turned automatically when card extraction detected. VMMC1 powered through independent supply other than battery; example, charge pump (CP). this case, input from VMMC1 higher than battery voltage. Table lists characteristics regulator. Table 4-8. VMMC1 Regulator Characteristics
Parameter Test Conditions Connected from VMMC1.OUT analog ground mode low-power mode mode Low-power mode mode: IMax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s 1.7945 2.7645 2.91 3.0555 Unit
Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics VOUT Input voltage Output voltage 1.85 1.9055 2.85 2.9355 3.09 3.15 3.2445
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
Ground current
Dropout voltage Transient load regulation Transient line regulation
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4.1.8
VMMC2 Regulator
VMMC2 regulator programmable linear voltage converter that powers slot includes discharge resistor overcurrent (short-circuit) protection. VMMC2 powered through independent supply other than battery (for example, CP). this case, input from VMMC2 higher than battery voltage. Table lists characteristics regulator. Table 4-9. VMMC2 Regulator Characteristics
Parameter Test Conditions Connected from VMMC2.OUT analog ground 1.164 1.261 1.455 1.746 1.795 2.425 2.522 2.716 2.765 2.91 3.056 1.85 2.85 3.15 1.03 1.236 1.339 1.545 1.854 1.906 2.575 2.678 2.884 2.936 3.09 3.245 Unit
Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics Input voltage
VOUT
Output voltage
mode low-power mode
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IMax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
Ground current
Dropout voltage Transient load regulation Transient line regulation
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4.1.9
VSIM Regulator
VSIM voltage regulator programmable, low-dropout, linear voltage regulator that supplies subscriber identity module (SIM)-card SIM-card driver. This regulator turned automatically when card extraction detected. Table 4-10 lists characteristics regulator. Table 4-10. VSIM Regulator Characteristics
Parameter Test Conditions Connected from VSIM.OUT analog ground 0.97 1.164 1.261 1.746 2.716 2.91 1.03 1.236 1.339 1.854 2.884 3.09 Unit
Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics Input voltage
VOUT
Output voltage
mode low-power mode
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IMax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
Ground current
Dropout voltage Transient load regulation Transient line regulation
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4.1.10 VAUX1 Regulator
VAUX1 regulator powers auxiliary devices. VAUX1 regulator also support inductive load such vibrator. While operating vibrator mode, VAUX1 following features: Programmable, register-controlled, soft-start function Enabled through VIBRA.SYNC Programmable, register-controlled, duty cycle (PWM generator) based nominal 4-Hz cycle derived from internal 32-kHz clock Table 4-11 lists characteristics regulator. Table 4-11. VAUX1 Regulator Characteristics
Parameter Output Load Conditions Filtering capacitor Filtering capacitor Vibrator inductive load Vibrator load resistance Electrical Characteristics Input voltage 1.455 1.746 2.425 2.716 2.91 1.545 1.854 2.575 2.884 3.09 5000 Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s Connected from VAUX1.OUT analog ground Connected from VAUX1.OUT analog ground Test Conditions Unit
VOUT
Output voltage
mode low-power mode
IOUT
Rated output current load regulation line regulation Turn-on time Turn-off time Wake-up time Ripple rejection
mode Low-power mode mode: IOUT IOUTmax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Soft-start function inductive load
Ground current
Dropout voltage Transient load regulation Transient line regulation
Parameter tested, used design specification only
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4.1.11 VAUX2 Regulator
VAUX2 regulator powers auxiliary devices. Table 4-12 lists characteristics regulator. Table 4-12. VAUX2 Regulator Characteristics
Parameter Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics Input voltage Connected from VAUX2.OUT analog ground Test Conditions Unit
VOUT
Output voltage
mode low-power mode
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IOUT IOUTmax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
Ground current
Dropout voltage Transient load regulation Transient line regulation
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4.1.12 VAUX3 Regulator
VAUX3 regulator powers auxiliary devices. Table 4-13 lists characteristics regulator. Table 4-13. VAUX3 Regulator Characteristics
Parameter Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics Input voltage 1.455 1.746 2.425 2.716 2.91 1.545 1.854 2.575 2.884 3.09 Connected from VAUX3.OUT analog ground Test Conditions Unit
VOUT
Output voltage
mode low-power mode
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IOUT IOUTmax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
Ground current
Dropout voltage Transient load regulation Transient line regulation
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4.1.13 VAUX4 Regulator
VAUX4 regulator powers auxiliary devices. VAUX4 regulator independent supply input preregulated external voltage. Table 4-14 lists characteristics regulator. Table 4-14. VAUX4 Regulator Characteristics
Parameter Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics Input voltage 0.672 0.97 1.164 1.261 1.455 1.746 1.795 2.425 2.522 2.716 2.765 2.91 3.056 1.85 2.85 3.15 0.728 1.03 1.236 1.339 1.545 1.854 1.906 2.575 2.678 2.884 2.936 3.09 3.245 Connected from VAUX4.OUT analog ground Test Conditions Unit
VOUT
Output voltage
mode low-power mode
IOUT
Rated output current load regulation line regulation Turn-on time Wake-up time Ripple rejection
mode Low-power mode mode: IOUT IOUTmax mode, VINmin VINmax IOUT IOUTmax IOUT (within VOUT) Full load capability VOUT IMax mode, IOUT mode, IOUT IOUTmax Low-power mode, IOUT Low-power mode, IOUT mode 55°C mode, IOUT IOUTmax ILoad: IMin IMax Slew: mA/s drops Slew: mV/s
Ground current
Dropout voltage Transient load regulation Transient line regulation
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4.1.14 Internal LDOs
Table 4-15 lists regulators that power device, output loads associated with them. Table 4-15. Output Load Conditions
Regulator VINTDIG Parameter Filtering capacitor Filtering capacitor VINTANA1 Filtering capacitor Filtering capacitor VINTANA2 Filtering capacitor Filtering capacitor VRUSB_3V1 Filtering capacitor Filtering capacitor VRUSB_1V8 Filtering capacitor Filtering capacitor VRUSB_1V5 Filtering capacitor Filtering capacitor Connected from VINTUSB1P5 Connected from VINTUSB1P8.OUT Connected from VUSB.3P1 Connected from VINTANA2.OUT analog ground Connected from VINTANA1.OUT analog ground Test Conditions Connected from VINTDIG.OUT analog ground Unit
4.1.15
generates 4.8-V (nominal) power supply voltage from battery VBUS pin. input voltage range battery voltage. operating frequency MHz. tolerates VBUS when power-down mode. integrates short-circuit current limitation Table 4-16 lists characteristics Table 4-16. Characteristics
Parameter Output Load Conditions Filtering capacitor Flying capacitor Filtering capacitor Electrical Characteristics Iload Input voltage Output voltage Rated output current Efficiency Setting time Startup time Short-circuit limitation current load regulation line regulation ILOADmin ILOADmax VBATmax ILoad IVBUS_5Vmax/2 IVBUS_5Vmax 2*4.7 IVBUS_5Vmax/2, 2*4.7 Transient line regulation VBATmin VBATmax 2*4.7 VBAT VBUS VBAT VBUS ILoad VBAT ILOADmax/2 ILOAmax mode: VBAT 5.25 Connected from VBUS VSSP Connected from 1.41 1.32 3.08 Test Conditions Unit
Transient load regulation
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4.1.16 Short-Circuit Protection Scheme
short-circuit current LDOs dc-dc converters TPS65950 approximately twice maximum load current. certain cases when output block shorted ground, power dissipation exceed 1.2-W requirement action taken. short-circuit protection scheme included TPS65950 ensure that output dc-dc short-circuited, power dissipation does exceed 1.2-W level. three LDOs, VRUSB3V1, VRUSB1V8, VRUSB1V5, included this short-circuit protection scheme, which monitors output voltage frequency generates interrupt (sc_it) when short circuit detected. scheme compares output voltage reference voltage detects short circuit voltage drops below this reference value (0.5 0.75 programmable). case VRUSB3V1 VRUSB1V8 LDOs, reference compared with divided-down voltage (1.5 typical). short circuit detected VRUSB3V1, power subchip switches this sleep mode. short circuit detected VRUSB1V8 VRUSB1V5, power subchip switches relevant LDO.
Power References
bandgap voltage reference filtered (resistance/capacitance [RC] filter) using external capacitor connected across VREF output analog ground (REFGND). VREF voltage scaled, distributed, buffered device. bandgap started fast mode (not filtered), automatically machine slow mode (filtered, less noisy) when required. Table 4-17 lists characteristics voltage references. Table 4-17. Voltage Reference Characteristics
Parameter Test Conditions Connected from VREF REFGND Unit
Output Load Condition Filtering capacitor
4.3.1
Power Control Backup Battery Charger
backup battery rechargeable, recharged from main battery. programmable voltage regulator powered main battery allows recharging backup battery. backup battery charge must enabled using control register. Recharging starts when conditions met: Main battery voltage backup battery voltage Main battery comparators backup battery system (BBS) give thresholds backup battery charge startup. programmed voltage charger gives end-of-charge threshold. programmed current charger gives charge current. Overcharging prevented measurement backup battery voltage through ADC. Table 4-18 lists characteristics backup battery charger. Table 4-18. Backup Battery Charger Characteristics
Parameter Test Conditions VBACKUP from 0.33 Unit
VBACKUP-to-MADC input attenuation
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Table 4-18. Backup Battery Charger Characteristics (continued)
Parameter Backup battery charging current Test Conditions VBACKUP BBCHEN BBISEL VBACKUP BBCHEN BBISEL VBACKUP BBCHEN BBISEL VBACKUP BBCHEN BBISEL VBACKUP BBCHEN BBISEL VBACKUP BBCHEN BBISEL VBACKUP BBCHEN BBISEL VBACKUP BBCHEN BBISEL backup battery charging voltage: VBBCHGEND IVBACKUP BBSEL IVBACKUP BBSEL IVBACKUP BBSEL IVBACKUP BBSEL 17.5 Unit
4.3.2
4.3.2.1
Battery Monitoring Threshold Detection
Power On/Power Backup Conditions
Table 4-19 lists threshold levels battery. Table 4-19. Battery Threshold Levels
Parameter Main battery charged threshold VMBCH Main battery threshold VMBLO Main battery high threshold VMBHI Test Conditions Measured VBAT terminal VBACKUP measured VBAT terminal (monitored terminal ONNOFF) Measured terminal VBAT, VBACKUP Measured terminal VBAT, VBACKUP 2.55 1.95 2.65 2.85 2.85 2.95 2.95 2.25 Unit
Batteries present threshold VBNPR Measured terminal VBACKUP with VBAT Measured terminal VBAT with VBACKUP (monitored terminal VRRTC)
4.3.3
VRRTC Regulator
VRRTC voltage regulator programmable, dropout, linear voltage regulator supplying (1.5 embedded real-time clock (32.768-kHz oscillator) dedicated I/Os digital host counterpart. VRRTC regulator also supply voltage power-management digital state-machine. VRRTC regulator supplied from line, switched main backup battery, depending system state. VRRTC output present long valid energy source present. VRRTC line supplied when VBAT 2.7, clamp circuit when backup mode. Table 4-20 describes regulator characteristics. Table 4-20. VRRTC Regulator Characteristics
Parameter Test Conditions Connected from VRTC.OUT analog ground mode mode 1.45 VBAT 1.55 Unit
Output Load Conditions Filtering capacitor Filtering capacitor Electrical Characteristics VOUT Input voltage Output voltage
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Table 4-20. VRRTC Regulator Characteristics (continued)
Parameter IOUT Rated output current load regulation line regulation Turn-on time Wake-up time mode Sleep mode mode: IOUT IOUTmax mode, VINmin VINmax IOUT IOUTmax IOUT VOUT VOUTfinal mode from power mode, IOUT VOUT VOUTfinal From backup mode, IOUT VOUT VOUTfinal Ripple rejection (VRRTC) VOUT IMAX Ground current mode, IOUT mode, IOUT IOUTmax Sleep mode, IOUT Sleep mode, IOUT mode Dropout voltage
Test Conditions
Unit
mode, IOUT IOUTmax ILOAD: IMIN IMAX Slew: mA/s drops Slew: mV/s Softstart Default mode
Transient load regulation Transient line regulation Overshoot Pull down resistance nominal output voltage
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Power Consumption
Table 4-21 describes power consumption, depending cases.
NOTE Typical power consumption obtained nominal operating conditions with TPS65950 stand-alone mode.
Table 4-21. Power Consumption
Mode Backup Description Only date maintained with couple registers backup domain. main source connected. Consumption backup battery. phone apparently user, main battery present well-charged. registers (registers backup domain) maintained. Wake-up capabilities (like PWRON button) available. subsystem powered main battery, supplies enabled with full current capability, internal reset released, associated processor running. main battery powers subsystem, selected supplies enabled low-consumption mode, associated processor low-power mode. VBAT present Typical Consumption 2.25
Wait-on
VBAT
243.2
Active Load
VBAT
3291 12505
Sleep Load
VBAT
1884.4
Table 4-22 lists regulator states each mode. Table 4-22. Regulator States Depending Cases
Regulator VAUX1 VAUX2 VAUX3 VAUX4 VMMC1 VMMC2 VPLL1 VPLL2 VSIM VDAC VINTANA1 VINTANA2 VINTDIG VDD1 VDD2 VUSB_1V5 VUSB_1V8 VUSB_3V1 Mode Backup Wait-On Sleep Load SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP Active Load SLEEP
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4.5.1
Power Management Boot Modes
modes corresponding BOOT0-BOOT1 combination value listed Table 4-23. Table 4-23. BOOT Mode Description
Name MC027 MC021 SC021 Description Reserved Master_C027_Generic Master_C021_Generic Slave_C021_Generic BOOT0 BOOT1
4.5.2
Process Modes
process modes parameter defines: boot voltage host core boot sequence associated with process dynamic voltage frequency scaling (DVFS) protocol associated with process
4.5.2.1
C027.0 Mode
Table 4-24 lists parameters C027.0 mode. Table 4-24. C027.0 Mode Description
Boot core voltage Power sequence DVFS protocol followed VDD1 VPLL VMODE1/2
4.5.2.2
C021.M Mode
Table 4-25 lists parameters C021.M mode. Table 4-25. C021.M Mode Description
Boot core voltage Power sequence DVFS protocol followed VPLL1, VDD2, VDD1 SmartReflex (I2C high speed)
4.5.3
4.5.3.1
Power-On Sequence
Timings Before Sequence_Start
starting time power-on sequence relative external events shown Figure 4-8.
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Vbkup User_Action
Starting_Event main battery insertion Vbat cycle32k Sequence_Start
Starting_Event charger insertion cycle32k Sequence_Start
Starting_Event VBUS insertion Vbus cycle32k Sequence_Start
Starting_Event PWRON button PWRON Pushbutton debouncing Sequence_Start
Starting_Event PWRON rising when device slave mode PWRON Sequence_Start
032-010
Figure 4-8. Timings Before Sequence Start 4.5.3.2 OMAP2 Power-On Sequence
Figure shows timing control that must occur Master_C027_Generic mode. Sequence_Start occurs according events shown Figure 4-8.
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Sequence_Start 4638 battery detection REGEN 1068 oscillator setting clock switch 1072 stabilization VDD1 1007 VDD1 stabilization VDD2 1052 VDD2 stabilization VPLL1 stabilization 32KCLKOUT SYSEN 2034 DcDc stabilization CLKEN 3418 HFCLKOUT NRESPWRON
032-011
Figure 4-9. Timings-OMAP2 Power-On Sequence 4.5.3.3 OMAP3 Power-On Sequence
Figure 4-10 shows timing control that must occur Master_C021_Generic mode. Sequence_Start occurs according events shown Figure 4-8.
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Sequence_Start 4608 battery detection REGEN 1068 oscillator setting clock switch 1179 stabilization VPLL1 1022 stabilization start DcDc ramping VDD2 1099 VDD2 stabilization VDD1 start ramping VDD1 1175 VDD1 stabilization 32KCLKOUT SYSEN 1179 stabilization CLKEN 1953 HFCLKOUT NRESPWRON
032-012
Figure 4-10. Timings-OMAP3 Power-On Sequence
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4.5.3.4
Power Slave_C021_Generic Mode
Figure 4-11 describes timing control that must occur Slave_C021_Generic mode. Sequence_Start symbolic internal signal ease description power sequences occurs according different events detailed Figure 4-8.
PWRON 4791 oscillator setting internal REGEN 1068 external supply ramp 1179 dc-dc stablilization VPLL1 1022 VDD2 1099 VDD2 stabilization VDD1 1175 VDD1 stabilization 32KCLKOUT SYSEN 1099 VDD2 stabilization CLKEN 1953 digital clock setting HFCLKOUT NRESPWRON
030-022
Figure 4-11. Timings-Power Slave_C021_Generic Model
4.5.4
Power-Off Sequence
This section describes signal behavior required power down system.
4.5.4.1
Power-Off Sequence Master Modes
Figure 4-12 shows timing control that occur during power-off sequence master modes.
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VBAT DEVOFF(register) NRESPWRON REGEN 32KCLKOUT DCDCs LDOs SYSEN HFCLKOUT CLKEN 3.42 before detection starting event NEXT_Startup_event
032-013
NOTE: timings typical values with default setup (depending resynchronization between power domains, state machinery priority, etc.).
Figure 4-12. Power-Off Sequence Master Modes value clock 19.2 (with values CFG_BOOT HFCLK_FREQ field accordingly), delay between DEVOFF divided (approximately This caused internal frequency used power Sswitching from clock value 19.2 MHz. DEVOFF event PWRON falling edge slave mode DEVOFF internal register write master mode.
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Real-Time Clock Embedded Power Controller
TPS65950 device contains provide clock timekeeping functions provide battery supervision control.
provides following basic functions: Time information (seconds/minutes/hours) directly binary-coded decimal (BCD) code Calendar information (day/month/year/day week) directly code Interrupt generation periodically second/1 minute/1 hour/1 day) precise time (alarm function) 32-kHz oscillator drift compensation time correction Alarm-triggered system wake-up event
5.1.1
Backup Battery
TPS65950 implements backup mode which backup battery keep running maintain clock time information even main supply present. backup battery rechargeable, device also provides backup battery charger recharged when main battery supply present. backup domain powers following: Internal 32.768-kHz crystal oscillator Eight storage registers Backup domain low-power regulator (VBRTC)
provides five system states optimal power system, listed Table 5-1. Table 5-1. System States
System State SUPPLY BACKUP WAIT-ON ACTIVE SLEEP Description system powered battery. system powered only with backup battery maintains only VBRTC supply. system powered main battery maintains only VRRTC supply. accept switch-on requests. system powered main battery; supplies enabled with full current capability. main battery powers system; selected supplies enabled, consumption mode.
Three categories events trigger state transitions: Hardware events: Supply/battery insertion, wake-up requests, plug, alarm Software events: Switch-off commands, switch-on commands, sleep-on commands Monitoring events: Supply/battery level check, main battery removal, main battery fail, thermal shutdown
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Audio/Voice Module
audio codec device includes five DACs ADCs provide multiple voice channels stereo downlink channels that support standard audio sample rates through I2S/TDM format interfaces. audio output stages device include stereo headset amplifiers, integrated class-D amplifiers providing stereo differential outputs, predrivers line outputs, earpiece amplifier. input audio stages include three differential microphone inputs, stereo line inputs, interface digital micrphones. Automatic programmable gain control available with necessary digital filtering, side-tone functions, pop-noise reduction. Figure block diagram audio/voice module.
HFCLKIN
High-speed (control)
Headset microphone
Voice interface
Bluetooth interface
Audio TDM/I2S interface
Main microphone
Stereo headset
microphone
Stereo hands-free class
Mono piece Bias LDOs (x3) Carkit/MCPC speaker/ microphone
Digital microphones
Vibrator H-bridge Stereo auxiliary input Audio/voice module
Device
032-014
Figure 6-1. Audio/Voice Module Block Diagram
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Audio/Voice Downlink (RX) Module
audio/voice module includes following output stages: Mono/stereo single-ended headset amplifier Stereo differential integrated class-D hands-free amplifiers Predriver output signals external class-D amplifiers (single-ended) Mono differential earpiece amplifier Vibrator H-bridge
6.1.1
6.1.1.1
Earphone Output
Earphone Output Characteristics
Analog signals from audio and/or voice interface earphone amplifier. This amplifier, with different gains, provides full differential signal terminals EARP EARM. Figure shows earphone amplifier. Table lists output characterstics earphone amplifier.
dBFs
Digital Gain
Analog Gain
diff
032-015
Figure 6-2. Earphone Amplifier Table 6-1. Earphone Amplifier Output Characteristics
Parameter Differential load impedance Gain range
Test Conditions
Unit
Audio path Voice path
61.25
Absolute gain error Maximum output power Peak-to-peak differential output voltage dBFs) Total harmonic distortion Default gain
Vrms differential output voltage Load impedance Default gain dBFs dBFs dBFs dBFs Gain Load
Load impedance Idle channel noise kHz, A-weighted) Output PSRR (for gains)
dBFs
Audio digital filter (1-dB steps) (6-dB steps) Voice digital filter (1-dB steps) ARXPGA (volume control) (2-dB steps) Output driver default gain setting assumes ARXPGA 2-dB gain setting (volume control) output driver 6-dB gain setting.
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6.1.1.2
External Components Application Schematic
Figure simplified schematic earphone speaker.
Board Chip
EARP
CEAR
EARM
032-016
Figure 6-3. Earphone Speaker
NOTE component values, Table 15-1.
6.1.2
Stereo Hands-Free
digital signal from audio and/or voice interface class-D amplifiers. These speaker amplifiers provide stereo differential signal terminal pairs (IHF.RIGHT.P, IHF.RIGHT.M IHF.LEFT.P, IHF.LEFT.M).
6.1.2.1
Stereo Hands-Free Output Characteristics
Figure shows stereo hands-free amplifier. Table lists output characteristics stereo hands-free amplifier.
Digital Gain
Analog Gain
10.4
diff
032-017
Figure 6-4. Stereo Hands-Free Amplifiers Table 6-2. Stereo Hands-Free Output Characteristics
Parameter VBAT voltage Load impedance Gain range Audio path Test Conditions -75.6 34.4 Unit
Audio digital filter (1-dB steps) (6-dB steps) Voice digital filter (1-dB steps) ARXPGA (volume control) (2-dB steps) Output driver 10.4 Audio/Voice Module Submit Documentation Feedback Product Folder Link(s): TPS65950
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Table 6-2. Stereo Hands-Free Output Characteristics (continued)
Parameter Absolute gain error Maximum output power (load impedance Peak-to-peak differential output voltage VBAT VBAT VBAT dBFs) VBAT dBFs) Total harmonic distortion (load impedance gain setting (VBAT dBFs dBFs dBFs dBFs Total harmonic distortion (load impedance (VBAT Idle channel noise kHz) PSRR (input signal sine, mVPP ripple with 10-s rise/fall times, 12.5% duty cycle) Efficiency Power dissipation Idle current consumption VBAT Clock frequency ramp generation IDDQ current 25°C dBFs gain From VBAT Power load Load impedance Power load Load impedance Without input signal 426.6 Test Conditions Voice path -49.6 6.25 dBFs dBFs 34.4 Unit
6.1.2.1.1 Short-Circuit Protection There short-circuit protection hands-free amplifiers limit power dissipation short-circuit protection disabled register. short circuit detected, short-circuit detection block switches hands-free speaker output stages. software restart required restart class-D amplifier. 6.1.2.2 External Components Application Schematic
Figure simplified schematic stereo hands-free.
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board
VBAT
Chip
VBAT.RIGHT/LEFT CHFR/CHFL Ferrite cheap bead LHFR.P/LHFL.P CHFR.P/CHFL.P Ferrite cheap bead LHFR.M/LHFL.M CHFR.M/CHFL.M GND.RIGHT/LEFT IHF.RIGHT/LEFT.M IHF.RIGHT/LEFT.P
032-018
Figure 6-5. Stereo Hands-Free
NOTE component values, Table 15-1.
ferrite bead, choose with high impedance high frequencies, with very impedance frequencies. example, MPZ1608S221A (recommended), N2012ZPS121, BKP1608HS271.
6.1.3
Headset
analog signal from audio and/or voice interface single-ended headset amplifiers. There configurations: Stereo single-ended mode: Left right headset amplifiers with different gains (-6, provide stereo signal HSOL HSOR terminals. pseudo-ground provided VMID terminal eliminate external capacitors. Stereo single-ended mode ac-coupled: Left right headset amplifiers with different gains (-6, provide stereo signal HSOL HSOR terminals. external capacitor required eliminate component signal.
6.1.3.1
Headset Output Characteristics
Figure shows headset amplifier. Table lists output characteristics headset amplifier.
dBFs
Digital Gain
Analog Gain
032-019
Figure 6-6. Headset Amplifier Table 6-3. Headset Output Characteristics
Parameter Load impedance
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Test Conditions
Unit
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Table 6-3. Headset Output Characteristics (continued)
Parameter Gain range
Test Conditions Audio path Voice path
Unit
Absolute gain error Maximum output power Peak-to-peak output voltage dBFs) Total harmonic distortion Default gain Load Idle channel noise kHz, A-weighted) (A-weighted over 20-kHz bandwidth) Output PSRR (for gains) Crosstalk between right left channels Single-Ended Mode (Pseudo-Ground Provided HSOVMID) Total harmonic distortion Default gain Load Idle channel noise kHz, A-weighted) Output PSRR (for gains)
0.53 Vrms differential output voltage Load impedance Default gain dBFs dBFs dBFs dBFs Default gain Load dBFs
17.56
Single-Ended Mode ac-Coupled
dBFs dBFs dBFs dBFs Default gain Load
Audio digital filter (1-dB steps) (6-dB steps) Voice digital filter (1-dB steps) ARXPGA (volume control) (2-dB steps) Output driver default gain setting assumes ARXPGA gain setting (volume control) output driver gain setting.
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6.1.3.2
External Components Application Schematic
Figure schematic headset 4-wire stereo jack without external FET. Table lists output characteristics this configuration.
board 4-wire stereo jack CHM.P HSMIC.P CHM.O CHM.M HSMIC.M HSOR HSOL Chip VHSMIC .OUT
032-20
Figure 6-7. Headset 4-Wire Stereo Jack Without External Table 6-4. Output Characteristics Headset 4-Wire Stereo Jack Without External
Parameter Test Conditions input capacitors output resistors form high-pass filter (HPF) with corner frequency 1/(2Rout/Cs) required ensure amplifier stability <100 Unit
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NOTE other component values, Table 15-1.
Table schematic headset 4-wire stereo jack with external FET. Table lists output characteristics this configuration.
board 4-wire stereo jack CHM.P HSMIC CHM.O CHM.M HSMIC HSOL Chip VHSMIC .OUT
HSOR
External
GPIO_6 MUTE
032-021
Figure 6-8. Headset 4-Wire Stereo Jack With External Table 6-5. Output Characteristics Headset 4-Wire Stereo Jack With External
Parameter Test Conditions input capacitors output resistors form with corner frequency 1/(2Rout/Cs) required ensure amplifier stability distortion caused parasitic diode external Unit
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NOTE other component values, Table 15-1.
Figure schematic headset 5-wire stereo jack. Table lists output characteristics this configuration.
board Chip VHSMIC.OUT
CHM.P
5-wire stereo jack
HSMIC.P
CHM.O
CHM.M
HSMIC.M HSOL HSOVMID HSOR
CHM.O
032-022
Figure 6-9. Headset 5-Wire Stereo Jack Table 6-6. Output Characteristics Headset 5-Wire Stereo Jack
Parameter Test Conditions required ensure amplifier stability <100 Unit
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NOTE other component values, Table 15-1.
Figure 6-10 schematic headset 4-wire stereo jack optimized.
board 4-wire stereo jack VHSMIC.OUT Chip
CHM.P
HSMIC
CHM.O
CHM.M
HSMIC.M
HSOL Ampli_HS
HSOR
Ampli_HS
Gain
032-023
Figure 6-10. Headset 4-Wire Stereo Jack Optimized
NOTE other component values, Table 15-1.
6.1.4
Headset Pop-Noise Attenuation
noise occurs when audio output amplifier switched Although speaker ac-coupled through external capacitor, sharp rise time given activation amplifier causes large spike propagate speakers. attenuation achieved through precharge discharge external coupling capacitor. antipop system using internal current generator controlling ramp charge discharge implemented headset output. pop-noise effect dramatically reduced external controlled 1.8-V output signal (MUTE pin). Figure 6-11 diagram headset noise. Table lists characteristics headset noise.
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MUTE
RAMP_DELAY EXTMUTE VMID_EN HSR/L_GAIN(1:0) RAMP_EN
Application mode RAMP_DELAY
VMID
dV/dt
032-024
Figure 6-11. Headset Pop-Noise Cancellation Diagram Table 6-7. Headset Pop-Noise Characteristics
Parameter dv/dt Pop-noise (A-weighted) Test Conditions Ramp charge discharge ac-coupling capacitor Serial resistor External FET: Rdson 0.12 Unit
6.1.5
Predriver External Class-D Amplifier
predriver amplifiers provide stereo signal PreD.LEFT PreD.RIGHT terminals drive external class-D amplifier. These terminals available stereo, single-ended, ac-coupled headset used.
6.1.5.1
Predriver Output Characteristics
Table lists output characteristics predriver.
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Table 6-8. Predriver Output Characteristics
Parameter Load impedance Gain range
Test Conditions
Unit
Audio path Voice path
Absolute gain error Peak-to-peak output voltage dBFs) Total harmonic distortion Default gain
Default gain dBFs dBFs dBFs dBFs Default gain Load dBFs dBFS
Load
Idle channel noise kHz, A-weighted) (A-weighted over 20-kHz bandwidth) Default gain Output PSRR (for gains)
Audio digital filter (1-dB steps) (6-dB steps) Voice digital filter (1-dB steps) ARXPGA (volume control) (2-dB steps) Output driver default gain setting assumes ARXPGA gain setting (volume control) output driver gain setting.
6.1.5.2
External Components Application Schematic
Figure 6-12 simplified schematic external class-D predriver.
board Chip
RPR/RPL
CPL/CPR PreDriverD
Class (TPA2010D1.)
Closed external class
CPR.O/CPL.O
RPL.O/RPR.O
CPL.M/CPR.M RPR.M/RPL.M
032-025
Figure 6-12. Predriver External Class Figure 6-12, input resistor (RPR RPL) sets gain external class TPS2010D1, gain defined according following equation: Gain (V/V) 2*150*103/(RPR RPL)
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NOTE other component values, Table 15-1.
6.1.6
Vibrator H-Bridge
digital signal from pulse width modulated generator vibrator H-bridge driver. vibrator H-bridge differential driver that drives vibrator motors. differential output allows dual rotation directions.
6.1.6.1
Vibrator H-Bridge Output Characteristics
Table lists output characteristics vibrator H-bridge. Table 6-9. Vibrator H-Bridge Output Characteristics
Parameter VBAT voltage Differential output swing (16- load) Output resistance (summed both sides) Load capacitance Load resistance Load inductance Total harmonic distortion Operating frequency VBAT VBAT Test Conditions Unit
6.1.6.2
External Components Application Schematic
Figure 6-13 simplified schematic vibrator H-bridge.
board Chip
VBAT
VBAT.RIGHT CV.V Ferrite cheap bead LV.P CV.P Vibrator Ferrite cheap bead LV.M CV.M VIBRA.GND (LED.GND) VIBRA.M VIBRA.P
032-026
Figure 6-13. Vibrator H-Bridge
NOTE other component values, Table 15-1.
Copyright 2008-2009, Texas Instruments Incorporated
Audio/Voice Module

TPS65950

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